JP2011150645A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform control so that a peripheral function part accesses a plurality of local memories or accesses part of local memories. <P>SOLUTION: A system bus controller (33) is provided that can control routing from a system bus to a first local bus and a second local bus responding to a communication request from a peripheral function part based on definition information concerning a first local memory and a second local memory in an address space of an information processor, and an operation mode of a CPU. A first local bus controller (13) is provided that can control the routing to the first local memory corresponding to the communication request from the peripheral function part based on the definition information, and a second local bus controller (23) is provided that can control the routing to the second local memory corresponding to the communication request from the peripheral function part based on the definition information, thereby optimizing access to the local memory. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory access technique in an information processing apparatus capable of dynamically switching an operation mode of a CPU (central processing unit) between a high reliability mode and a high performance mode.

  In a system equipped with a plurality of CPUs, the operation modes of these CPUs are roughly divided into a high reliability mode and a high performance mode. The high-reliability mode is an operation mode typified by a lock step, and is an operation mode that enables error detection, error correction, and the like by synchronizing multiple CPUs to execute the same program. One high-performance mode is a general multi-core system, and is an operation mode that achieves high performance as a whole system by causing each CPU to execute different programs. These operation modes are generally used while being fixed to one of the systems. Patent Documents 1 to 6 describe a method of switching an operation mode of a CPU during the operation of the system and a technology related thereto.

JP 09-073436 A JP 2006-302289 A Special table 2008-518339 gazette Special table 2008-518338 gazette Special table 2008-518340 gazette Japanese Patent Application Laid-Open No. 07-230436

  The inventor of the present application examined the case of applying a mode switching method during the operation of the system to a field requiring real-time performance such as an embedded system.

  When applying a mode switching method during system operation to a field that requires real-time performance such as an embedded system, the same data is arranged in a resource such as a local memory tightly coupled to each CPU in the high-reliability mode. Can be considered. Further, data used by each CPU in the high-performance mode is required to be arranged only in the local memory of each CPU from the viewpoint of reducing the memory usage.

  When attention is paid to one piece of data in the local memory, access to the data from the CPU and peripheral functions is always performed in a time-sharing manner. For example, input data from the outside is stored in the local memory through the peripheral function, and after a certain amount is accumulated, it is analyzed by the CPU, or data created in advance by the CPU is output to the outside through the peripheral function. The usage method is mentioned. Such access in time division is indispensable so as not to cause inconsistency in data update and reference. That is, it can be said that the program executed by the CPU at a certain timing and the access to the local memory from the peripheral function unit are irrelevant.

  Further, considering the switching of the CPU operation mode during the operation of the system, the following occurs.

  Data on a local memory accessed by a program executed in a certain operation mode by the CPU is accessed by the peripheral function unit before and after the program operates. The fact that the CPU operation mode is switched during the operation of the system means that the CPU operation mode may be different before and after the operation of the program. In other words, when the peripheral function unit accesses the local memory, it means that a mechanism for setting whether to access a plurality of local memories or only a part of the local memories is necessary. For example, in the field of engine control and the like in automobiles, it is necessary to constantly monitor and control the external state, so that the peripheral function unit cannot be stopped. Without such a mechanism, the system cannot be established.

  Further, when such access is possible, the peripheral function accesses only the local memory of the specific CPU while the CPU is accessing the local memory in the high reliability mode, so that the local memory accesses the local memory. There is a possibility that contention occurs and synchronization between CPUs is lost. Therefore, it is necessary to make it possible to access only a specific local memory without causing loss of synchronization.

  Although the above cited references 1 to 6 describe a method of switching the operation mode of the CPU during the operation of the system and a technique related thereto, a plurality of local memories are used when the peripheral function unit accesses the local memory. However, the control of whether to access to some local memory is not considered.

  An object of the present invention is to access a plurality of local memories when a peripheral function unit accesses the local memory in a system that dynamically switches the operation mode of the plurality of CPUs between a high-reliability mode and a high-performance mode. Or providing a technique capable of controlling whether to access a part of local memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the information processing apparatus is coupled to the first CPU, the first local bus coupled to the first CPU, the first local memory coupled to the first local bus, the second CPU, and the second CPU. A second local bus; a second local memory coupled to the second local bus; a system bus coupleable to the first local memory and the second local memory; and peripheral functions coupled to the system bus A part. The information processing apparatus can execute a high reliability mode in which the first CPU and the second CPU execute the same program as the operation mode of the CPU, and different programs in the first CPU and the second CPU. With high performance mode. In such an information processing apparatus, communication from the peripheral function unit is performed based on the definition information about the first local memory and the second local memory in the address space of the information processing apparatus and the operation mode of the CPU. A system bus controller capable of controlling routing from the system bus to the first local bus and the second local bus corresponding to the request is provided. In addition, based on the definition information, a first local bus controller that can control routing from the first local bus to the first local memory, corresponding to a communication request from the peripheral function unit, and the definition information And a second local bus controller capable of controlling the routing from the second local bus to the second local memory corresponding to the communication request from the peripheral function unit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, in a system that can be dynamically switched between the high-reliability mode and the high-performance mode, when the peripheral function unit accesses the local memory, whether to access a plurality of local memories or a part of the local memories It is possible to provide a technology capable of controlling whether access is performed.

It is a block diagram of a configuration example of an information processing apparatus according to the present invention. It is explanatory drawing of the address space managed with the said information processing apparatus. It is a flowchart of the routing process by the system bus controller contained in the said information processing apparatus. It is a structural example explanatory drawing of the system bus controller contained in the said information processing apparatus. It is a flowchart of the routing process by the local bus controller contained in the said information processing apparatus. It is explanatory drawing of a structural example of the local bus controller contained in the said information processing apparatus. It is explanatory drawing of the address space managed with the said information processing apparatus. FIG. 3 is an explanatory diagram illustrating a configuration example of a local bus and a system bus included in the information processing apparatus. It is a flowchart of the routing process by the system bus controller contained in the said information processing apparatus. It is a structural example explanatory drawing of the system bus controller contained in the said information processing apparatus. It is a flowchart of the routing process by the local bus controller contained in the said information processing apparatus. It is explanatory drawing of a structural example of the local bus controller contained in the said information processing apparatus. It is explanatory drawing of the address space managed with the said information processing apparatus. FIG. 3 is an explanatory diagram illustrating a configuration example of a local bus and a system bus included in the information processing apparatus. It is a flowchart of the routing process by the system bus controller contained in the said information processing apparatus. It is a structural example explanatory drawing of the system bus controller contained in the said information processing apparatus. It is a flowchart of the routing process by the local bus controller contained in the said information processing apparatus. It is explanatory drawing of a structural example of the local bus controller contained in the said information processing apparatus. It is a flowchart which shows the process in the system bus interface contained in the said information processing apparatus.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] An information processing apparatus (100) according to a representative embodiment of the present invention includes a first CPU (11), a first local bus (12) coupled to the first CPU, and the first local bus. A first local memory (14) coupled to the second CPU (21), a second local bus (22) coupled to the second CPU, and a second local memory coupled to the second local bus ( 24). The information processing apparatus (100) includes a system bus (32) that can be coupled to the first local memory and the second local memory, and a peripheral function unit (41) coupled to the system bus. . Further, the information processing apparatus (100) executes, as CPU operation modes, a high-reliability mode in which the first CPU and the second CPU execute the same program, and different programs in the first CPU and the second CPU. With high performance mode possible.

  In such an information processing device (100), the peripheral function unit is based on the definition information about the first local memory and the second local memory in the address space of the information processing device and the operation mode of the CPU. A system bus controller (33) capable of controlling routing from the system bus to the first local bus and the second local bus corresponding to a communication request (access request) from is provided. Further, in the information processing apparatus, a first local bus controller capable of controlling routing from the first local bus to the first local memory corresponding to a communication request from the peripheral function unit based on the definition information ( 13) and a second local bus controller (23) capable of controlling the routing from the second local bus to the second local memory, corresponding to the communication request from the peripheral function unit, based on the definition information. Is provided. Here, “routing” refers to selecting an optimum route for signal transmission.

  When the CPU operation mode is switched during the operation of the application system of the information processing apparatus, the CPU operation mode may be different before and after the operation of the program. Therefore, in order to operate the application system in which the CPU operation mode is switched during the operation of the application system of the information processing apparatus, when the peripheral function unit accesses the local memory, the plurality of local memories are accessed. It is necessary to appropriately control whether to access only a part of local memory.

  According to the information processing apparatus according to the representative embodiment of the present invention, the system bus controller includes the definition information about the first local memory and the second local memory in the address space of the information processing apparatus, and the Based on the operation mode of the CPU, routing control from the system bus to the first local bus and the second local bus corresponding to the communication request from the peripheral function unit is performed. The first local bus controller performs routing control from the first local bus to the first local memory corresponding to the communication request from the peripheral function unit based on the definition information. Further, the second local bus controller performs routing control from the second local bus to the second local memory corresponding to the communication request from the peripheral function unit based on the definition information. By performing such control, when access to the local memory from the peripheral function unit occurs, it is appropriately controlled whether to access multiple local memories or only some local memories. Therefore, the application system in which the operation mode of the CPU is switched during the operation of the system can be operated normally. Such an effect is particularly noticeable in the field of engine control and the like in an automobile when the peripheral function unit cannot be stopped because it is necessary to constantly monitor and control the external state.

  [2] In the above [1], in response to read access from the peripheral function unit to both the first local memory and the second local memory, the data output from the first local memory, and the first (2) A system bus interface (31) capable of comparing data output from the local memory and outputting the comparison result to the peripheral function unit can be provided. By performing the data comparison by the system bus interface, it is possible to avoid use of undesired read data in the peripheral function unit, so that the high reliability of the system can be improved.

  [3] In the above [2], when the first local bus controller accesses an area accessible to the second local memory in the high reliability mode, the first local bus controller The memory can be replaced with an access that does not involve a change in the contents of the memory. In addition, when the second local bus controller accesses an area accessible to the first local memory in the high reliability mode, the second local bus controller changes the contents of the memory to the second local memory. It can be configured to replace access without it.

  When the peripheral function unit accesses only the local memory of the specific CPU while the CPU is accessing the local memory in the high reliability mode, an access conflict occurs in the local memory, and synchronization between the CPUs occurs. However, as described above, by replacing the access without changing the contents of the memory, the operation can be continued without causing the CPU to lose synchronization.

  [4] In the above [3], as the definition information, in the address space in the information processing apparatus, an area accessible to the first local memory, an area accessible to the second local memory, and the one local An area accessible to both the memory and the second local memory can be defined. With such a definition, routing control in the system bus controller, the first local bus controller, and the second local bus controller can be accurately performed.

  [5] In the above [3], as the definition information, an area accessible to the first local memory and an area accessible to the second local memory memory are defined in the address space in the information processing apparatus, An identifier indicating whether access is to both the first local memory and the second local memory can be defined in the first local bus, the second local bus, and the system bus. In this case, the definition information and the identifier are used in the routing control in the system bus controller, the first local bus controller, and the second local bus controller. Thus, when identifiers indicating whether or not the access is to both the first local memory and the second local memory are defined in the first local bus, the second local bus, and the system bus. The area accessible to both the first local memory and the second local memory need not be defined in the address space of the information processing apparatus.

  [6] In the above [3], an area accessible to both the first local memory and the second local memory is defined in the address space of the information processing apparatus. An identifier for identifying whether the access is to the first local memory, to the second local memory, or to both the first local memory and the second local memory. The first local bus, the second local bus, and the system bus are defined. In this case, the definition information and the identifier are used in the routing control by the system bus controller, the first local bus controller, and the second local bus controller. As described above, when the identifier is defined in the first local bus, the second local bus, and the system bus, the area accessible to the first local memory and the area accessible to the second local memory are as follows. It is not necessary to define the address space in the information processing apparatus.

2. Details of Embodiments Embodiments will be further described in detail.

<Embodiment 1>
FIG. 1 shows a configuration example of an information processing apparatus according to the present invention.

  The information processing apparatus 100 shown in FIG. 1 is not particularly limited, but includes CPUs 11 and 21, local buses 12 and 22, local bus controllers 13 and 23, local memories 14 and 24, a system bus interface 31, a system bus 32, and a system bus. A controller 33 and a peripheral function unit 41 are included.

  The CPUs 11 and 12 are connected to the local memories 14 and 24 via the local buses 12 and 22, respectively. The local bus controllers 13 and 23 control arbitration and routing in the case of access conflict between the bus masters in each local bus. Is called. The CPUs 11 and 21, the local buses 12 and 22, the local bus controllers 13 and 23, and the local memories 14 and 24 are arranged so as to be compatible with the high reliability mode and the high performance mode, and compare the data output to the system bus 32. Connection control with the system bus 32 is performed in the system bus interface 31.

  The system bus controller 33 controls arbitration, routing, and the like when there is an access conflict between bus masters in the system bus 32. The peripheral function unit 41 has a bus master function of the system bus 32 and can access the local memories 14 and 24 via the system bus 32, the system bus interface 31, and the local buses 12 and 22. Various implementations of the peripheral function unit 41 are assumed. For example, a DMA (Direct Memory Access) controller, a CAN (Controller Area Network) controller, a FlexRay controller, a PCI (Peripheral Component Interconnect) controller, and the like can be mounted as the peripheral function unit 41. The address issued by the peripheral function unit 41 as a bus master is determined by various methods such as instructions from the CPUs 11 and 21 to the peripheral function unit 41, hardware fixing, and input from outside the system.

  FIG. 2 shows an address space in the information processing apparatus 100. In the address space of the information processing apparatus 100, an area a1 accessible only to the local memory 14, an area a2 accessible only to the local memory 24, and an area a3 accessible to both the local memories 14 and 24 are defined.

  The system bus controller 33 responds to a communication request (access request) from the peripheral function unit 41 based on the definition information and CPU operation mode shown in FIG. And 22 to 22 are controlled. The system bus controller 33 includes a decoder 401 as shown in FIG. The decoder 401 decodes the CPU mode signal, the communication request signal req from the peripheral function unit 41, and the address signal add transmitted via the system bus 32. The system bus controller 33 performs routing control based on the decoding result.

  In the decoder 401, the decoding logic is configured such that processing as shown in the flowchart of FIG. 3 is performed by hardware, for example. By configuring the decoder 401 with hardware, processing as shown in the flowchart of FIG. 3 can be executed at high speed. For example, when the operation mode of the CPU is the high-reliability mode, whether the access is to the area a1, whether the access is to the area a2, whether the access is to the area a3, whether to the other area The contents of the routing process are determined according to whether or not the access is (No. 302 to 304). In other words, in the case of the high-reliability mode, the access to the areas a1, a2, and a3 is routed to the local buses 12 and 22 (302 to 304, 306), and in the case of access to another area, the other area. (305, 307). When the operation mode of the CPU is the high-performance mode, the routing destination differs depending on the access to the area a1, the access to the area a2, and the access to the area a3. In the case of access to the area a1, it is routed to the local bus 12 (308, 312). In the case of access to the area a2, it is routed to the local bus 22 (309, 313). Are routed to both local buses 12 and 22 (310, 314). In the case of access to another area, the other area is accessed (311 and 315).

  The local bus controller 13 includes a decoder 601 as shown in FIG. The decoder 601 decodes the request signal req and the address signal add. In the local bus controller 13, routing control is performed based on the decoding result of the decoder 601.

  In the decoder 601, the decoding logic is configured so that processing as shown in the flowchart of FIG. 5 is performed by hardware, for example. By configuring the decoder 601 with hardware, processing as shown in the flowchart of FIG. 5 can be executed at high speed. For example, in the case of access to the area a1 and access to the area a3, routing is performed from the local bus 12 to the local memory 14 (501, 502, 504). In the case of access to the area a2, it is converted to dummy access (503, 505). Here, the “dummy access” is an access in which the local bus performs the same signal change as the normal access but does not change the data stored in the local memory 14. That is, in the dummy access, data is not written to the local memory 14 even in the case of a write access, for example. In order to realize such dummy access, for example, one bit in the local bus 12 is defined as a dummy access bit, and when the dummy access bit is activated by the local bus controller 13, a write cycle is started. However, a logic that does not write data to the local memory 14 in the cycle may be provided in the local memory 14.

  The local bus controller 23 and the local memory 24 are configured in the same manner as the local bus controller 13 and the local memory 14.

  Next, the operation of the above configuration will be described.

  FIG. 3 shows the flow of routing processing by the system bus controller 33. FIG. 5 shows a flow of routing processing by the local bus controller 13.

  The high reliability mode is generally realized by operating the CPUs 11 and 21 in a completely synchronized state. However, in order to avoid a factor that causes an error in a plurality of CPUs at the same time, it is also possible to employ a system in which each CPU is operated while being shifted by a fixed clock cycle. In the following, in order to simplify the description, the description will be given assuming that each CPU operates in a completely synchronized state.

  First, the system operation when the CPUs 11 and 21 are operating in the high reliability mode will be described.

  The peripheral function unit 41 is directed to either the area a1 accessible only to the local memory 14 with respect to the system bus 32, the area a2 accessible only to the local memory 24, or the area a3 accessible to both the local memories 14 and 24. When the access is issued, the system bus controller 33 routes the access to both the local buses 12 and 22 (302, 303, 304, and 306). In the case of access to another area, it is routed to another area (305, 307). When the local bus controller 13 accesses the area a1 accessible only to the local memory 14 and the area a3 accessible to both the local memories 14 and 24, the local bus controller 13 routes the access to the local memory 14 as it is (501, 502). 504) is replaced with dummy access to the local memory 14 when the area a2 accessible only to the local memory 24 is accessed (505). Similarly, when the local bus controller 23 accesses the area a2 accessible only to the local memory 24 and the area a3 accessible to both the local memories 14 and 24, the access is directly routed to the local memory 24. If there is an access to the area a1 accessible only to the local memory 14, it is replaced with a dummy access to the local memory 24. When the access to the area a3 accessible to both the local memories 14 and 24 is a read, in the system bus interface 31, whether the read data from the local memory 14 and the read data from the local memory 24 have the same value and It is compared whether each output timing is the same. In this comparison, when the values of the read data are not the same or when the output timing is not the same, the read data is not used for the processing in the peripheral function unit 41. Thereby, high reliability is maintained.

  Next, the operation when the CPUs 11 and 21 are operating in the high performance mode will be described.

  When the peripheral function unit 41 issues access to the system bus 32 toward the area a1 accessible only to the local memory 14, the system bus controller 33 routes access only to the local bus 12 (308, 312). ). Similarly, when the peripheral function unit 41 issues access to the system bus 32 toward the area a2 accessible only to the local memory 24, the system bus controller 33 routes access only to the local bus 22 ( 309, 313). When the peripheral function unit 41 issues access to the system bus 32 toward the area a3 accessible to both the local memories 14 and 24, the system bus controller 33 routes access to both the local buses 12 and 22. (310, 314). In the case of access to another area, routing is performed to the other area (311 and 315).

  When the access to the area a3 accessible to both the local memories 14 and 24 is a read, the output timing of the read data from the local memory 14 and the read data from the local memory 24 differs depending on the usage status of the local buses 12 and 23. Sometimes. For this reason, output to the system bus 32 is suppressed until both read data are prepared in the system bus interface 31, and after both read data are prepared, the values of the read data are compared and output to the system bus 32. .

  The system bus interface 31 can be provided with hardware for executing processing as shown in FIG. By executing the processing as shown in FIG. 19 with hardware, processing can be performed at high speed.

  First, in the system bus controller 33, it is determined whether or not the access from the peripheral function unit 41 is an access to both the local memories 14 and 24 (1901). When the access from the peripheral function unit 41 is access to both the local memories 14 and 24, it is determined whether or not the memory is being read (1902). When the memory is being read, it is determined whether or not there is a read result from both the local memories 14 and 24 (1903). If there is a read result from both the local memories 14, 24, it is determined whether or not the read results from both the local memories 14, 24 are equal to each other (1904). When the read results from both the local memories 14 and 24 are equal to each other, the read data is output by being routed to the read request source (peripheral function unit 41) (1905). If the read results from both the local memories 14, 24 are not equal to each other, an error signal is transmitted to the read request source (peripheral function unit 41) (1906). As a result, undesired read data can be avoided from being used at the read request source (peripheral function unit 41), thereby maintaining high reliability.

  If the access from the peripheral function unit 41 is not the access to both the local memories 14 and 24, it is determined whether or not the memory is being read (1907). If the memory is being read, the system bus controller 33 determines whether there is a memory read result, and if there is a memory read result, it is routed to the read request source (peripheral function unit 41). As a result, data is output (1909).

  As described above, according to the first embodiment, the system bus controller 33 includes the definition information (a1, a2, a3) about the first local memory and the second local memory in the address space of the information processing apparatus 100, and Based on the operation mode of the CPU, routing control from the system bus 32 to the local buses 12 and 22 corresponding to the communication request from the peripheral function unit 41 is performed. The local bus controller 13 performs routing control from the first local bus to the first local memory corresponding to the communication request from the peripheral function unit 41 based on the definition information (a1, a2, a3). Do. Further, the local bus controller 23 performs routing control from the local bus 22 to the local memory 24 corresponding to the communication request from the peripheral function unit 41 based on the definition information (a1, a2, a3). By performing such control, when access from the peripheral function unit 41 to the local memories 14 and 24 occurs, whether to access a plurality of local memories 14 and 24, or a part of the local memories 14 or 24. Therefore, it is possible to appropriately control whether to access only to the application system, so that the application system in which the operation mode of the CPU is switched during the operation of the system can be operated normally.

<Embodiment 2>
In the system having the same configuration of FIG. 1 as in the first embodiment, an accessible area a1 and an accessible area a2 are defined in the address space of the information processing apparatus 100, as shown in FIG. The At this time, as shown in FIG. 8, the identifiers iden are defined in the local buses 12 and 22 and the system bus 32 together with the address signal add, data data, communication request signal req, communication permission signal gra, and write signal write. The The address signal add and the data data have a 32-bit configuration, and the others have a 1-bit configuration. The identifier iden indicates whether or not the access from the peripheral function unit 41 is an access to both the local memories 14 and 24. The logical value of the identifier iden is determined by the peripheral function unit 41. For example, when the identifier iden is a logical value “1”, it indicates that the access from the peripheral function unit 41 is an access to both the local memories 14 and 24, and when the identifier iden is a logical value “0”, This indicates that the access from the peripheral function unit 41 is not an access to both the local memories 14 and 24.

  The system bus controller 33 includes a decoder 1001 as shown in FIG. The decoder 1001 decodes a CPU mode signal, a communication request signal req, an address signal add, and an identifier iden. In the system bus controller 33, routing control is performed based on the decoding result. The decoder 1001 has decoding logic so that the processing shown in FIG. 9 is performed by hardware, for example.

  The local bus controller 13 includes a decoder 1201 as shown in FIG. The decoder 1201 decodes the request signal req, the address signal add, and the identifier iden. In the local bus controller 13, routing control is performed based on the decoding result of the decoder 1201. The decoder 1201 has a decoding logic so that the processing shown in the flowchart of FIG. 11 is performed by hardware, for example. The local bus controller 23 is configured in the same manner as the local bus controller 13.

  FIG. 9 shows the flow of routing processing by the system bus controller 33. FIG. 11 shows the flow of routing processing by the local bus controller 13.

  First, the operation of the system when the CPUs 11 and 21 are operating in the high reliability mode will be described. When the peripheral function unit 41 issues an access to either the area a1 accessible to the local memory 14 or the area a2 accessible to the local memory 24 with respect to the system bus 32, the identifier value in the access is set. Regardless, the system bus controller 33 routes access to both the local buses 12 and 22 (902, 903, 905). In the case of access to another area, it is routed to another area (904, 906). When the local bus controller 13 accesses the area a1 accessible only to the local memory 14, the local bus controller 13 routes the access to the local memory 14 as it is (1101, 1104). When there is access to the area a2 accessible to the local memory 24 and the identifier indicates access to both the local memories 14 and 24, the address is changed to that indicating the local memory 14 and routing to the local memory 14 is performed. (1102, 1103, 1104). However, when the area a2 accessible to the local memory 24 is accessed and the identifier does not indicate access to both the local memories 14 and 24, it is replaced with dummy access to the local memory 14 (1102, 1103, 1105). Similarly, the local bus controller 23 routes the access to the local memory 24 as it is when the area a <b> 2 accessible only to the local memory 24 is accessed. When there is access to the area a1 accessible to the local memory 14 and the identifier indicates access to both the local memories 14 and 24, the address is changed to that indicating the local memory 24, and routing to the local memory 24 is performed. . However, when the area a 1 accessible to the local memory 14 is accessed and the identifier does not indicate access to both the local memories 14 and 24, the local memory 24 is replaced with a dummy access. When the access to the area a1 accessible to the local memory 14 or the area a2 accessible to the local memory 24 is a read and the identifier indicates the access to both the local memories 14 and 24, the system bus interface 31 It is compared whether the value of the read data from the memory 14 and the value of the read data from the local memory 24 are the same and whether the output timings are the same. In other words, the output timing of the read data from the local memory 14 and the read data from the local memory 24 may differ depending on the usage status of the local buses 12 and 23. After the read data is prepared, the read data values are compared and output to the system bus 32. The specific processing here is as shown in FIG. 19 as in the case of the first embodiment. If there is an access to another area, it is routed to another area (904, 906).

  Next, the operation of the system when the CPUs 11 and 21 are operating in the high performance mode will be described. When the peripheral function unit 41 issues access to the system bus 32 toward the area a1 accessible to the local memory 14 with the identifier as a value that does not indicate access to both the local memories 14 and 24, the system bus controller 33 Access is routed only to the local bus 12 (907, 911, 912). Similarly, when the peripheral function unit 41 issues access to the system bus 32 toward the area a2 accessible to the local memory 24 with the identifier not indicating the access to both the local memories 14 and 24, the system bus similarly The controller 33 routes access only to the local bus 22 (908, 909, 914). A value indicating that the peripheral function unit 41 has access to both the local memories 14 and 24 toward the area a1 accessible to the local memory 14 with respect to the system bus 32 and the area a2 accessible to the local memory 24 When the access is issued, the access is routed to both the local buses 12 and 22 (911, 909, 913). When the identifier indicates access to both the local memories 14 and 24 in the read access to the area a1 accessible to the local memory 14 or the area a2 accessible to the local memory 24, the read data from the local memory 14 and the local memory The output timing of the read data from 24 may differ depending on the usage status of the local buses 12 and 23. For this reason, output to the system bus 32 is suppressed until both read data are prepared in the system bus interface 31, and after both read data are prepared, the values of the read data are compared and output to the system bus 32. The specific processing here is as shown in FIG. 19 as in the case of the first embodiment. When there is an access to another area, routing is performed to the other area (910, 915).

<Embodiment 3>
In the system having the same configuration as that of the first embodiment shown in FIG. 1, an area a <b> 3 that can access the local memories 14 and 24 is defined in the address space of the information processing apparatus 100 as shown in FIG. 13. At this time, a 2-bit identifier iden is defined in the local buses 12 and 22 and the system bus 32 as shown in FIG. With this 2-bit identifier iden, it is possible to identify whether the access from the peripheral function unit 41 is access to the local memory 14, access to the local memory 24, or access to both the local memories 14 and 24. For example, when the identifier iden of the 2-bit configuration is the logical value “10”, it indicates that the access from the peripheral function unit 41 is the access to the local memory 14, and the identifier iden of the 2-bit configuration is the logical value “01”. "" Indicates that the access from the peripheral function unit 41 is an access to the local memory 24. Further, when the identifier iden having a 2-bit configuration is the logical value “11”, it indicates that the access from the peripheral function unit 41 is the access to the local memories 14 and 24. The logical value of the identifier iden is determined by the peripheral function unit 41.

  The system bus controller 33 includes a decoder 1601 as shown in FIG. The decoder 1601 decodes a CPU mode signal, a communication request signal req, an address signal add, and an identifier iden. In the system bus controller 33, routing control is performed based on the decoding result. The decoder 1001 has a decoding logic so that, for example, the processing shown in FIG. 15 is performed by hardware.

  The local bus controller 13 includes a decoder 1801 as shown in FIG. The decoder 1801 decodes the request signal req, the address signal add, and the identifier iden. In the local bus controller 13, routing control is performed based on the decoding result of the decoder 1801. The decoder 1801 has a decoding logic so that the processing shown in the flowchart of FIG. 17 is performed by hardware. The local bus controller 23 is configured in the same manner as the local bus controller 13.

  FIG. 15 shows the flow of routing processing by the system bus controller 33 included in the information processing apparatus. FIG. 17 shows the flow of routing processing by the local bus controller 13.

  First, the operation of the system when the CPUs 11 and 21 are operating in the high reliability mode will be described. When the peripheral function unit 41 issues an access to the system bus 32 toward the area a3 accessible to the local memories 14 and 24, the system bus controller 33 does not depend on the value of the identifier iden in the access. Access is routed to both 12 and 22 (1502, 1504). The local bus controller 13 routes the access to the local memory 14 as it is when the identifier iden indicates access to the local memory 14 and whether to access both the local memories 14 and 24 (1702, 1703). 1704), if the identifier iden indicates access to the local memory 24, it is replaced with dummy access to the local memory 14 (1705). Similarly, the local bus controller 23 routes the access as it is to the local memory 24 when the identifier iden indicates access to the local memory 24 and when the identifier iden indicates access to both the local memories 14 and 24. When iden indicates access to the local memory 14, it is replaced with dummy access to the local memory 24. When access to the area a3 accessible to the local memories 14 and 24 is read and the identifier iden indicates access to both the local memories 14 and 24, the system bus interface 31 reads the data read from the local memory 14 and It is compared whether the values of the read data from the local memory 24 are the same and whether the output timings are the same. In other words, since the output timing of the read data from the local memory 14 and the read data from the local memory 24 may differ depending on the usage status of the local buses 12 and 22, the system bus 32 until both read data are collected in the system bus interface 31. After the read data is prepared, the read data values are compared and output to the system bus 32. The specific processing here is as shown in FIG. 19 as in the case of the first embodiment. If there is an access to another area, it is routed to another area (1503, 1505).

  Next, the operation of the system when the CPUs 11 and 21 are operating in the high performance mode will be described. When the peripheral function unit 41 issues an access to the system bus 32 toward the area a3 accessible to the local memories 14 and 24, the system bus controller 33 does not depend on the value of the identifier iden in the access. Access is routed to both 12, 22 (1506, 1507, 1510). The local bus controller 13 routes the access as it is to the local memory 14 when the identifier iden indicates access to the local memory 14 and when the identifier iden indicates access to both the local memories 14 and 24. When the access to the local memory 24 is indicated, the access to the local memory 14 is not generated (1507, 1511). Similarly, the local bus controller 23 routes the access as it is to the local memory 24 when the identifier iden indicates access to the local memory 24 and when the identifier iden indicates access to both the local memories 14 and 24. When iden indicates access to the local memory 14, no access is made to the local memory 24 (1507, 1509). When the identifier iden indicates access to both the local memories 14 and 24 in the read access to the area a3 accessible to the local memories 14 and 24, the read data from the local memory 14 and the output of the read data from the local memory 24 are output. The timing may vary depending on the usage status of the local buses 12 and 23. For this reason, output to the system bus 32 is suppressed until both read data are prepared in the system bus interface 31, and after both read data are prepared, the values of the read data are compared and output to the system bus 32. The specific processing here is as shown in FIG. 19 as in the case of the first embodiment. If there is an access to another area, it is routed to another area (1508, 1512).

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the above example, the CPU having the CPUs 11 and 21 has been described. However, the number of CPUs included in the information processing apparatus 100 may be plural, and is not limited to two.

11,21 CPU
12, 22 Local bus 13, 23 Local bus controller 14, 24 Local memory 31 System bus interface 32 System bus 33 System bus controller 41 Peripheral function unit 401, 601, 1001, 1201, 1601, 1801 Decoder

Claims (6)

A first CPU;
A first local bus coupled to the first CPU;
A first local memory coupled to the first local bus;
A second CPU;
A second local bus coupled to the second CPU;
A second local memory coupled to the second local bus;
A system bus connectable to the first local memory and the second local memory;
A peripheral function unit coupled to the system bus,
Information processing having a high-reliability mode in which the first CPU and the second CPU execute the same program as the operation mode of the CPU, and a high-performance mode in which the first CPU and the second CPU can execute different programs. A device,
The system bus corresponding to a communication request from the peripheral function unit based on definition information about the first local memory and the second local memory in the address space of the information processing apparatus and an operation mode of the CPU A system bus controller capable of controlling routing from the first local bus to the second local bus;
A first local bus controller capable of controlling routing from the first local bus to the first local memory corresponding to a communication request from the peripheral function unit based on the definition information;
A second local bus controller capable of controlling routing from the second local bus to the second local memory corresponding to a communication request from the peripheral function unit based on the definition information. Information processing apparatus.   In response to read access from the peripheral function unit to both the first local memory and the second local memory, data output from the first local memory, data output from the second local memory, and The information processing apparatus according to claim 1, further comprising: a system bus interface capable of comparing the comparison results and outputting the comparison result to the peripheral function unit. When the first local bus controller accesses an area accessible to the second local memory in the high-reliability mode, the first local memory does not change the contents of the memory. Replaced with access,
When the second local bus controller accesses an area accessible to the first local memory in the high-reliability mode, the second local memory does not change the contents of the memory. The information processing apparatus according to claim 2, wherein the information processing apparatus is replaced with access. As the definition information, the address space in the information processing apparatus is accessed to an area accessible to the first local memory, an area accessible to the second local memory, and both the first local memory and the second local memory. Possible areas are defined,
The information processing apparatus according to claim 3, wherein the definition information is used in the routing control in the system bus controller, the first local bus controller, and the second local bus controller. As the definition information, an area accessible to the first local memory and an area accessible to the second local memory memory are defined in the address space in the information processing apparatus,
An identifier indicating whether the access is to both the first local memory and the second local memory is defined in the first local bus, the second local bus, and the system bus,
The information processing apparatus according to claim 3, wherein the definition information and the identifier are used in the routing control in the system bus controller, the first local bus controller, and the second local bus controller. As the definition information, an area accessible to both the first local memory and the second local memory is defined in the address space in the information processing apparatus,
An identifier that can identify whether the access is to the first local memory, the second local memory, or both the first local memory and the second local memory. Defined in the first local bus, the second local bus, and the system bus;
The information processing apparatus according to claim 3, wherein the definition information and the identifier are used in the routing control by the system bus controller, the first local bus controller, and the second local bus controller.

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