JP2011150619A - Electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a calculation amount to delete a writing stroke which intersects with a deletion stroke. <P>SOLUTION: The CPU 40 of electronic equipment 40 specifies coordinate data at a position within a unit area (A) among a series of positions constituting the writing stroke and also coordinate data at a position within a unit area (A) among a series of positions constituting the deletion stroke, among the coordinate data stored in a writing buffer WB concerning one unit area (A) among the unit areas A to which both the writing stroke and the deletion stroke enter, and then, determines by a round robin, the presence/absence of intersection of a line segment connecting the adjacent positions within the unit area (A) among a series of positions constituting the writing stroke with a line segment connecting the adjacent positions within the unit area (A) among a series of positions constituting the deletion stroke by the use of the specified coordinate data. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic device capable of handwriting input.

  2. Description of the Related Art Conventionally, electronic devices that can input characters and figures by handwriting by indicating a position on a screen with an indicator such as a pen or a finger are known. In such an electronic device, the locus (stroke) of the position designated by the indicator is input. For example, when writing the letter “T” on the image displayed on the screen, the user inputs two writing strokes of a vertical bar and a horizontal bar with an instruction, whereby “T” is written on the image. .

  As one type of such an electronic device, one that can erase a writing stroke that intersects the erasing stroke by inputting the erasing stroke is known. As such an electronic device, as described in paragraph 0005 of Patent Document 1, a line segment connecting two adjacent points in a series of positions (coordinate points) constituting an erasing stroke and a writing stroke are constituted. In general, it is determined whether or not to erase the writing stroke by determining the intersection with a line segment connecting two adjacent points in a series of positions to be erased.

JP 2000-259335 A

However, the amount of calculation for determining the intersection is enormous, and increases as the sampling period for position detection is shorter, and increases as the screen is wider.
Therefore, an object of the present invention is to provide an electronic apparatus that can reduce the amount of calculation for erasing a writing stroke that intersects an erasing stroke.

An electronic apparatus according to the present invention includes a screen that is divided into a plurality of unit areas and displays an image, a tablet that repeatedly detects a designated position in the screen and outputs coordinate data, and a position in the screen Of the coordinate data output from the tablet when the trajectory composed of a series of positions detected from the start to the end of the instruction is a stroke and the stroke written in the image is a writing stroke. A writing buffer for sequentially storing coordinate data of positions constituting the writing stroke, and when the stroke for erasing the writing stroke is an erasing stroke, among the coordinate data output from the tablet, An erasure buffer for sequentially storing coordinate data of positions constituting the erasure stroke, and a position stored in the write buffer. Among the data, an image generation unit that generates the image in which the writing stroke that has not been erased is written using coordinate data of a series of positions that constitute the writing stroke that has not been erased, and the series of data When the coordinate data of the position is stored in the erasure buffer, the writing stroke that enters at least one unit area among the unit areas that the erasing stroke enters among the writing strokes that are not erased. In each of the unit areas in which the writing stroke and the erasing stroke enter together for each of the candidate specifying unit specified as the target stroke and the writing stroke specified as the target stroke, the writing stroke One of the line segments that connect the series of positions adjacent to each other, and the erasing stroke A partial determination process is performed to determine whether or not any of the line segments connecting the series of constituent positions adjacent to each other intersects, and the writing stroke in which the result of the partial determination process is affirmative is erased A partial determination erasure unit, wherein the partial determination erasure unit is configured to include a part of the unit area in which the write stroke and the erasure stroke enter together in the partial determination process related to one write stroke. For one unit area, out of the coordinate data stored in the write buffer, the coordinate data of the position in the unit area of the series of positions constituting the write stroke and the erase stroke are configured. The coordinate data of the position in the unit area among the series of positions to be identified, and using the identified coordinate data, the coordinate data in the series of positions constituting the writing stroke A round robin is used to determine whether or not there is an intersection between a line segment that connects positions in the unit area adjacent to each other, and a line segment that connects positions in the unit area adjacent to each other among the series of positions constituting the erasing stroke. It is characterized by that.
Generally, when erasing a writing stroke that intersects with an erasing stroke, whether or not to erase a certain writing stroke is determined by determining all the lines constituting the erasing stroke and all the lines constituting the writing stroke. This is done by comparing the line segment with the brute force. On the other hand, in the present invention, the screen is divided into a plurality of unit areas, and the line segment in the unit area among the line segments constituting the writing stroke and the unit among the line segments constituting the erasing stroke. The line segments in the area are compared brute force, and if any of the former line segment and any of the latter line segment intersect, the writing stroke is erased. Therefore, according to the present invention, it is possible to reduce the amount of calculation for erasing the writing stroke that intersects the erasing stroke.

In this electronic apparatus, when a set of one or more writing strokes is a session, the writing stroke belongs to one of the one or more sessions, and the candidate specifying unit circumscribes the session. When the coordinate data of the series of positions is stored in the erasure buffer, the area enclosed by the rectangles to be enclosed is surrounded by a rectangle circumscribing the erasure stroke composed of the series of positions. A session specifying unit that specifies the session region that overlaps with a region, specifies the writing stroke belonging to the session related to the specified session region, and the erasure among the writing strokes specified by the session specifying unit The writing straw that enters at least one of the unit areas in which a stroke enters. It is preferable to provide a target stroke identification unit that identifies as the target stroke.
According to this electronic apparatus, there is no unit area where both the erase stroke and the write stroke enter the write stroke belonging to the session related to the session area that does not overlap the area surrounded by the rectangle circumscribing the erase stroke. Can be considered. This contributes to further reduction in the amount of computation. Of course, the session specifying unit and the target stroke specifying unit may not be provided, and the unit area into which the writing stroke enters may be specified among all the writing strokes in the unit area into which the erasing stroke enters. Note that each session includes only a series of writing strokes that satisfy the conditions relating to the session. For example, a series of writing strokes in which the period from the end to the start of the position instruction in the screen is shorter than a certain reference time may belong to the same session.

In this electronic apparatus, for each of the writing strokes not specified as the target stroke among the writing strokes specified by the session specifying unit, a series of positions constituting the writing stroke are adjacent to each other. All determination processing is performed to determine whether any of the connecting line segments and any of the line segments connecting the series of positions constituting the erasing stroke adjacent to each other, and the result of the all determination processing is An all-determination erasing unit that erases the affirmative writing stroke, and the all-determination erasing unit determines the series of positions constituting the writing stroke in the all-determination process relating to one writing stroke. Whether or not there is a crossover between the line segment connecting adjacent lines and the line segment connecting the series of positions constituting the erasing stroke adjacent to each other It may be.
According to this electronic apparatus, it is possible to determine whether or not a writing stroke that does not enter any of the unit areas to which the erasing stroke enters can determine whether or not it intersects with the erasing stroke, thereby improving the erasing accuracy. Of course, it is also possible not to provide a complete determination erasure unit and not to erase a writing stroke that does not enter any unit area into which the erasing stroke enters. In this case, the calculation amount is reduced.

In each of the electronic devices described above, the all determination erasure unit may execute the all determination processing for each of the writing strokes for which the determination result of the partial determination processing is not positive.
According to this electronic device, the erasure accuracy is improved. Of course, the complete determination erasure unit may not execute the complete determination process for any of the writing strokes for which the determination result of the partial determination process is not positive. In other words, the writing stroke for which the determination result of the partial determination process is not affirmative may not be erased. In this case, the calculation amount is reduced.

It is a top view which shows the external appearance of the electronic device 100 which concerns on one Embodiment of this invention. 6 is a plan view showing an operation (erase mode) of electronic device 100. FIG. 2 is a block diagram showing an electrical configuration of electronic device 100. FIG. 3 is a diagram schematically showing a relationship between a screen 11 of an electronic device 100 and a unit area A. FIG. 4 is a diagram schematically showing an example of contents of write data WD and erase data ED stored in a RAM 60 of the electronic device 100. FIG. It is a figure which shows typically the update example of the write data WD and the erasure | elimination data ED. It is a figure which shows typically the update example of the write data WD and the erasure | elimination data ED. It is a figure which shows typically the update example of the write data WD and the erasure | elimination data ED. It is a figure which shows typically the update example of the write data WD and the erasure | elimination data ED. It is a figure which shows the flow of the erasure | elimination process which the electronic device 100 performs. It is a figure which shows the flow of the erasure | elimination process which the electronic device 100 performs. It is a figure which shows the flow of the erasure | elimination process which the electronic device 100 performs. It is a figure which shows an example of the state of the electronic device 100 typically.

<1. Configuration>
FIG. 1 is a plan view showing an appearance of an electronic device 100 according to an embodiment of the present invention. As shown in this figure, the electronic device 100 includes a screen 11 on which an image is displayed, and is operated by a pen 200 that indicates a position in the screen 11. The position instruction by the pen 200 is started by a pen-down operation for bringing the pen 200 into contact with or close to the screen 11, and is ended by a pen-up operation for moving the pen 200 away from the screen 11.

  The electronic device 100 inputs the locus of the pen 200 from the pen-down operation to the pen-up operation. The handling of the input locus differs depending on the operation mode (write mode / erase mode) of the electronic device 100. In the writing mode, as shown in FIG. 1, an image in which the input locus is written is displayed on the screen 11. In the erasing mode, as shown in FIG. 2, an image from which a trajectory that intersects the input trajectory is erased is displayed on the screen 11. In addition, although the locus | trajectory input in deletion mode is shown with the broken line in each figure, it is not actually displayed.

  As shown in FIG. 1, a switching button 21 for switching the operation mode is displayed on the screen 11. The user of the electronic device 100 can switch the operation mode of the electronic device 100 by operating the pen 200 and pressing the switching button 21. The content of the operation of the pen 200 for pressing the switching button 21 is arbitrary. For example, the switching button 21 may be pressed by a pen-down operation on the switching button 21, or the switching button 21 may be pressed by a pen-up operation on the switching button 21.

  FIG. 3 is a block diagram illustrating an electrical configuration of the electronic device 100. As shown in this figure, the electronic device 100 includes a display unit 10, a tablet 30, a CPU (Central Processing Unit) 40, a ROM 50 (Read Only Memory), a RAM (Random Access Memory) 60, and a VRAM (Video RAM) 70 and storage 80.

  The display unit 10 is, for example, an LCD (Liquid Crystal Display), has a screen 11, and displays an image indicated by image data stored in the VRAM 70 on the screen 11. The tablet 30 repeatedly detects the position indicated by the pen 200 among the positions in the screen 11 and sequentially outputs coordinate data indicating the coordinates of the detected position. These coordinate data are supplied to the CPU 40.

  The storage 80 is a rewritable nonvolatile storage device such as a hard disk, and stores various data. The RAM 60 functions as a work memory for the CPU 40 and stores write data WD and erase data ED described later. The ROM 50 stores a program executed by the CPU 40. The CPU 40 executes various processes by executing the above program using the RAM 60 as a work memory.

  The processing executed by the CPU 40 includes processing for storing image data in the VRAM 70, processing for switching the operation mode based on the coordinate data from the tablet 30, and writing data WD and erasing data ED based on the coordinate data from the tablet 30. For example, a process for updating data, a process for reading / writing data from / to the storage 80, and the like.

Here, “stroke”, “session”, and “unit area” will be described.
The “stroke” is a trajectory of the pen 200 from the pen-down operation to the pen-up operation. Specifically, the “stroke” is a trajectory configured by a series of positions detected by the tablet 30 from the pen-down operation to the pen-up operation. Of the strokes, a stroke written in the image displayed on the screen 11 is a “writing stroke”, and a stroke for erasing the writing stroke is an “erasing stroke”. The writing stroke is managed using a stroke number that individually identifies a plurality of writing strokes.

  A “session” is a set of one or more writing strokes, and the writing stroke belongs to one of the one or more sessions. Each session includes only a series of writing strokes that satisfy the conditions relating to the session. In this embodiment, in principle, a series of writing strokes in which a period from a pen-up operation to a pen-down operation is shorter than a predetermined reference time belongs to the same session.

  For example, in FIG. 1, all writing strokes constituting the first “This is a pen.” Are included in one session, and the next “This is a pen. This is a pen.” All writing strokes constituting "" are included in another session, and all writing strokes constituting the last "This is a pen. Thi" are included in another session.

  However, in this embodiment, when the operation mode is switched between the pen-up operation of a certain writing stroke and the pen-down operation of the next writing stroke, the period from the pen-up operation to the pen-down operation is Even if it is shorter than the reference time, these two writing strokes belong to different sessions. The sessions are managed using session numbers that individually identify a plurality of sessions.

  The “unit area” is an area in the screen 11. The relationship between the screen 11 and the unit area A is as shown in FIG. In this figure, a part of the screen 11 on the left side of FIG. 2 is shown enlarged. As shown in FIG. 4, the CPU 40 manages the screen 11 by dividing it into unit areas A of 54 rows and 42 columns. The unit area A is managed using a unit area number that individually identifies the unit area A of 54 rows and 42 columns. For example, the unit region number of the unit region A in the second row and first column is “43”. Hereafter, k is a natural number, and the unit area A whose unit area number is k is referred to as “unit area Ak”. Of course, the number of rows and the number of columns in the unit area A is not limited to 54 rows and 42 columns.

  FIG. 5 is a diagram illustrating the contents of the write data WD and the erase data ED stored in the RAM 60, and corresponds to FIG. The write data WD is data related to the write stroke and session, and includes coordinate data c1, c2,..., Write stroke data WS1, WS2,.

  The coordinate data c1, c2,... Are coordinate data sequentially output from the tablet 30 in the writing mode, and are sequentially stored in the write buffer WB in the RAM 60. The write buffer WB is a storage area in which a plurality of unit storage areas for storing coordinate data one by one are connected, and addresses “w1”, “w2”,... Are assigned to these unit storage areas in order from the top. Has been. That is, the coordinate data ck output k-th from the tablet 30 in the writing mode is stored in the unit storage area whose address is “wk”.

  The writing stroke data WSk is a series of positions constituting the writing stroke having the stroke number “k” (the kth input stroke in the writing mode) among the coordinate data stored in the writing buffer WB. Specify coordinate data. For this specification, an address in the write buffer WB is used. For example, the write stroke data WS1 includes the start address “w1” of the storage position of the coordinate data c1 to c51 of a series of positions constituting the write stroke (the horizontal bar “T” in FIG. 4) having the stroke number “1”. "And the end address" w51 ".

  The writing stroke data WSk includes each of the unit areas A including one or more positions in a series of positions constituting the writing stroke whose stroke number is “k”, and the writing stroke for the unit area A. Is associated with the entry address. The entry address of a certain writing stroke with respect to a certain unit area A is the address of the storage position of the coordinate data output from the tablet 30 immediately after the writing stroke has entered the unit area A.

  For example, unit areas A including one or more positions in a series of positions constituting a writing stroke having a stroke number “1” (horizontal bar “T” in FIG. 4) are unit areas A130, A131, and A132. Yes, since the entry addresses of the writing strokes for these three unit areas A are “w1”, “w18”, and “w37”, the writing stroke data WS1 includes unit area numbers “130”, “131”, “131” is associated with the entry addresses “w1”, “w18”, and “w37”, respectively.

  The session data SSk is data indicating a writing stroke included in the session having the session number k, and associates the session number “k” with the stroke numbers of all writing strokes included in the session. For example, the session data SS1 indicates all the writing strokes included in the session having the session number “1” (the first “This is a pen.” In FIG. 1), and the session number “1” The stroke numbers “1”, “2”,..., “14” of all writing strokes included in the session are associated with each other.

  The erase data ED is data relating to the erase stroke, and includes coordinate data d1, d2,... And erase stroke data ES. The coordinate data d1, d2,... Are coordinate data sequentially output from the tablet 30 in the erase mode, and are sequentially stored in the erase buffer EB in the RAM 60. The erasing buffer EB is a storage area in which a plurality of unit storage areas for storing coordinate data one by one are connected. Addresses “e1”, “e2”,... Are assigned to these unit storage areas in order from the top. ing. However, the storage position of the coordinate data in the erase buffer EB is initialized for each erase stroke. That is, the storage of the coordinate data in the erase buffer EB is overwritten for each erase stroke.

  The erase stroke data ES specifies coordinate data of a series of positions constituting the latest erase stroke (the last input stroke in the current erase mode) among the coordinate data stored in the erase buffer EB. For this specification, an address in the erase buffer EB is used. Here, the broken line in FIG. 4 is the latest erase stroke, and the erase stroke data ES indicates the end address “e22” of the storage position of the coordinate data d1 to d22 of a series of positions constituting the erase stroke.

  Further, the erase stroke data ES associates each unit area A including one or more positions among a series of positions constituting the latest erase stroke with the entry address of the erase stroke for the unit area A. The erase stroke entry address for a certain unit area A is the address of the storage position of the coordinate data output from the tablet 30 immediately after the erase stroke enters the unit area A.

  Here, since the broken line in FIG. 4 is the latest erase stroke, the unit areas A including one or more positions in the series of positions constituting the latest erase stroke are the unit areas A174 and A132. The entry addresses of the erase strokes for these two unit areas A are “e1” and “e14”. Therefore, the erase stroke data ES associates the unit area numbers “174” and “132” with the entry addresses “e1” and “e14”, respectively.

  Note that the CPU 40 uses the coordinate data of a series of positions constituting the writing stroke not erased among the coordinate data stored in the writing buffer WB, and the image in which the writing stroke not erased is written. The image data of the generated image is written in the VRAM 70. Further, the CPU 40 can store the data on the RAM 60 in the storage 80 or read the data stored in the storage 80 in accordance with a user instruction.

<2. Operation>
As described above, the CPU 40 updates the write data WD and the erase data ED based on the coordinate data from the tablet 30. The state of this update will be described by taking as an example a case where a horizontal bar and a vertical bar of “T” are written in an image in which no writing stroke is written, and then the horizontal bar of “T” is deleted. However, the initial operation mode is the write mode.

  First, the user operates the pen 200 so as to input a horizontal bar of “T” (writing stroke WST1). Specifically, as shown in FIG. 6, the pen-down operation is performed in the unit area A130, the pen 200 is moved so as to pass through the unit area A131, and the pen-up operation is performed in the unit area A132.

  At this time, the CPU 40 sequentially stores the coordinate data c1 to c51 sequentially supplied from the tablet 30 in the write buffer WB. CPU 40 also updates write data WD to associate session number “1” of the current session with stroke number “1” of write stroke WST1.

Further, the CPU 40 updates the write data WD, so that the write stroke WST1 is supplied immediately before the pen-up operation with the address of the storage position of the coordinate data supplied immediately after the pen-down operation as the head address. The address of the coordinate data storage location is the end address.
Further, every time coordinate data is supplied, the CPU 40 determines whether or not the writing stroke WST1 has entered the unit area A, that is, whether or not the pen 200 has entered the unit area A, and the result of this determination Is affirmative, the write data WD is updated to associate the unit area number of the unit area A with the address (entrance address) of the storage position of the coordinate data for the write stroke WST1. The result of this determination is also affirmative when coordinate data is supplied immediately after the pen-down operation.
That is, with respect to the writing stroke WST1, the CPU 40 uses “w1” as the head address, “w51” as the tail address, unit area numbers “130”, “131”, “132” and the entry addresses “w1”, “w18”. ”And“ w37 ”are written in the RAM 60.

  Next, the user operates the pen 200 so as to input a vertical bar of “T” (writing stroke WST2). Specifically, as shown in FIG. 7, a pen-down operation is performed in the unit area A131, the pen 200 is moved so as to pass through the unit area A173, and a pen-up operation is performed in the unit area A215. However, the period from the pen-up operation of the “T” horizontal bar to the pen-down operation of the “T” vertical bar is shorter than the above-described reference time.

  At this time, the CPU 40 sequentially stores the coordinate data c52 to c91 sequentially supplied from the tablet 30 in the write buffer WB. CPU 40 also updates write data WD to associate session number “1” of the current session with stroke number “2” of write stroke WST1. Further, for the writing stroke WST2, the CPU 40 sets “w52” as a head address, “w91” as a tail address, unit area numbers “132”, “173”, “215” and entry addresses “w52”, “w68”. ”And“ w86 ”are written in the RAM 60.

  Next, the user operates the switching button 21 in FIG. 1 to switch the operation mode of the electronic device 100 from the writing mode to the erasing mode. As a result, an operation signal to that effect is supplied to the CPU 40. When the CPU 40 receives the operation signal, the CPU 40 updates the write data WD so that the session number “1” is associated with the stroke numbers “1” and “2” as shown in FIG. The data is SS1.

  Next, the user operates the pen 200 so as to input an erasing stroke EST that intersects the writing stroke WST1. Specifically, as shown in FIG. 8, a pen-down operation is performed in the unit area A174, and a pen-up operation is performed in the unit area A132. At this time, the CPU 40 sequentially stores the coordinate data d1 to c22 sequentially supplied from the tablet 30 in the erasure buffer EB.

Further, the CPU 40 updates the erase data ED so that the address of the storage position of the coordinate data supplied immediately before the pen-up operation is set as the end address for the erase stroke EST.
Further, every time the coordinate data is supplied, the CPU 40 determines whether or not the erase stroke EST has entered the unit area A, that is, whether or not the pen 200 has entered the unit area A, and the result of this determination is If the determination is affirmative, the erase data ED is updated to associate the unit area number of the unit area A with the address (entrance address) of the storage position of the coordinate data for the erase stroke EST. The result of this determination is also affirmative when coordinate data is supplied immediately after the pen-down operation.
That is, for the erase stroke EST, the CPU 40 writes “e22” as the end address, and writes the erase stroke data ES that associates the unit area numbers “174” and “132” with the entry addresses “e1” and “e14” in the RAM 60. .

  Then, the CPU 40 performs an erasing process for erasing the writing stroke WST1 that intersects the erasing stroke EST. By this erasure process, the write data WD and the erasure data ED are updated as shown in FIG. Specifically, the session data SS1 is data that associates the session number “1” with the stroke number “1”, and the write stroke data WS1 and the erase stroke data ES are deleted. That is, write stroke WST1 is erased.

<3. Erase process>
Hereinafter, the contents of the erasure process will be described with reference to FIGS. FIG. 10 to FIG. 12 are diagrams showing the flow of the erasing process, and they are connected at connection points assigned the same numbers to form one flowchart. FIG. 13 is a diagram schematically illustrating an example of the state of the electronic device 100. In the following description, the description will be basically made generally with reference to FIGS. 10 to 12 and specifically described with reference to FIG. 13 as appropriate.

  As shown in FIG. 10, in the erasing process, the CPU 40 first determines whether or not an erasing stroke has been input (S1). If the result of this determination is negative (NO), the process proceeds to step S1. return. When the erase stroke is input and the result of the determination in step S1 is affirmative (YES), the CPU 40 refers to the erase data ED and specifies a rectangular area of the erase stroke (S2). The rectangular area of the erasing stroke is an area surrounded by a rectangle circumscribing the erasing stroke, and in FIG. 13, is a rectangular area α surrounded by a rectangle circumscribing the erasing stroke EST.

  Next, the CPU 40 sets the first session as the target session (S3), and determines whether or not the session area of the target session and the rectangular area of the erase stroke overlap (S4). In the case of FIG. 13, the session with the session number “1” is the target session, and a region surrounded by a rectangle circumscribing the session is the session region β1, and whether the rectangular region α and the session region β1 overlap each other. Is determined. The session area β1 is specified with reference to the write data WD.

  If the rectangular area of the target session and the rectangular area of the erasing stroke overlap, and the result of the determination in step S3 is affirmative, the CPU 40 sets the first writing stroke belonging to the target session as the target stroke (S7), and the erasing stroke. The first unit area A is set as the target unit area (S8). In the case of FIG. 13, the writing stroke WST1 is the target stroke, and among the unit areas A into which the erasing stroke EST has entered, the unit area A215 into which the erasing stroke EST has entered first becomes the target unit area.

  Next, the CPU 40 refers to the write data WD and determines whether or not the target stroke has entered the target unit area (S9). If the result of this determination is negative, the CPU 40 determines whether or not there is a unit area A next to the erase stroke (S10). The unit area A next to the erasing stroke is a unit area A in which the erasing stroke enters the target unit area among the unit areas A of the erasing stroke. If the determination result of step S10 is affirmative, the CPU 40 sets the unit area A next to the erasing stroke as the target unit area (S11), and returns the process to step S9. That is, in the case of FIG. 13, the target unit areas change in the order of unit areas A215, A173, A174, and A132.

  If the target stroke has entered the target unit area and the result of determination in step S9 is affirmative, the CPU 40 refers to the write data WD and the erase data ED as shown in FIG. The erasure side start address is determined (S12). Specifically, the entry address associated with the target unit area for the target stroke is used as the write side start address, and the entry address associated with the target unit area for the erase stroke is used as the erase side start address. In the case of FIG. 13, the entry address “w52” associated with the unit area A132 for the write stroke WST1 is the write side start address, and the entry address “e31” associated with the unit area A132 for the erase stroke EST. Becomes the erase side start address.

  Next, the CPU 40 refers to the write data WD to determine whether or not there is a next unit area A of the target stroke (S13). If the result of this determination is affirmative, the target unit area for the target stroke is determined. The address immediately before the entry address associated with the next unit area A is set as the write end address (S14). If the result of this determination is negative, the end address of the target stroke is set as the write end address. (S15). In the case of FIG. 13, the result of the determination in step S13 is negative, and the end address “w51” of the write stroke WST1 becomes the write side end address.

  Next, the CPU 40 refers to the erasure data ED and determines whether or not there is a unit area A next to the erasure stroke (S16). If the result of this determination is affirmative, The address immediately before the entry address associated with the next unit area A is set as the erasure end address (S17). If the result of this determination is negative, the end address of the erase stroke is set as the erasure end address ( S18). In the case of FIG. 13, the result of the determination in step S16 is negative, and the end address “e44” of the erase stroke EST becomes the erase side end address.

  On the other hand, if the result of the determination in step S10 in FIG. 10 is negative, that is, if there is no unit area in which both the target stroke and the erasing stroke have entered, the CPU 40 writes the data as shown in FIG. The start side address and the erase side start address are determined (S19). Specifically, referring to the write data WD, the start address of the target stroke is set as the write side start address, and the start address (“e1”) of the erase stroke is set as the erase side start address. Next, the CPU 40 refers to the write data WD and the erase data ED, sets the end address of the target stroke as the write side end address, and sets the end address of the erase stroke as the erase side end address (S20).

  When the write side start address, write side end address, erase side start address and erase side end address are determined, the CPU 40 uses the write side start address coordinate data as the write side first coordinate data (S21). Then, it is determined whether or not the address of the storage position next to the storage position of the writing side first coordinate data is an address before the writing side end address (S22). When the result of this determination is affirmative, the CPU 40 uses the coordinate data of the erase side start address as the erase side first coordinate data (S23), and the address of the storage position next to the storage position of the erase side first coordinate data is the erase side. It is determined whether the address is before the end address (S24).

  If the result of this determination is affirmative, the CPU 40 uses the coordinate data stored at the storage position next to the storage position of the write side first coordinate data as the write side second coordinate data, while the erase side first coordinate. The coordinate data stored at the storage position next to the data storage position is set as the erase-side second coordinate data (S25). The CPU 40 then forms a line segment (write side line segment) connecting the position related to the write side first coordinate data and the position related to the write side second coordinate data, and the position related to the erase side first coordinate data and the erase side. It is determined whether or not a line segment (erase-side line segment) connecting with the position related to the second coordinate data intersects (S26).

  If the result of this determination is affirmative, the CPU 40 deletes the target stroke (S27). Specifically, the write data WD is updated so that the data related to the target stroke is deleted from the RAM 60. In this embodiment, since the start address and the end address are held for the writing stroke, it is not necessary to delete the coordinate data from the writing buffer WB.

  On the other hand, when the result of the determination in step S26 is negative, the CPU 40 sets the erasure side second coordinate data as the erasure side first coordinate data (S28), and returns the process to step S24. Therefore, the processes of steps S24 to S28 are repeatedly executed until the target stroke is erased or the address of the storage position next to the storage position of the erase-side first coordinate data is not the address before the erase-side end address. The

  When the address of the storage position next to the storage position of the erase side first coordinate data is not the address before the erase side end address and the result of the determination in step S24 is negative, the CPU 40 writes the write side second coordinate data. The first-side coordinate data is set to the insertion side (S29), and the process returns to step S22. Therefore, the processes in steps S22 to S29 are repeated until the target stroke is deleted or the address of the storage position next to the storage position of the writing side first coordinate data is not the address before the writing side end address. Executed.

  That is, the CPU 40 writes the write side coordinate data, which is a series of coordinate data from the write side start address to the write side end address of the write buffer WB, and the erase side start address to the erase side end address of the erase buffer EB. A line segment that connects a series of positions related to the write side coordinate data adjacent to each other and a line that connects a series of positions related to the erase side coordinate data adjacent to each other using the erase side coordinate data that is a series of coordinate data of The presence / absence of intersection with the minute is determined by brute force, and the target stroke is deleted when it intersects even once.

  For example, in the case of FIG. 13, a line segment connecting the position indicated by the coordinate data c1 and the position indicated by the coordinate data c2 is set as a write side line segment. First, the position and coordinate data indicated by the write side line segment and the coordinate data d1 are used. It is determined whether or not there is an intersection with the erase side line connecting the position indicated by d2, and then the intersection of the write side line segment and the erase side line connecting the position indicated by the coordinate data d2 and the position indicated by the coordinate data d3. Next, it is determined whether or not there is an intersection between the write side line segment, the position indicated by the coordinate data d43, and the erase side line segment connecting the position indicated by the coordinate data d44, and then the coordinate data c1 is The line segment connecting the indicated position and the position indicated by the coordinate data c2 is defined as the writing side line segment, and the presence / absence of the intersection of the line segments is sequentially determined, and as a result, the writing stroke WST1 is erased.

  If the target stroke is erased, or the address of the storage position next to the storage position of the writing side first coordinate data is no longer the address before the writing side end address, the determination result in step S22 is negative. The CPU 40 determines whether or not there is a next writing stroke (S30). The result of this determination is affirmative when a writing stroke that is not a target stroke remains in the target session, and negative in other cases.

  If the determination result of step S30 is affirmative, the CPU 40 sets the next writing stroke as the target stroke (S31), and returns the process to step S8. That is, the above processing is performed for all writing strokes belonging to the target session. In the case of FIG. 13, since the writing stroke WST2 that is not the target stroke remains in the target session, the writing stroke WST2 becomes the target stroke. When the target stroke is the writing stroke WST2, the process of step S12 is performed after the process of step S12 is performed twice, but the target stroke is not erased.

  On the other hand, if the result of the determination in step S30 is negative, the CPU 40 determines whether there is a session next to the target session (S5). If the result of this determination is affirmative, the CPU 40 targets the next session. A session is set (S6), and the process returns to step S4. That is, the above processing is performed for all sessions. However, in the case of FIG. 13, since neither the session area β2 nor β3 overlaps the rectangular area α, it is not determined whether or not the line segment intersects for a session different from the session having the session number “1”.

  When there is no next session and the result of the determination in step S5 is negative, the CPU 40 updates the erase data ED so that the data related to the erase stroke is deleted from the RAM 60, and the process returns to step S1. In the present embodiment, since the end address is held for the erase stroke, it is not necessary to delete the coordinate data from the erase buffer EB.

As described above, when coordinate data of a series of positions is stored in the erasure buffer EB, the CPU 40 stores at least one unit area among the unit areas A into which the erasure stroke enters among the non-erasable write strokes. For each of the candidate specifying unit that specifies the writing stroke entering A as the target stroke (the writing stroke for which the determination result of step S9 is affirmative), and the writing stroke specified as the target stroke, the writing stroke In either of the unit areas A where the erasing stroke and the erasing stroke enter together, one of the line segments connecting the series of positions constituting the writing stroke to each other and the series of positions constituting the erasing stroke are connected to each other. A partial determination process is performed to determine whether any of the line segments intersects, and the result of the partial determination process is positive Functions as a part determining erasing unit for erasing the writing strokes.
Further, as a partial determination erasure unit, the CPU 40 performs writing for one unit area A among the unit areas A in which both the writing stroke and the erasing stroke enter in the partial determination processing related to one writing stroke. Among the coordinate data stored in the insertion buffer WB, the coordinate data of the position in the unit area A among the series of positions constituting the writing stroke and the unit area of the series of positions constituting the erasing stroke The coordinate data of the position in A is specified, and using the specified coordinate data, the line segment that connects the positions in the unit area A next to each other out of a series of positions constituting the writing stroke, and the erasing stroke The presence or absence of intersection with the line segment that connects the positions in the unit area A adjacent to each other in the series of positions constituting the area is determined brute force.
Therefore, according to the present invention, it is possible to reduce the amount of calculation for erasing the writing stroke that intersects the erasing stroke.

Further, when the coordinate data of a series of positions constituting the erase stroke is stored in the erase buffer, the CPU 40 is a rectangle circumscribing the erase stroke constituted by the series of positions among the write strokes that are not erased. The session area that overlaps the enclosed area (rectangular area) is identified, and the session identifying unit that identifies the writing stroke belonging to the session related to the identified session area, and the erasure among the writing strokes identified by the session identifying unit It functions as a target stroke specifying unit that specifies, as a target stroke, a writing stroke that enters at least one unit area A among the unit areas A into which the stroke enters.
Therefore, according to the electronic device 100, it is not necessary to perform the processing after step S7 on the writing stroke belonging to the session related to the session area that does not overlap the area surrounded by the rectangle circumscribing the erasing stroke. This contributes to further reduction in the amount of computation.

In addition, the CPU 40 writes the writing for each of the writing strokes that are not specified as the target stroke among the writing strokes that are specified by the session specifying unit (the writing stroke in which the determination result of step S10 is negative). Execute all judgment processing to determine whether one of the line segments that connect a series of positions that make up a stroke intersects with one of the line segments that connect a series of positions that make up an erasure stroke The all-determination process functions as an all-determination erasing unit that erases a positive writing stroke, and the all-determination erasing unit constitutes the writing stroke in the all-determination process for one writing stroke. Whether or not there is a crossing between a line segment connecting a series of positions adjacent to each other and a line segment connecting a series of positions constituting an erasure stroke A constant.
Therefore, according to the electronic device 100, since it is determined whether or not a writing stroke that does not enter any of the unit areas into which the erasing stroke enters is determined to intersect with the erasing stroke, the erasing accuracy is improved.

  Further, the CPU 40 performs all determination processing for each writing stroke for which the determination result of the partial determination processing described above is not affirmative as the all determination erasure unit. Although there is a slight possibility that the writing stroke and the erasing stroke in which the determination result of the partial determination process is not affirmative may intersect, the electronic device 100 improves the erasing accuracy.

  In the present embodiment, the writing stroke can be erased for the data stored in the storage 80. As a method for realizing this function, there is a method in which the CPU 40 stores the write data WD and the erase data ED and identification information corresponding to the address of the buffer in the storage 80, and uses this identification information to access the coordinate data. It is done.

<4. Modification>
The present invention is not limited to the above-described embodiment, and may include various modifications obtained by modifying the above-described embodiment and combinations thereof. Such a modification is illustrated below.
For example, the session specifying unit and the target stroke specifying unit may not be provided, and the unit region where the writing stroke enters may be specified among all the writing strokes among the unit regions where the erasing stroke enters.
Further, for example, the entire determination erasure unit may not be provided, and a writing stroke that does not enter any unit area in which the erasing stroke enters may not be erased. According to this modification, the amount of calculation is reduced.
Further, for example, the all determination erasing unit may not execute the all determination process for any writing stroke for which the determination result of the partial determination process is not affirmative. In other words, the writing stroke for which the determination result of the partial determination process is not affirmative may not be erased. According to this modification, the amount of calculation is reduced.

100 …… Electronic device, 200 …… Pen, 10 …… Display, 11 …… Screen, 21 …… Switch button, 30 …… Tablet, 40 …… CPU, 60 …… RAM, A …… Unit area, EB ... Erase buffer, EST ... Erase stroke, WB ... Write buffer, WSTk ... Write stroke, ck, dk ... Coordinate data, wk, ek ... Address, α ... Rectangle area, β1-β3 ... ... session area.

Claims (4)

A screen on which an image is displayed divided into a plurality of unit areas;
A tablet that repeatedly detects the indicated position in the screen and outputs coordinate data;
When the locus composed of a series of positions detected from the start to the end of the position indication in the screen is a stroke, and the stroke written in the image is a writing stroke, it is output from the tablet. A write buffer for sequentially storing coordinate data of positions constituting the write stroke among the coordinate data;
When the stroke for erasing the writing stroke is an erasing stroke, among the coordinate data output from the tablet, an erasing buffer that sequentially stores coordinate data of positions constituting the erasing stroke;
Of the coordinate data stored in the write buffer, the coordinate data of a series of positions constituting the write stroke not erased is used to generate the image in which the write stroke not erased is written. An image generator;
When the coordinate data of the series of positions is stored in the erasure buffer, the writing that enters at least one unit area of the unit areas that the erasing stroke enters among the writing strokes that are not erased. A candidate identifying unit that identifies the included stroke as the target stroke;
For each of the writing strokes specified as the target stroke, in any one of the unit regions where the writing stroke and the erasing stroke enter together, the series of positions constituting the writing stroke are adjacent to each other. Executing a partial determination process for determining whether or not one of the line segments connecting with each other and one of the line segments connecting the series of positions constituting the erasing stroke adjacent to each other, and performing the partial determination process A partial determination erasing unit for erasing the writing stroke with a positive result of
The partial determination erasure unit is configured to perform the write operation on one unit area of the unit areas in which the write stroke and the erase stroke enter together in the partial determination process related to one write stroke. Among the coordinate data stored in the buffer, the coordinate data of the position in the unit area among the series of positions constituting the writing stroke and the unit of the series of positions constituting the erasing stroke Specifying the coordinate data of the position in the area, and using the specified coordinate data, the line segment connecting the positions in the unit area adjacent to each other in the series of positions constituting the writing stroke, and the erasing Determining the presence or absence of intersection with the line segment connecting the positions in the unit area adjacent to each other among the series of positions constituting the stroke,
An electronic device characterized by that. When a set of one or more of the writing strokes is a session, the writing stroke belongs to any one of the one or more of the sessions,
The candidate specifying unit
When an area surrounded by a rectangle circumscribing the session is defined as a session area, a rectangle circumscribing the erasure stroke constituted by the series of positions when the coordinate data of the series of positions is stored in the erasure buffer. A session identifying unit that identifies the session region that overlaps with the region surrounded by, and identifies the writing stroke belonging to the session associated with the identified session region;
A target stroke specifying unit that specifies, as the target stroke, the writing stroke that enters at least one of the unit areas that the erasing stroke enters among the writing strokes specified by the session specifying unit. With
The electronic device according to claim 1. Among the writing strokes specified by the session specifying unit, for each of the writing strokes not specified as the target stroke, any of line segments connecting a series of positions constituting the writing stroke adjacent to each other And an all-determination process that determines whether or not one of the line segments that connect the series of positions constituting the erasing stroke intersects each other, and the result of the all-determination process is affirmative An all judgment erasing unit that erases the stroke,
The all determination erasure unit, in the all determination process related to one of the writing strokes, the line segment connecting the series of positions constituting the writing stroke next to each other, and the series of the erasing strokes Judgment of round-robin presence or absence of intersection with the line segment that connects the positions next to each other,
The electronic device according to claim 2. The all determination erasure unit also executes the all determination processing for each of the writing strokes for which the determination result of the partial determination processing is not positive.
The electronic device according to any one of claims 1 to 3, wherein

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