JP2011139407A - Reception circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication circuit capable of performing transmission/reception as expected even when a reference signal of a transmission circuit and that of a reception circuit are fixedly deviated or temporally varied by manufacturing dispersion of an LSI, random dispersion of a transistor, power noise or signal noise. <P>SOLUTION: In this reception circuit which receives a serial signal, an error rate is minimized by optimizing a clock signal becoming momentum for the reception circuit to introduce data in transmission/reception circuit connection, power turning-on or normal operation with respect to deviation of a regular effective data period appearing in a reception signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a receiving circuit capable of reducing an error rate even when a signal waveform deviates from an ideal waveform, for example, in an odd-numbered and even-numbered data width in serial communication.

  In recent years, in order to improve the data rate of signals transmitted / received between large-scale integrated circuits (hereinafter abbreviated as large-scale LSIs), attempts to transmit / receive using serial signals instead of conventional parallel signals are increasing. However, when a serial communication circuit is configured using silicon metal oxide semiconductor (MOS) transistors, it is observed that the transmission waveform deviates from the ideal waveform due to the phenomenon that the threshold voltage of the transistor varies randomly. The Since this defect occurs statistically, it becomes a serious problem particularly when it is desired to improve the error rate of a large-scale LSI having a large number of serial signals. Therefore, there is a demand for a communication receiving circuit that does not easily deteriorate the error rate even if there is a shift in the transmission waveform.

  As countermeasures against these problems, Patent Document 1 discloses a parallel-serial conversion circuit and a technique of changing the frequency ratio of clock frequencies in the serial-parallel conversion circuit and performing data conversion in synchronization with the clock. Patent Document 2 discloses a technique for correctly decoding Manchester encoded data and reducing the error rate of decoding results. Patent Document 3 discloses a technique in which a data signal and a clock are transmitted through two parallel transmission lines, the clock is delay-adjusted with a variable delay circuit, and an optimum delay time that minimizes the error rate is set. . Patent Document 4 discloses a technique for minimizing the error rate by adjusting the clock timing.

JP 2006-238302 A JP 2006-86844 A JP 2003-218847 A Japanese Patent Laid-Open No. 2007-258995

  As described above, in a large-scale LSI, there is a problem that a transmission waveform is deviated from an ideal waveform due to variations in transistors and an error rate is deteriorated.

  The first object of the present invention is when the reference signal of the transmitting circuit and the reference signal of the receiving circuit are fixedly shifted due to manufacturing variations of large-scale LSI, random variations of transistors, power supply noise, and signal noise, It is an object of the present invention to provide a communication circuit capable of performing transmission / reception as expected even when it fluctuates. A second object of the present invention is to provide a receiving circuit including a learning circuit that minimizes an error rate by training using a predetermined data pattern. A third object of the present invention is to provide a receiving circuit that adjusts an operation parameter so that an error rate is minimized even during normal data communication, instead of training by a predetermined pattern.

  According to one aspect of the present invention, an amplifier circuit that amplifies an input serial data signal, a circuit that generates a clock, a clock distribution circuit that distributes the clock, and an N-phase clock from the output of the clock distribution circuit (N is an integer equal to or greater than 4), a first selector that receives the N-phase clock and outputs first to M * 2 clocks (M is an integer equal to or greater than 2); A second selector that outputs the M * 2 + 1 to M * 4 clocks with the phase clock as an input; the first to M * 2 clocks as a clock input; and the output of the amplifier circuit as a data input. First to M * 2 edge detection latches and M * 2 + 1 to M * 4 clocks as clock inputs and M * 2 + 1 to M * 4 outputs from the amplifier circuit as data inputs. Data detection The output of the first to M * 2 edge detection latches, the output of the M * 2 + 1 to M * 4 data detection latches, and the output of the clock distribution circuit. A first edge determination logic for outputting a signal for controlling one selector; outputs of the first to M * 2 edge detection latches; and outputs of the M * 2 + 1 to M * 4 data detection latches. A second edge determination logic that receives an output of the clock distribution circuit and outputs a signal for controlling the second selector; an output of the M * 2 + 1 to M * 4 data detection latches; The serial signal receiving circuit is characterized by comprising an alignment circuit that receives the output of the clock distribution circuit and outputs a serial data output signal.

  According to another aspect of the present invention, an amplifier circuit amplifies the input serial data signal and outputs it as an amplifier output, and the multiphase clock generator circuit M * 2 times the effective period of the serial data signal ((M Is an N-phase clock (N is an integer greater than or equal to 4), and the first edge determination logic determines whether the first to (M * 2) edge detection latch outputs From the output of the M * 2 + 1 to M * 4 data detection latches, it is determined whether the edge of the edge detection clock is earlier or later than the edge of the serial data signal, and the N-phase clock is minimized so that the difference between the two is minimized. Are selected as the first to M * 2 edge detection clocks, respectively, and the first selector uses the first to M * 2 edge detection clocks as the first to M * 2 edge clocks. Output to detection latch Then, each of the first to M * 2 edge detection latches takes in the amplifier output using the inputted first to M * 2 edge detection clocks, and outputs a second edge determination logic. However, from the outputs of the first to M * 2 edge detection latches and the outputs of the M * 2 + 1 to M * 4 data detection latches, was the edge of the data detection clock earlier than the center of the serial data signal? It is determined whether it is late or not, and the M * 2 + 1 to M * 4 data detection clocks are selected from the N-phase clocks so that the difference between them is minimized. M * 2 + 1 to M * 4 data detection clocks are output to the M * 2 + 1 to M * 4 data detection latches, and each of the M * 2 + 1 to M * 4 data detection latches Enter The amplifier output is captured using the M * 2 + 1 to M * 4 data detection clocks, and the alignment circuit outputs the output from the M * 2 + 1 to M * 4 data detection latches to the serial number. A reception method is obtained in which the data signals are aligned according to the data rate and output as a serial data output signal.

  According to still another aspect of the present invention, an amplifier circuit that amplifies an input serial data signal, a circuit that generates a clock, a clock distribution circuit that distributes the clock, and an N-phase output from the output of the clock distribution circuit A circuit that generates a clock (N is an integer of 4 or more), a first selector that receives the N-phase clock and outputs first to M-th clocks (M is an integer of 2 or more), and the N-phase A second selector that receives the clock and outputs the M * 2 + 1 to M * 3 clocks, and a first selector that outputs the M + 1 to M * 2 clocks that receive the first to Mth clocks. An M + 1 inverter, an M + 1 to M * 2 inverter that receives the M * 2 + 1 to M * 3 clocks and outputs an M * 3 + 1 to M * 4 clock, and the first ~ M * 2 clock The first to M * 2th edge detection latches having the lock input and the output of the amplifier circuit as the data input, and the M * 2 + 1 to M * 4 clocks as the clock input and the output of the amplifier circuit as the clock input The M * 2 + 1 to M * 4 data detection latches used as data inputs, the outputs of the first to M * 2 edge detection latches, and the M * 2 + 1 to M * 4 data detection latches. An output, a first edge determination logic that outputs a signal for controlling the first selector, and an output of the first to M * 2 edge detection latches; A second edge determination logic that receives the output of the M * 2 + 1 to M * 4 data detection latches and the output of the clock distribution circuit and outputs a signal for controlling the second selector; and the Mth * 2 + 1 to M * 4th The output of the over data detection latch, the output and the clock distribution circuit is inputted, the serial signal reception circuit, wherein the alignment circuit for outputting the serial data output signal, in that it consists of is obtained.

  According to still another aspect of the present invention, an amplifier circuit that amplifies an input serial data signal, a circuit that generates a clock, a clock distribution circuit that distributes the clock, and an N-phase output from the output of the clock distribution circuit A circuit that generates a clock (N is an integer of 4 or more), a first selector that receives the N-phase clock and outputs first to M-th clocks (M is an integer of 2 or more), and the N-phase A second selector that receives the clock and outputs the M * 2 + 1 to M * 4 clocks, and a first selector that receives the M + 1 to M * 2 clocks and receives the first to Mth clocks. An M + 1 inverter, an M + 1 to M * 2 inverter that receives the M * 2 + 1 to M * 3 clocks and outputs an M * 3 + 1 to M * 4 clock, and the first ~ M * 2 clock The first to M * 2th edge detection latches having the lock input and the output of the amplifier circuit as the data input, and the M * 2 + 1 to M * 4 clocks as the clock input and the output of the amplifier circuit as the clock input The M * 2 + 1 to M * 4 data detection latches used as data inputs, the outputs of the first to M * 2 edge detection latches, and the M * 2 + 1 to M * 4 data detection latches. An output, a first edge determination logic that outputs a signal for controlling the first selector, and an output of the first to M * 2 edge detection latches; A second edge determination logic that receives the output of the M * 2 + 1 to M * 4 data detection latches and the output of the clock distribution circuit and outputs a signal for controlling the second selector; and the Mth * 2 + 1 to M * 4th The output of the over data detection latch, the output and the clock distribution circuit is inputted, the serial signal reception circuit, wherein the alignment circuit for outputting the serial data output signal, in that it consists of is obtained.

  The effect of the present invention is that the error rate can be minimized by optimizing the phase of the data clock of the receiving circuit even if a regular waveform shift occurs in the transmission waveform.

It is a block diagram which shows the whole structure of the receiver circuit in the 1st Embodiment of this invention. It is a block diagram which shows the whole structure of the receiver circuit in the 2nd Embodiment of this invention. It is a block diagram which shows the whole structure of the receiver circuit in the 3rd Embodiment of this invention. It is a block diagram which shows the whole structure of the receiver circuit in the 4th Embodiment of this invention. It is a block diagram which shows the whole structure of the receiver circuit in the 5th Embodiment of this invention. It is a block diagram which shows the whole structure of the receiver circuit in the 6th Embodiment of this invention. It is a block diagram which shows the whole structure of the receiver circuit in the 7th Embodiment of this invention. FIG. 3 is a timing chart showing the basic operation of the serial signal receiving circuit of the present invention. FIG. 6 is a timing diagram showing a correlation between a serial data signal when the odd-numbered and even-numbered valid periods of the serial data signal are different in the receiving circuit of the present invention, and the clock of the edge detection latch and the data detection latch. FIG. 6 is a timing diagram showing a correlation between a serial data signal and the edge detection latch and the clock of the data detection latch when the first to fourth valid periods of the serial data signal are periodically different in the receiving circuit of the present invention. FIG. 7 is a timing diagram in which the serial data signal and the edge detection latch and the clock of the data detection latch are synchronized when the first to fourth valid periods of the serial data signal are periodically different in the receiving circuit of the present invention. FIG. 6 is a timing diagram illustrating a method for adjusting a serial data signal, an edge detection latch, and a data detection latch clock when the first to fourth valid periods of the serial data signal of the serial signal receiving circuit of the present invention are periodically different. .

  Embodiments of the present invention will be described in detail with reference to the drawings. The present invention relates to a receiving circuit capable of reducing an error rate even when a signal waveform deviates from an ideal waveform, for example, in a serial communication in which the data width of a received serial data signal is different.

  A serial signal receiving circuit of the present invention includes an amplifier circuit, an edge detection latch, a data detection latch, a clock generation circuit, a multiphase clock generation circuit, first and second selectors, first and second edge determination logic, and an alignment circuit. Is provided. The amplifier circuit receives the serial data input signal, limits the bandwidth of the serial data input signal, and amplifies the received serial data signal. A plurality of edge detection latches and data detection latches are provided. The output of the amplifier circuit is fetched in accordance with each input clock, and “0” or “1” is determined and output. The clock generation circuit generates a clock that is an integral multiple of the data rate or a fraction of an integer. The multiphase clock generation circuit generates a multiphase clock from the clock.

  The first and second selectors select a latch clock to be supplied to each of the edge detection latch and the data detection latch from the multiphase clock. The first and second edge determination logic controls the first and second selectors so as to select the optimum phase of the multiphase clock. The alignment circuit rearranges the output of the data detection latch in accordance with the data rate of the serial data input signal and outputs a serial data output signal. Furthermore, an error rate detection circuit can be provided, and the error rate detection circuit calculates the error rate by observing the output of the alignment circuit or the output of the data detection latch and the edge detection latch.

  As a result, the first and second edge determination logic can select the optimum phase of the multiphase clock so that the error rate is minimized. In this way, M * 2 data detection latches take in data with M * 2 as a cycle, but the clock that triggers data detection for the deviation of the effective time width of the periodic data that appears in the serial transmission signal. Adjust to minimize the error rate.

  9 to 12 are timing charts showing the correlation between the serial data signal in the receiving circuit, the edge detection latch that receives the serial data signal, and the clock of the data detection latch. When transmitting a high-speed serial data signal, the clock duty ratio of the transmission circuit varies from 50:50, so that the odd-numbered and even-numbered data valid periods have different waveforms as in the serial data signal of FIG. There are many cases. For example, the receiving circuit selects an optimum clock from among the multiphase clocks, and receives it using four sets of edge detection latches and four sets of data detection latches. In this case, as shown in FIG. 9, even if the clocks 70 to 73 of the edge detection latch are shifted from the true data edge, the shift amounts a0 to a3 are set such that a0 = a1 = a2 = a3. Adjust the clock phase. Further, adjustment is made so that the clocks 80 to 83 of the data detection latch rise from the rising edge of the clocks 70 to 73 of the edge detection latch in half the effective period. By adjusting the clocks of the edge detection latch and the data detection latch in this way, all the data detection latches capture the center of the valid period of the serial data signal, and the error rate is optimized.

  In order to transmit a higher-speed serial data signal, the serial data signal may be transmitted using a four-phase clock. In this case, as shown in FIG. A case occurs. The shifts c0 to c3 between the rising edges of the clocks 70 to 73 of the edge detection latch at equal intervals and the edges of the true serial data signal are adjusted so that c0 = c1 + c2 + c3. Further, the difference between the rising edges of the clocks 80 to 83 of the data detection latch and the rising edges of the clocks 70 to 73 of the edge detection latch is adjusted to be ½ of the effective period. Even if the edge detection latch and the latch clock for the data detection latch are adjusted as described above, a portion where the edge of the serial data signal and the clock edge of the data detection latch are closest is generated as shown in “worst margin” in FIG. And the error rate gets worse.

  In such a case, as shown in FIG. 11, the edges of the clocks 70 to 73 of the edge detection latch are adjusted so as to be aligned with the true edges of the serial data signal. The receiving circuits shown in FIGS. 5 to 7 to be described later have a configuration in which the phases of the clocks 70 to 73 of the edge detection latch do not have to be equidistant, and are provided with adjusting means that can correspond to individual edges. . In order to adjust the clocks 70 to 73 of the edge detection latch so as to be aligned with the true edge of the serial data signal, it is determined whether the edge detection latch has captured the immediately preceding data or the immediately following data, and the frequency of both Adjust so that is equal. As shown in FIG. 12, the width of the true edge on the immediately preceding data side may be different from the width of the edge on the immediately following data side. The error rate may be improved by intentionally shifting from the center of the difference between the edges of the edge detection latch clock 71 and the clock 72 like the clock 81 of the data detection latch shown in FIG. The receiver circuit shown in FIG. 7 measures how much the error rate is optimized by shifting the clocks 80 to 83 of the data detection latch from the edges of the clocks 71 to 73 of the edge detection latch. Means are provided for determining the phase of the clocks 80-83 of the data detection latch that optimizes the error rate.

  In the present invention, M * 2 edge detection latches and data detection latches are provided, and an N-phase clock is used as a multiphase clock. Furthermore, L redundant data detection latches are provided, and (M * 2 + L) data detection latches can be provided. By configuring the receiving circuit in this way and adjusting the clocks of the edge detection latch and the data detection latch, the error rate can be optimized.

  In the following, the configuration and operation of the best mode for carrying out the present invention will be described using specific embodiments, assuming that M = 2, N = 64, and L = 1. However, M, N, and L may be other values as long as they are integers satisfying M ≧ 2, N ≧ 4, and L ≧ 1.

(Example 1)
FIG. 1 is a block diagram showing the overall configuration of a receiving circuit according to the first embodiment of the present invention. The reception circuit includes a clock generation circuit 10, a clock distribution circuit 11, 1-bit reception circuits 112 to 115, serial data input signals 90 to 93, and serial data output signals 95 to 98. The 1-bit reception circuit 112 includes a clock distribution circuit 20, a multiphase clock generation circuit 21, selectors 22 and 23, edge determination logics 24 and 25, edge detection latches 30 to 33, data detection latches 34 to 37, an amplifier circuit 29, An alignment circuit 26 and inverters 12 to 15 are provided. The 1-bit receiving circuits 112 to 115 have the same configuration, and only the serial data input signals 90 to 93 inputted thereto are different from the al output signals 95 to 98 outputted, respectively. The configuration of only the receiving circuit 112 is shown and described.

  The clock generation circuit 10 generates a clock that is an integral multiple or a fraction of an integer of the data rate of the serial data input signal. In the present invention, a clock having the same rate as the data rate of the serial data input signal is generated. The clock distribution circuit 11 distributes the clock 40 from the clock generation circuit 10 to each of the 1-bit reception circuits 112 to 115.

  The 1-bit receiving circuit 112 receives the serial data input signal 90 and outputs a serial data output signal 95. The amplifier circuit 29 receives the serial data signal 90 and outputs the amplified amplifier output signal 99 to the edge detection latch circuits 30 to 33 and the data detection latch circuits 34 to 37. The clock distribution circuit 20 receives the clock 41 from the clock distribution circuit 11 and outputs the clock 50 to the multiphase clock generation circuit 21, the edge determination logics 24 and 25, and the alignment circuit 26. The multiphase clock generation circuit 21 has a multiphase clock (600 to 600) which divides the effective period of the serial data signal into 16 equal parts with a period of 4 (= M * 2) times the effective period of the serial data signal from the input clock 50. 663). It is necessary to generate a clock of period 4 (M * 2) × divided number 16 phases, but here, half of the 32 phases are generated, and the remaining 32 phases use the former 32 phase inversion logic. In the first embodiment, since the clock output from the selector is inverted by the inverter circuits 12 to 15, only the former 32 phases are generated, and the latter 32 phases may not be generated. Accordingly, in FIG. 1, 32-phase multiphase clocks (600 to 631) are generated, and the generated multiphase clocks are output to the selectors 22 and 23.

  The edge determination logics 24 and 25 receive the outputs 75 to 78 from the edge detection latch, the outputs 85 to 88 from the data detection latch, and the clock 50, and select the optimum multiphase clock so as to select the optimum multiphase clock. , 23 is adjusted. The selector 22 selects the optimum multiphase clock based on the control signal 51 from the edge determination logic 24 and outputs the edge detection latch latch clocks 70 and 71 to the edge detection latches 30 and 31 and the inverters 12 and 13. To do. The clocks 70 and 71 are adjusted so as to be shifted by the same period as the valid period of the serial data signal. The inverters 12 and 13 invert the input clocks 70 and 71 of the edge detection latch and output them to the edge detection latches 32 and 33 as latch clocks 72 and 73 of the edge detection latch.

  The selector 23 selects the optimum multiphase clock based on the control signal 52 from the edge determination logic 25 and outputs the data detection latch latch clocks 80 and 81 to the data detection latches 34 and 35 and the inverters 14 and 15. To do. The inverters 14 and 15 invert the input data detection latch latch clocks 80 and 81 and output the inverted data detection latch clocks 82 and 83 to the data detection latches 36 and 37, respectively. Here, the inverters 12 to 15 are used to generate clocks 72, 73, 82, and 83 obtained by inverting the clocks 70, 71, 80, and 81. However, in the case of using multi-line logic that realizes one signal with two or more wires, the signals generated by the first to fourth inverters 12 to 15 are substituted with any one of the multi-line signals. 4 inverters may be omitted.

  The edge detection latches 30 to 33 latch the amplifier output signal 99 based on the latch clocks 70, 71, 72, 73 of the edge detection latch. The data detection latches 34 to 37 latch the amplifier output signal 99 based on the latch clocks 80, 81, 82, 83 of the data detection latch. The clocks 80 to 83 of the data detection latch are adjusted so as to be shifted from the clocks 70 to 73 by a half of the effective period of the serial data signal. The alignment circuit 26 aligns the outputs 85 to 88 from the data detection latches 34 to 37 with the clock 50 and outputs a serial data output signal 95.

  Regarding the operation of the receiving circuit described above, the basic operation of the receiving circuit will be described with reference to the timing chart of FIG. In the timing diagram, the clock 50, the multiphase clocks 600 to 631, the amplifier output signal 99 of the serial data signal, the edge clocks 70 to 73, the outputs 75 to 78 of the edge detection latch, the data clocks 80 to 83, the data The detection latch outputs 85 to 88 and the serial data output signal 95 are shown.

  The clock 50 has the same data rate as that of the serial data signal, and the multiphase clocks 600 to 631 have a period of 4 (= M * 2) times the valid period of the serial data signal. The multiphase clocks 600 to 631 correspond to the first half of the quadruple effective period of the serial data signal, and the remaining second half multiphase clocks 632 to 663 are the same as the first half multiphase clocks 600 to 631. Since it is an inverted signal, it is not shown.

  The serial data signal 90 input to the 1-bit receiving circuit 112 is amplified by the amplifier circuit 29 and becomes an amplifier output signal 99. The four edge detection latches 31 to 33 are driven by clocks 70 to 73, respectively. The clocks 70 to 73 are adjusted so as to be shifted by the same period as the valid period of the serial data signal. Since the outputs 75 to 78 from the edge detection latches 31 to 33 are captured at the rising edge of the clock, the period is 4 (= M * 2) times the effective period of the serial data signal.

  The four data detection latches 34 to 37 are driven by clocks 80 to 83, respectively. As shown in the figure, each of the clocks 70 to 73 and the clocks 80 to 83 is shifted by substantially the same period as the valid period of the serial data signal, and the clocks 70 to 73 and the clocks 80 to 83 are of the valid period of the serial data signal. It is adjusted so as to deviate almost by half. However, each of the clocks 70 to 73 and the clocks 80 to 83 can have its phase difference set independently. Since the outputs 85 to 88 from the data detection latches 34 to 37 are captured at the rising edge of the clock, the period is 4 (= M * 2) times the effective period of the serial data signal. The data alignment circuit aligns the outputs 85 to 88 of the data detection latch and outputs a serial data output signal 95.

  The first edge determination logic 24 detects the valid edge by observing the outputs 85 to 88 of the data detection latch. Further, it is determined from the outputs 75 to 78 of the edge detection latch and the outputs 85 to 88 of the data detection latch during the edge valid period whether the edge detection clock is earlier or later than the edge of the serial data signal. It is determined whether it is early or late with respect to the clocks of the four edge detection latches for a certain period of time, and the selector 22 is adjusted so that the number of early and late cases becomes the same, and an appropriate multiphase clock is selected. Similarly, the second edge determination logic adjusts the selector 23 so that the output of the selector 22 and the output of the selector 23 are shifted by a half of the valid period of the serial data signal. That is, the clock of the edge detection latch is set so as to shift the valid period of the serial data signal so that it can be synchronized with the edge of the serial data signal. The clock of the data detection latch is set so as to be shifted from the clock of the latch detection latch by 1/2 of the effective period of the serial data signal so that it can be synchronized with the center of the effective period of the serial data signal.

  FIG. 9 is a timing diagram showing the correlation among the serial data signal, the clock of the edge detection latch, and the clock of the data detection latch. Here, the serial data signal shown in FIGS. The edge detection latch clocks 70 to 73 and the data detection latch clocks 80 to 83 indicate the positions of the rising edges of the clocks. The clocks 70 and 72 of the first and third edge detection latches 30 and 32 arrive earlier than the edges of the serial data signal by a0 and a2, respectively, and the clocks 71 and 73 of the second and fourth edge detection latches 31 and 33 are reached. Arrives later than the edge of the serial data signal by a1 and a3. When the odd-numbered and even-numbered data valid periods of the serial data signal are different, a0 = a2 and a1 = a3, and the number of appearances when the clock of the edge detection latch is early and late is the same, that is, a0 = a2 = a1. The edge determination logic adjusts the selectors 22 and 23 so that = a3. At this time, the clock of the data detection latch is located at the center of the valid period of the serial data signal as shown in FIG. 9, and the error rate is minimized.

  In the present embodiment, a multi-phase clock that uses 4 (= M * 2) times as long as the effective period of the serial data signal and divides the effective period of the serial data signal into 16 equal parts is used. The multi-phase clock generation circuit generates a multi-phase clock for the first half of the effective period of the real data signal and inverts the generated multi-phase clock for the first half of the period to double the second half of the effective period. A multi-phase clock for a period is used. The clock of the edge detection latch and the data detection latch is selected from the multiphase clock for the first half cycle, and the multiphase clock for the second half cycle is a signal inverted by the inverter of the multiphase clock for the first half cycle. To do. The edge of the edge detection latch is aligned with the edge of the serial data signal, and the edge of the clock of the data detection latch is positioned at the center of the valid period of the serial data signal to capture the serial data signal. According to the present embodiment, a receiving circuit capable of reducing the error rate of the serial data signal can be obtained.

(Example 2)
FIG. 2 is a block diagram showing an overall configuration of a receiving circuit according to the second embodiment of the present invention. The reception circuit includes a clock generation circuit 10, a clock distribution circuit 11, 1-bit reception circuits 112 to 115, serial data input signals 90 to 93, and serial data output signals 95 to 98. The 1-bit reception circuit 112 includes a clock distribution circuit 20, a multiphase clock generation circuit 21, selectors 22 and 23, edge determination logics 24 and 25, edge detection latches 30 to 33, data detection latches 34 to 37, an amplifier circuit 29, An alignment circuit 26 and inverters 12 to 13 are provided.

  The configuration of the receiving circuit shown in FIG. 2 differs from that in FIG. 1 in the first embodiment in the means for supplying the clock to the data detection latch. In the second embodiment, the inverters 14 and 15 that supply the clocks 82 and 83 to the data detection latches 36 and 37 are omitted, and the clocks 80 to 83 to the data detection latches 34 to 37 are all supplied from the selector 23. ing. The clocks 80 and 82 and 81 and 83 in the first embodiment have a fixed phase difference because they are inverted by an inverter, and are not related to a clock having a free phase difference.

  However, the multiphase clock generation circuit 21 of this embodiment generates 64-phase multiphase clocks 600 to 663 and supplies them to the selectors 22 and 23. As in the first embodiment, the selector 22 selects two clocks 70 and 71 from among the 32-phase multiphase clocks 600 to 631 and inverts them by an inverter to obtain clocks 72 and 73. On the other hand, the selector 23 selects four clocks 80 to 83 from the 64-phase multiphase clocks 600 to 663. Therefore, the clocks 80 to 83 can all be independently independent clocks having a free phase difference. Since other configurations are the same as those of the first embodiment (FIG. 1), description thereof is omitted.

  The basic operation of the serial signal receiving circuit shown in FIG. 2 will be described with reference to the timing diagrams of FIGS. The multiphase clock generation circuit 10 generates a multiphase clock (600 to 631) that divides the effective period of the serial data signal into 16 equal parts with a period of 4 (= M * 2) times the effective period of the serial data signal. It is necessary to generate a clock of period 4 (M * 2) × divided number 16 phases. Here, half of the 32 phases are generated, and the remaining 32 phases are generated by using the inverted logic of the former 32 phases. did. Therefore, in FIG. 8, only the first half 32 phases are illustrated.

  Four edge detection latches 30 to 33 are provided and driven by clocks 70 to 73, respectively. The selector 22 selects and outputs clocks 70 and 71 from the 64-phase clock. Clocks 72 and 73 are clocks obtained by inverting clocks 70 to 71 by inverters 12 and 13. The clocks 70 and 71 are adjusted so as to be shifted by the same period as the valid period of the serial data signal. Further, the clocks 80 to 83 of the data detection latch are adjusted so as to deviate from the clocks 70 to 73 by approximately ½ of the effective period of the serial data signal, but the phase difference can be adjusted independently. The data alignment circuit aligns the outputs 85 to 88 of the data detection latch and outputs a serial data output signal 95.

  The first edge determination logic 24 detects the valid edges by observing the outputs 85 to 88 of the data detection latch. Also, it is determined from the edge detection latch outputs 75 to 78 and the data detection latch outputs 85 to 88 during the edge valid period whether the edge detection clock is earlier or later than the edge of the serial data signal. It is determined whether it is early or late with respect to the clocks of the four edge detection latches for a certain period of time, and the selector 22 is adjusted so that the number of early and late cases becomes the same, and an appropriate multiphase clock is selected. Similarly, the second edge determination logic 25 adjusts the selector 23 and sets the output of the selector 22 and the output of the selector 23 to have a constant phase difference, but the phase difference is one of the valid period of the serial data signal. To be able to choose freely without fixing to / 2.

  FIG. 10 is a diagram showing a correlation among timings of the serial data signal, the clock of the edge detection latch, and the clock of the data detection latch. The clock of the first edge detection latch arrives earlier than the edge of the serial data signal by c0, and the clocks of the second, third, and fourth edge detection latches arrive later than the edge of the serial data signal by c1, c2, and c3. ing. The edge determination logics 24 and 25 adjust the selectors 22 and 23 so that the number of appearances when the clock of the edge detection latch is early and late is the same, that is, c0 = c1 + c2 + c3.

  At this time, if the data detection latch clock is set to be shifted from the edge detection latch by a half of the valid period of the serial data signal as shown in FIG. 10, the data detection latch clock at the timing of “worst margin” in the figure. The edge of the serial data input signal approaches and the error rate gets worse. Therefore, the phase difference between the clocks 80 to 83 of the data detection latch and the clock of the edge detection latch is not fixed to ½ of the valid period of the serial data signal but is made variable. For example, the phase of the clock 82 of the data detection latch is made earlier than ½ of the effective period, so that the serial data signal can be easily latched. Thus, by independently adjusting the clock of the data detection latch, it is possible to reduce the error rate by reliably taking in the serial data.

  In this embodiment, the clock for the data detection latch can be freely selected independently from the multiphase clock for a period of 4 times. The edge of the edge detection latch and the edge of the serial data signal are combined, and the edge of the clock of the data detection latch is set to a free position within the valid period of the serial data signal to capture the serial data signal. According to the present embodiment, a receiving circuit capable of reducing the error rate of the serial data signal can be obtained.

(Example 3)
FIG. 3 is a block diagram showing an overall configuration of a receiving circuit according to the third embodiment of the present invention. The reception circuit includes a clock generation circuit 10, a clock distribution circuit 11, 1-bit reception circuits 112 to 115, serial data input signals 90 to 93, and serial data output signals 95 to 98. The 1-bit reception circuit 112 includes a clock distribution circuit 20, a multiphase clock generation circuit 21, selectors 22 and 23, edge determination logics 24 and 25, edge detection latches 30 to 33, data detection latches 34 to 37, an amplifier circuit 29, An alignment circuit 26, inverters 12 to 13, and an error rate detection circuit 27 are provided.

  In the configuration of the receiving circuit shown in FIG. 3, an error rate detection circuit 27 is added to the second embodiment (FIG. 2). The error rate detection circuit 27 of the third embodiment receives the serial data output signal 95 from the alignment circuit 26 and the clock 50 from the clock distribution circuit 20 and outputs them to the edge determination logics 24 and 25. The error rate detection circuit 27 receives the serial data output signal 95 and compares the expected value of the error rate detection circuit to calculate the error rate. The error rate is fed back to the edge determination logics 24 and 25, and the edge determination logics 24 and 25 select an optimal clock. Since other configurations are the same as those of the second embodiment (FIG. 2), description thereof is omitted.

  The basic operation of the serial signal receiving circuit shown in FIG. 3 will be described with reference to the timing charts of FIGS. The multi-phase clock generation circuit 10 generates a multi-phase clock (600 to 631) that divides the effective period of the serial data signal into 16 equal parts with a period of 4 (= M * 2) times the effective period of the serial data signal. It is necessary to generate a clock of period 4 (M * 2) × divided number 16 phases. Here, half of the 32 phases are generated, and the remaining 32 phases are generated by using the inverted logic of the former 32 phases. did. Therefore, in FIG. 8, only the first half 32 phases are illustrated.

  Four edge detection latches 30 to 33 are provided and driven by clocks 70 to 73, respectively. The selector 22 outputs the clocks 70 and 71 from the 64-phase clock, and the clocks 72 to 73 are inverted signals of the clocks 70 to 71 by the inverters 12 and 13. The clocks 70 and 71 are adjusted so as to be shifted by the same period as the valid period of the serial data signal. Further, the clocks 80 to 83 of the data detection latch are adjusted so as to deviate from the clocks 70 to 73 by approximately ½ of the effective period of the serial data signal, but the phase difference can be adjusted independently. The data alignment circuit 26 aligns the outputs 85 to 88 of the data detection latch according to the clock 50 and outputs a serial data output signal 95.

  The first edge determination logic 24 detects the valid edges by observing the outputs 85 to 88 of the data detection latches 34 to 37. Further, it is determined from the outputs 75 to 78 of the edge detection latches 30 to 33 and the outputs 85 to 88 of the data detection latches 34 to 37 during the edge valid period whether the edge detection clock is earlier or later than the edge of the serial data signal. It is determined whether it is early or late with respect to the clocks of the four edge detection latches for a certain period of time, and the selector 22 is adjusted so that the number of early and late cases becomes the same, and an appropriate multiphase clock is selected. Similarly, the second edge determination logic 25 sets the error rate detection circuit 27 to adjust the selector 23 so that the output of the selector 22 and the output of the selector 23 have a constant phase difference. The error rate is set to the minimum without being fixed to ½ of the signal valid period.

  FIG. 10 is a timing diagram showing the correlation among the serial data signal, the clock of the edge detection latch, and the clock of the data detection latch. The clock of the first edge detection latch 24 arrives earlier than the edge of the serial data signal by c0, and the clocks of the second, third, and fourth edge detection latches arrive later than the edge of the serial data signal by c1, c2, and c3. is doing. The edge determination logic adjusts the selectors 22 and 23 so that the number of appearances when the clock of the edge detection latch is early and late is the same, that is, c0 = c1 + c2 + c3. At this time, if the clock of the data detection latch is set so as to deviate from the clock of the edge detection latch by ½ of the valid period of the serial data signal as shown in FIG. 10, the data detection latch is at the timing of “worst margin” in the figure. The edge of the clock and the serial data input signal approach each other, and the error rate deteriorates. Therefore, the phase difference between the clocks 80 to 83 of the data detection latch and the clocks 70 to 73 of the edge detection latch is not fixed to ½ of the effective period of the serial data signal but is made variable.

  In order to obtain the phase difference between the clocks 80 to 83 of the data detection latch and the clocks 70 to 73 of the edge detection latch that minimize the error rate, the following procedure is performed. An error rate is calculated by repeatedly receiving a predetermined transmission data string and comparing the output of the alignment circuit with the expected value of the error rate detection circuit. Next, the phase difference between the clock 80 of the data detection latch and the clocks 70 to 73 of the edge detection latch is changed to search for a point where the error rate is minimized. Subsequently, the same processing is performed on the clocks 81, 82, and 83, and the same processing is further repeated once or more on the signals 80, 81, 82, and 83. However, it can be omitted if the error rate measured so far achieves the desired characteristics.

  In this embodiment, an error rate detection circuit is provided, and the reception circuit repeatedly receives a predetermined transmission data string and compares the output of the alignment circuit with the expected value of the error rate detection circuit to calculate the error rate. Next, the phase difference between the clock of each data detection latch and the clock of the edge detection latch is changed to search for a point where the error rate is minimized. According to the present embodiment, a receiving circuit capable of reducing the error rate of the serial data signal can be obtained.

Example 4
FIG. 4 is a block diagram showing an overall configuration of a receiving circuit according to the fourth embodiment of the present invention. The reception circuit includes a clock generation circuit 10, a clock distribution circuit 11, 1-bit reception circuits 112 to 115, serial data input signals 90 to 93, and serial data output signals 95 to 98. The 1-bit reception circuit 112 includes a clock distribution circuit 20, a multiphase clock generation circuit 21, selectors 22 and 23, edge determination logics 24 and 25, edge detection latches 30 to 33, data detection latches 34 to 38, an amplifier circuit 29, An alignment circuit 26, inverters 12 to 13, and an error rate detection circuit 27 are provided.

  In the configuration of the receiving circuit shown in FIG. 4, a data detection latch 38 is added to the block diagram 3 in the third embodiment. A clock 84 for the data detection latch 38 is additionally output from the selector 23. The data detection latch 38 receives the amplifier output signal 99 by the clock 84 and outputs the output 89 to the error rate detection circuit 27. The data detection latch 38 is a redundant data detection latch. An error rate due to a phase difference between the redundant data detection latch and the original data detection latch is determined, and an optimum clock phase is set so as to reduce the error rate. adjust. Redundant data detection latches can be compared with the respective data detection latches to reduce the error rate. Since other configurations are the same as those of the third embodiment (FIG. 3), description thereof is omitted.

  The basic operation of the serial signal receiving circuit shown in FIG. 4 will be described with reference to the timing diagrams of FIGS. The multi-phase clock generation circuit 10 generates a multi-phase clock (600 to 631) that divides the effective period of the serial data signal into 16 equal parts with a period of 4 (= M * 2) times the effective period of the serial data signal. It is necessary to generate a total of 64 clocks of period 4 (M * 2) × divided number 16 phases. Here, half of 32 phases are generated, and the remaining 32 phases use the former 32 phase inversion logic. It was. Therefore, in FIG. 8, only 32 phases corresponding to the double period of the first half are shown.

  Four edge detection latches are provided and driven by clocks 70 to 73, respectively. The selector 22 generates clocks 70 and 71 from the 64-phase clock, and the clocks 72 to 73 are inverted signals of the clocks 70 to 71. The clocks 70 and 71 are adjusted so as to be shifted by the same period as the valid period of the serial data signal. Further, the clocks 80 to 83 of the data detection latch are adjusted so as to deviate from the clocks 70 to 73 by approximately ½ of the effective period of the serial data signal, but the phase difference can be adjusted independently. The data alignment circuit 26 aligns the outputs 85 to 88 of the data detection latch and outputs a serial data output signal 95.

  The first edge determination logic 24 detects the valid edges by observing the outputs 85 to 88 of the data detection latches 34 to 37. Further, it is determined from the outputs 75 to 78 of the edge detection latches 30 to 33 and the outputs 85 to 88 of the data detection latch during the edge valid period whether the edge detection clock is earlier or later than the edge of the serial data signal. It is determined whether it is early or late with respect to the clocks of the four edge detection latches for a certain period of time, and the selector 22 is adjusted so that the number of early and late cases becomes the same, and an appropriate multiphase clock is selected. Similarly, the second edge determination logic 25 sets the error rate detection circuit 27 to adjust the selector 23 so that the output of the selector 22 and the output of the selector 23 have a constant phase difference. The error rate is set to the minimum without being fixed to ½ of the signal valid period.

  FIG. 10 is a timing diagram showing the correlation among the serial data signal, the clock of the edge detection latch, and the clock of the data detection latch. The clock 70 of the first edge detection latch 24 arrives earlier than the edge of the serial data signal by c0, and the clocks 71, 72, 73 of the second, third, and fourth edge detection latches are serial data by c1, c2, and c3. It arrives later than the edge of the signal. The edge determination logic adjusts the selectors 22 and 23 so that the number of appearances when the clock of the edge detection latch is early and late is the same, that is, c0 = c1 + c2 + c3. At this time, as shown in FIG. 10, if the clock of the data detection latch is set so as to be shifted from the edge detection latch by half of the valid period of the serial data signal, the data detection latch of the data detection latch is at the timing of “worst margin” in the figure. The edge of the clock and the serial data input signal approaches, and the error rate deteriorates. Therefore, the phase difference between the clocks 80 to 83 of the data detection latch and the clocks 70 to 73 of the edge detection latch is not fixed to ½ of the effective period of the serial data signal but is made variable.

  In order to obtain the phase difference between the clocks 80 to 83 of the data detection latch and the clocks 70 to 73 of the edge detection latch that minimize the error rate, the following procedure is performed. The receiving circuit receives a data string (not necessarily a predetermined transmission data string). The error rate detection circuit 27 advances or delays the phase of the clock 84 that drives the redundant data detection latch 38 via the second edge determination logic 25 and the second selector 23. The phase of the clock 84 is adjusted, and the phase range of the clock 84 in which the data detection latch 34 and the redundant data detection latch 38 capture the same value is determined. The phase of the clock 80 is adjusted to an average value of the phase range of the clock 84 or a phase that is advanced or delayed from the average value by a predetermined value or ratio. This requires a predetermined period.

  Next, the same phase adjustment is performed on the clock of the data detection latch 35, the phase range of the clock 84 is determined, and the average value or a phase that has been advanced or delayed from the average value by a predetermined value or ratio. The phase of the clock 81 is matched. Subsequently, similar processing is performed on the clocks 82 and 83 to update the phases of the clocks 82 and 83. Further, the same processing is repeated once or more for the signals 80, 81, 82, 83. However, it can be omitted if the error rate measured so far achieves the desired characteristics.

  The clock 84 and redundant data detection latch 38 are operated for a period of time or until the error rate achieves the desired characteristics, but may be stopped thereafter. Alternatively, the phases of the clocks 80 to 83 can be updated so as to improve the error rate degradation caused by temperature change and aging change by performing the above procedure continuously or intermittently.

  In this embodiment, a redundant data detection latch is provided, the phase difference between the redundant data detection latch and the original data detection latch is determined, and the optimum clock phase is adjusted to reduce the error rate. Yes.

(Example 5)
FIG. 5 is a block diagram showing an overall configuration of a receiving circuit according to the fifth embodiment of the present invention. The reception circuit includes a clock generation circuit 10, a clock distribution circuit 11, 1-bit reception circuits 112 to 115, serial data input signals 90 to 93, and serial data output signals 95 to 98. The 1-bit reception circuit 112 includes a clock distribution circuit 20, a multiphase clock generation circuit 21, selectors 22 and 23, edge determination logics 24 and 25, edge detection latches 30 to 33, data detection latches 34 to 37, an amplifier circuit 29, An alignment circuit 26 is provided.

  The configuration of the receiving circuit shown in FIG. 5 differs from that shown in FIG. 1 in the first embodiment in the means for supplying clocks to the edge detection latch and the data detection latch. In the fifth embodiment, the inverters 12, 13, 14, and 15 that supply the clocks 72, 73, 82, and 83 are omitted, and all the clocks to the edge detection latches 30 to 33 and the data detection latches 34 to 37 are Directly supplied from the selectors 22 and 23. The multiphase clock generation circuit 21 of the present embodiment generates 64-phase multiphase clocks 600 to 663 and supplies them to the selectors 22 and 23. The selectors 22 and 23 select four clocks 70 to 73 and 80 to 83 from the multiphase clocks 600 to 663 of 64 phases, respectively. Therefore, the clocks 70 to 73 and 80 to 83 can all be independently independent clocks having a free phase difference. Since other configurations are the same as those of the first embodiment (FIG. 1), description thereof is omitted.

  The clocks of the edge detection latch and the data detection latch of this embodiment are all output from the selectors 22 and 23, and can be independently selected as clocks having different phase differences. Since other configurations are the same as those of the first embodiment (FIG. 1), description thereof is omitted.

  The basic operation of the serial signal receiving circuit shown in FIG. 5 will be described with reference to the timing charts of FIGS. The multi-phase clock generation circuit 10 generates a multi-phase clock (600 to 631) that divides the effective period of the serial data signal into 16 equal parts with a period of 4 (= M * 2) times the effective period of the serial data signal. It is necessary to generate a clock of period 4 (M * 2) × divided number 16 phases. Here, half of the 32 phases are generated, and the remaining 32 phases are generated by using the inverted logic of the former 32 phases. did. Therefore, in FIG. 8, only the first half 32 phases are illustrated.

  Four edge detection latches 30 to 33 are provided and driven by clocks 70 to 73, respectively. The clocks 70 to 73 are adjusted so as to be shifted by substantially the same period as the effective period of the serial data signal, but the phase difference can be adjusted independently. Further, the clocks 80 to 83 of the data detection latch are adjusted so as to deviate from the clocks 70 to 73 by approximately ½ of the effective period of the serial data signal, but the phase difference can be adjusted independently. The data alignment circuit 26 aligns the outputs 85 to 88 of the data detection latch and outputs a serial data output signal 95.

  The first edge determination logic 24 detects the valid edges by observing the outputs 85 to 88 of the data detection latches 34 to 37. Also, it is determined from the edge detection latch outputs 75 to 78 and the data detection latch outputs 85 to 88 during the edge valid period whether the edge detection clock is earlier or later than the edge of the serial data signal. The second edge determination logic 25 determines whether the data detection latch clocks 80-83 were earlier or later than the center of the edge detection latch clocks 70-73.

  FIG. 10 is a timing diagram showing the correlation among the serial data signal, the clock of the edge detection latch, and the clock of the data detection latch. When the phase difference between the clocks 70 to 73 of the edge detection latch is fixed at the same value as the data valid period of the serial data, the first clock of the edge detection latch 24 arrives earlier than the edge of the serial data signal by c0. The second, third, and fourth clocks of the edge detection latch 24 arrive later than the edge of the serial data signal by c1, c2, and c3 (FIG. 10). Here, the edge detection latch clock is adjusted independently, and c0 = 0, c1 = 0, c2 = 0, and c3 = 0, thereby correctly recognizing the edge of the serial data signal.

  The second edge determination logic 25 adjusts the selector 23 and sets the clocks 80 to 83 of the data detection latches 34 to 37 so that the error rate can be minimized. The phase difference between the clocks 80 to 83 and the clocks 70 to 73 of the edge detection latch is set to a half of the effective period of the serial data signal, or from a half thereof to a constant value, a constant rate earlier value, or a later value. Set to. The error rate can be minimized by setting the clocks 80 to 83 of the data detection latches 34 to 37 to be approximately in the middle of the valid period of the serial data signal.

  Further, since the error rate is determined by the minimum value of the phase difference between the clock of the edge detection latch and the clock of the data detection latch written as “worst margin” in FIG. 10, it is necessary to optimize the phases of the clocks of all the data detection latches. Instead, the optimization may be performed by focusing on the clock of the data detection latch sandwiched between adjacent minimum edge detection clock phase differences.

  In the present embodiment, the clocks of the edge detection latch and the data detection latch are selected from 64-phase multiphase clocks and supplied from the selectors 22 and 23. Therefore, the clock phase can be freely optimized, so that the edge of the serial data signal can be recognized correctly. Further, the data detection latch clock can be freely optimized with respect to the edge detection latch clock, so that the error rate can be minimized.

(Example 6)
FIG. 6 is a block diagram showing an overall configuration of a receiving circuit according to the sixth embodiment of the present invention. The reception circuit includes a clock generation circuit 10, a clock distribution circuit 11, 1-bit reception circuits 112 to 115, serial data input signals 90 to 93, and serial data output signals 95 to 98. The 1-bit reception circuit 112 includes a clock distribution circuit 20, a multiphase clock generation circuit 21, selectors 22 and 23, edge determination logics 24 and 25, edge detection latches 30 to 33, data detection latches 34 to 37, an amplifier circuit 29, An alignment circuit 26 and an error rate detection circuit 27 are provided.

  In the configuration of the receiving circuit shown in FIG. 6, an error rate detection circuit 27 is added to FIG. 5 in the fifth embodiment. The error rate detection circuit 27 receives the serial data output signal 95 from the alignment circuit 26, the clock 50 from the clock distribution circuit 20 and the outputs 75 to 78 of the edge detection latch, and uses the output signal 55 as the edge determination logic 24, 25. Output to. Since other configurations are the same as those of the fifth embodiment (FIG. 5), description thereof is omitted.

  The basic operation of the serial signal receiving circuit shown in FIG. 5 will be described with reference to the timing charts of FIGS. The multi-phase clock generation circuit 10 generates a multi-phase clock (600 to 631) that divides the effective period of the serial data signal into 16 equal parts with a period of 4 (= M * 2) times the effective period of the serial data signal. It is necessary to generate a clock of period 4 (M * 2) × divided number 16 phases, but here, half of the 32 phases are generated, and the remaining 32 phases use the former 32 phase inversion logic. Therefore, in FIG. 8, only the first half 32 phases are illustrated.

  Four edge detection latches are provided and driven by clocks 70 to 73, respectively. The clocks 70 to 73 are adjusted so as to be shifted by substantially the same period as the effective period of the serial data signal, but the phase difference can be adjusted independently. Further, the clocks 80 to 83 of the data detection latch are adjusted so as to deviate from the clocks 70 to 73 by approximately ½ of the effective period of the serial data signal, but the phase difference can be adjusted independently. The data alignment circuit aligns the outputs 85 to 88 of the data detection latch and outputs a serial data output signal 95.

  The first edge determination logic 24 detects the valid edge by observing the outputs 85 to 88 of the data detection latch. The first edge determination logic 24 determines whether the edge detection clock is earlier or later than the edge of the serial data signal from the edge detection latch outputs 75 to 78 and the data detection latch outputs 85 to 88 during the edge valid period. .

  FIG. 10 is a timing diagram showing the correlation among the serial data signal, the clock of the edge detection latch, and the clock of the data detection latch. When the phase difference between the clocks 70 to 73 of the edge detection latch is fixed to the same value as the data valid period of the serial data, the first clock of the edge detection latch arrives earlier than the edge of the serial data signal by c0, and the edge detection latch The second, third, and fourth clocks arrive later than the edge of the serial data signal by c1, c2, and c3 (FIG. 10). Here, the edges of the serial data signal are correctly recognized by independently adjusting the clocks of the edge detection latches and setting c0 = 0, c1 = 0, c2 = 0, and c3 = 0.

  The second edge determination logic 25 adjusts the selector 23 and sets the clocks 80 to 83 of the data detection latches 34 to 37 so that the error rate can be minimized. The phase difference between the clocks 80 to 83 and the clocks 70 to 73 of the edge detection latch is set to a half of the effective period of the serial data signal, or from a half thereof to a constant value, a constant rate earlier value, or a later value. Set to. The error rate can be minimized by setting the clocks 80 to 83 of the data detection latches 34 to 37 to be approximately in the middle of the valid period of the serial data signal.

  In order to obtain the phases of the clocks 80 to 83 of the data detection latch and the clocks 70 to 73 of the edge detection latch that minimize the error rate, the following procedure is performed. The first edge determination logic is such that the frequency of the output signal 75 received by the edge detection latch 30 and repeatedly received by the edge detection latch 30 is the same as the frequency before the clock edge and the frequency after the clock edge. 24 adjusts the phase of the clock 70. Whether it is before or after the clock edge is determined by comparing the output signal 75 with the output signals 85 to 88 of the data detection latch. Further, the output signals 85 to 88 of the data detection latch are observed, and the count is not performed when the data does not change before and after the focused edge. Similarly, the clocks 71 to 73 are adjusted.

  Next, similarly to the first edge determination logic 24, the second edge determination logic 25 observes the output signals 75 to 78 and 85 to 88. The phase difference between the clocks 80 to 83 distributed to the data detection latch is a half of the valid period of the serial data signal from the clocks 70 to 73 of the edge detection latch, or a value that is a fixed value or a fixed rate earlier than that half, or a delayed value. Set to be. Subsequently, the same processing is repeated once or more for the signals 80, 81, 82, 83. However, it can be omitted if the error rate measured so far achieves the desired characteristics.

  The error rate detection circuit calculates the error rate by comparing the output of the alignment circuit and the expected value of the error rate detection circuit, and controls the edge determination logics 24 and 25. The error rate can be improved by adjusting the phase difference (a constant value or a constant ratio) between the clocks 70 to 73 and the clocks 80 to 83 of the edge detection latch.

  In this embodiment, an error rate detection circuit is provided, and the reception circuit repeatedly receives a predetermined transmission data string and compares the output of the alignment circuit with the expected value of the error rate detection circuit to calculate the error rate. Next, the phase difference between the clock of each data detection latch and the clock of the edge detection latch is changed to search for a point where the error rate is minimized. According to this embodiment, a receiving circuit with a low error rate of the serial data signal can be obtained.

(Example 7)
FIG. 7 is a block diagram showing an overall configuration of a receiving circuit according to the seventh embodiment of the present invention. The reception circuit includes a clock generation circuit 10, a clock distribution circuit 11, 1-bit reception circuits 112 to 115, serial data input signals 90 to 93, and serial data output signals 95 to 98. The 1-bit reception circuit 112 includes a clock distribution circuit 20, a multiphase clock generation circuit 21, selectors 22 and 23, edge determination logics 24 and 25, edge detection latches 30 to 33, data detection latches 34 to 38, an amplifier circuit 29, An alignment circuit 26 and an error rate detection circuit 27 are provided.

  In the configuration of the receiving circuit shown in FIG. 7, a data detection latch 38 is added to FIG. 6 in the sixth embodiment. A clock 84 for the data detection latch 38 is additionally output from the selector 23. The data detection latch 38 receives the amplifier output signal 99 by the clock 84 and outputs the output 89 to the error rate detection circuit 27. The data detection latch 38 is a redundant data detection latch. An error rate due to a phase difference between the redundant data detection latch and the original data detection latch is determined, and an optimum clock phase is set so as to reduce the error rate. adjust. Redundant data detection latches can be compared with the respective data detection latches to reduce the error rate. Since other configurations are the same as those of the sixth embodiment (FIG. 6), description thereof is omitted.

  The basic operation of the serial signal receiving circuit shown in FIG. 7 will be described with reference to the timing charts of FIGS. The multi-phase clock generation circuit 10 generates a multi-phase clock (600 to 631) that divides the effective period of the serial data signal into 16 equal parts with a period of 4 (= M * 2) times the effective period of the serial data signal. It is necessary to generate a clock of period 4 (M * 2) × divided number 16 phases, but here, half of the 32 phases are generated, and the remaining 32 phases use the former 32 phase inversion logic. FIG. 8 shows only the first half of the 32-phase multiphase clock (600 to 631).

  Four edge detection latches 30 to 33 are provided and driven by clocks 70 to 73, respectively. The clocks 70 to 73 are adjusted so as to be shifted by substantially the same period as the effective period of the serial data signal, but the phase difference can be adjusted independently. Further, the clocks 80 to 83 of the data detection latches 34 to 37 are adjusted so as to deviate from the clocks 70 to 73 by approximately ½ of the effective period of the serial data signal, but the phase difference can be adjusted independently. The data detection latch 38 is a redundant data detection latch for adjustment. The data alignment circuit aligns the outputs 85 to 88 of the data detection latch and outputs a serial data output signal 95.

  The first edge determination logic 24 detects the valid edges by observing the outputs 85 to 88 of the data detection latches 34 to 37. The first edge determination logic 24 determines whether the edge detection clock is earlier or later than the edge of the serial data signal from the edge detection latch outputs 75 to 78 and the data detection latch outputs 85 to 88 during the edge valid period. To do.

  FIG. 10 is a timing diagram showing the correlation among the serial data signal, the clock of the edge detection latch, and the clock of the data detection latch. When the phase difference between the clocks 70 to 73 of the edge detection latches 30 to 33 is fixed to the same value as the data valid period of the serial data, the clock 70 of the first edge detection latch arrives earlier than the edge of the serial data signal by c0. ing. The clocks 71, 72 and 73 of the second, third and fourth edge detection latches arrive later than the edges of the serial data signal by c1, c2 and c3 (FIG. 10). Here, the edges of the serial data signal are correctly recognized by independently adjusting the clocks of the edge detection latches and setting c0 = 0, c1 = 0, c2 = 0, and c3 = 0.

  The second edge determination logic 25 adjusts the selector 23 and sets the clocks 80 to 83 of the data detection latches 34 to 37 so that the error rate can be minimized. The phase difference between the clocks 80 to 83 and the clocks 70 to 73 of the edge detection latch is set to a half of the effective period of the serial data signal, or from a half thereof to a constant value, a constant rate earlier value, or a later value. Set to. The error rate can be minimized by setting the clocks 80 to 83 of the data detection latches 34 to 37 to be approximately in the middle of the valid period of the serial data signal.

  In order to obtain the phase difference between the clocks 80 to 83 of the data detection latch and the clocks 70 to 73 of the edge detection latch that minimize the error rate, the following procedure is performed. First, the first edge determination logic adjusts the phase of the clock 70 so that the output 75 captured by the edge detection latch 30 has the same frequency before the clock and the frequency after the clock. Whether it is before or after the clock is determined by comparing the output 75 of the edge detection latch with the outputs 85 to 88 of the data detection latch. Further, the outputs 85 to 88 are observed, and the count is not performed when the data does not change before and after the focused edge. Similarly, the clocks 71 to 73 are adjusted.

  Next, a data string (not necessarily a predetermined transmission data string) is received. First, the phase range of the clock 84 in which the data detection latch 34 and the redundant data detection latch 38 capture the same value is determined. The error rate detection circuit 27 adjusts the phase of the clock 84 for driving the redundant data detection latch 38 via the second edge determination logic 25 and the second selector 23 to be advanced or delayed. Thus, the error rate detection circuit 27 determines the phase range of the clock 84 in which the data detection latch 34 and the redundant data detection latch 38 capture the same value. The phase of the clock 80 is adjusted to the average value or a phase that is advanced or delayed from the average value by a predetermined value or ratio. This requires a predetermined period.

  Next, the phase range of the clock 84 in which the data detection latch 35 and the redundant data detection latch 38 capture the same value is determined. The phase range of the clock 84 in which the data detection latch 35 and the redundant data detection latch 38 capture the same value is determined by increasing or decreasing the phase of the clock 84 that drives the redundant data detection latch 38. The phase of the clock 81 is adjusted to the average value or a phase that is advanced or delayed from the average value by a predetermined value or ratio. Subsequently, similar processing is performed on the clocks 82 and 83 to update the phases of the clocks 82 and 83. Further, the same processing is repeated once or more for the clocks 80, 81, 82, 83. However, it can be omitted if the error rate measured so far achieves the desired characteristics.

  The clock 84 and redundant data detection latch 38 are operated for a period of time or until the error rate achieves the desired characteristics, but may be stopped thereafter. Alternatively, the phases of the clocks 80 to 83 can be updated so as to improve the error rate degradation caused by temperature change and aging change by performing the above procedure continuously or intermittently.

  In this embodiment, a redundant data detection latch is further provided, and the error rate can be reduced by determining the phase difference between the redundant data detection latch and the original data detection latch and adjusting the optimum clock phase. . According to the present embodiment, a receiving circuit capable of reducing the error rate of the serial data signal can be obtained.

  The receiving circuit of the present invention generates a multi-phase clock from the clock, and selects the multi-phase clock generated from the clocks of the edge detection latch and the data detection latch. The clock of the edge detection latch is adjusted so as to be shifted by substantially the same period as the valid period of the serial data signal. Further, the clock of the data detection latch is adjusted so as to deviate from the clock of the edge detection latch by approximately ½ of the effective period of the serial data signal.

  The M * 2 edge detection latches align with the edges of the serial data signal, and the M * 2 data detection latches latch data at a position approximately half the effective period of the serial data signal. The M * 2 data detection latch fetches data with M * 2 as the cycle, but the error rate is the clock that triggers the data detection for the time gap in which the periodic data appearing in the serial data signal is valid. Adjust to a minimum. The alignment circuit outputs a rearranged output data signal by matching the output of the data detection latch with the data rate of the input serial data signal.

  Furthermore, an error rate detection circuit can be provided. The error rate detection circuit can calculate the error rate by observing the output of the alignment circuit or the output of the data detection latch and the edge detection latch. As described above, the data error rate is obtained by selecting at least M * 2 edge detection latches and data detection latches, and selecting an optimum clock from among the multi-phase clocks for capturing data with M * 2 as a cycle. A small receiving circuit can be obtained.

  The effect of the present invention is that the error rate can be minimized by optimizing the phase of the data clock of the receiving circuit even if a regular waveform shift occurs in the transmission waveform. The second selector of the present invention generates a data clock, but conventionally, the phase is 180 degrees out of phase with the edge first selector. However, in the present invention, the phase of the second selector and the first selector can be freely set, so that the error rate can be optimized.

  In the present invention, since the second selector can also independently adjust the phases of all the clocks supplied to the data latch, it is possible to cope with various deviations in the deviation of the transmission signal from the ideal waveform. Yes, the error rate can be minimized.

  Furthermore, the present invention can provide means for searching for the edge of the data clock that minimizes the error rate using a predetermined training pattern. It is also possible to provide means for searching for the edge of the data clock that minimizes the error rate with redundant latches while performing normal communication.

  In the present invention, the number of clocks can be reduced by outputting a smaller number of clocks than the number of edge detection latches and distributing a signal generated by an inverter (inverted in the case of two-wire logic) to the edge detection latches. Furthermore, it is possible to provide means for independently adjusting the phases of all the clocks distributed to the edge detection latches. Furthermore, it is possible to provide means for independently adjusting the phases of all the clocks distributed to the edge detection latches, and an error rate detection circuit for detecting the error rate while considering the output of the edge detection latch.

  As described above, the present invention has been described as the embodiments and examples, but the present invention is not limited to the above embodiments. Various changes can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 10 Clock generation circuit 11, 20 Clock distribution circuit 12, 13, 14, 15 Inverter 21 Multiphase clock generation circuit 22, 23 Selector 24, 25 Edge determination logic 26 Alignment circuit 27 Error rate detection circuit 29 Amplifier circuit 30, 31, 32 33 Edge detection latches 34, 35, 36, 37, 38 Data detection latches 40, 41, 50 Clock 51, 52 Control signal 55 for selector 55 Output signals 600 to 631 for error rate detection circuit Multiphase clocks 70, 71, 72, 73 Edge detection latch clocks 75, 76, 77, 78 Edge detection latch outputs 80, 81, 82, 83, 84 Data detection latch clocks 85, 86, 87, 88, 89 Data detection latch outputs 90, 91, 92, 93 Serial data input signal 99 Amplifier output signal 95, 6,97,98 serial data output signal 112, 113, 114, and 115 1-bit serial data receiving circuit

Claims (8)

  An amplifier circuit that amplifies the input serial data signal, a circuit that generates a clock, a clock distribution circuit that distributes the clock, and an N-phase clock (N is an integer of 4 or more) from the output of the clock distribution circuit A first selector that outputs the first to M * 2 clocks (M is an integer equal to or greater than 2), and the N phase clock as an input. A second selector that outputs the M * 4th clock, and first to M * 2 edges that use the first to M * 2 clocks as clock inputs and the output of the amplifier circuit as a data input. A detection latch, M * 2 + 1 to M * 4 data detection latches having the M * 2 + 1 to M * 4 clocks as clock inputs and the output of the amplifier circuit as a data input; 2nd M * 2 An output of an edge detection latch, an output of the M * 2 + 1 to M * 4 data detection latches, and an output of the clock distribution circuit are input, and a first control signal is output to control the first selector. The edge determination logic, the output of the first to M * 2 edge detection latches, the output of the M * 2 + 1 to M * 4 data detection latches, and the output of the clock distribution circuit are input. The second edge determination logic that outputs a signal for controlling the second selector, the output of the M * 2 + 1 to M * 4 data detection latches, and the output of the clock distribution circuit are input, and serial data A serial signal receiving circuit comprising: an alignment circuit that outputs an output signal.   Furthermore, an error rate detection circuit and an M * 4 + L (L is an integer equal to or greater than 1) data detection latch are provided, and the M * 4 + L data detection latch is newly output from the second selector. The M * 4 + L clock is supplied as a clock input, the output of the amplifier circuit is used as a data input, and data is output as an output to the error rate detection circuit. The output of the M * 4 + L data detection latch, the output of the clock distribution circuit, and the output of the first to M * 2 edge detection latches are input, and the logic of the first and second edge determination circuit logic is input. The serial signal receiving circuit according to claim 1, further comprising: an error rate detection circuit that outputs a control signal.   Further, the serial data output signal, the output of the clock distribution circuit, and the output of the first to M * 2 edge detection latches are input, and control signals for the first and second edge determination circuit logics are input. The serial signal receiving circuit according to claim 1, further comprising: an error rate detecting circuit that outputs a signal.   The amplifier circuit amplifies the input serial data signal and outputs it as an amplifier output. The multiphase clock generation circuit equally divides the period of M * 2 times (M is an integer of 2 or more) the effective period of the serial data signal. N-phase clock (N is an integer of 4 or more) is generated, and the first edge determination logic detects the outputs of the first to M * 2 edge detection latches and the M * 2 + 1 to M * 4 data detections. From the output of the latch, it is determined whether the edge of the edge detection clock is earlier or later than the edge of the serial data signal, and the first to M * th * of the N-phase clocks are respectively selected so that the difference between them is minimized. The first selector outputs the first to M * 2 edge detection clocks to the first to M * 2 edge detection latches, and the first to first M * 2 edge detection clocks are selected. D of M * 2 Each of the first detection latches captures the amplifier output using the input first to M * 2 edge detection clocks, and the second edge determination logic has the first to M * 2th edge detection logic. From the output of the edge detection latch and the output of the M * 2 + 1 to M * 4 data detection latches, it is determined whether the edge of the data detection clock is earlier or later than the center of the serial data signal, and the difference between the two is the largest. The M * 2 + 1 to M * 4 data detection clocks are selected from the N-phase clocks so as to decrease, and the second selector detects the M * 2 + 1 to M * 4 data detections. The M * 2 + 1 to M * 4 data detection latches are output to the M * 2 + 1 to M * 4 data detection latches, and the M * 2 + 1 to M * 4 data detection latches are respectively input to the input M * 2 + 1 to M * 2th. M * The amplifier output is fetched using the data detection clock, and the alignment circuit aligns the outputs from the M * 2 + 1 to M * 4 data detection latches according to the data rate of the serial data signal, A receiving method characterized by outputting as a serial data output signal.   An amplifier circuit that amplifies the input serial data signal, a circuit that generates a clock, a clock distribution circuit that distributes the clock, and an N-phase clock (N is an integer of 4 or more) from the output of the clock distribution circuit A first selector that inputs the N-phase clock and outputs the first to M-th clocks (M is an integer equal to or greater than 2), and the N-phase clock as an input. A second selector that outputs an M * 3 clock; first to Mth inverters that receive the first to Mth clocks and output M + 1 to M * 2 clocks; The M + 1 to M * 2 inverters that receive the 2 + 1 to M * 3 clocks and output the M * 3 + 1 to M * 4 clocks, and the first to M * 2 clocks as clock inputs. The amplifier circuit The first to M * 2 edge detection latches whose outputs are data inputs, the M * 2 + 1 to M * 4 clocks as clock inputs, and the M * 2 + 1th amplifier circuits whose outputs are data inputs. To the M * 4 data detection latch, the outputs of the first to M * 2 edge detection latches, the outputs of the M * 2 + 1 to M * 4 data detection latches, and the clock distribution circuit A first edge determination logic for outputting a signal for controlling the first selector; an output of the first to M * 2 edge detection latches; and the M * 2 + 1 to M *. And the output of the data detection latch No. 4 and the output of the clock distribution circuit, the second edge determination logic for outputting a signal for controlling the second selector, and the M * 2 + 1 to M * 4th The output of the data detection latch and the clock Click the output of the distribution circuit are inputted, a serial signal reception circuit, wherein the alignment circuit for outputting the serial data output signal, in that it consists of.   An amplifier circuit that amplifies the input serial data signal, a circuit that generates a clock, a clock distribution circuit that distributes the clock, and an N-phase clock (N is an integer of 4 or more) from the output of the clock distribution circuit A first selector that inputs the N-phase clock and outputs the first to M-th clocks (M is an integer equal to or greater than 2), and the N-phase clock as an input. A second selector that outputs an M * 4 clock; first to Mth inverters that receive the first to Mth clocks and output M + 1 to M * 2 clocks; The M + 1 to M * 2 inverters that receive the 2 + 1 to M * 3 clocks and output the M * 3 + 1 to M * 4 clocks, and the first to M * 2 clocks as clock inputs. The amplifier circuit The first to M * 2 edge detection latches whose outputs are data inputs, the M * 2 + 1 to M * 4 clocks as clock inputs, and the M * 2 + 1th amplifier circuits whose outputs are data inputs. To the M * 4 data detection latch, the outputs of the first to M * 2 edge detection latches, the outputs of the M * 2 + 1 to M * 4 data detection latches, and the clock distribution circuit A first edge determination logic for outputting a signal for controlling the first selector; an output of the first to M * 2 edge detection latches; and the M * 2 + 1 to M *. And the output of the data detection latch No. 4 and the output of the clock distribution circuit, the second edge determination logic for outputting a signal for controlling the second selector, and the M * 2 + 1 to M * 4th The output of the data detection latch and the clock Click the output of the distribution circuit are inputted, a serial signal reception circuit, wherein the alignment circuit for outputting the serial data output signal, in that it consists of.   And an error rate detection circuit that receives the serial data output signal and the output of the clock distribution circuit and outputs a control signal of the first and second edge determination circuit logics. The serial signal receiving circuit according to claim 6.   Further, an error rate detection circuit and an M * 4 + L data detection latch (L is an integer equal to or greater than 1) are provided, and the M * 4 + L data detection latch receives the M * 4 + L clock from the second selector. Is supplied as a clock input, the output of the amplifier circuit is used as a data input, and data is output as an output to the error rate detection circuit. The error rate detection circuit includes the M * 2 + 1 to M * 4 + L data detection latches. , An output of the clock distribution circuit, and an output of the first to M * 2 edge detection latches, and output a control signal of the first and second edge determination circuit logic. The serial signal receiving circuit according to claim 6, further comprising a detection circuit.

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