JP2011138243A - Storage device and method for controlling storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a redundant storage device that maintains reliability while improving a data transfer speed and the limited number of rewrites. <P>SOLUTION: The storage device includes systems A and B each configured of a plurality of non-volatile semiconductor elements (NAND-Flash 7) connected to a plurality of buses (buses 0 to 3). The non-volatile semiconductor elements are associated with each other such that when the buses (buses 0 to 3) in the system A connected to the non-volatile semiconductor elements (NAND-Flash 7) are changed, the buses (buses 4 to 7) in the system B connected to the non-volatile semiconductor elements are changed, accordingly. In response to a write request or a read request, the non-volatile semiconductor element (NAND-Flash 7) in one of the systems A and B is selected such that the non-volatile semiconductor element (NAND-Flash 7) connected to the same bus is not repeatedly selected. The non-volatile semiconductor element (NAND-Flash 7) in the other system is selected based on its association with the selected non-volatile semiconductor element (NAND-Flash 7). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a storage device and a control method for the storage device, and more particularly to a storage device suitable for storing data using a nonvolatile semiconductor storage element, and a control method for the storage device.

  The computer is provided with a storage device in order to hold a program to be used for calculation execution or to temporarily store information necessary for the calculation process. As this storage device, a fixed disk is often used, and a nonvolatile semiconductor storage element has come to be used together with the advantage that it is highly resistant to information loss. Although a memory device using this nonvolatile semiconductor memory element has an advantage of non-volatility, however, as with other types of memory devices, it is possible to memorize that information instructed to be written is not normally retained. The possibility of anomalies still remains.

  Therefore, even in a storage device using this nonvolatile semiconductor memory element, multiplexing is performed, and one of the multiplexed systems is used as a main memory, and the remaining system is provided as an auxiliary memory, and a program or temporary There is known a technique for storing retained information in a superimposed manner. In this way, for example, even if an abnormality occurs in the main storage device of the multiplexed system, the calculation can be continued using the storage contents of the auxiliary storage device. Such a technique is known, for example, in Japanese Patent Application Laid-Open No. 2008-123481.

JP 2008-123481 A

  The nonvolatile semiconductor element cannot avoid the problem of the number of rewrites as a characteristic peculiar to the element. That is, when the number of rewrites exceeds the limit number, the reliability of the stored contents is lowered. Therefore, in a semiconductor device having a multiplexed system, if rewriting concentrates on a specific element in any system, a decrease in reliability of the nonvolatile semiconductor element affects the entire system. Even if there is a margin in the number of times of rewriting in the non-volatile semiconductor element of this system, the memory device as a multiplex system is affected.

  Furthermore, the problem of data transfer rate cannot be avoided due to the characteristics peculiar to the element. That is, the speed at which data is written to or read from the storage element (data transfer speed) is lower than the speed at which the data to be written is prepared or the read data is transferred (data transfer speed). Is normal. Therefore, in a semiconductor device having a multiplexed system, if a transfer speed delay occurs in any of the systems, the storage device as a multiplexed system can be used even if the transfer in the other system is performed at the required speed. As a result, the data transfer rate is insufficient.

  An object of the present invention is to provide a storage device using a nonvolatile semiconductor memory element and a storage device having a redundant system and capable of maintaining reliability against the requirement of data transfer speed and the number of rewrites. It is to provide a control method.

  To achieve the above object, according to the present invention, a plurality of systems including a plurality of buses are provided, a plurality of nonvolatile semiconductor elements are connected to each of the plurality of buses, and a first system is connected to the plurality of systems. And the second system, each of the first system nonvolatile semiconductor element and each of the second system nonvolatile semiconductor elements is the first system nonvolatile semiconductor element. Are connected to each other so that the buses to which the second non-volatile semiconductor elements are connected are different when the buses to which the second system is connected are different. The nonvolatile semiconductor element in one of the first system and the second system is selected so that a nonvolatile semiconductor element connected to a different bus is selected between the selection of the nonvolatile semiconductor element and the previous selection of the nonvolatile semiconductor element And the selected nonvolatile semiconductor element Configured to select the non-volatile semiconductor device in the other system on the basis of the association with respect.

  Further, in the above, in response to a write request or a read request, a non-volatile semiconductor element connected to a different bus is selected in a predetermined number of non-volatile semiconductor element selections and a previous non-volatile semiconductor element selection. In this way, the configuration for selecting the nonvolatile semiconductor element in one of the first system and the second system is such that the nonvolatile semiconductor element connected to the same bus continues in response to a write request or a read request. The configuration is replaced with a configuration in which the nonvolatile semiconductor element in one of the first system and the second system is selected so as not to be selected.

  Alternatively, in response to a write request or a read request, a non-volatile semiconductor element connected to a different bus is selected in a predetermined number of non-volatile semiconductor element selections and a previous non-volatile semiconductor element selection. A configuration for selecting a nonvolatile semiconductor element in one of the first system and the second system is to read or write a nonvolatile semiconductor element according to a predetermined selection in response to a write request or a read request. The nonvolatile semiconductor element read or write related to the previous selection is replaced with a configuration in which the selection overlaps at least part of the time.

  According to the present invention, it is possible to maintain the reliability against the requirement of the data transfer rate and the number of rewrites by balancing the redundant systems.

The figure which showed the example of a structure of the non-volatile semiconductor memory device concerning embodiment of this invention. The figure which showed the example of the access timing restriction | limiting of the non-volatile semiconductor element concerning embodiment of this invention. The figure which showed the example of the data area | region of the non-volatile semiconductor element concerning embodiment of this invention, and restrictions of writing and erasing. The figure which showed the process of writing of the head logical address +0 by the structure at the time of setting M = 4 and N = 3 in FIG. The figure which showed the write-in process of the top logical address +1 by the structure at the time of setting M = 4 and N = 3 in FIG. The figure which showed the process of writing of the head logical address +2 by the structure when M = 4 and N = 3 in FIG. The figure which showed the process of writing of the head logical address +3 by the structure when M = 4 and N = 3 in FIG. The figure which showed the process of writing of the head logical address +4 by the structure when M = 4 and N = 3 in FIG. The figure which showed the process of writing of the head logical address +5 by the structure at the time of setting M = 4 and N = 3 in FIG. The figure which showed the process of writing of head logical address +6 by the structure at the time of setting M = 4 and N = 3 in FIG. The figure which showed the process of writing of the head logical address +7 by the structure at the time of setting M = 4 and N = 3 in FIG. The figure which showed the write-in process of the head logical address of the next command with the structure when FIG. 1 is set to M = 4 and N = 3. The figure which showed the example of the flowchart of a chip | tip selection process. The schematic diagram of a chip | tip selection process. The figure of matching of a logical address and a physical address. The figure which showed the process of a read by the structure at the time of setting M = 4 and N = 3 in FIG. The figure which showed the reading process from the buffer in a read by the structure at the time of setting M = 4 and N = 3 in FIG. The figure which showed the time chart of the write access to NAND-Flash7 with respect to the write command from a host. The figure which showed the time chart of the read access to NAND-Flash7 with respect to the read command from a host. The figure which showed another form of the flowchart of a chip | tip selection process. Another schematic diagram of chip selection processing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing an example of the configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention. The nonvolatile semiconductor memory device 2 is connected to the host CPU 1 via a host connection bus. The nonvolatile semiconductor memory device 2 includes a logical address / physical address conversion process 3, a chip selection process 4, a buffer memory 5, a data transfer control unit 6, and a NAND-Flash 7 that is one of the nonvolatile semiconductor memory elements. And buffer 8. The NAND-Flash 7 is generically called a chip or “element”, but it is physically composed of several semiconductors, and includes one that functions as a single chip (“element”). NAND-Flash 7 has a duplex configuration of A and B systems. NAND-Flash 7 is connected by a bus which is a 2M data transfer path from bus 0 to bus 2M-1. N NAND-Flashes 7 are connected to one bus. The non-volatile semiconductor memory device 2 includes M × N × 2 NAND-Flashes 7 for both the A system and the B system. As shown in the figure, the coordinates of NAND-Flash 7 are expressed as chip (0, 0) to chip (2M-1, 2N-1), respectively. The data transfer rate of the buffer memory 5 is sufficiently faster than the data transfer rate of the host connection bus that connects the host CPU 1 and the nonvolatile semiconductor device 2. Further, the data transfer rate of the host connection bus is sufficiently faster than the data transfer rate of the NAND-Flash 7 alone. With this configuration, a bottleneck in data transfer requested from the host is data transfer of the NAND-Flash 7 alone. Data is duplicated by the A system and the B system, and the A system and the B system have a mirror configuration having the same data. This is done by the data transfer control 6 writing the write data from the host to both the A system and the B system. If the data is missing, it is complemented with the opposite data.

  Next, the access timing constraint of NAND-Flash 7 will be described. FIG. 2 is a diagram showing an example of access timing constraints of the nonvolatile semiconductor device according to the embodiment of the present invention. There are three types of NAND-Flash7 access: page write access when data is written, page read access when data is read, and block erase access when data is erased. In page write access, the bus is occupied for the write data transfer time Tw20, the write data is transferred to the NAND-Flash 7, and after the program time Tp21 for occupying the NAND-Flash 7 in units of chips, the write data is actually NAND- Written in Flash7. In the page read access, the read data is read from the NAND-Flash 7 while occupying the bus during the read data transfer time Tr22. In the block erase access, the NAND-Flash 7 is occupied by the chip unit during the erase time Te23 and erased by the block unit.

  Next, the data area and restrictions on writing and erasing will be described. FIG. 3 is a diagram showing an example of the data area and write / erase restrictions of the nonvolatile semiconductor device according to the embodiment of the present invention. The data area of the NAND-Flash 7 is composed of a plurality of blocks 70. One block 70 includes a plurality of pages 71. The page 71 can be written only in ascending order of the page within one block. In addition, data can be erased only for each block.

  Next, processing for a write data transfer request from the host CPU will be described. FIG. 4 is a diagram showing a configuration when M = 4 and N = 3 in FIG. An example will be described in which a head logical address (Logical Address: LA) = 5 and a data size = 8 pages are received as a write command from the host CPU. The bold line in the figure is the data path.

  When the data transfer control unit 6 of the nonvolatile semiconductor memory device 2 receives the write command, the data transfer control unit 6 transfers the write data to the buffer memory 5.

  Next, the data transfer control unit 6 inquires of the chip to be written to the chip selection processing 4. The chip selection process 4 selects a chip and returns the coordinates of the selected chip to the data transfer control unit 6. FIG. 4 shows a case where the data transfer control unit 6 responds from the chip selection process 4 with (0, 0) as the A system chip and (4, 0) as the B system chip.

  FIG. 13 shows an example of a flowchart of the chip selection process 4. Chip selection is started at S0. Let (x, y) be the coordinates of the A-system chip previously selected in S1. In S2, it is determined whether the bus has been completed. If x does not match M−1, it is assumed that the bus has not been reached, and the process of S3 is performed. If x is equal to M−1, it is considered that the circuit has made a complete round of the bus, and the process of S6 is performed. In S3, it is considered that the bus has not been completed, and x is updated to x + 1. In S4, (x, y) is selected as the A system chip, the B system is the A system mirror, and (x + M, y) is selected as the B system chip. In S5, the chip selection is completed, and the coordinate of the selected chip is returned to the data transfer control unit 6. In S6, it is considered that the bus has been completed and x is updated to 0. Next, in S7, it is determined whether all the chips have been completed. If y does not match N−1, it is considered that all the chips have not been made, and the process of S8 is performed. If y is equal to N-1, it is considered that all the chips have made a round, and the process of S9 is performed. In S8, it is considered that all the chips have not been made, and y is updated to y + 1. Thereafter, the processes of S4 and S5 described above are performed. In S9, it is considered that all the chips have made a round and y is updated to 0. Thereafter, the processes of S4 and S5 described above are performed.

  Next, the data transfer control unit 6 outputs the coordinates and the logical address of the selected A-system chip to the logical address / physical address conversion process 3, and the physical address is returned from the logical address / physical address conversion process 3. The physical address is a chip coordinate, a NAND-Flash7 block (number) 70, and a page (number) 71, and is an address that designates a physical data storage area of the NAND-Flash7. The logical address / physical address conversion process 3 manages the correspondence between logical addresses and physical addresses. The data transfer control unit 6 performs page write access to the NAND-Flash using the physical address returned from the logical address / physical address conversion processing 3. FIG. 4 shows a process of writing the data of the first logical address (LA = 5) to (0, 0) and (4, 0) among the eight pages of the command request.

  FIG. 5 shows the write processing of the logical address (LA = 6) of the first logical address + 1. The data transfer control unit 6 inquires of the chip to be written to the chip selection processing 4 while storing the write data from the host CPU 1 in the buffer memory 5.

  FIG. 13 shows an example of a flowchart of the chip selection process 4. Chip selection is started at S0. The coordinates of the A-system chip selected last in S1 are set to (0, 0). In S2, it is determined whether the bus has been completed. Since x = 0 does not coincide with M-1 = 3, it is considered that the circuit does not make a round of the bus, and the process of S3 is performed. In S3, it is considered that the bus has not been made, and (0, 0) is updated to (1, 0). At S4, (1, 0) is selected as the A system chip, the B system is an A system mirror, and (1 + 4 = 5, 0) is selected as the B system chip. In S5, the chip selection is completed, and the data transfer control unit 6 responds with the selected system coordinates of (1, 0) of the A system and (5, 0) of the B system.

  The data transfer control unit 6 outputs the coordinates and the logical address of the selected A-system chip to the logical address / physical address conversion process 3, and the physical address is returned from the logical address / physical address conversion process 3. FIG. 5 shows a process of writing the data of the logical address (LA = 6) of the first logical address + 1 in (1, 0) and (5, 0) among the eight pages of the command request.

  FIG. 6 shows a write process for the logical address (LA = 7) of the first logical address + 2. The data transfer control unit 6 inquires of the chip to be written to the chip selection processing 4 while storing the write data from the host CPU 1 in the buffer memory 5.

  FIG. 13 shows an example of a flowchart of the chip selection process 4. Chip selection is started at S0. It is assumed that the coordinates of the A-system chip previously selected in S1 are (1, 0). In S2, it is determined whether the bus has been completed. Since x = 1 does not coincide with M-1 = 3, it is considered that the circuit does not make a round of the bus, and the process of S3 is performed. In S3, it is assumed that the bus has not been made, and (1, 0) is updated to (2, 0). In S4, (2, 0) is selected as the A system chip, the B system is the A system mirror, and (2 + 4 = 6, 0) is selected as the B system chip. In S5, the chip selection is finished, and the data transfer control unit 6 responds with the selected system coordinates of (2,0) of the A system and (6,0) of the B system.

  The data transfer control unit 6 outputs the coordinates and the logical address of the selected A-system chip to the logical address / physical address conversion process 3, and the physical address is returned from the logical address / physical address conversion process 3. FIG. 6 shows a process of writing the data of the logical address (LA = 7) of the top logical address + 2 to (2, 0), (6, 0) among the eight pages of the command request.

  Write processing of the logical address (LA = 8) of the head logical address + 3 is shown in FIG. The data transfer control unit 6 inquires of the chip to be written to the chip selection processing 4 while storing the write data from the host CPU 1 in the buffer memory 5.

  FIG. 13 shows an example of a flowchart of the chip selection process 4. Chip selection is started at S0. It is assumed that the coordinates of the A-system chip previously selected in S1 are (2, 0). In S2, it is determined whether the bus has been completed. Since x = 2 does not coincide with M-1 = 3, it is considered that the circuit does not make a round of the bus, and the process of S3 is performed. In S3, it is assumed that the bus has not been made, and (2,0) is updated to (3,0). At S4, (3,0) is selected as the A-system chip, B-system is the A-system mirror, and (3 + 4 = 7,0) is selected as the B-system chip. In S5, the chip selection is completed, and A (3, 0) of the A system and (7, 0) of the B system are returned to the data transfer control unit 6 as the coordinates of the selected chip. The data transfer control unit 6 outputs the coordinates and the logical address of the selected A-system chip to the logical address / physical address conversion process 3, and the physical address is returned from the logical address / physical address conversion process 3. FIG. 7 shows a process of writing the data of the logical address (LA = 8) of the top logical address + 3 to (3, 0), (7, 0) among the eight pages of the command request.

  Write processing of the logical address (LA = 9) of the head logical address + 4 is shown in FIG. The data transfer control unit 6 inquires of the chip to be written to the chip selection processing 4 while storing the write data from the host CPU 1 in the buffer memory 5.

  FIG. 13 shows an example of a flowchart of the chip selection process 4. Chip selection is started at S0. The coordinates of the A-system chip selected last time in S1 are set to (3, 0). In S2, it is determined whether the bus has been completed. Since x = 3 coincides with M−1 = 3, it is considered that the circuit has made a round of the bus, and the process of S6 is performed. In S6, it is considered that the bus has been completed, and (3, 0) is updated to (0, 0). Next, in S7, it is determined whether all the chips have been completed. Since y = 0 coincides with N-1 = 2, it is considered that all the chips have not been made, and the process of S8 is performed. In S8, it is considered that all the chips have not been made, and (0, 0) is updated to (0, 1). In S4, (0, 1) is selected as the A system chip, the B system is the A system mirror, and (0 + 4 = 4, 1) is selected as the B system chip. In S5, the chip selection is completed, and the data transfer control unit 6 responds with the selected system coordinates of the selected system as (0, 1) and B system (4, 1). The data transfer control unit 6 outputs the coordinates and the logical address of the selected A-system chip to the logical address / physical address conversion process 3, and the physical address is returned from the logical address / physical address conversion process 3. FIG. 7 shows a process of writing the data of the logical address (LA = 9) of the top logical address +4 to (0, 1) and (4, 1) among the 8 pages of the command request.

  FIG. 9 shows the write processing of the logical address (LA = 10) of the first logical address + 5. The data transfer control unit 6 inquires of the chip to be written to the chip selection processing 4 while storing the write data from the host CPU 1 in the buffer memory 5.

  FIG. 13 shows an example of a flowchart of the chip selection process 4. Chip selection is started at S0. The coordinates of the A-system chip selected last time in S1 are (0, 1). In S2, it is determined whether the bus has been completed. Since x = 0 does not coincide with M-1 = 3, it is considered that the circuit has not made a round of the bus, and the process of S3 is performed. In S3, it is assumed that the bus has not been made, and (0, 1) is updated to (1, 1). In S4, (1, 1) is selected as the A system chip, the B system is an A system mirror, and (1 + 4 = 5, 1) is selected as the B system chip. In S5, the chip selection is completed, and the data transfer control unit 6 responds with the selected system coordinates of the selected system as (1, 1) of the A system and (5, 1) of the B system. The data transfer control unit 6 outputs the coordinates and the logical address of the selected A-system chip to the logical address / physical address conversion process 3, and the physical address is returned from the logical address / physical address conversion process 3. FIG. 9 shows the process of writing the data of the logical address (LA = 10) of the top logical address +5 to (1, 1) and (5, 1) among the eight pages of the command request.

  FIG. 10 shows the write processing of the logical address (LA = 11) of the first logical address + 6. The data transfer control unit 6 inquires of the chip to be written to the chip selection processing 4 while storing the write data from the host CPU 1 in the buffer memory 5.

  FIG. 13 shows an example of a flowchart of the chip selection process 4. Chip selection is started at S0. Let the coordinates of the A-system chip selected last time in S1 be (1, 1). In S2, it is determined whether the bus has been completed. Since x = 1 does not coincide with M-1 = 3, it is considered that the circuit does not make a round of the bus, and the process of S3 is performed. In S3, it is assumed that the bus has not been made, and (1,1) is updated to (2,1). In S4, (2, 1) is selected as the A system chip, the B system is the A system mirror, and (2 + 4 = 6, 1) is selected as the B system chip. In S5, the chip selection is terminated, and the data transfer control unit 6 responds with the selected system coordinates of the selected system as (2, 1) of the A system and (6, 1) of the B system. The data transfer control unit 6 outputs the coordinates and the logical address of the selected A-system chip to the logical address / physical address conversion process 3, and the physical address is returned from the logical address / physical address conversion process 3. FIG. 10 shows a process of writing the data of the logical address (LA = 11) of the top logical address +6 to (2, 1) and (6, 1) among the eight pages of the command request.

  FIG. 11 shows a write process of the logical address (LA = 12) of the top logical address + 7. The data transfer control unit 6 inquires of the chip to be written to the chip selection processing 4 while storing the write data from the host CPU 1 in the buffer memory 5.

  FIG. 13 shows an example of a flowchart of the chip selection process 4. Chip selection is started at S0. Let the coordinates of the A-system chip selected last time in S1 be (2, 1). In S2, it is determined whether the bus has been completed. Since x = 2 does not coincide with M-1 = 3, it is considered that the circuit does not make a round of the bus, and the process of S3 is performed. In S3, it is assumed that the bus has not been made, and (2,1) is updated to (3,1). In S4, (3, 1) is selected as the A system chip, the B system is the A system mirror, and (3 + 4 = 7, 1) is selected as the B system chip. In S5, the chip selection is completed, and the data transfer control unit 6 responds with the selected system coordinates of the selected system as (3, 1) and B system (7, 1).

  The data transfer control unit 6 outputs the coordinates and the logical address of the selected A-system chip to the logical address / physical address conversion process 3, and the physical address is returned from the logical address / physical address conversion process 3. FIG. 11 shows a process of writing the data of the logical address (LA = 12) of the top logical address +7 to (3, 1) and (7, 1) among the eight pages of the command request. This process completes the transfer for the data size requested by the command.

  FIG. 12 shows the processing of the start logical address (LA = LA + X) of the next write command. The data transfer control unit 6 inquires of the chip to be written to the chip selection processing 4 while storing the write data from the host CPU 1 in the buffer memory 5. FIG. 13 shows an example of a flowchart of the chip selection process 4. Chip selection is started at S0. Let the coordinates of the A-system chip selected last time in S1 be (3, 1). In S2, it is determined whether the bus has been completed. Since x = 3 coincides with M−1 = 3, it is considered that the circuit has made a round of the bus, and the process of S6 is performed. In S6, it is considered that the bus has been completed and (3, 1) is updated to (0, 1). Next, in S7, it is determined whether all the chips have been completed. Since y = 1 coincides with N-1 = 2, it is considered that all the chips have not been made, and the process of S8 is performed. In S8, it is considered that all the chips have not been made, and (0, 1) is updated to (0, 2). In S4, (0, 2) is selected as the A system chip, the B system is an A system mirror, and (0 + 4 = 4, 2) is selected as the B system chip. In S5, the chip selection is completed, and the data transfer control unit 6 responds with the selected system coordinates (A, (0, 2) and B system (4, 2)). The data transfer control unit 6 outputs the coordinates and the logical address of the selected A-system chip to the logical address / physical address conversion process 3, and the physical address is returned from the logical address / physical address conversion process 3. FIG. 12 shows a process in which the data of the first logical address (LA = LA + X) of the next command is written to (0, 2), (4, 2).

  In this way, the chip selection process 4 selects the NAND-Flash 7 according to the coordinates of the previously selected chip regardless of whether or not it is within the command range. The logical addresses are continuous within the command range, and the order of the consecutive logical addresses matches the order of the selected NAND-Flash 7.

  FIG. 14 shows a schematic diagram of the chip selection process. The previously selected NAND-Flash 7 chip is indicated by a thick arrow, and the selected NAND-Flash 7 chip is indicated by the tip of the thick arrow. The A system and the B system are mirrors, and the B system chip always selects (x + M, y) for the coordinates (x, y) of the A system chip in the light. That is, the data (x, y) and (x + M, y) match. Regardless of the logical address, the chip to be selected is updated every write access to make a uniform round.

  FIG. 15 shows the correspondence between logical addresses and physical addresses recognized by the logical address / physical address conversion process. This shows a state after writing logical addresses (LA = 5 to 8, LA + X) from FIG. 4 to FIG. The logical address is associated with coordinates X, coordinates Y, block numbers, and page numbers of the NAND-Flash7 chip as physical addresses. The logical address / physical address conversion process 3 assigns a block number and a page number to the logical address and chip coordinates output by the data transfer control 6 according to the use status of the block and page.

  Next, processing for a read data transfer request from the host CPU will be described. FIG. 16 shows processing when a head logical address (LA = 5) and data size = 8 pages are received as commands from the host CPU. The bold line in the figure is the data path.

  When the data transfer control unit 6 of the nonvolatile semiconductor memory device 2 receives the read command, the data transfer control unit 6 inquires of the logical address / physical address conversion processing 3 about the physical address corresponding to the logical address.

  The data transfer control unit 6 inquires the logical address / physical address conversion processing 3 about the physical address of the head logical address = 5. The logical address / physical address conversion process 3 responds with chip coordinates (0, 0), block number 1, and page number 1 as physical addresses in accordance with the correspondence between logical addresses and physical addresses in FIG. The data transfer control unit 6 requests page read of the first logical address = 5 with this physical address.

  Next, the data transfer control unit 6 inquires of the logical address / physical address conversion processing 3 about the physical address of the logical address = 6 of the first logical address + 1. The logical address / physical address conversion process 3 responds with chip coordinates (1, 0), block number 1, and page number 1 as physical addresses in accordance with the correspondence between the logical addresses and physical addresses in FIG. The data transfer control unit 6 requests a page read of the logical address = 6 with this physical address.

  Next, the data transfer control unit 6 inquires of the logical address / physical address conversion processing 3 about the physical address of logical address = 7 of the head logical address + 2. The logical address / physical address conversion process 3 responds with chip coordinates (2, 0), block number 1, and page number 1 as physical addresses in accordance with the correspondence between the logical addresses and physical addresses in FIG. The data transfer control unit 6 requests a page read of the logical address = 6 with this physical address.

  Next, the data transfer control unit 6 inquires the logical address / physical address conversion processing 3 about the physical address of the logical address = 8 of the head logical address + 3. The logical address / physical address conversion process 3 responds with chip coordinates (3, 0), block number 1, and page number 1 as physical addresses in accordance with the correspondence between the logical addresses and physical addresses in FIG. The data transfer control unit 6 requests a page read of the logical address = 6 with this physical address.

  Next, the data transfer control unit 6 inquires of the logical address / physical address conversion processing 3 about the physical address of the logical address = 9 of the top logical address + 4. The logical address / physical address conversion process 3 responds with chip coordinates (0, 1), block number 1, and page number 1 as physical addresses in accordance with the correspondence between the logical addresses and physical addresses in FIG. The data transfer control unit 6 has already requested a page read to the chip coordinate (0, 0), recognizes that the bus 0 is occupied, and performs a page read to the B system (4, 1). Request.

  Next, the data transfer control unit 6 inquires of the logical address / physical address conversion processing 3 about the physical address of the logical address = 10 of the first logical address + 5. The logical address / physical address conversion process 3 responds with the chip coordinates (1, 1), the block number 1, and the page number 1 as the physical address in accordance with the correspondence between the logical address and the physical address in FIG. The data transfer control unit 6 has already requested a page read to the chip coordinate (1, 0), recognizes that the bus 1 is occupied, and performs a page read to the B system (5, 1). Request.

  Next, the data transfer control unit 6 inquires of the logical address / physical address conversion processing 3 about the physical address of the logical address = 11 of the first logical address + 6. The logical address / physical address conversion process 3 responds with chip coordinates (2, 1), block number 1, and page number 1 as physical addresses in accordance with the correspondence between the logical addresses and physical addresses in FIG. The data transfer control unit 6 has already requested a page read to the chip coordinate (1, 0), recognizes that the bus 2 is occupied, and performs a page read to the B system (6, 1). Request.

  Next, the data transfer control unit 6 inquires of the logical address / physical address conversion processing 3 about the physical address of the logical address = 12 of the head logical address + 7. The logical address / physical address conversion process 3 responds with chip coordinates (3, 1), block number 1, and page number 1 as physical addresses in accordance with the correspondence between the logical addresses and physical addresses in FIG. The data transfer control unit 6 has already requested a page read to the chip coordinate (3, 0), recognizes that the bus 3 is occupied, and performs a page read to the B system (7, 1). Request.

  Thus, by making a round of NAND-Flash 7 by chip selection at the time of writing, it is not necessary to wait for the bus in page read of 2 × M pages within the range of the logical address of the write request from the host.

  FIG. 20 shows another form of the chip selection process. In FIG. 13, the B system chip selects (x + M, y) in the process of S4, but in FIG. 20, the B system chip is selected (2M-1-x, 2N-1-y) in the process of S40. I am doing so. FIG. 21 shows a schematic diagram of the chip selection process in the case of such changes. The previously selected NAND-Flash 7 chip is indicated by a thick arrow, and the selected NAND-Flash 7 chip is indicated by the tip of the thick arrow. The A system and the B system are mirrors, and the B system chip always selects (2M-1-x, 2N-1-y) for the coordinates (x, y) of the A system chip in the light. Even in such a case, it is not necessary for the data transfer control unit 6 to wait for the bus in the page read for 2 × M pages by following the correspondence between the A system and the B system. As shown in another form of the chip selection process in FIG. 20, if the conditions for updating N and M are matched, the A system and the B system do not need to be physically perfect mirrors.

  FIG. 17 shows a process in which the data transfer control unit 6 requests page read and stores the read data in the buffer memory and reads it from the buffer memory. The data transfer control unit 6 requests the NAND-Flash 7 to perform page read and transfers the read data to the buffer memory 5 while transferring the read data from the buffer memory 5 to the host CPU 1 via the host connection bus.

  FIG. 18 shows a time chart of write access to the NAND-Flash 7 in response to a write command from the host. This shows a case where 24 pages are written from the chip (0, 0) with M = 4 and N = 3. The write access to the NAND-Flash 7 has the page write access timing constraint shown in FIG.

  Assuming that the data transfer delay time passing through the buffer memory 5 is Td, if the write data transfer time Tw20 occupying the bus is smaller than Td × M, it is not necessary to wait for the bus when it makes a circuit. As a configuration of the nonvolatile semiconductor device, one of the conditions for securing the write performance is to make M larger than Tw ÷ Td.

  Further, if the sum of the program times Tp21 and Tw20 that occupy the chip is smaller than Td × M × N, it is not necessary to wait for the chip when it makes a round. As a configuration of the nonvolatile semiconductor device, one of the conditions for securing the write performance is to make M × N larger than (Tp + Tw) ÷ Td.

  Further, under the above conditions, if the data transfer rate indicated by page data size / Td is larger than the transfer rate of the host connection bus, the bottleneck is no longer a nonvolatile semiconductor device except for processing such as block erase.

  FIG. 19 shows a time chart of read access to the NAND-Flash 7 in response to a read command from the host. This shows a case where 48 pages are written from the chip (0, 0) with M = 4 and N = 3. The read access to the NAND-Flash 7 has the page read access timing constraint shown in FIG. Assuming that the data transfer delay time via the buffer memory is Tt, the data transfer speed represented by 2 × M × page data size / (Tt + Tr) is obtained from the transfer speed of the host connection bus connecting the host CPU 1 and the nonvolatile semiconductor device 2. Is large, the bottleneck is not a nonvolatile semiconductor device except for the time until the first read data output.

1 Host CPU
2 Nonvolatile semiconductor memory device 3 Logical address / physical address conversion process 4 Chip selection process 5 Buffer memory 6 Data transfer control unit 7
20 Tw (write data transfer time)
21 Tp (program time)
22 Tr (read data transfer time)
23 Te (erasing time)
70 blocks 71 pages

Claims (10)

  A plurality of systems including a plurality of buses, a plurality of nonvolatile semiconductor elements connected to each of the plurality of buses, the plurality of systems including a first system and a second system; Each of the first system nonvolatile semiconductor elements and each of the second system nonvolatile semiconductor elements are different from each other if the bus to which the first system nonvolatile semiconductor elements are connected is different. The buses to which the non-volatile semiconductor elements of the system are connected are differently associated with each other, and a predetermined number of non-volatile semiconductor elements are selected and the previous non-volatile semiconductor element is selected in response to a write request or a read request. And selecting a non-volatile semiconductor element in one of the first system and the second system so that a non-volatile semiconductor element connected to a different bus is selected, and for the selected non-volatile semiconductor element Based on the correspondence, the other Storage devices and selects the non-volatile semiconductor device in.   2. The memory device according to claim 1, wherein a chip address is assigned to each of the nonvolatile semiconductor elements, and the current chip address is selected based on the previous chip address selection.   3. The nonvolatile semiconductor element according to claim 2, wherein each of the nonvolatile semiconductor elements is provided with a physical address that physically specifies the element including information corresponding to the chip address, and the logical address is used for the selection of the nonvolatile semiconductor element. A storage device that stores information associating logical addresses with physical addresses based on a table.   4. If there is an abnormality in the non-volatile semiconductor element of one of the first system and the second system selected last time, the information of the non-volatile semiconductor element of the other system is substituted. And a storage device.   2. The bus code for identifying a bus and an element identification code for identifying one of the nonvolatile semiconductor elements connected to the bus are attached to each of the nonvolatile semiconductor elements, and the bus code and A non-volatile semiconductor element to be selected is specified by changing the element specifying code.   6. The storage device according to claim 5, wherein the bus code is changed after a time required for reading the nonvolatile semiconductor element elapses.   7. The method according to claim 6, wherein reading of the non-volatile semiconductor element with respect to one of the first system and the second system is completed, and then reading of the next non-volatile semiconductor element is started. Storage device.   A plurality of systems including a plurality of buses, a plurality of nonvolatile semiconductor elements connected to each of the plurality of buses, the plurality of systems including a first system and a second system; Each of the first system nonvolatile semiconductor elements and each of the second system nonvolatile semiconductor elements are different from each other if the bus to which the first system nonvolatile semiconductor elements are connected is different. Non-volatile semiconductor elements connected to the same bus in response to a write request or a read request in response to a write request or a read request A non-volatile semiconductor element in one of the first system and the second system is selected so that is not continuously selected.   A plurality of systems including a plurality of buses, a plurality of nonvolatile semiconductor elements connected to each of the plurality of buses, the plurality of systems including a first system and a second system; Each of the first system nonvolatile semiconductor elements and each of the second system nonvolatile semiconductor elements are different from each other if the bus to which the first system nonvolatile semiconductor elements are connected is different. The buses to which the non-volatile semiconductor elements of the system are connected are different from each other, and in response to a write request or a read request, the read or write of the non-volatile semiconductor element according to the predetermined selection and the previous selection are performed. A memory device, wherein the predetermined number of times of selection is performed so that reading or writing of the nonvolatile semiconductor element overlaps at least in part of time.   In each of the first system and the second system configured to connect a plurality of nonvolatile semiconductor elements to each of the plurality of buses, each of the first system nonvolatile semiconductor elements and the second system Each of the nonvolatile semiconductor elements is associated with each other so that if the bus to which the first nonvolatile semiconductor element is connected is different, the bus to which the second nonvolatile semiconductor element is connected is different. In response to a write request or a read request, the nonvolatile semiconductor element connected to a different bus is selected in the predetermined selection of the nonvolatile semiconductor element and the previous selection of the nonvolatile semiconductor element. Memory for selecting a nonvolatile semiconductor element in one of the first system and the second system and selecting a nonvolatile semiconductor element in the other system based on the association with the selected nonvolatile semiconductor element Equipment Your way.

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