JP2011135413A - Peak holding circuit, and output voltage control circuit including the peak holding circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for making compact an output voltage control circuit which controls the output voltage of a power supply circuit, supplying an operating voltage to a speaker amplifier, in accordance with the operation state of the speaker amplifier. <P>SOLUTION: The peak holding circuit, included in an output voltage control circuit which performs operation control over the power supply which is supplied with a plus voltage BVDD and a ground voltage VSS, and supplies the potential difference between the plus voltage VPP and minus voltage VMM to each speaker amplifier as the operating voltage, includes first and second P-channel FETs which are supplied at drains thereof with an output voltage VMM and applied at gates thereof with output voltages of respective speaker amplifiers, and a third P-channel FET which is supplied at the drain and gate thereof with the ground voltage VSS, as three P-channel FETs (field-effect transistors) having sources thereof connected in common, and outputs a voltage generated at the common connection point of the sources thereof. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for controlling an output voltage of a power supply circuit capable of adjusting an output voltage such as a charge pump.

  A charge pump may be used as a power supply circuit that shares an operating voltage with an amplifier that drives a speaker included in a headphone stereo or a mobile phone (see, for example, Patent Document 1). Since the charge pump can adjust the output voltage, the power applied to the entire system should be kept low by adjusting the voltage applied to the amplifier according to the signal level of the amplifier output signal and input signal. Because you can. For such adjustment of the output voltage, an output voltage control circuit (see FIGS. 8A to 8C) including a so-called peak hold circuit is often used.

  8A to 8C show output control of the power supply circuit 20 that outputs the high potential side voltage VPP and the low potential side voltage VMM to each of the amplifiers 30L and 30R (more precisely, the high potential side voltage VPP). It is a figure which shows the structural example of the output voltage control circuit which performs (output control). For example, in the output voltage control circuit shown in FIG. 8A, the comparator 612 compares the output signal OUTL of the amplifier 30L that drives the left channel speaker 40L and the output signal OUTR of the amplifier 30R that drives the right channel speaker 40R. The switch 614 is switched according to the comparison result. In the output voltage control circuit shown in FIG. 8A, the switch 614 is switched so that the larger one of the signals OUTL and OUTR is output as the signal N1. That is, in the configuration illustrated in FIG. 8A, the peak hold circuit is formed by the comparator 612 and the switch 614. The operational amplifier 616 in FIG. 8A generates a control signal CVPP corresponding to the level difference between the high-potential-side output voltage VPP of the power supply circuit 20 and the signal N1 (that is, VPP−N1) and outputs it to the power supply circuit 20. Therefore, if the power supply circuit 20 is caused to adjust the high-potential-side output voltage VPP so that the signal level of the control signal CVPP becomes small, the high-potential-side output voltage VPP is obtained from the amplifiers 30L and 30R. It follows the larger one of the output signals OUTL and OUTR.

  The configuration of the output voltage control circuit shown in FIG. 8B is obtained by adding a resistor 618 and a constant current source 620 to the output voltage control circuit shown in FIG. In FIG. 8B, illustration of a power supply circuit to be controlled by the output voltage control circuit and an amplifier that receives an operating voltage shared from the power supply circuit is omitted. The resistor 618 and the constant current source 620 in FIG. 8B form a peak hold circuit together with the comparator 612 and the switch 614. As shown in FIG. 8B, the resistor 618 and the constant current source 620 are inserted in series between the switch 614 and the ground, and the voltage appearing at the common connection point of the resistor 618 and the constant current source 620 is a signal. N1 is given to the operational amplifier 616. The signal N1 has a value obtained by subtracting an offset (R × I) corresponding to the current value I of the constant current source 620 and the resistance value R of the resistor 618 from the signal N2 (the larger one of the signal OUTL and the signal OUTR). . Therefore, according to the output voltage control circuit shown in FIG. 8B, the power supply circuit according to the level difference (VPP−N1) between the high potential side output voltage VPP of the power supply circuit and the signal N1 (N2−R × I). The output control is performed.

  The configuration of the output voltage control circuit in FIG. 8C is obtained by adding a comparator 622 and a switch 624 to the output voltage control circuit shown in FIG. The comparator 622 and the switch 624 in FIG. 8C form a peak hold circuit together with the comparator 612, the switch 614, the resistor 618, and the constant current source 620. In the comparator 622 in FIG. 8C, the signal N3 (the larger one of the signals OUTL and OUTR) is compared with the ground potential VSS, and the switch 624 is switched according to the comparison result. Specifically, the switch 624 is switched so that the larger one of the signal N3 and the ground potential VSS is output as the signal N2. The subsequent operation is the same as the operation of the output voltage control circuit shown in FIG.

JP 2008-306269 A

However, the output voltage control circuit shown in each of FIGS. 8A to 8C includes a comparator and a switch in the peak hold circuit that forms the main part thereof. Since the comparator and the switch have a relatively large circuit area, there is a problem that the circuit area of the peak hold circuit having these as a constituent element becomes large, and it is difficult to reduce the size of the output voltage control circuit.
The present invention has been made in view of the above problems, and is an output voltage control for controlling an output voltage of a power supply circuit that supplies an operating voltage to a power amplifier circuit such as a speaker amplifier in accordance with an operating state of the power amplifier circuit. An object of the present invention is to provide a technique that enables a circuit to be miniaturized.

  In order to solve the above problems, the present invention provides a first field effect transistor in which a drain and a gate are connected in common and a first voltage is applied to the common connection point, and a second voltage is applied to each drain. Second and third field effect transistors that are applied to the respective gates, and third and fourth voltages whose voltage values fluctuate around the first voltage are applied to the respective gates. The sources of the first, second, and third field effect transistors are connected in common, and a peak hold circuit that outputs a voltage that appears at the common connection point is provided.

  In each of the second and third field effect transistors included in the peak hold circuit of the present invention, the drain voltage is fixed to the second voltage, and the input voltage applied to each gate (ie, the third or third field effect transistor). An output voltage corresponding to the fourth voltage) appears at the source. On the other hand, the drain voltage and the gate voltage of the first field effect transistor are fixed to the first voltage, and a voltage corresponding to the gate voltage always appears at the source. Since the sources of the first, second and third field effect transistors are connected in common, if the three field effect transistors are all N-channel field effect transistors, the first, third and fourth A voltage corresponding to the largest one of the voltages appears at the common connection point of the sources of these three field effect transistors. On the other hand, if these three field effect transistors are all P-channel field effect transistors, the voltage corresponding to the smallest of the first, third, and fourth voltages is the three field effect transistors. Appear at the common connection point of the source. As described above, according to the peak hold circuit of the present invention, the maximum (or minimum) of the three voltages to be compared (the first, third, and fourth voltages) without using a switch or a comparator. It is possible to output a voltage that follows the above. As another aspect of the present invention, an aspect in which an output voltage control circuit including the peak hold circuit as a component is provided is also conceivable.

1 is a block diagram illustrating a configuration example of a speaker system 1 including an output voltage control circuit 10 according to an embodiment of the present invention. 3 is a diagram illustrating an example of output control by the output voltage control circuit 10. FIG. 3 is a block diagram showing a configuration example of a VPP control circuit 110 of the output voltage control circuit 10. FIG. 3 is a block diagram showing a configuration example of a VMM control circuit 120 of the output voltage control circuit 10. FIG. It is a figure which shows the variation of the combination of the operating voltage of a VPP control circuit or a VMM control circuit. It is a block diagram which shows the structural example of the VMM control circuit of another structure. It is a block diagram which shows the structural example of the VPP control circuit of another structure. It is a figure which shows the structural example of the conventional output voltage control circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(A: Configuration)
FIG. 1 is a block diagram illustrating a configuration example of a speaker system 1 including an output voltage control circuit 10 according to an embodiment of the present invention. The speaker system 1 is incorporated in, for example, a mobile phone or a portable game terminal and reproduces sound under the control of a host CPU (not shown). As shown in FIG. 1, a speaker system 1 includes speakers 40L and 40R for left and right channels, amplifiers 30L and 30R that drive the speakers, a power supply circuit 20 that supplies operating voltages to the amplifiers, and the power supply circuit. 20 and an output voltage control circuit 10 for performing output control. Hereinafter, when it is not necessary to distinguish each of the speakers 40L and 40R, it is abbreviated as “speaker 40”, and when it is not necessary to distinguish between each of the amplifiers 30L and 30R, it is abbreviated as “amplifier 30”. .

  The power supply circuit 20 is a church pump, for example, and has a configuration capable of switching the output voltage. The power supply circuit 20 outputs a first external power supply (not shown in FIG. 1) that outputs a positive voltage BVDD (for example, 1.8 [V]) and a voltage VSS (for example, 0 [V]). 2 is connected to an external power source (grounded in the present embodiment: not shown in FIG. 1), and generates a high potential side output voltage VPP and a low potential side output voltage VMM under the control of the output voltage control circuit 10. . In the present embodiment, the voltage difference between the voltages VPP and VMM becomes the operating voltage of the amplifier 30.

  The amplifier 30 is supplied with the high-potential-side output voltage VPP and the low-potential-side output voltage VMM from the power supply circuit 20, amplifies the input audio signal using the voltage difference between the two voltages as an operating voltage, and outputs the output audio that is the amplification result. The signal is output to the speaker 40. As shown in FIG. 1, the amplifier 30R amplifies the right channel input audio signal INR to generate and output an output signal OUTR for driving the speaker 40R, and the amplifier 30L amplifies the left channel input audio signal INL. Then, an output signal OUTL for driving the speaker 40L is generated and output. These output signals OUTL and OUTR are applied not only to the speakers 40L and 40R, but also to the output voltage control circuit 10.

  As shown in FIGS. 2A and 2B, each of the signals OUTL and OUTR is a signal whose voltage value varies around the voltage VSS. As shown in FIG. 2A, the output voltage control circuit 10 has a high potential side output voltage VPP so as to follow the largest one of the output signal OUTL of the amplifier 30L, the output signal OUTR of the amplifier 30R, and the voltage VSS. The high-potential-side output voltage VPP is a voltage that varies between the voltage BVDD and the voltage VSS (for example, varies in the range of 1.8 to 0.2 [V]). . Further, as shown in FIG. 2B, the output voltage control circuit 10 supplies the low potential side output voltage VMM to the power supply circuit 20 so as to follow the smallest one of the output signal OUTL, the output signal OUTR, and the voltage VSS. The low-potential-side output voltage VMM varies between the voltage VSS and a voltage when the polarity of the voltage BVDD is inverted (hereinafter, voltage BVSS) (for example, from −0.2). The voltage varies in the range of −1.8 [V].

  The output voltage control circuit 10 includes a VPP control circuit 110 and a VMM control circuit 120 as shown in FIG. The VPP control circuit 110 is supplied with voltages BVDD, VSS, VPP, OUTL and OUTR, and the VMM control circuit 120 is supplied with voltages BVDD, VSS, VMM, OUTL and OUTR. Although details will be described later, in the VPP control circuit 110, the difference between the voltages BVDD and VSS is the operating voltage, and in the VMM control circuit 120, the difference between the voltages BVDD and VMM is the operating voltage. Here, other combinations of the operation voltages of the VPP control circuit and the VMM control circuit are also conceivable, but details thereof will be described in the modification example (1).

  The VPP control circuit 110 generates a control signal CVPP having a signal level corresponding to the difference between the high-potential-side output voltage VPP of the power supply circuit 20 and the output signal OUTL, OUTR and the largest voltage VSS, This is applied to the circuit 20. In the power supply circuit 20, the processing for adjusting the voltage VPP is performed so that the signal level of the control signal CVPP is reduced, as in FIGS. 8A to 8C, so that the voltage VPP is output from the output signal OUTL. , OUTR and voltage VSS are followed. On the other hand, the VMM control circuit 120 generates a control signal CVMM having a signal level corresponding to the difference between the voltage VMM and the smallest one of the output signals OUTL and OUTR and the voltage VSS and supplies the control signal CVMM to the power supply circuit 20. In the power supply circuit 20, a process for adjusting the voltage VMM is performed so that the signal level of the control signal CVMM is reduced, whereby the voltage VMM follows the smallest of the output signals OUTL, OUTR and the voltage VSS. It becomes.

  Conventionally, the VPP control circuit 110 and the VMM control circuit 120 are generally configured by combining switches and comparators as shown in FIGS. 8A to 8C. However, this embodiment is characterized in that these circuits are configured without using a switch or a comparator. Hereinafter, the VPP control circuit 110 and the VMM control circuit 120 that clearly show the features of this embodiment will be mainly described.

FIG. 3 is a diagram illustrating a configuration example of the VPP control circuit 110.
The VPP control circuit 110 includes four N-channel field effect transistors (205, 210, 215, and 275), twelve resistors (220 to 265, 280, and 285), a constant current source 270, and an operational amplifier 290. It is out. Although detailed illustration is omitted in FIG. 3, the resistance values of the resistors 220, 230, 240, and 260 are Rx [Ω], the resistance values of the resistors 225, 235, 245, and 265 are Ry [Ω], and the resistance The resistance values of 250 and 280 are Rz [Ω], and the resistance values of resistors 255 and 285 are Rw [Ω]. The threshold voltages Vnth of the N-channel field effect transistors 205 to 215 and 275 are the same, and the back gates of the four N-channel field effect transistors are connected to the sources.

  N-channel field effect transistors 205, 210, and 215 have their drains connected to terminals BVDD (terminals to which voltage BVDD is input, hereinafter, the other terminals are similarly distinguished by the sign of the input voltage). Are connected, and each source is connected in common. The resistor 220 and the resistor 225 are inserted in series between the terminal BVDD and the terminal OUTL, and a common connection point between the resistor 220 and the resistor 225 is connected to the gate of the N-channel field effect transistor 205. Therefore, a voltage corresponding to the output signal OUTL of the amplifier 30L (voltage obtained by dividing (boosting) the output signal OUTL by the resistors 220 and 225) is applied to the gate of the N-channel field effect transistor 205.

  The resistor 230 and the resistor 235 are inserted in series between the terminal BVDD and the terminal VSS, and the common connection point of the resistor 230 and the resistor 235 is connected to the gate of the N-channel field effect transistor 210. Therefore, a voltage corresponding to voltage VSS (voltage obtained by dividing (boosting) voltage VSS by resistors 230 and 235) is applied to the gate of N-channel field effect transistor 210. The resistor 240 and the resistor 245 are inserted in series between the terminal BVDD and the terminal OUTR, and the common connection point of the resistor 240 and the resistor 245 is connected to the gate of the N-channel field effect transistor 215. Therefore, a voltage corresponding to the output signal OUTR of the amplifier 30R (voltage obtained by dividing (boosting) the output signal OUTR by the resistors 240 and 245) is applied to the gate of the N-channel field effect transistor 215.

  Each of the N-channel field effect transistors 205, 210 and 215 in FIG. 3 has a drain voltage fixed to a constant value (voltage BVDD), and each back gate is connected to each source. For this reason, the sources applied to the N-channel field effect transistors 205, 210, and 215 are connected to the voltages applied to the gates (that is, the output signal OUTL, the voltage VSS, and the output signal OUTR, respectively, at the same voltage dividing ratio). A voltage (voltage obtained by dividing the voltage applied to the gate by a threshold voltage Vnth) appears. That is, these three N-channel field effect transistors function as a common drain amplifier circuit (source follower circuit). Although details will be described later, in the VPP control circuit 110 of this embodiment, these three N-channel field effect transistors serve as a peak hold circuit.

  The resistor 250 and the resistor 255 are inserted in series between the common connection point of the sources of the N-channel field effect transistors 205, 210, and 215 and the terminal VSS. A common connection point between the resistors 250 and 255 is connected to the negative input terminal of the operational amplifier 290. Therefore, a voltage obtained by dividing (stepping down) the voltage VN1 appearing at the common connection point of the sources of the N-channel field effect transistors 205, 210, and 215 by the resistor 250 and the resistor 255 at the negative input terminal of the operational amplifier 290. VN2 is applied.

  A resistor 260 and a resistor 265 are inserted in series between the terminal BVDD and the terminal VPP, and a constant current source 270 is inserted between the common connection point of the resistor 260 and the resistor 265 and the terminal VSS. . The common connection point of the resistor 260 and the resistor 265 is connected to the gate of the N-channel field effect transistor 275. The drain of the N-channel field effect transistor 275 is connected to the terminal BVDD, and the source is connected via the resistors 280 and 285. Each is connected to a terminal VSS. Although details will be described later, the N-channel field effect transistor 275, together with the operational amplifier 290, serves as a control signal generation unit that generates a control signal CVPP instructing adjustment of the voltage VPP and outputs it to the power supply circuit 20.

The positive input terminal of the operational amplifier 290 is connected to the common connection point of the resistor 280 and the resistor 285. Therefore, voltage VN4 obtained by dividing (stepping down) source voltage VN3 of N channel field effect transistor 275 by resistors 280 and 285 is applied to the positive input terminal of operational amplifier 290. The operational amplifier 290 outputs to the power supply circuit 20 a control signal CVPP having a signal level corresponding to the voltage difference between the voltage VN4 applied to the positive input terminal and the voltage VN2 applied to the negative input terminal (that is, VN4−VN2).
The above is the configuration of the VPP control circuit 110.

FIG. 4 is a diagram illustrating a configuration example of the VMM control circuit 120.
As shown in FIG. 4, the VMM control circuit 120 includes four P-channel field effect transistors (305, 310, 315 and 320), five resistors (325 to 345), a constant current source 350, an operational amplifier. 355. Although detailed illustration is omitted in FIG. 4, the resistance values of the resistors 325 and 340 are Ra [Ω], the resistance values of the resistors 330 and 345 are Rb [Ω], and the resistance value of the resistor 335 is Rc [Ω. ]. The threshold voltages Vpth of the P channel field effect transistors 305 to 320 are the same, and the back gates of the four P channel field effect transistors are connected to the sources.

  The sources of the P-channel field effect transistors 305, 310, and 315 are commonly connected. The P-channel field effect transistor 305 has a drain and a gate commonly connected to the terminal VSS, and a voltage higher than the voltage VSS by the threshold voltage Vpth appears at the source of the P-channel field effect transistor 305. P channel field effect transistors 310 and 315 have their drains connected to terminal VMM, the gate of P channel field effect transistor 310 is connected to terminal OUTL, and the gate of P channel field effect transistor 315 is connected to terminal OUTR. ing. A voltage higher than the voltage applied to each gate by a threshold voltage Vpth appears at the source of each of these P-channel field effect transistors 310 and 315. Although details will be described later, in the VMM control circuit 120 of this embodiment, the P-channel field effect transistors 305, 310, and 315 serve as a peak hold circuit.

  As shown in FIG. 4, a resistor 325 and a resistor 330 are interposed in series between the terminal BVDD and the common connection point of the sources of the P-channel field effect transistors 305, 310, and 315. A common connection point between the resistor 325 and the resistor 330 is connected to the negative input terminal of the operational amplifier 355. Therefore, when the voltage VN5 appears at the common connection point of the sources of the P-channel field effect transistors 305, 310, and 315, the voltage VN5 is divided (boosted) by the resistors 325 and 330 at the negative input terminal of the operational amplifier 355. The voltage VN6 obtained in this way is input.

The drain of the P-channel field effect transistor 320 is connected to the terminal VMM, and the source is connected to the terminal BVDD via resistors 345 and 340. A common connection point between the resistor 345 and the resistor 340 is connected to the positive input terminal of the operational amplifier 355. A constant current source 350 and a resistor 355 are inserted in series between the terminal BVDD and the terminal VMM, and a common connection point between the constant current source 350 and the resistor 355 is connected to the gate of the P-channel field effect transistor 320. Has been. Therefore, a voltage VN7 higher than the gate voltage (VMM + Rc × I) by the threshold voltage Vpth appears at the source of the P-channel field effect transistor 320, and a voltage obtained by dividing (boosting) this voltage VN7 by the resistors 340 and 345. VN8 is input to the positive input terminal of the operational amplifier 355. Therefore, the operational amplifier 355 outputs the control signal CVMM having a signal level corresponding to the difference (VN8−VN6) between the voltage VN8 input to the positive input terminal and the voltage VN6 input to the negative input terminal to the power supply circuit 20. In the present embodiment, the power supply circuit 20 executes processing for adjusting the low potential side output voltage VMM so that the signal level of the control signal CVMM becomes small. That is, the P-channel field effect transistor 320 and the operational amplifier 355 in FIG. 4 serve as control signal generation means for generating a control signal CVMM instructing adjustment of the voltage VMM and outputting it to the power supply circuit 20.
The above is the configuration of the VMM control circuit 120.

(B: Operation)
Next, operations of the VPP control circuit 110 and the VMM control circuit 120 will be described.
(B-1: Operation of VPP control circuit 110)
As described above, each of the N-channel field effect transistors 205, 210, and 215 of the VPP control circuit 110 functions as a common-drain amplifier circuit, and a voltage lower than the voltage applied to each gate by the threshold voltage Vnth. Appears in the source. For example, assuming that the voltage dividing ratio by the resistor 220 and the resistor 225, the voltage dividing ratio by the resistor 230 and the resistor 235, and the voltage dividing ratio by the resistor 240 and the resistor 245 are r1, each of the N-channel field effect transistors 205, 210, and 215 The voltages appearing at the sources of r1 × OUTL−Vnth, r1 × VSS−Vnth, and r1 × OUTR−Vnth, respectively.

  Since the sources of the N-channel field effect transistors 205, 210, and 215 are commonly connected, the voltage VN1 at the common connection point is dominated by the largest one of the voltage VSS, the output signal OUTR, and the output signal OUTL. . For example, when VSS <OUTR <OUTL, the source voltages of the N-channel field effect transistor 210 and the N-channel field effect transistor 215 gradually increase from their original values. As shown in FIG. 3, since these three N-channel field effect transistors have their back gates connected to the sources, the N-channel field effect transistor 210 and the N-channel field effect transistor 215 have their gates increased due to an increase in the source voltage. When the voltage between the back gate decreases and the voltage between the gate and the back gate falls below the threshold voltage Vnth, it turns off. Therefore, if OUTL is the maximum among the voltages VSS, OUTR, and OUTL, VN1 = r1 × OUTL−Vnth. Similarly, when OUTR is maximum, VN1 = r1 × OUTR−Vnth, and when VSS is maximum, VN1 = r1 × VSS−Vnth. As described above, the voltage VN1 corresponding to the maximum voltage among the voltages applied to the gates appears at the common connection point of the sources of the N-channel field effect transistors 205, 210, and 215. The two N-channel field effect transistors serve as a peak hold circuit.

  A voltage VN2 obtained by dividing the voltage VN1 by the resistor 250 and the resistor 255 is input to the negative input terminal of the operational amplifier 290. When the voltage dividing ratio by the resistor 250 and the resistor 255 is r2, VN2 = r2 × VN1. For example, if OUTR <VSS <OUTL, VN2 = r2 × (r1 × OUTL−Vnth). On the other hand, a voltage VN4 obtained by dividing the source voltage VN3 of the N-channel field effect transistor 275 by the resistors 280 and 285 is input to the positive input terminal of the operational amplifier 290. The N-channel field effect transistor 275 functions as a common-drain amplifier circuit, and a voltage r1 obtained by adding an offset of set by the constant current source 270 to a voltage obtained by dividing the voltage VPP by resistors 260 and 265 at the gate. * VPP + ofset is applied. Also for this N-channel field effect transistor 275, since the back gate is connected to the source, the source voltage VN3 is r1 × VPP + ofset−Vnth. Therefore, VN4 = r2 × (r1 × VPP + ofset−Vnth), and the operational amplifier 290 increases the difference between the voltage VN4 and the voltage VN2 (that is, the difference between the voltage VPP and the maximum of OUTL, OUTR, and VSS). The corresponding control signal CVPP is output. Thus, according to the VPP control circuit 110 of the present embodiment, the control signal CVPP is generated according to the difference between the voltage VPP and the maximum of OUTL, OUTR, and VSS without using a comparator or a switch. Can be output.

(B-2: Operation of the VMM control circuit 120)
Next, the operation of the VMM control circuit 120 will be described. First, the voltage appearing at the source of each of the P-channel field effect transistors 305, 310 and 315 will be considered. As described above, the drain and gate of the P-channel field effect transistor 305 are commonly connected to the terminal VSS, and the back gate of the P-channel field effect transistor 305 is connected to the source. Therefore, when the P-channel field effect transistor 305 is turned on, the voltage appearing at its source is VSS + Vpth. On the other hand, a voltage obtained by adding a threshold voltage Vpth to each gate voltage (OUTL or OUTR) appears at each source of the P-channel field effect transistors 310 and 315.

  Since the sources of the P-channel field effect transistors 305, 310, and 315 are commonly connected, the voltage VN5 at the common connection point is dominated by the smallest one of the voltage VSS, the output signal OUTR, and the output signal OUTL. . For example, if VSS <OUTR <OUTL, the source voltages of the P-channel field effect transistor 310 and the P-channel field effect transistor 315 gradually decrease from their original values. Since the back gate of each P-channel field transistor shown in FIG. 4 is connected to the source, in the P-channel field effect transistor 310 and the P-channel field effect transistor 315, the voltage between the gate and the back gate is reduced due to the decrease in the source voltage. When the voltage between the gate and the back gate exceeds the threshold voltage Vpth, it is turned off. Therefore, if VSS is the minimum among VSS, OUTR, and OUTL, VN5 = VSS + Vpth. Similarly, when OUTR is minimum, VN5 = OUTR + Vpth, and when OUTL is minimum, VN5 = OUTL + Vpth. In this way, the voltage VN5 corresponding to the minimum of the voltages applied to the respective gates appears at the common connection point of the sources of the P-channel field effect transistors 305, 310, and 315. The two P-channel field effect transistors serve as a peak hold circuit.

  A voltage VN6 obtained by dividing the voltage VN5 by the resistor 325 and the resistor 330 is input to the negative input terminal of the operational amplifier 355. If the voltage dividing ratio by the resistor 325 and the resistor 330 is r3, VN6 = r3 × VN5. For example, if VSS <OUTR <OUTL, VN6 = r3 × (VSS−Vpth). On the other hand, a voltage VN8 obtained by dividing the source voltage VN7 of the P-channel field effect transistor 320 by the resistors 340 and 345 is input to the positive input terminal of the operational amplifier 355. A voltage (VMM + ofset) obtained by adding an offset of set by the constant current source 350 and the resistor 335 to the voltage VMM is applied to the gate of the P-channel field effect transistor 320, and the source voltage VN7 becomes VMM + ofset + Vpth. Therefore, VN8 = r3 × (VMM + ofset + Vpth), and the operational amplifier 355 controls according to the difference between the voltage VN8 and the voltage VN6 (that is, the difference between the voltage VMM and the minimum one of OUTL, OUTR, and VSS). The signal CVMM is output. As described above, the VMM control circuit 120 can generate and output the control signal CVMM corresponding to the difference between the minimum voltage OUTL, OUTR, and VSS and the voltage VMM without using a comparator or a switch. It becomes possible.

  As described above, according to the output voltage control circuit 10 of the present embodiment, the high potential side output voltage VPP of the power supply circuit 20 changes following the largest one of the signals OUTL and OUTR and the voltage VSS. Further, the low potential side output voltage VMM of the power supply circuit 20 changes following the smallest one of the signals OUTL and OUTR and the voltage VSS. That is, according to the present embodiment, the output voltages VPP and VMM of the power supply circuit 20 can be controlled according to the output signals OUTL and OUTR of the amplifiers 30L and 30R to which the operating voltage is supplied by the power supply circuit 20. In addition, since the VPP control circuit 110 and the VMM control circuit 120 according to the present embodiment do not include a comparator or a switch as a component, it is compared with the conventional configuration shown in FIGS. Thus, the circuit area can be reduced, and the entire output voltage control circuit 10 can be reduced in size.

(C: deformation)
Although one embodiment of the present invention has been described above, the following modifications may of course be added to this embodiment.
(1) In the embodiment described above, the voltage difference between the voltage VSS, which is the ground voltage, and the voltage BVDD, which is the positive voltage, is used as the operating voltage of the power supply circuit 20, and the voltage difference between the voltage BVDD and the voltage VSS is the operation of the VPP control circuit 110. The voltage difference between the voltage BVDD and the voltage VMM was used as the operating voltage of the VMM control circuit 120. However, the operating voltage of the power supply circuit 20 may be a voltage difference between the voltage VSS and the voltage BVSS, or may be a voltage difference between the voltage BVDD and the voltage BVSS. Similarly, the operating voltages of the VPP control circuit and the VMM control circuit are not limited to the above combinations. Specifically, two types of voltages are selected from the voltages BVDD, VPP, VSS, VMM, and BVSS, and the voltage difference between the two types of voltages can be used as the operating voltage of the VPP control circuit (or VMM control circuit). . However, it should be noted that the VPP control circuit and the VMM control circuit do not operate if the voltage difference between two voltages selected from these five voltages is too small. For example, in the combination of the voltage BVDD and the voltage VPP, the voltage BVDD is 1.8 [V] and the voltage VPP varies in the range of 0.2 to 1.8 [V]. When the voltage difference between the two becomes about 0 [V], the circuit does not operate. With this in mind, the combinations of voltages that can guarantee the operation of the VPP control circuit and the VMM control circuit are limited to the combinations indicated by ◯ in FIG.

  FIG. 6 is a diagram illustrating a circuit configuration example of a VMM control circuit that receives supply of the voltage VSS and the voltage BVSS and uses a voltage difference between the two voltages as an operating voltage. 6 and 3, the configuration of the VMM control circuit in FIG. 6 is such that the terminal BVDD of the VPP control circuit 110 shown in FIG. 3 is replaced with the terminal BVSS, and further, N-channel field effect transistors 205 to 215 are used. 275 and 275 are replaced with P-channel field effect transistors 405 to 415 and 475. In the VMM control circuit shown in FIG. 6, P-channel field effect transistors 405 to 415 serve as a peak hold circuit. On the other hand, FIG. 7 is a diagram showing a circuit configuration example of a VPP control circuit that receives supply of the voltage VPP and the voltage BVSS and uses the voltage difference between the two voltages as an operating voltage. As apparent from the comparison between FIG. 7 and FIG. 4, the configuration of the VPP control circuit of FIG. 7 is such that the terminal VMM of the VMM control circuit 120 shown in FIG. 4 is replaced with the terminal VPP and the terminal BVDD is replaced with the terminal BVSS. The P channel field effect transistors 305 to 320 are the same as the N channel field effect transistors 505 to 520. In the VPP control circuit shown in FIG. 7, N-channel field effect transistors 505 to 515 serve as a peak hold circuit.

(2) In the above-described embodiment, the voltage VN2 (the voltage VN1 appearing at the common connection point of the sources of the N-channel field effect transistors 205, 210, and 215) is divided by the resistors 250 and 255 at the negative input terminal of the operational amplifier 290 in FIG. The voltage VN4 (the voltage obtained by dividing the source voltage VN3 of the N-channel field effect transistor 275 by the resistors 280 and 285) was applied to the positive input terminal of the operational amplifier 290. However, the voltage VN1 is applied to the negative input terminal of the operational amplifier 290, and the voltage VN3 is applied to the positive input terminal (that is, the control signal CVPP having a signal level corresponding to the difference between the voltage VN3 and the voltage VN1 is supplied to the operational amplifier 290. Of course, it is also possible to output. That is, in the configuration of the VPP control circuit 110 shown in FIG. 3, the resistors 250, 255, 280 and 285 are not essential components and can be omitted. Also in the configuration of the VMM control circuit 120 shown in FIG. 4, the resistors 325, 330, 340, and 345 are not essential components and can be omitted. For the same reason, the resistors 250, 255, 280, and 285 in FIG. 6 can be omitted, and the resistors 325, 330, 340, and 345 in FIG. 7 can be omitted.

  Since the constant current source 270 in FIG. 3 is for giving an offset to the gate voltage of the N-channel field effect transistor 275, the constant current source 270 is It is unnecessary. In the configuration in which constant current source 270 is omitted, a voltage obtained by dividing voltage VPP by resistors 260 and 265 is applied to the gate of N-channel field effect transistor 275. Similarly, the constant current source 350 and the resistor 335 shown in FIG. 4 can be omitted. If these are omitted, the terminal VMM may be connected to the gate of the P-channel field effect transistor 320.

  Further, in the configuration shown in FIG. 3, the resistors 220 to 245, 260, and 265 may be omitted. When these resistors are omitted, the terminal OUTL is the gate of the N-channel field effect transistor 205, the terminal VSS is the gate of the N-channel field effect transistor 210, the terminal OUTR is the gate of the N-channel field effect transistor 215, and the terminal VPPs may be connected to the gates of the N-channel field effect transistors 275, respectively. Similarly, in the configuration shown in FIG. 6, the resistors 220 to 245, 260, and 265 can be omitted. When these resistors are omitted, the terminal OUTL is connected to the gate of the P-channel field effect transistor 405, and the terminal VSS may be connected to the gate of the P-channel field effect transistor 410, the terminal OUTR may be connected to the gate of the P-channel field effect transistor 415, and the terminal VMM may be connected to the gate of the P-channel field effect transistor 475.

(3) In the above-described embodiment, the high-potential-side output voltage VPP (low-potential-side) so as to follow the maximum (minimum) output signal OUTL of the amplifier 30L, the output signal OUTR of the amplifier 30R, and the ground voltage VSS. The output voltage VMM) was adjusted. However, the high-potential-side output voltage VPP (low-potential-side output voltage VMM) is adjusted to follow the maximum (minimum) of the input signal INL of the amplifier 30L, the input signal INR of the amplifier 30R, and the ground voltage VSS. May be. This can be realized by supplying the input signal INL to the output voltage control circuit 10 instead of the output signal OUTL and supplying the input signal INR to the output voltage control circuit 10 instead of the output signal OUTR. In short, a signal indicating the operation status of each of the amplifiers 30L and 30R to which the operating voltage is supplied by the power supply circuit 20 is given to the output voltage control circuit 10, and the high potential side output voltage VPP and the low potential side are based on these signals. Any mode for adjusting the output voltage VMM may be used.

(4) In the above-described embodiment, the output voltage control circuit 10 controls the output voltage of the power supply circuit 20 that supplies the operating voltage to the speaker amplifier. However, even if the present invention is applied to an output voltage control circuit that controls an output voltage of a power supply circuit that supplies an operating voltage to a power amplifier circuit that drives an electric motor in accordance with an output signal (or input signal) of the power amplifier circuit. Of course it is good.

DESCRIPTION OF SYMBOLS 1 ... Speaker system, 10 ... Output voltage control circuit, 110 ... VPP control circuit, 120 ... VMM control circuit, 20 ... Power supply circuit, 30L, 30R ... Amplifier, 40L, 40R ... Speaker, 205-215, 275, 505-520 ... N-channel field effect transistors, 305 to 320, 405 to 415, 475 ... P-channel field effect transistors, 220 to 265, 280, 285, 325 to 345 ... resistors, 270, 350 ... constant current sources, 290, 355 ... operational amplifiers .

Claims (2)

  A drain and a gate are commonly connected, a first field effect transistor to which a first voltage is applied to the common connection point, a second voltage is applied to each drain, and the first voltage is applied to each gate. Second and third field effect transistors to which third and fourth voltages whose voltage values fluctuate around one voltage are applied, respectively, and the first, second and third field effect transistors The peak hold circuit that outputs the voltage that appears at the common connection point. An output in which the first and second voltages are supplied to generate the third and fourth voltages, the input signal is amplified according to the applied operating voltage, and the voltage value fluctuates around the first voltage. In an output voltage control circuit for controlling the operation of a power supply circuit that applies a voltage difference between the third and fourth voltages as an operating voltage to first and second power amplifier circuits that respectively output signals,
Either one of the third and fourth voltages is set as a control target voltage,
A drain and a gate are commonly connected, a first field effect transistor in which the first voltage is applied to the common connection point, and second and third electric fields in which the control target voltage is applied to each drain A second field effect transistor in which the output signal of the first power amplifier circuit is applied to the gate; and a third electric field in which the output signal of the second power amplifier circuit is applied to the gate. A peak hold circuit that outputs a voltage that appears at the common connection point, and the sources of the first, second, and third field effect transistors are connected in common.
A fourth field effect transistor in which a voltage corresponding to the voltage to be controlled is applied to a drain and a gate; and a difference between an output voltage of the peak hold circuit and a voltage appearing at a source of the fourth field effect transistor is small. A control signal generation unit that generates a control signal instructing to adjust the control target voltage and outputs the control signal to the power source;
An output voltage control circuit comprising:

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