JP2011135112A - Connection structure of semiconductor device - Google Patents

Connection structure of semiconductor device Download PDF

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JP2011135112A
JP2011135112A JP2011085304A JP2011085304A JP2011135112A JP 2011135112 A JP2011135112 A JP 2011135112A JP 2011085304 A JP2011085304 A JP 2011085304A JP 2011085304 A JP2011085304 A JP 2011085304A JP 2011135112 A JP2011135112 A JP 2011135112A
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electrode
electrodes
bump
power supply
integrated circuit
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JP5447426B2 (en
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Toru Taura
徹 田浦
Hirobumi Inoue
博文 井上
Yuuki Fujimura
雄己 藤村
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

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Abstract

<P>PROBLEM TO BE SOLVED: To improve deterioration in the electrical properties due to the coupling capacitances of adjoining connection bumps, without having to change the size of a semiconductor device. <P>SOLUTION: An electrode pitch and an electrode size on a semiconductor integrated circuit are equal to an electrode pitch and an electrode size on a wiring substrate, respectively, and regarding a connecting structure of electrodes, a plurality of power supply electrodes or ground electrodes are successively arranged such that the electrodes on the semiconductor integrated circuit face the electrodes on the wiring substrate, respectively. In a region where signal electrodes are arranged interposing the power supply electrodes or the ground electrodes, the signal electrodes are mutually connected by bumps. In a portion where the power supply electrodes and ground electrodes of the semiconductor integrated circuit adjoin, each of the power supply electrodes and the ground electrodes on the semiconductor integrated circuit and the wiring substrate is connected by the bumps; and each of other power supply electrodes and of the ground electrodes are not connected by the bump. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体集積回路とこれを搭載する配線基板とのバンプによる電極間の接続構造に関する。   The present invention relates to a connection structure between electrodes by bumps between a semiconductor integrated circuit and a wiring board on which the semiconductor integrated circuit is mounted.

近年の半導体装置形状は小型、高密度化が進み、その電極ピッチも狭くなってきている。信号電極ピッチが狭くなるとその電極上に配置したバンプ間の結合容量が増大しクロストークが無視できなくなってきている。図１０と図１１は従来のバンプ接続構造において、それぞれ先行技術として開示されている特開平６−１０４２６０と特開平３−１９８３５８に記載された接続構造を示したものである。この対策として、図１０においては半導体集積回路の信号電極周囲にグランド電極を配置し、信号バンプ５をグランドバンプ６で囲う構造とすることにより、信号電極間のクロストークによるノイズの低減を図っている。図１１においては、信号用バンプの周囲に電源用バンプを設けさらに信号リードをグランドリードで囲う構造とし、クロストークの低減を図っている。   In recent years, the shape of a semiconductor device has been reduced in size and increased in density, and the electrode pitch has been reduced. When the signal electrode pitch is narrowed, the coupling capacitance between bumps arranged on the electrodes increases, and crosstalk cannot be ignored. FIG. 10 and FIG. 11 show connection structures described in Japanese Patent Application Laid-Open Nos. 6-104260 and 3-198358, respectively, which are disclosed as prior art in conventional bump connection structures. As a countermeasure, in FIG. 10, a ground electrode is arranged around the signal electrode of the semiconductor integrated circuit, and the signal bump 5 is surrounded by the ground bump 6 to reduce noise due to crosstalk between the signal electrodes. Yes. In FIG. 11, a power supply bump is provided around the signal bump and the signal lead is surrounded by a ground lead to reduce crosstalk.

特開平６−１０４２６０JP-A-6-104260 特開平３−１９８３５８JP 3-198358

上述した従来のバンプ接続構造においては、図１０と図１１中の信号用バンプとグランド用バンプあるいは電源用バンプは、バンプ間の空気またはモールド樹脂を介することで、等価的に図１２に示すバンプ間の結合容量の等価回路１２０６−１，１２０６−２に示す様な結合容量を持つこととなる。この結合容量により、半導体集積回路とこれを搭載する配線基板間を伝送されるべき高周波域の信号が、グランド用バンプへ流れ込み、信号に損失が生じる。また、グランド用バンプへ信号が漏れ込むことにより、半導体集積回路内のグランドレベルが振られ、回路動作を不安定にする。   In the conventional bump connection structure described above, the signal bump and ground bump or power supply bump in FIGS. 10 and 11 are equivalently shown in FIG. It has a coupling capacity as shown in an equivalent circuit 1206-1, 1206-2 of the coupling capacity between them. Due to this coupling capacitance, a signal in a high frequency range to be transmitted between the semiconductor integrated circuit and the wiring board on which the semiconductor integrated circuit is mounted flows into the ground bump, and a loss occurs in the signal. Further, when a signal leaks into the ground bump, the ground level in the semiconductor integrated circuit is shaken, and the circuit operation becomes unstable.

したがって本発明の目的は、従来の様な隣接するバンプの結合容量による高周波域の信号特性の悪化を軽減した半導体集積回路とこれを搭載する配線基板とのバンプによる電極間の接続構造を提供することである。   Accordingly, an object of the present invention is to provide a connection structure between electrodes by bumps between a semiconductor integrated circuit and a wiring board on which the semiconductor integrated circuit is mounted, in which deterioration of high-frequency signal characteristics due to the coupling capacity of adjacent bumps is reduced. That is.

本発明の半導体装置の接続構造は、半導体集積回路上の電極ピッチと電極サイズが配線基板上の電極ピッチと電極サイズに等しく、且つ電極の接続構造に関し、半導体集積回路上の電極と配線基板上の電極がそれぞれ対向して配置した、電源電極または、グランド電極が複数個連続して並び、信号電極が電源電極またはグランド電極を挟んで配置したエリアでは、前記信号電極同志をバンプで接続し、前記半導体集積回路の電源電極とグランド電極が隣接する部分は前記半導体集積回路上と前記配線基板上の電源電極とグランド電極のそれぞれをバンプで接続し、それ以外の電源電極とグランド電極については接続しないことを特徴としている。
また、半導体集積回路上の電極ピッチと電極サイズが配線基板の電極ピッチと電極サイズに等しい電極のレイアウトで、半導体集積回路上の電極が２つ以上連なって同一信号の入力端あるいは、電極が２つ以上連なって同一信号の出力端となっている場合、この２つ以上連なった電極の内１つだけを前記配線基板の電極とバンプにより接続することを特徴としている。 The connection structure of the semiconductor device according to the present invention relates to the electrode pitch and electrode size on the semiconductor integrated circuit equal to the electrode pitch and electrode size on the wiring substrate, and relates to the electrode connection structure. In the area where a plurality of power supply electrodes or ground electrodes are arranged in series and the signal electrodes are arranged across the power supply electrode or the ground electrode, the signal electrodes are connected by bumps, The power supply electrode and the ground electrode adjacent to each other in the semiconductor integrated circuit are connected to the power supply electrode and the ground electrode on the semiconductor integrated circuit and the wiring board with bumps, and the other power supply electrode and the ground electrode are connected. It is characterized by not.
Further, in the electrode layout in which the electrode pitch and the electrode size on the semiconductor integrated circuit are equal to the electrode pitch and the electrode size of the wiring board, two or more electrodes on the semiconductor integrated circuit are connected to each other so that the same signal input end or two In the case where two or more are connected to serve as an output end of the same signal, only one of the two or more connected electrodes is connected to the electrode of the wiring board by a bump.

本発明の第１の効果は、バンプ接合部の電気的特性が改
善されることである。その理由は、信号電極間の隣接バンプとの結合容量が小さくなるためである。第２の効果は、電源、グランド間のノイズが低減されることである。その理由は、電源バンプとグランドバンプの間隔を狭く配置することにより結合容量を増大させる事が出来、バイパスコンデンサとしての役割を果たすことがためである。本発明の接続構造では、電源電極とグランド電極のバンプ間隔は狭くなり、信号電極のバンプ間隔は広がる。従って電源−グランド電極のバンプ間の結合容量が増大し、バイパスコンデンサの役割を果たすので電源ノイズを低減できる。また、信号電極のバンプ間の結合容量は低減し、クロストークによるノイズが低減し、電気特性を改善できるという効果がある。 The first effect of the present invention is that the electrical characteristics of the bump bonding portion are improved. This is because the coupling capacitance between adjacent bumps between the signal electrodes is reduced. The second effect is that noise between the power supply and the ground is reduced. The reason is that the coupling capacitance can be increased by arranging the gap between the power supply bump and the ground bump to be narrow, and it serves as a bypass capacitor. In the connection structure of the present invention, the bump interval between the power electrode and the ground electrode is reduced, and the bump interval between the signal electrodes is increased. Therefore, the coupling capacitance between the bumps of the power supply and the ground electrode is increased, and the power supply noise can be reduced because it acts as a bypass capacitor. Further, the coupling capacitance between the bumps of the signal electrode is reduced, noise due to crosstalk is reduced, and electrical characteristics can be improved.

本発明の第１の実施形態を示すバンプによる接続構造断面図である。It is connection structure sectional drawing by the bump which shows the 1st Embodiment of this invention. 本発明の第２の実施形態を示すバンプによる接続構造断面図である。It is connection structure sectional drawing by the bump which shows the 2nd Embodiment of this invention. 本発明の第３の実施形態を示すバンプによる接続構造断面図である。It is connection structure sectional drawing by the bump which shows the 3rd Embodiment of this invention. 本発明の第４の実施形態を示すバンプによる接続構造断面図である。It is connection structure sectional drawing by the bump which shows the 4th Embodiment of this invention. 本発明の第５の実施形態を示すバンプによる接続構造断面図である。It is connection structure sectional drawing by the bump which shows the 5th Embodiment of this invention. 本発明の第６の実施形態を示すバンプによる接続構造断面図である。It is connection structure sectional drawing by the bump which shows the 6th Embodiment of this invention. 本発明の第７の実施形態を示すバンプによる接続構造断面図である。It is connection structure sectional drawing by the bump which shows the 7th Embodiment of this invention. 本発明の第８の実施形態を示すバンプによる接続構造断面図である。It is connection structure sectional drawing by the bump which shows the 8th Embodiment of this invention. 本発明の第９の実施形態を示すバンプによる接続構造断面図である。It is connection structure sectional drawing by the bump which shows the 9th Embodiment of this invention. 従来のバンプによる接続構造におけるバンプ間の結合容量を示す断面図。Sectional drawing which shows the coupling capacity between bumps in the connection structure by the conventional bump. 従来のバンプによる接続構造を示す平面図である。It is a top view which shows the connection structure by the conventional bump. 従来のバンプによる接続構造におけるバンプ間の結合容量を示す断面図。Sectional drawing which shows the coupling capacity between bumps in the connection structure by the conventional bump.

次に、本発明について図面を参照しながら説明する。図１は本発明の第１の実施形態を示す断面図である。これは半導体集積回路１０１の電極ピッチと電極サイズが、配線基板１０２の電極ピッチと電極サイズと異なる場合であり、半導体回路１０１の電極の中心１１３を通る電極表面に対して垂直な直線１１５が、配線基板１０２上の電極の中心１１４通過する半導体集積回路１０２上の電極および、配線基板上の電極を信号電極１０３、１０７−３とし、これらの電極をバンプによって接続する。 Next, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a first embodiment of the present invention. This is a case where the electrode pitch and electrode size of the semiconductor integrated circuit 101 are different from the electrode pitch and electrode size of the wiring substrate 102, and a straight line 115 perpendicular to the electrode surface passing through the center 113 of the electrode of the semiconductor circuit 101 is The electrode on the semiconductor integrated circuit 102 that passes through the center 114 of the electrode on the wiring board 102 and the electrode on the wiring board are signal electrodes 103 and 107-3, and these electrodes are connected by bumps.

上記の信号電極の接続に加えて、半導体集積回路１０２上の隣接する２つの電極間の中点１１１を通る電極表面に対して垂直な直線１１６が、配線基板１０２上の隣接する２つの電極間の中点１１２を通過する場合、前記半導体集積回路１０１上の２つの電極をそれぞれグランド電極１０５−１、電源電極とし１０４−１、この２つの電極１０５−１、１０４−１のそれぞれと対をなす、配線基板上の電極をグランド電極１０７−１、電源電極１０７−２とし、半導体集積回路１０１上と配線基板上１０２の２つのグランド電極１０５−１、１０７−１をバンプによって接続し、同様に２つの電源電極１０４−１、１０７−２をバンプによって接続する。   In addition to the signal electrode connection described above, a straight line 116 perpendicular to the electrode surface passing through the midpoint 111 between two adjacent electrodes on the semiconductor integrated circuit 102 is formed between the two adjacent electrodes on the wiring substrate 102. When passing through the middle point 112, the two electrodes on the semiconductor integrated circuit 101 are the ground electrode 105-1 and the power supply electrode 104-1, respectively, and the two electrodes 105-1 and 104-1 are paired with each other. The electrodes on the wiring board are the ground electrode 107-1 and the power supply electrode 107-2, and the two ground electrodes 105-1 and 107-1 on the semiconductor integrated circuit 101 and the wiring board 102 are connected by bumps. The two power supply electrodes 104-1 and 107-2 are connected to each other by bumps.

上記の様なバンプ接続方法をとることにより、電源電極を接続するバンプ１１０−１とグランド電極を接続するバンプ１０９−１は近接し、結合容量が大きくなることでバイパスコンデンサの効果をなし、電源のノイズを低減できる。また、信号電極を接続するバンプ１０３とグランド電極や電源電極を接続するバンプ１０９−１，１１０−２の間隔が広がり、結合容量が低減することで信号電極を接続するバンプの電気特性の改善が図れる。   By adopting the bump connection method as described above, the bump 110-1 for connecting the power supply electrode and the bump 109-1 for connecting the ground electrode are close to each other, and the effect of the bypass capacitor is achieved by increasing the coupling capacitance. Noise can be reduced. In addition, the gap between the bump 103 connecting the signal electrodes and the bumps 109-1 and 110-2 connecting the ground electrode and the power supply electrode is widened, and the coupling capacitance is reduced, thereby improving the electrical characteristics of the bumps connecting the signal electrodes. I can plan.

図２は本発明の第２の実施形態である。これは半導体集積回路２０１の電極ピッチと電極サイズが、配線基板２０２の電極ピッチと電極サイズとが異なる場合で、図１の実施形態と異なる点は配線基板側の電極ピッチと電極サイズである。半導体集積回路２０１上の隣接する２つの電極間の中点２０９を通る電極表面に対して垂直な直線２１６が、配線基板２０２上の隣接する２つの電極間の中点２１０を通過する場合、半導体集積回路２０１上の２つの電極をそれぞれグランド電極２０４−１、電源電極２０３−１とし、この２つの電極２０４−１、２０３―１のそれぞれと対をなす配線基板上の電極をグランド電極２０６−１、電源電極２０６−２とし、半導体集積回路上と配線基板上の２つのグランド電極をバンプ２０８−１によって接続し、同様に２つの電源電極をバンプ２０７−１によって接続する。上記の様なバンプ接続方法をとることにより、グランド電極を接続するバンプ２０８−１と電源電極を接続するバンプ２０７−１は近接し結合容量が大きくなり、バイパスコンデンサの効果をなし、電源のノイズを低減できる。   FIG. 2 shows a second embodiment of the present invention. This is the case where the electrode pitch and the electrode size of the semiconductor integrated circuit 201 are different from the electrode pitch and the electrode size of the wiring board 202. The difference from the embodiment of FIG. 1 is the electrode pitch and the electrode size on the wiring board side. When a straight line 216 perpendicular to the electrode surface passing through the midpoint 209 between two adjacent electrodes on the semiconductor integrated circuit 201 passes through the midpoint 210 between the two adjacent electrodes on the wiring substrate 202, the semiconductor Two electrodes on the integrated circuit 201 are a ground electrode 204-1 and a power supply electrode 203-1, respectively, and an electrode on a wiring board paired with each of the two electrodes 204-1 and 203-1 is a ground electrode 206-. 1. As a power supply electrode 206-2, two ground electrodes on a semiconductor integrated circuit and a wiring board are connected by a bump 208-1, and similarly, two power supply electrodes are connected by a bump 207-1. By adopting the bump connection method as described above, the bump 208-1 for connecting the ground electrode and the bump 207-1 for connecting the power supply electrode are close to each other and the coupling capacitance is increased, and the effect of the bypass capacitor is achieved. Can be reduced.

図３は本発明の第３の実施形態である。これは半導体集積回路３０１の電極ピッチと電極サイズが、配線基板３０２の電極ピッチと電極サイズとが異なる場合で、第１、第２と異なる点は配線基板側の電極ピッチと電極サイズである。半導体集積回路３０１上の隣接する２つの電極間の中点３１０を通る電極表面に対して垂直な直線３１６が、配線基板３０２上の隣接する２つの電極間の中点３１１を通過する場合、半導体集積回路３０１上の２つの電極をそれぞれグランド電極３０７−２、電源電極３０８−１とし、この２つの電極３０７−２、３０８−１のそれぞれと対をなす配線基板上の電極をグランド電極３０９−１、電源電極３０９−２とし、半導体集積回路上と配線基板上の２つのグランド電極３０７−２、３０９−１をバンプ３０４によって接続し、同様に２つの電源電極３０８−１、３０９−２をバンプ３０５によって接続する。これに加え半導体集積回路３０１上の同一信号の入力端または同一信号の出力端として連なって配置した信号電極３０３−１、３０３−２の内、最も近傍にあるバンプ３０５から離れた電極３０３−２を信号電極として、配線基板３０２上の信号電極３０９−３に、バンプ３０６によって接続する。   FIG. 3 shows a third embodiment of the present invention. This is the case where the electrode pitch and the electrode size of the semiconductor integrated circuit 301 are different from the electrode pitch and the electrode size of the wiring board 302. The first and second differences are the electrode pitch and the electrode size on the wiring board side. When a straight line 316 perpendicular to an electrode surface passing through a midpoint 310 between two adjacent electrodes on the semiconductor integrated circuit 301 passes through a midpoint 311 between two adjacent electrodes on the wiring substrate 302, the semiconductor Two electrodes on the integrated circuit 301 are a ground electrode 307-2 and a power supply electrode 308-1, respectively, and an electrode on a wiring board that is paired with each of the two electrodes 307-2 and 308-1 is a ground electrode 309-. 1. The power supply electrode 309-2 is used. Two ground electrodes 307-2 and 309-1 on the semiconductor integrated circuit and the wiring board are connected by the bump 304. Similarly, the two power supply electrodes 308-1 and 309-2 are connected to each other. Connection is made by bumps 305. In addition, of the signal electrodes 303-1 and 303-2 arranged in series as the same signal input end or the same signal output end on the semiconductor integrated circuit 301, the electrode 303-2 away from the nearest bump 305. Is connected to the signal electrode 309-3 on the wiring substrate 302 by a bump 306 as a signal electrode.

上記の様なバンプ接続方法をとることにより、グランド電極を接続するバンプ３０４と電源電極を接続するバンプ３０５は近接し結合容量が大きくなり、バイパスコンデンサの効果をなし、電源のノイズを低減できる。また、信号電極を接続するバンプ３０６と電源電極を接続するバンプ３０５の間隔は広がり、結合容量が低減することにより信号電極を接続するバンプの電気特性の改善が図れる。   By adopting the bump connection method as described above, the bump 304 for connecting the ground electrode and the bump 305 for connecting the power supply electrode are close to each other and the coupling capacitance is increased, so that the effect of the bypass capacitor can be achieved and the noise of the power supply can be reduced. In addition, the distance between the bump 306 connecting the signal electrode and the bump 305 connecting the power electrode is widened, and the coupling capacitance is reduced, so that the electrical characteristics of the bump connecting the signal electrode can be improved.

本発明の第４の実施形態を図４に示す。これは半導体集積回路４０１の電極ピッチと電極サイズが配線基板４０２の電極ピッチと電極サイズとが等しい場合で、半導体集積回路４０１上の隣接して配置された電源電極４０９−１とグランド電極４０８−２は配線基板４０２上の電源電極４１０−２とグランド電極４１１−１に電源バンプ４０６とグランドバンプ４０５を介して接続する。また信号電極４０４に隣接する電源電極４０９−３やグランド電極４０８−３は接続しない。   A fourth embodiment of the present invention is shown in FIG. This is a case where the electrode pitch and the electrode size of the semiconductor integrated circuit 401 are equal to the electrode pitch and the electrode size of the wiring substrate 402, and the power supply electrode 409-1 and the ground electrode 408- arranged adjacent to each other on the semiconductor integrated circuit 401. 2 is connected to the power supply electrode 410-2 and the ground electrode 411-1 on the wiring substrate 402 through the power supply bump 406 and the ground bump 405. Further, the power supply electrode 409-3 and the ground electrode 408-3 adjacent to the signal electrode 404 are not connected.

上記の様なバンプ接続方法をとることにより、電源電極を接続するバンプ４０６とグランド電極を接続するバンプ４０５の結合容量は大きくなり、バイパスコンデンサの効果をなし、電源のノイズを低減できる。また、信号電極を接続するバンプ４０７と電源電極を接続するバンプ４０６または、グランド電極を接続するバンプ４０５との結合容量が低減することにより、接合部の電気特性の改善が図れる。   By adopting the bump connection method as described above, the coupling capacitance between the bump 406 for connecting the power supply electrode and the bump 405 for connecting the ground electrode is increased, and the effect of the bypass capacitor can be achieved and the noise of the power supply can be reduced. In addition, since the coupling capacitance between the bump 407 connecting the signal electrode and the bump 406 connecting the power supply electrode or the bump 405 connecting the ground electrode is reduced, the electrical characteristics of the joint can be improved.

本発明の第５の実施形態を図５に示す。半導体集積回路５０１上の電極ピッチと電極サイズと配線基板５０２上の電極ピッチと電極サイズとが等しい場合についてであり、半導体集積回路５０１上の電極について、同一信号の入力端であるかまたは、同一信号の出力端である信号電極である隣接する電極５０４−１と電極５０４−２について任意のどちらか、図３では５０４−２にバンプ５０５を配置し、配線基板５０２上の電極５０３−２と接続する。同一信号の入力端または出力端である信号電極５０３−３、５０３−４の接続については、バンプ５０５から遠いほうの信号電極５０３−４と５０４−４をバンプ５０６で接続する。同様にバンプ５０６から遠い方の電極５０４−６と５０３−６をバンプ５０７で接続する。上記の様なバンプ接続方法をとることにより、各信号電極を接続するバンプ５０５，５０６，５０７の間隔が広がり、結合容量は減少し、電気特性を改善できる。   A fifth embodiment of the present invention is shown in FIG. This is a case where the electrode pitch and electrode size on the semiconductor integrated circuit 501 are the same as the electrode pitch and electrode size on the wiring substrate 502, and the electrodes on the semiconductor integrated circuit 501 are the same signal input ends or the same. A bump 505 is disposed on any one of the adjacent electrodes 504-1 and 504-2 which are signal electrodes which are signal output ends, in FIG. Connecting. Regarding connection of signal electrodes 503-3 and 503-4 which are input ends or output ends of the same signal, signal electrodes 503-4 and 504-4 farther from the bump 505 are connected by the bump 506. Similarly, electrodes 504-6 and 503-6 far from the bump 506 are connected by the bump 507. By adopting the bump connection method as described above, the interval between the bumps 505, 506, and 507 connecting the signal electrodes is widened, the coupling capacitance is reduced, and the electrical characteristics can be improved.

図６は半導体集積回路上の電極ピッチと電極サイズおよび配線基板の電極ピッチと電極サイズが図１の実施形態と同じであり、接続部バンプを導電性ピラーに置き換えた本発明の第６の実施形態である。導電性ピラーは金属または導電性樹脂または絶縁体にメッキして導電性を持たせたものであり、円柱形状あるいは角柱形状とした。前記の様な導電性ピラーによる接続方法をとることにより、第１の実施形態と同様に、電源電極を接続する導電性ピラー６１０−１とグランド電極を接続する導電性ピラー６０９−１は近接し、バイパスコンデンサの効果をなし、電源のノイズを低減でき、信号電極を接続する導電性ピラー６０８と、グランド電極６０５−２や電源電極６０４−１を接続する導電性ピラー６１０−２，６０９−１の間隔が広がり、結合容量が低減することにより信号電極を接続する導電性ピラーの電気特性の改善が図れる。   FIG. 6 shows the sixth embodiment of the present invention in which the electrode pitch and electrode size on the semiconductor integrated circuit and the electrode pitch and electrode size of the wiring board are the same as those in the embodiment of FIG. 1, and the connection bumps are replaced with conductive pillars. It is a form. The conductive pillar is a metal or conductive resin or insulator plated to have conductivity, and has a cylindrical shape or a prismatic shape. By adopting the connection method using the conductive pillar as described above, the conductive pillar 610-1 for connecting the power supply electrode and the conductive pillar 609-1 for connecting the ground electrode are close to each other as in the first embodiment. The effect of the bypass capacitor is achieved, the noise of the power supply can be reduced, and the conductive pillar 608 for connecting the signal electrode and the conductive pillars 610-2 and 609-1 for connecting the ground electrode 605-2 and the power supply electrode 604-1. As a result, the electrical characteristics of the conductive pillar connecting the signal electrodes can be improved.

図７と図８は図６の実施形態における導電性ピラー形状を変形した、それぞれ第７、第８の実施形態である。図７は電極面よりもピラー７１０−１を断面の狭いものとし、半導体集積回路７０１上の電極７０５−１と配線基板７０２上の電極７０７−１を接続した構造である。また、図８は半導体集積回路８０１上の電極と配線基板８０２上の電極の間隔よりも長いピラーを屈曲させ半導体集積回路上の電極と配線基板上の電極を接続した構造である前記の様な導電性ピラーによる接続方法をとることにより、第１の実施形態と同様の理由により、さらに電源のノイズを低減でき、信号電極を接続する導電性ピラーの電気特性の改善が図れる。   7 and 8 are seventh and eighth embodiments, respectively, in which the conductive pillar shape in the embodiment of FIG. 6 is modified. FIG. 7 shows a structure in which the pillar 710-1 has a narrower cross section than the electrode surface, and the electrode 705-1 on the semiconductor integrated circuit 701 and the electrode 707-1 on the wiring substrate 702 are connected. FIG. 8 shows a structure in which a pillar longer than the distance between the electrode on the semiconductor integrated circuit 801 and the electrode on the wiring substrate 802 is bent to connect the electrode on the semiconductor integrated circuit and the electrode on the wiring substrate. By adopting the connection method using the conductive pillar, the noise of the power source can be further reduced for the same reason as in the first embodiment, and the electrical characteristics of the conductive pillar connecting the signal electrode can be improved.

図９は半導体集積回路上の電極ピッチと電極サイズおよび配線基板の電極ピッチと電極サイズが第１の実施形態と同じで、接続部バンプをボールバンプに置き換えたものである。ボールバンプは銅製の球９１７を芯としている、半導体回路上の電極９０５−１と配線基板上の電極９０７−１の間に半田ボール９１０−１を形成することで行う。上記の様なボールバンプによる接続方法をとることにより、第１の実施形態と同様に、電源電極を接続するボールバンプ９０９−１とグランド電極を接続する銅製の球９１０−１は近接し、バイパスコンデンサの効果をなし、電源のノイズを低減できる。また、信号電極を接続するボールバンプ９０８に対する、グランド電極９０５−２を接続するボールバンプ９１０−２と電源電極９０４−１を接続するボールバンプ９０９−１の間隔が広がり、結合容量が低減することにより信号電極を接続するボールバンプの電気特性の改善が図れる。   In FIG. 9, the electrode pitch and electrode size on the semiconductor integrated circuit and the electrode pitch and electrode size of the wiring board are the same as those in the first embodiment, and the connection portion bumps are replaced with ball bumps. The ball bump is performed by forming a solder ball 910-1 between an electrode 905-1 on a semiconductor circuit and an electrode 907-1 on a wiring board, each having a copper ball 917 as a core. By using the connection method using the ball bumps as described above, the ball bump 909-1 for connecting the power supply electrode and the copper ball 910-1 for connecting the ground electrode are close to each other and bypassed, as in the first embodiment. Capacitor effect and power supply noise can be reduced. Further, the distance between the ball bump 910-2 connecting the ground electrode 905-2 and the ball bump 909-1 connecting the power supply electrode 904-1 with respect to the ball bump 908 connecting the signal electrode is widened, and the coupling capacitance is reduced. As a result, the electrical characteristics of the ball bumps connecting the signal electrodes can be improved.

１０１，２０１，３０１，４０１，５０１，６０１，７０１，８０１，９０１，１２０１ 半導体集積回路
１０２，２０２，３０２，４０２，５０２，６０２，７０２，８０２，９０２，１２０２ 配線基板
１０３，１０７−３，３０３−１，３０３−２，３０９−３，４０３，４０４，５０４−１〜６，５０３−１〜６，６０３，６０７−３，９０３，９０７−３，１２０４−２，１２０３−２ 信号電極
１０４−１，１０４−２，１０７−２，１０７−５，２０３−１，２０３−２，２０６−２，２０６−４，３０８−１，３０８−２，３０９−２，４０９−１〜３，４１１−１〜３，６０４−１，６０４−２，６０７−２，７０７−５，７０４−１，７０４−２，７０７−２，７０７−５，８０４−１，８０４−２，８０７−２，８０７−５，９０４−１，９０４−２，９０７−２，９０７−５，１２０３−３，１２０４−３ 電源電極
１０５−１，１０５−２，１０７−１，１０７−４，２０４−１，２０４−２，２０６−１，２０６−３，３０７−１，３０７−２，３０９−１，４０８−１〜３，４１０−１〜３，６０５−１〜２，６０７−１，６０７−４，７０５−１〜２，７０７−１，７０７−４，８０５−１〜２，８０７−１，８０７−４，９０５−１〜２，９０７−１，９０７−４，１２０３−１，１２０４−１ グランド電極
１０７−１〜５，２０６−１〜４，３０９−１〜３，６０６−１〜３，７０６−１〜３ ８０６−１〜３，９０６−１〜３ 電極
１１０−１，１０９−１，１０８，１１０−２，１０９−２，２０８−１，２０７−１，２０８−２，２０７−２，３０４，３０５，３０６，４０５，４０６，４０７，５０５，５０６，５０７，１２０５−１，１２０５−２，１２０４−３ バンプ
１１１，１１２，２０９，２１０，３１０，３１１，６１１，６１２，７１１，７１２，８１１，８１２，９１１，９１２ 隣接する２電極間の中央
１１３，１１４，６１３，６１４，７１３，７１４，８１３，８１４，９１３，９１４ 電極の中心
１１５，１１６，６１５，６１６，７１５，７１６，８１５，８１６，９１５，９１６ 電極表面に対して垂直な直線
６１０−１，６０９−１，６０８，６１０−２，６０９−２，７１０−１，７０９−１，７０８，７１０−２，７０９−２，８１０−１，８０９−１，８０８，８１０−２，８０９−２ 導電性ピラー
９１０−１，９０９−１，９０８，９１０−２，９０９−２ ボールバンプ
１２０６−１，１２０６−２ バンプ間の結合容量の等価回路
９１７ 銅製の球 101, 201, 301, 401, 501, 601, 701, 801, 901, 1201 Semiconductor integrated circuit 102, 202, 302, 402, 502, 602, 702, 802, 902, 1202 Wiring substrate 103, 107-3, 303 -1,303-2, 309-3, 403, 404, 504-1 to 6, 503-1 to 6, 603, 607-3, 903, 907-3, 1204-2, 1203-2 Signal electrode 104- 1, 104-2, 107-2, 107-5, 203-1, 203-2, 206-2, 206-4, 308-1, 308-2, 309-2, 409-1 to 411, 411- 1-3,604-1,604-2,607-2,707-5,704-1,704-2,707-2,707-5,804-1,804-2,807-2,807 5, 904-1, 904-2, 907-2, 907-5, 1203-3, 1204-3 Power supply electrode 105-1, 105-2, 107-1, 107-4, 204-1, 204-2 206-1, 206-3, 307-1, 307-2, 309-1, 408-1 to 3, 410-1 to 3, 605-1 to 2, 607-1, 607-4, 705-1. To 2,707-1, 707-4, 805-1 to 2,807-1, 807-4, 905-1 to 2,907-1, 907-4, 1203-1, 1204-1 Ground electrode 107- 1-5, 206-1 to 4, 309-1 to 3, 606-1 to 3,706-1 to 3806-1 to 3,906-1 to 3 Electrode 110-1, 109-1, 108, 110 -2, 109-2, 208-1, 207-1, 208-2, 207- , 304, 305, 306, 405, 406, 407, 505, 506, 507, 1205-1, 1205-2, 1204-3 Bump 111, 112, 209, 210, 310, 311, 611, 612, 711, 712 , 811, 812, 911, 912 Center between two adjacent electrodes 113, 114, 613, 614, 713, 714, 813, 814, 913, 914 Electrode center 115, 116, 615, 616, 715, 716, 815 , 816, 915, 916 Straight lines perpendicular to the electrode surface 610-1, 609-1, 608, 610-2, 609-2, 710-1, 709-1, 708, 710-2, 709-2, 810-1, 809-1, 808, 810-2, 809-2 Conductive pillar 910-1, 909-1, 908, 91 -2,909-2 equivalent coupling capacitance between ball bumps 1206-1,1206-2 bumps circuit 917 copper spheres

Claims (5)

半導体集積回路上の電極ピッチと電極サイズが配線基板上の電極ピッチと電極サイズに等しく、且つ電極の接続構造に関し、半導体集積回路上の電極と配線基板上の電極がそれぞれ対向して配置した、電源電極または、グランド電極が複数個連続して並び、信号電極が電源電極またはグランド電極を挟んで配置したエリアでは、前記信号電極同志をバンプで接続し、前記半導体集積回路の電源電極とグランド電極が隣接する部分は前記半導体集積回路上と前記配線基板上の電源電極とグランド電極のそれぞれをバンプで接続し、それ以外の電源電極とグランド電極については接続しないことを特徴とした半導体装置の接続構造。 The electrode pitch and the electrode size on the semiconductor integrated circuit are equal to the electrode pitch and the electrode size on the wiring board, and the electrode connection structure is such that the electrode on the semiconductor integrated circuit and the electrode on the wiring board are arranged to face each other. In an area where a plurality of power supply electrodes or ground electrodes are continuously arranged and the signal electrodes are arranged with the power supply electrode or the ground electrode sandwiched therebetween, the signal electrodes are connected by bumps, and the power supply electrode and the ground electrode of the semiconductor integrated circuit are connected. Is connected to the power supply electrode and the ground electrode on the semiconductor integrated circuit and the wiring board by bumps, and the other power supply electrode and the ground electrode are not connected. Construction. 半導体集積回路上の電極ピッチと電極サイズが配線基板の電極ピッチと電極サイズに等しい電極のレイアウトで、半導体集積回路上の電極が２つ以上連なって同一信号の入力端あるいは、電極が２つ以上連なって同一信号の出力端となっている場合、この２つ以上連なった電極の内１つだけを前記配線基板の電極とバンプにより接続することを特徴とした半導体装置の接続構造。 An electrode layout in which the electrode pitch and electrode size on the semiconductor integrated circuit are equal to the electrode pitch and electrode size of the wiring board, and two or more electrodes on the semiconductor integrated circuit are connected to each other to input the same signal or two or more electrodes. A connection structure for a semiconductor device, characterized in that, when the same signal is output continuously, only one of the two or more connected electrodes is connected to the electrode of the wiring board by a bump. 前記バンプは金属球を押しつぶした楕円球状の金属バンプであり、この楕円球状の金属バンプで接続する構造を特徴とした請求項１または２記載の半導体装置の接続構造。 3. The semiconductor device connection structure according to claim 1, wherein the bump is an elliptical metal bump formed by crushing a metal sphere, and the connection is made by the elliptical metal bump. 前記バンプを金属あるいは導電性樹脂を、円柱形状あるいは角柱形状に形成した導電性ピラーとし、この導電性ピラーで接続する構造を特徴とした請求項１または２記載の半導体装置の接続構造。 3. The semiconductor device connection structure according to claim 1, wherein the bump is a conductive pillar in which a metal or a conductive resin is formed in a columnar shape or a prismatic shape, and is connected by the conductive pillar. 前記バンプを銅製の球を芯とした半田ボールによって形成したボールバンプとし、このボールバンプで接続する構造を特徴とした請求項１または２記載の半導体装置の接続構造。 3. The semiconductor device connection structure according to claim 1, wherein the bump is a ball bump formed by a solder ball having a copper sphere as a core, and the ball bump is used for connection.
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