JP2011135098A - Method of manufacturing wafer-level csp - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin CSP which can be assembled at wafer level. <P>SOLUTION: On a reverse-surface side of a wafer, electric junction between the top and the reverse of the wafer is made using a side face of a through hole formed at a specified place on a scribe line, and an electrode for substrate mounting is arranged. The through hole is formed by reverse-surface polishing, using back grind, on a recess formed by half-etching on the scribe line of a semiconductor substrate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a small package for housing a semiconductor element.

  Electronic mobile devices such as mobile phones and digital cameras are highly demanded for miniaturization and weight reduction, and electronic components constituting the electronic devices are required to be smaller, thinner and lighter. Currently, small packages such as BGA and CSP are applied to small portable electronic devices, and it is expected that chip-scale ultra-small packages that can be assembled on the bare chip or at the wafer level will be introduced in the future. In particular, a CSP (chip size package or chip scale package) formed at a wafer level is attracting attention as a next-generation package because it is smaller than conventional BGA and CSP and easier to handle than a bare chip.

  A sectional structure of a typical wafer level CSP is shown in FIG. The manufacturing method is manufactured by the following process. The semiconductor substrate 15 after the wafer process is ground to about 500 μm by back grinding, a protective film 17 such as polyimide is formed on the semiconductor substrate 15, and the electrode pad 16 and other necessary portions are opened. Next, a copper rewiring layer 18 is formed by plating, and the electrodes are rearranged in an array. In order to form an electrode for external connection, a copper post 19 is formed by a plating method, and then a mold resin 20 is sealed. Finally, bump electrodes 21 for board mounting are formed by ball mounter or screen printing. Conventionally, a wafer-level CSP has been manufactured by the above method.

JP-A-10-135270

  However, in the wafer level CSP, it is necessary to form a copper post in order to form an electrode for external connection. Since the copper post is connected to the bump electrode or the mounting substrate, the post surface must be completely exposed to copper, but the copper post is plated, resulting in variations in the height of the post. This causes a problem that the bonding reliability with the solder ball is lowered. Further, in order to absorb the variation in the height of the post, it is necessary to make the transfer pressure of the molding apparatus highly accurate and to use a special film, which causes a problem that the manufacturing cost of the package becomes high. Furthermore, the copper post becomes the flow resistance of the mold resin, and the resin does not spread uniformly on the wafer surface, causing the problem that the resin is not filled and the assembly yield is lowered.

  Further, since the bump electrode for substrate bonding is formed on the copper post on the mold resin sealing side, the formation of the bump electrode cannot be performed by an electrolytic plating method, but is performed by a ball mount or a screen printing method. Therefore, it becomes difficult to form a narrow pitch bump electrode of 100 μm or less.

  The wafer level CSP of the present invention has a structure in which an electrode for substrate bonding is formed on the back surface of a wafer and a copper post is not used. Moreover, since there are no substrate mounting electrodes on the mold sealing surface, all of the above problems can be solved.

  The wafer level CSP of the present invention has a substrate mounting electrode on the back side of the wafer, and the structure is such that electrical bonding between the front and back of the wafer is performed using the side surface of the through hole formed at a specific location on the scribe line. It is realized by taking. The through hole is formed by half-etching the scribe line of the silicon substrate to form a recess and then polishing the back surface.

  The wafer level CSP of the present invention does not require the formation of a copper post for forming an electrode for external connection, improves the molding apparatus to absorb post variations, and eliminates the need to use a special film. The manufacturing cost of the package can be reduced. Since there is no copper post, the mold resin spreads uniformly on the wafer surface without receiving flow resistance, so that the resin is not filled and assembly yield is improved. In addition, since there are no bumps for substrate bonding on the mold resin sealing surface side, bumps can be formed by electrolytic plating as well as solder ball mount and screen printing, and a narrow pitch bump electrode of 100 μm or less can be formed.

It is a top view of the semiconductor device of the first embodiment. It is sectional drawing of the semiconductor device of a 1st Example. It is sectional drawing of the semiconductor device of a 1st Example. It is sectional drawing of the semiconductor device of a 1st Example. It is sectional drawing of the semiconductor device of a 1st Example. It is sectional drawing of the semiconductor device of a 2nd Example. It is sectional drawing of the semiconductor device of a 3rd Example. It is sectional drawing of the conventional wafer level CSP.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a top view showing a first embodiment of the present invention, and FIGS. 2 to 4 are sectional views. The structure of the wafer level CSP of the first embodiment will be described with reference to the drawings.

  As shown in FIG. 2A, the wafer after the formation of the semiconductor circuit used for package assembly has an electrode pad 2 formed on the semiconductor substrate 1 and a protective film 3 such as silicon nitride formed on the electrode pad 2 as an electrode. A form formed on portions other than the pads 2 and the scribe lines 4 is used.

  In the first step, as shown in FIG. 2B, the half etching portion 5 is selectively wet-etched at a specific portion of the scribe line area to form a recess having a depth of about 50 to 100 μm.

  Next, as shown in FIG. 2C, an insulating film 6 such as polyimide is formed on the entire surface of the wafer, and the electrode pad 2 and the half-etched portion 5 on the scribe line are selectively opened as shown in FIG. To do. At this time, the insulating film on the bottom surface of the recess is removed, but the insulating film remains on the side surface of the recess.

  Next, after forming a copper film having a thickness of 2000 to 5000 mm by sputtering, the resist 7 is patterned into a desired shape as shown in FIG. 3A, and the thickness is about 20 to 50 μm as shown in FIG. A metal wiring layer 8 such as copper or aluminum is formed by a plating method, and an insulating layer 9 such as polyimide is formed on the entire surface as necessary.

  Next, as shown in FIG. 3C, a mold resin 10 having a thickness of about 30 μm to 100 μm is applied to the entire surface of the semiconductor circuit by transfer molding or potting for the purpose of improving the protection of the semiconductor circuit, the handling of the package, and the heat dissipation. Seal.

  Next, as shown in FIG. 3D, the silicon substrate 1 is back-ground to a thickness of 20 μm to 200 μm according to the mounting application. Due to the back grinding, the end surface of the portion of the metal wiring 8 embedded in the concave portion of the half-etched portion 5 is exposed to the back surface side.

  Next, as shown in FIG. 4A, after an insulating film 11 such as polyimide is formed on the ground surface of the semiconductor substrate 1, it is patterned into a desired shape (FIG. 4B). Next, after a metal film such as copper is formed on the entire back surface of the wafer by sputtering or the like, resist patterning is performed, and an electrode pad 12 having a thickness of about 10 to 50 μm is formed on the semiconductor substrate 1 as shown in FIG. It is formed on the back surface of the substrate by a method such as plating.

  Finally, as shown in FIG. 5, the center of the scribe line is diced at a cutting margin of about 50% of the scribe width to divide the package into pieces. By the above-described method, a wafer level package having the mounting electrode pads 12 on the back surface of the semiconductor substrate 1 can be provided.

  Next, a second embodiment of the present invention will be described. FIG. 6 is a sectional view showing a second embodiment of the present invention. An electrode pad 2 is formed on a part of the surface of the semiconductor substrate 1, a protective film 3 is formed around the electrode pad 2, an insulating film 6 is formed on the protective film 3, and an insulating film 9 is formed on the uppermost layer. Yes. An insulating film 11 and an electrode pad are formed on a part of the back surface of the semiconductor substrate 1. As shown in FIG. 6, since the second embodiment has a structure in which mold resin sealing is not performed, the thickness of the package can be reduced to 100 μm or less, and it can be used for applications such as an IC card.

  Next, a third embodiment of the present invention will be described. FIG. 7 is a sectional view showing a third embodiment of the present invention. As shown in FIG. 7, in the third embodiment, bump electrodes 13 can be formed on the mounting electrode pads on the back surface of the wafer by a ball mount method, a screen printing method or an electric field plating method. Enable. At this time, if the insulating film formed on the back surface of the wafer is used instead of the cushioning material 14 such as an elastomer, the stress between the mounting substrate and the bump is absorbed, and the reliability at the time of mounting is improved.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Electrode pad 3 Protective film 4 Scribe area 5 Half etching location 6 Insulating film 7 Resist 8 Metal wiring layer 9 Insulating layer 10 Mold resin 11 Insulating film 12 Electrode pad 13 Bump electrode 14 Buffer material 15 Semiconductor substrate 16 Electrode pad 17 Protective film 18 Rewiring layer 19 Copper post 20 Mold resin 21 Bump electrode

Claims (4)

Selectively half-etching a specific portion in a scribe line of a semiconductor wafer provided with a plurality of semiconductor circuits each having a first electrode pad to form a recess having a bottom surface and side surfaces;
After the first insulating film is formed on the entire surface of the semiconductor wafer, the first insulating film is formed on the electrode pad and on the bottom surface of the recess, leaving the first insulating film on the side surface of the recess. Removing and opening,
Forming a metal wiring layer covering the recess from the first electrode pad after patterning the resist into a predetermined shape;
Forming an insulating layer on the entire surface of the semiconductor wafer;
Grinding the metal wiring layer from the bottom surface of the recess and grinding from the back side so that the semiconductor substrate of the semiconductor wafer has a desired thickness;
Forming a second insulating film in a predetermined region on the back surface of the ground semiconductor substrate;
Forming a metal film on the entire back surface of the semiconductor substrate, and forming a second electrode pad for mounting on the surface of the second insulating film with a patterned resist;
A method of manufacturing a wafer level CSP, comprising: a step of dicing and dividing the center of the scribe line.   The method of manufacturing a wafer level CSP according to claim 1, further comprising a step of forming a mold resin on the entire surface of the insulating layer.   The method of manufacturing a wafer level CSP according to claim 1, wherein the metal wiring layer is formed by a plating method.   4. The method of manufacturing a wafer level CSP according to claim 1, further comprising a step of forming a bump electrode on the surface of the second electrode pad.

Images