JP2011134288A - Code generation device and code generation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a code generation device, capable of generating a program code that fluctuates power supply voltage of a memory at a time considering a voltage fluctuation time. <P>SOLUTION: The code generation device includes: an insert position calculation means which calculates an insert position for inserting a control code to a program code to be written to a memory having a plurality of areas, the control code controlling power source voltage so that the areas are switched in a state where the power source voltage is stabilized; a memory map generation means which generates a memory map based on configuration information of the memory and the insert position; and a code generation means which inserts the control code to the insert position to generate a program code. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a code generation device and a code generation method for generating a memory map using a program code in which a code for controlling a power supply voltage supplied to a memory is inserted.

  In recent digital circuits, various contrivances have been made to reduce power consumption. For example, reduction of circuit operation rate of digital circuit, stop of clock supplied to digital circuit (hereinafter referred to as clock gating), reduction of clock frequency, interruption of power supplied to digital circuit (hereinafter referred to as power gating), low power supply Methods such as voltage conversion are known.

  In addition, in a memory included in a digital circuit, a device is devised to reduce power consumption. For example, in the case of a memory, there are known a method of stopping the clock when there is no memory access, a method of cutting off the power supply voltage supplied to the memory when it has not been operated for a certain period of time, and a method of reducing the power supply voltage supplied to the memory. It has been.

  As a method for reducing the power supply voltage of the memory, a method in which the memory autonomously reduces the power supply voltage and a method in which an instruction is received from an external processor or the like to reduce the power supply voltage are known. In the method of reducing the power supply voltage of the memory, a power reduction effect can be expected when the power supply voltage is finely controlled in accordance with the execution state of the processing in the digital circuit.

JP 2000-215100 A

  However, many conditional branches exist in the program, and it is difficult to determine which memory power supply voltage should be reduced at which timing.

  Further, when the power supply voltage of the memory is lowered, a voltage change time for changing the power supply voltage is generated. Therefore, for example, when the power supply voltage of the memory is controlled by an instruction from the outside, it is necessary to instruct the fluctuation of the power supply voltage in consideration of the voltage fluctuation time. The voltage fluctuation time corresponds to several tens to several hundreds of cycles of the processor clock, and it is extremely difficult to predict the timing of changing the power supply voltage in consideration of the voltage fluctuation time.

  Accordingly, an object of the present invention is to provide a code generation device and a code generation method capable of generating a program code for changing a power supply voltage of a memory at a timing in consideration of a voltage change time.

  In order to solve the above-described problem, an insertion position for inserting a control code for controlling the power supply voltage is calculated so that the area can be switched in a state where the power supply voltage is stable in a program code written in a memory having a plurality of areas. An insertion position calculating means; a memory map generating means for creating a memory map based on the memory structure information and the insertion position; a code generating means for generating a program code by inserting the control code into the insertion position; Have

  A program for causing a computer to execute the above means as a function, or a computer-readable storage medium storing the program may be used.

  It is possible to generate a program code for changing the power supply voltage of the memory at a timing in consideration of the voltage change time.

It is a figure which shows an example of the system which controls the power supply voltage of a memory. It is a figure which shows an example of the relationship between the static call graph of the function contained in a program code, and a memory map. It is a figure which shows an example of the memory map of the program code produced | generated in this embodiment. It is a figure for demonstrating a code production | generation apparatus. It is a flowchart explaining operation | movement of a code generation apparatus. It is a figure for demonstrating calculation of the division position when there is no branch in a function. It is a figure for demonstrating calculation of the division position when a function has a branch. 6 is a flowchart illustrating calculation of a division position of an assembly code 55 shown in step S51 of FIG. 6 is a flowchart for explaining determination of a memory map shown in step S52 of FIG. It is a figure which shows an example of number-of-calls information. It is a figure which shows an example of function size information. It is a figure which shows an example of the structure information of a memory unit. It is a figure which shows an example of labeling. It is a 1st flowchart explaining memory allocation. It is a 2nd flowchart explaining memory allocation. It is a 3rd flowchart explaining memory allocation. It is a 4th flowchart explaining memory allocation. FIG. 6 is a first flowchart illustrating insertion of a control code shown in step S53 of FIG. It is a 2nd flowchart explaining insertion of the control code shown to step S53 of FIG. It is a figure explaining an example of operation | movement of the semiconductor integrated circuit with which the binary with power supply control produced | generated by the code production | generation apparatus of 1st embodiment was mounted. It is a figure which shows an example of the assembly input into a code generation apparatus. It is a figure which shows an example of the call graph of the function defined in the assembly. It is a 1st figure which shows an example of the assembly after the control code is inserted. It is a 2nd figure which shows an example of the assembly after the control code is inserted. It is a 1st flowchart explaining insertion of the control code when an interruption process is considered. It is a figure which shows an example of a call graph. It is a 2nd flowchart explaining insertion of a control code when an interruption process is considered. It is a figure for demonstrating the case where the memory allocated to a function is multiple. It is a flowchart explaining memory allocation in case the memory allocated to a function is plurality. It is a flowchart explaining insertion of a control code when a plurality of memories are assigned to a function. It is a flowchart explaining operation | movement of the code generation apparatus of 4th embodiment. FIG. 32 is a flowchart for describing calculation of a control code insertion position shown in step S3101 of FIG. 31. FIG. FIG. 33 is a flowchart for describing calculation of a control code insertion position shown in step S3208 of FIG. 32. FIG. FIG. 32 is a flowchart describing determination of a memory map shown in step S3102 of FIG. 31. FIG. FIG. 32 is a first flowchart illustrating control code insertion shown in step S3103 of FIG. 31. FIG. FIG. 32 is a second flowchart illustrating control code insertion shown in step S3103 of FIG. 31. FIG. It is a figure explaining an example of operation | movement of the semiconductor integrated circuit with which the binary with power supply control produced | generated by the code production | generation apparatus of 4th Embodiment was mounted. It is a figure for demonstrating the premise of 5th embodiment. It is a figure explaining the function structure of the code generation apparatus of 5th embodiment. It is a figure which shows an example of the memory map information in 5th embodiment. It is a flowchart explaining insertion of the control code by the code generation device of the fifth embodiment. It is a figure explaining the process of a sleep release code insertion process part and a sleep code insertion process part. It is a figure which shows the case where the function funcX is the main function funcM. It is a figure which shows the case where the function funxX is the function funcB1. It is a figure which shows the case where the function funcX is the function funcD2. It is a figure which shows the case where the function funcX is the function funcC3. It is a figure for demonstrating the premise of 6th embodiment. It is a figure explaining the function structure of the code generation apparatus of 6th embodiment. It is a flowchart explaining insertion of the control code by the code generator of 6th Embodiment. It is a flowchart explaining preparation of the table by the sleep possible table preparation part of 6th Embodiment. It is a flowchart explaining operation | movement of the code generation apparatus of 7th embodiment. It is a figure explaining the determination of the memory map in 7th embodiment. It is a figure which shows an example of the call frequency information between functions. It is a figure which shows an example of calculation of the code amount of a function group. It is a flowchart explaining the process of the calling frequency calculation part of 7th Embodiment. It is a figure which shows an example of a calling frequency table. It is a flowchart explaining the process of the constant voltage memory allocation part at the time of use of 7th Embodiment. It is a figure which shows an example of the size information of a fixed voltage memory at the time of use. It is a figure which shows an example of the allocation result of the fixed voltage memory at the time of use.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, the concept of the present embodiment will be described with reference to FIGS.

  FIG. 1 is a diagram illustrating an example of a system that controls a power supply voltage of a memory. The system shown in FIG. 1 includes a memory unit 10, a processor 20, and a register 30. The memory unit 10, the processor 20, and the register 30 are connected by a bus 40.

  The memory unit 10 is, for example, an SRAM (Static Random Access Memory), and can hold contents written with the power supply voltage lowered. The memory unit 10 includes a memory A to a memory E that are a plurality of areas. Each of the memories A to E may be a separate memory, or may be a memory area in which one memory is divided into a plurality of areas. The memories A to E can be used separately as an instruction memory and a data memory, and a power supply line 41 that supplies a power supply voltage to each is connected via a voltage converter 42 that varies the power supply voltage. Yes. The processor 20 sets the switching of the power supply voltage for each of the memories A to E in the register 30, and the voltage converter 42 varies the power supply voltage of the memories A to E according to the set value of the register 30.

  In the present embodiment, a control code for controlling the power supply voltage is inserted into the program code so that the control of fluctuations in the power supply voltage of the memories A to E can be completed in units of functions included in the program code.

  FIG. 2 is a diagram illustrating an example of a relationship between a static call graph of a function included in a program code and a memory map.

  In the present embodiment, in the memory unit 10, a memory that is in a constant voltage state (hereinafter referred to as a constant voltage memory) that is supplied with a constant power supply voltage, and a power supply voltage that is low when not in use. A memory that is in a low voltage state (hereinafter, a constant voltage memory when used) is provided. The low voltage is a voltage lower than a constant voltage. The constant voltage memory in use can hold the contents written in the memory even in a low voltage state.

  In this embodiment, a function that is predicted to be executed for a long time is always placed in a constant voltage memory. A function that is predicted to be executed for a long time is a main function or the like whose function call hierarchy is higher. A function called by the main function or the like is divided into a first half part (hereinafter, a constant voltage part) and a second half part (hereinafter, a low voltage part). The code of the constant voltage part of the function is always placed in the constant voltage memory.

  In the example of FIG. 2, the memory A is always a constant voltage memory, and a main function funcM is arranged. In the memory A, function func1 called by the main function funcM and constant voltage parts Z1 and Z2 of the function func2 are arranged. In the memory A, another function func3 called by the function func1 and the function func2 is arranged. The memory B and the memory C are constant voltage memories in use, and low voltage portions K1 and K2 of the functions func1 and function func2 are arranged.

  In the present embodiment, when the function func1 and the function func2 are divided, the codes that can be executed within the voltage fluctuation time in the functions func1 and func2 are arranged in the memory A as constant voltage parts Z1 and Z2, and the subsequent codes Are arranged in the memory B and the memory C as the low voltage parts K1 and K2. Then, a program code is generated by inserting a code for setting the memory B and the memory C into a constant voltage state at the beginning of the functions func1 and func2.

  The voltage fluctuation time in the present embodiment is the time taken for the power supply voltage to change from a constant voltage to a low voltage, or the time taken for the power supply voltage to change from a low voltage to a constant voltage.

  The program code generated according to the present embodiment is written in a memory such as an LSI (Large Scale Integration). In the LSI in which the program code generated according to the present embodiment is written, it is possible to realize a control for changing the power supply voltage of the memory at a timing considering the voltage change time, and to absorb the voltage change time. Details of function division and code insertion will be described later.

  In the program code generated according to the present embodiment, for example, a control code for putting the memory B, which is a constant voltage memory in use, into a constant voltage state is inserted at the head of the constant voltage unit Z1 of the function func1. Therefore, when the execution of the constant voltage unit Z1 of the function func1 is completed and the memory for executing the low voltage unit Z2 is switched from the memory A to the memory B, the memory B is in a constant voltage state. Therefore, in this embodiment, the memory can be switched in a state where the power supply voltage is stably supplied to the memory.

  FIG. 3 is a diagram illustrating an example of a memory map of program codes generated in the present embodiment.

  In the memory unit 10, the memory A having a start address of 0x0000 and an end address of 0x0fff has a main function funcM, a power supply control code for setting the memory B in a constant voltage state, a constant voltage unit Z1 of the function func1, and a memory C having a constant voltage. A power supply control code to be set, a constant voltage portion Z2 of the function func2, and other functions func3 are arranged. In the memory B whose start address is 0x1000 and end address is 0x1ffff, other functions not shown in FIG. 2 and the low voltage part K1 of the function func1 are arranged. In the memory C having a start address of 0x2000 and an end address of 0x2ffff, another function not shown in FIG. 2 and a low voltage part K2 of the function func2 are arranged.

  If the program code is implemented according to the memory map shown in FIG. 3, the power supply voltages of the memory B and the memory C can be controlled at a timing in consideration of the voltage variation time. Therefore, the memory B and the memory C can be shifted from the low voltage state to the constant voltage state at an appropriate timing.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. First, the code generation apparatus according to the first embodiment for generating a program code will be described.

  FIG. 4 is a diagram for explaining the code generation device. The code generation device 100 according to the present embodiment inserts a control code for controlling a power supply voltage supplied to the memory unit 10 into the assembly 50 when an assembly 50 as a program code and a parameter 60 described later are input. The assembly 50 in which the control code is inserted is assembled and linked to generate and output a binary 70 with power supply control.

  The code generation device 100 according to the present embodiment includes an input device 101, an output device 102, a drive device 103, an auxiliary storage device 104, a memory device 105, an arithmetic processing device 106, and an interface device 107, which are mutually connected by a bus B. Composed.

  The input device 101 includes a keyboard and a mouse, and is used to input various signals. The output device 102 includes a display device and is used to display various windows and data. The interface device 107 includes a modem, a LAN card, and the like, and is used for connecting to a network.

  The code generation program of this embodiment is at least a part of various programs that control the code generation device 100. The code generation program is provided by, for example, distribution of the recording medium 108 or downloading from a network. The recording medium 108 on which the code generation program is recorded is information such as a CD-ROM, a flexible disk, a magneto-optical disk, etc., a recording medium for recording information optically, electrically, or magnetically, a ROM, a flash memory, etc. Various types of recording media, such as a semiconductor memory that electrically records data, can be used.

  When the recording medium 108 on which the code generation program is recorded is set in the drive device 103, the code generation program is installed from the recording medium 108 to the auxiliary storage device 104 via the drive device 103. The code generation program downloaded from the network is installed in the auxiliary storage device 104 via the interface device 107.

  The auxiliary storage device 104 stores the installed code generation program and also stores necessary files, data, and the like. For example, the assembly 50 and the parameter 60 may be stored in the auxiliary storage device 104. The memory device 105 reads and stores the code generation program from the auxiliary storage device 104 when the computer is activated. The arithmetic processing unit 106 implements various processes as described later according to the code generation program stored in the memory device 105.

  The assembly 50 of this embodiment includes assembly code 55 for each function. Further, the parameter 60 of the present embodiment includes the number of cycles N, the structure information 62 of the memory unit 10, and the control code pattern 63. The number of cycles N is a value set in advance with one instruction described in the assembly 50 as one cycle. The number of cycles N in this embodiment is set so that the time taken to execute instructions for the number of cycles N corresponds to the voltage fluctuation time of the power supply voltage to the memory unit 10.

  The structure information 62 of the memory unit 10 indicates respective start addresses and end addresses in the memories A to E included in the memory unit 10. The control code pattern 63 is a control code pattern for controlling the power supply voltage to the memories A to E. The control code pattern 63 is determined by determining a specific parameter included in the control code pattern 63. The control code pattern 63 includes, for example, a power control code pattern 64 for changing the memory A to the memory E from a constant voltage state to a low voltage state or from a low voltage state to a constant voltage state, a jump for jumping from a divided position to a divided point A control code pattern 65 (see FIG. 9) is included.

  The operation of the code generation device 100 of this embodiment will be described below with reference to FIG. FIG. 5 is a flowchart for explaining the operation of the code generation device. Details of the processing of each step described in FIG. 5 will be described later.

  In the code generation device 100 of the present embodiment, when the assembly 50 and the number of cycles N included in the parameter 60 are input, the code generation device 100 calculates the division position of the assembly code 55 for each function (step S51). . In the present embodiment, the division position calculated in step S51 is the insertion position where the control code is inserted.

  When the division position of the assembly code 55 is calculated in step S51, the code generation device 100 arranges the assembly code 55 divided based on the division position and the structure information 62 of the memory unit 10 included in the parameter 60. A memory map is determined (step S52).

  When the memory map is generated, the code generation device 100 determines a parameter to be substituted for the control code pattern 63 included in the parameter 60, generates a control code, and inserts the control code at the division position of the assembly code 55 (step). S53). Assume that the assembly 50 into which the control code is inserted is an assembly 50A. The code generation apparatus 100 assembles and links the assembly 50A including the assembly code 55 into which the control code is inserted (step S54), and outputs the power-controlled binary 70 including the control code to complete the code generation.

  The binary 70 with power control output from the code generation apparatus 100 of the present embodiment may be recorded on a recording medium different from the recording medium 108.

  Next, the calculation of the function division position in the present embodiment will be described with reference to FIGS.

  In the code generation device 100 of the present embodiment, a predetermined number of cycles N is set in advance. In this embodiment, a cycle for executing one instruction is defined as one cycle. The number of cycles N in this embodiment is set so that the time taken to execute instructions for N cycles corresponds to the voltage fluctuation time.

  The code generation device 100 calculates the farthest address that can be reached in the number of cycles N in the assembly code 55 included in the assembly 50 as a division position. Then, the code generation device 100 divides the assembly code 55 by using the assembly code 55 as a constant voltage part up to an instruction that can be executed in the N cycle, and using an instruction that does not reach within the N cycle as a low voltage part.

  In the code generation device 100 of this embodiment, a function that is predicted to be executed for a long time, such as a main function, may be set not to be divided in advance.

  FIG. 6 is a diagram for explaining the calculation of the division position when there is no branch in the function. FIG. 6A shows an instruction flow, and FIG. 6B shows an example of division.

  The function func1 included in the assembly 50 will be described as an example. As shown in FIG. 6A, when there is no conditional branch in the processing flow of the function func1, the instruction flow is a linear flow. Therefore, the N cycle simply means that the address of the Nth instruction is the farthest address that can be reached in the cycle number N (hereinafter, the farthest address).

  As shown in Example 1 of FIG. 6B, the code generation device 100 sets the constant voltage portion Z1 from the start address to the farthest address of the assembly code 55 of the function func1, and the assembly code 55 of the function func1 from the farthest address. The assembly code 55 of the function func1 is divided so that the low-voltage part K1 is reached up to the end address of. Therefore, in the present embodiment, the farthest address is a division position calculated by the code generation device 100.

  As shown in Example 2 of FIG. 6B, when the function func3 is executable from the start address to the end address within N cycles, the assembly code 55 of the function func3 is always transferred to the constant voltage memory without being divided. Deploy.

  FIG. 7 is a diagram for explaining the calculation of the division position when there is a branch in the function. FIG. 7A shows the instruction flow, and FIG. 7B shows an example of division.

  When there is a branch in the function, the code generation device 100 sets the farthest address that can be reached through the branch point when the instruction in N cycles is traced.

  When the function func1 is a function having a branch shown in FIG. 7A, the instruction flow after passing through the branch point 1 is divided into a path 1 and a path 2. When the function func1 is a code as shown in FIG. 7B, the path 2 going from the branch point 1 to the n3 cycle is to an address away from the start address of the assembly code 55 of the function func1 within N cycles. Can reach. Therefore, the code generation device 100 calculates the farthest address that can reach the N cycle in the path 2 as the farthest address (division position). Then, the code generation device 100 divides the range from the start address of the assembly code 55 of the function func1 to the farthest address as a constant voltage unit Z1, and the range from the farthest address to the end address of the assembly code 55 of the function func1 as a low voltage unit K1. .

  FIG. 8 is a flowchart for explaining the calculation of the division position of the assembly code 55 shown in step S51 of FIG. The process described with reference to FIG. 8 is executed on the assembly code 55 for each function included in the assembly 50.

  When the number of cycles N included in the assembly 50 and the parameter 60 is input, the code generation apparatus 100 according to the present embodiment initializes the work queue in a state where the start instruction node of the function and the number of cycles = 0 are stacked. (Step S801).

  Next, the code generation device 100 extracts the instruction node and the cycle number from the queue (step S802). Then, the code generation device 100 determines whether the instruction node fetched from the queue is a return instruction or whether the number of cycles is greater than N (step S803). In step S803, if the instruction node fetched from the queue is not a return instruction and the number of cycles is not greater than N, the code generating apparatus 100 proceeds to step S804. In step S803, if the instruction node fetched from the queue is a return instruction, or if the number of cycles is greater than N, the code generation device 100 performs the processing in step S807 and later described later.

  In step S804, the code generation device 100 determines whether the instruction node fetched from the queue is a conditional branch instruction. If the instruction is a conditional branch instruction in step S804, the code generating apparatus 100 proceeds to step S805. In step S805, the code generation device 100 obtains a branch destination instruction node and loads the instruction node on the queue. If it is not a conditional branch instruction in step S804, the code generation device 100 proceeds to step S806. In step S806, the code generation device 100 loads the instruction node next to the conditional branch instruction on the queue.

  Subsequently, the code generation device 100 determines whether or not the current address of the instruction node is an address farther from the start address of the assembly code 55 than the farthest address (step S807). The farthest address to be compared with the current address in step S807 is a temporary farthest address having an initial value set in advance. The current address of the instruction node is the address of the instruction node loaded in the last queue.

  If it is determined in step S807 that the current address is farther from the start address of the assembly code 55 than the temporary farthest address, the process proceeds to step S808. In step S808, the code generation device 100 substitutes the current address for the temporary farthest address, and determines the current address as the farthest address.

  If the current address is closer to the start address of the assembly code 55 than the temporary farthest address in step S807, the process proceeds to step S809. In step S809, the code generation device 100 determines whether or not the queue is empty. If the queue is not empty, the code generation device 100 repeats the processes in and after step S803.

  If the queue is empty in step S809, the code generation device 100 proceeds to step S810, determines the farthest address as the division position of the assembly code 55, and the code length from the start address of the assembly code 55 to the farthest address. Is a constant voltage portion, and the code length from the farthest address to the end address of the assembly code 55 is the low voltage portion, and the calculation of the division position is completed. The constant voltage portion of the assembly code 55 is a code that is always placed in the constant voltage memory, and the low voltage portion of the assembly code 55 is a cord that is placed in the constant voltage memory when in use.

  In the present embodiment, the number of cycles is extracted with a cycle for executing one instruction as one cycle, but the present invention is not limited to this. For example, the code generation device 100 may hold a table in which instruction codes are associated with the number of cycles, and may retrieve the number of cycles by referring to the table for each instruction code.

  Next, determination of a memory map in the code generation device 100 will be described with reference to FIG. FIG. 9 is a flowchart illustrating the determination of the memory map shown in step S52 of FIG.

  The code generation device 100 refers to the assembly code 55 for each function and extracts the number of times the function having the low voltage unit is called as the number of calls information (step S901). FIG. 10 shows an example of the call count information. In the call count information 51 shown in FIG. 10, functions func1 and func2 are extracted as functions that call a function having a low voltage part. The number-of-calls information 51 associates a function name with the number of times a function having a low-voltage part is called in a constant voltage part for each function, and the number of times a function having a low-voltage part is called in a low-voltage part. Information.

  Returning to FIG. 9, the code generation device 100 extracts the code size s_v of the power control code and the code size s_j of the jump control code from the power control code pattern 64 and the jump code pattern 65 included in the control code pattern 63. .

  Next, the code generation device 100 corrects the code size of the assembly 50 (step S903). The code generation device 100 corrects the code size of the assembly 50 based on the number-of-calls information 51 extracted in step S901, the code size s_v and code size s_j extracted in step S902, and function size information 52 described later. Do.

  Details of the code size correction will be described below.

  In the code generation device 100, when the division position of the assembly code 55 included in the assembly 50 is calculated, the code generation device 10 sets the function size information 52 in which the function name is associated with information on the size of the assembly code 55 for each function. Is generated. FIG. 11 is a diagram illustrating an example of function size information. The function size information 52 is information in which the function name of the assembly code 55 for which the division position is determined is associated with the size of the low voltage portion and the size of the constant voltage portion for each function. In the function size information 52 shown in FIG. 11, the function func1, which is the function name of the function having the low voltage part, the size of the constant voltage part of the function func1, and the size of the low voltage part of the function func1 are associated with each other. Similarly, the function func2 is associated with the function name of the function func2, the size of the constant voltage portion of the function func2, and the size of the low voltage portion of the function func2.

  In the code generation device 100, when the assembly code 55 is divided into the constant voltage portion and the low voltage portion, the constant voltage memory in use in which the low voltage portion is arranged is specified in the memory in which the assembly code 55 of the constant voltage portion is arranged. It is necessary to insert a jump control code to be used and a power supply control code for making the constant voltage memory in a constant voltage state when in use.

  Therefore, the code generation device 100 includes a function call information 51 having a low voltage part, a function size information 52 of a function having a low voltage part, a code size s_v of a power supply control code, and a code size s_j of a jump control code. Based on this, the size of the assembly code 55 for each function is corrected. More specifically, for a function having a low voltage part, (size of a constant voltage part) is (code size s_v) × (number of times a function having a low voltage part is called in the constant voltage part + 1) + (code size (s_j) is added, and (size of the low voltage part) is corrected by adding (code size s_v of the power supply control code) × (number of times the function having the low voltage part is called in the low voltage part). On the other hand, the function having no low voltage part is corrected by adding (code size s_v) × (number of times the function having the low voltage part is called in the constant voltage part). Then, the code generation device 100 corrects the code size of the assembly 50 by reflecting the correction result of the assembly code 55 of the function having the low voltage part on the size of the assembly 50.

  When the correction of the code size of the assembly 50 is completed, the code generation device 100 performs memory allocation in both the constant voltage memory and the constant voltage memory when in use (step S904). Memory allocation is performed based on the structure information 62 of the memory unit 10 included in the parameter 60. FIG. 12 is a diagram illustrating an example of the structure information of the memory unit. The structure information 62 is information in which memory names, start addresses, and end addresses of a plurality of memories included in the memory unit 10 are associated with each other. Details of the memory allocation will be described later.

  Returning to FIG. 9, when the allocation of the memory is completed, the code generation device 100 labels the low voltage portion of the assembly code 55 (step S905) and completes the memory map determination. The code generation device 100 labels (function name) _L at the start portion of the low voltage portion of the assembly code 55 whose division position is determined. FIG. 13 is a diagram illustrating an example of labeling. For example, the code generation device 100 labels the start address of the low voltage portion of the assembly code 55 of the function func1 arranged in the memory A, which is a constant voltage memory when in use, as a function func1_L. Similarly, for the function func2, the function func2_L is labeled at the start address of the low voltage portion of the assembly code 55 of the function func2 arranged in the memory B.

  Next, memory allocation in step S904 in FIG. 9 will be described with reference to FIGS. The code generation device 100 according to the present embodiment may always perform memory allocation to the constant voltage memory and memory allocation to the constant voltage memory when in use by any of the methods shown in FIGS. 14 to 17.

  FIG. 14 is a first flowchart for explaining memory allocation. When the correction of the code size of the assembly 50 is completed, the code generation device 100 assigns the assembly code 55 included in the assembly 50 from the top of the plurality of memories included in the memory unit 10 (step S1401). Next, the code generation device 100 assigns the assembly code 55 that first appears in the assembly 50 to the first memory (memory A), and determines whether the assembly code 55 crosses the boundary between the memory A and the memory B (step). S1402).

  When straddling a memory boundary in step S1402, the code generation device 100 assigns the assembly code 55 only to the memory B (step S1403). When the boundary of the memory is not crossed in step S1402, the code generation device 100 assigns the assembly code 55 to the memory A, and determines whether the assembly code 55 of all the functions included in the assembly 50 is assigned (step S1404). ). When the allocation of all assembly codes 55 is completed in step S1404, the code generation device 100 ends the memory allocation.

  FIG. 15 is a second flowchart for explaining memory allocation. When the correction of the code size of the assembly 50 is completed, the code generation device 100 sorts the function names included in the assembly 50 in alphabetical order (step S1501). Next, the code generation device 100 executes the processing from step S1401 to step S1404 in FIG.

  FIG. 16 is a third flowchart for explaining memory allocation. When the correction of the code size of the assembly 50 is completed, the code generation device 100 scans the memory unit 10 to obtain a memory to which the assembly code 55 that appears first in the assembly 50 is allocated without crossing the memory boundary. A code 55 is assigned (step S1601).

  The code generation device 100 determines whether or not all the assembly codes 55 included in the assembly 50 have been assigned in the process of step S1601 (step S1602), and when all the assembly codes 55 have been assigned, the memory assignment ends.

  FIG. 17 is a fourth flowchart for explaining memory allocation. When the correction of the code size of the assembly 50 is completed, the code generation device 100 sorts the assembly codes 55 included in the assembly 50 in descending order of the code size (step S1701). Then, the code generation device 100 executes the processes of steps S1601 and S1602 in FIG. 16 (step S1702).

  Next, control code insertion in the code generation device 100 will be described. The code generation apparatus 100 according to the present embodiment inserts a jump control code to a constant voltage memory in use, in which a low voltage part is assigned to a division position, into an assembly code 55 of a function having a low voltage part. In addition, the code generation device 100 inserts a power supply control code for setting the constant voltage memory in use in which the low voltage portion is assigned to the head portion of the assembly code 55 to a constant voltage state. Further, the code generation device 100 determines whether or not the constant voltage memory at the time of use in which the low voltage portion of the assembly code 55 is arranged can be in a low voltage state after executing the function. Insert a power supply control code that puts the constant voltage memory in a low voltage state.

  The insertion of the control code will be described below with reference to FIGS. FIG. 18 is a first flowchart for explaining the insertion of the control code shown in step S53 of FIG.

  The code generation device 100 extracts a function having a low voltage part from the functions included in the assembly 50 to generate a list L1 of functions having a low voltage part (step S1801). The list L1 may be extracted when the function size information 52 is extracted in the code size correction described with reference to FIG.

  The code generation device 100 selects one function func from the list L1 created in step S1801, extracts the assembly code 55 of the selected function and sets it as a file f (step S1802).

  Next, the code generation device 100 embeds parameters in the power control code pattern 64 and the jump control code pattern 65 based on the division position calculated in step S51 and the memory map determined in step S52 (step S1803). For example, when the code of the low voltage portion of the assembly code 55 extracted in the file f is arranged in the memory B, the code generation device 100 designates a memory to be in a constant voltage state in the power control code pattern 64 “memory B "Is embedded as a parameter. The code generating apparatus 100 embeds the start address of the low voltage part of the function func obtained by referring to the memory map determined in step S52 as the jump destination address in the jump control code pattern 65.

  When the parameter is embedded, the code generation device 100 inserts the power control code and the jump control code in which the parameter is embedded into the file f (step S1804). Next, the code generation device 100 determines whether or not the list L1 created in step S1801 is empty (step S1805), and repeatedly executes steps S1802 to S1804 until the list L1 becomes empty. When the list L1 becomes empty, the process proceeds to step S1901 described later.

  FIG. 19 is a second flowchart for explaining control code insertion shown in step S53 of FIG. FIG. 19 shows processing executed after the list L1 becomes empty.

  The code generation device 100 creates a static call graph (call relation diagram) of the functions included in the assembly 50 (step S1901). Next, the code generation device 100 creates a list L2 in which the address of the function call instruction in the assembly 50 is associated with the called function name (step S1902).

  The code generation device 100 extracts the address of one call instruction as the address x from the list L2, and extracts the function name called at the address x as the character string variable funcx (step S1903). The code generation device 100 places a memory in which the function indicated by the character string variable funcx is placed as Mx, and updates the character string variable func with the character string variable funcx (step S1904). Subsequently, the code generation device 100 replaces the character string variable func with the caller function name of the function indicated by the character string variable func, and places the memory in which the function indicated by the character string variable funcx is placed as M (step S1905). .

  Next, the code generation device 100 determines whether or not the memory M and the memory Mx are the same memory (step S1906). In consideration of repetitive execution, which will be described later, the code generation device 100 arranges the assembly code 55 of the called function and either the assembly code 55 of the function called from the main function to the caller function in the same memory. It is judged whether or not.

  If the memory M and the memory Mx are the same in step S1906, the process proceeds to step S1907.

  If the memory M and the memory Mx are not the same memory in step S1906, the code generation device 100 determines whether or not the character string variable func (here, indicating the caller function) indicates the main function (step S1908). . If it is determined that the character string variable func indicates the main function, the code generation device 100 embeds a parameter in the power control code pattern 64 and determines the power control code (step S1909). The parameter embedded here is a parameter for setting the memory Mx in which the call destination function indicated by the character string variable funcx is placed into a low voltage state.

  When the parameter is embedded in the power control code pattern 64, the code generation device 100 inserts the power control code immediately after the address x extracted in step S1902 (step S1910), and the process proceeds to step S1907.

  In step S1907, the code generation device 100 determines whether or not the list L2 is empty. When the list L2 is empty, the control code insertion is terminated. If the list L2 is not empty, the process returns to step S1903, and the processes of steps S1903 to S1906 and steps S1908 to S1910 are repeated.

  Note that FIG. 19 does not describe the case where a plurality of caller functions exist, but when there are a plurality of caller functions, step S2704 and step S2705 are executed for all callers.

  When the control code is inserted into the assembly 50, the code generation apparatus 100 assembles and links the assembly 50A after the control code is inserted, and outputs the binary 70 with power control.

  The operation of an LSI or the like on which the power supply controlled binary 70 output by the code generation device 100 of this embodiment is mounted will be described below with reference to FIG. FIG. 20 is a diagram for explaining an example of the operation of the semiconductor integrated circuit in which the binary with power supply control generated by the code generation device of the first embodiment is mounted.

  In FIG. 20, the execution state of the function arranged in the memory and the state of the power supply voltage of the memory are shown in correspondence with each other. The memory A is always a constant voltage memory, and the memories B, C, and D are constant voltage memories when in use.

  When the function func1 is called by the main function funcM arranged in the memory A, the function func1 is executed. A power supply control code for setting the memory B to a constant voltage state is inserted at the start address of the function func1. Therefore, when the execution of the function func1 is started, the memory B starts to shift to a constant voltage state. In the function func1, a jump control code is inserted so as to jump to the memory B when an instruction for N cycles is executed. Therefore, the function func1 jumps to the memory B after N cycles and starts executing the assembly code of the low voltage part of the function func1. Here, the voltage fluctuation time of the memory B corresponds to a time related to execution of N cycles of instructions. Therefore, when the function func1 jumps to the memory B, the memory B is in a constant voltage state. The functions func2 and func3 are the same as the function func1.

  Hereinafter, an operation example of the code generation device 100 according to the present embodiment will be described with reference to FIGS. 21 to 24.

  FIG. 21 is a diagram illustrating an example of an assembly input to the code generation device.

  When the assembly 50 shown in FIG. 21 is input, the code generation device 100 inserts a control code into the assembly code 50. The assembly 50 may include functions other than the functions defined in FIG.

  FIG. 22 is a diagram illustrating an example of a call graph of functions defined in an assembly. The functions func1 and func2 are called by the main function funcM. The function func3 is called by the function func1 and the function func2.

  FIG. 23 is a first diagram illustrating an example of an assembly after the control code is inserted, and FIG. 24 is a second diagram illustrating an example of the assembly after the control code is inserted. FIG. 23 shows an example of code that is always placed in the memory A that is a constant voltage memory, and FIG. 24 shows an example of code that is placed in the memory B and the memory C that are constant voltage memories when in use. Yes.

  Code A1 and code A2 in FIG. 23 are codes inserted by the insertion of the control code described in FIG. The code A1 is a power supply control code for performing control to shift the memory B from the constant voltage state to the low voltage state when the execution of the function func1 in which the low voltage unit is arranged in the memory B is completed. The code A2 is a power supply control code for performing control to shift the memory C from the constant voltage state to the low voltage state when the execution of the function func2 in which the low voltage unit is arranged in the memory C is completed.

  Code B1 and code B2 in FIG. 23 are codes inserted by the insertion of the control code described in FIG. The code B1 is a power supply control code for shifting the memory B in which the low voltage part of the function func1 is arranged from the low voltage state to the constant voltage state immediately after the execution of the constant voltage part of the function func1. The code B2 is a jump control code for jumping to the memory B in which the low voltage part of the function func1 is arranged. The code B2 is inserted at the end of the constant voltage portion of the function func1.

  The code B3 is a power supply control code for shifting the memory C in which the low voltage part of the function func2 is arranged from the low voltage state to the constant voltage state immediately after the execution of the constant voltage part of the function func2. The code B4 is a jump control code for jumping to the memory C in which the low voltage part of the function func2 is arranged. The code B4 is inserted at the end of the constant voltage part of the function func2.

  The code C in FIG. 24 is a label given by the labeling of the low voltage part described in step S905 in FIG. The code C is given to the start address of the low voltage part of the function func1 arranged in the memory B. Similarly, the code D in FIG. 24 is given to the start address of the low voltage part of the function func2 arranged in the memory C.

  As described above, according to the present embodiment, in a function, a code that can be executed within N cycles corresponding to the voltage variation time is always placed in a constant voltage memory, and a code that cannot be executed within N cycles is used. Place in constant voltage memory. Then, a control code for causing the constant voltage memory to be in a constant voltage state when in use is inserted at the head of the code always arranged in the constant voltage memory. In the present embodiment, with the above configuration, it is possible to generate a program code that varies the power supply voltage of the memory at a timing that takes into account the voltage variation time.

(Second embodiment)
A second embodiment of the present invention will be described below with reference to the drawings. The second embodiment is different from the first embodiment in that interrupt processing is considered. Therefore, in the following description of the second embodiment, only differences from the first embodiment will be described, and those having the same functional configuration as the first embodiment will be used in the description of the first embodiment. The same reference numerals as those used are assigned, and the description thereof is omitted.

  FIG. 25 is a first flowchart for explaining insertion of a control code in consideration of interrupt processing.

  In step S1805 of FIG. 18, when the list L1 is empty, the code generation device 100 creates a static call graph of the functions included in the assembly 50 (step S2501). When the call graph is created, the code generation device 100 extracts a set of functions that can be reached from the interrupt handler INT_HANDLER, and divides the extracted functions into the following sets (step S2502). The code generation device 100 includes a function that can reach the extracted function only from the main function funcM, a set of functions that can be reached only from the interrupt handler INT_HANDLER, and a function that can be reached from both the main function funcM and the interrupt handler INT_HANDLER. Divide into sets.

  The next code generation device 100 generates a copy of the function that can be reached from both the main function funcM and the interrupt handler INT_HANDLER (step S2503). The code generation device 100 creates a branch for making the interrupt handler INT_HANDLER accessible from the function that can be reached only from the main function funcM and the function that can be reached only from the interrupt handler INT_HANDLER (step S2504). Then, the process proceeds to the process described in FIG.

  The call graph generated in FIG. 25 will be described below with reference to FIG. FIG. 26 is a diagram illustrating an example of a call graph. FIG. 26A shows an example of the call graph generated in step S2501 of FIG. FIG. 26B shows a call graph of the call graph shown in FIG. 26A when step S2504 in FIG. 25 is completed.

  In step S2502 of FIG. 5, the set of functions included in the assembly 50 is a set of functions F1 that can be reached only from the main function funcM, a set of functions F2 that can be reached only from the interrupt handler INT_HANDLER, and a main function funcM and an interrupt. It is divided into a set of functions F3 reachable from both the handler INT_HANDLER.

  When the set of functions is divided, a set F3a that is a copy of the set F3 is generated in step S2503 of FIG. 5, and the connection destination of the branch from the set F2 toward the set F3 is set as the set F3a. Next, in step S2504 in FIG. 25, the code generation device 100 creates a branch connecting the function included in the set F1 and the function included in the set F3 and the interrupt handler INT_HANDLER.

  The set F3 is handled with two types of functions, one for interrupt and one for normal use (when there is no interrupt), so two nodes are started. As a data structure, there are a method of preparing two types of node management tables and a method of holding four types of lists (two types of output and input) of the adjacent branch of the call graph.

  FIG. 27 is a second flowchart for explaining insertion of a control code when interrupt processing is considered. The processing from step S2701 to step S2709 in FIG. 27 is the same as the processing from step S1902 to step S1910 in FIG.

  As described above, in this embodiment, it is possible to generate a code in which a control code is inserted in consideration of a case where an interrupt occurs during execution of a function.

(Third embodiment)
A third embodiment of the present invention will be described below with reference to the drawings. The third embodiment is different from the first embodiment in that a case where a plurality of memories are allocated to functions is considered. Therefore, in the following description of the third embodiment, only differences from the first embodiment will be described, and those having the same functional configuration as the first embodiment will be used in the description of the first embodiment. The same reference numerals as those used are assigned, and the description thereof is omitted.

  In the first embodiment and the second embodiment, there is a premise that there is one memory allocated to the function before the control code is inserted, and the function does not cross the memory boundary. In the present embodiment, a case is considered in which a plurality of memories are allocated to the function before the control code is inserted.

  FIG. 28 is a diagram for explaining a case where a plurality of memories are allocated to functions. In FIG. 28, a memory A is allocated to the main function funcM, a memory B is allocated to the function func0, a memory C is allocated to the function func1, a memory A is allocated to the function func2, and a memory is allocated to the function func3. B and memory C are allocated.

  In the example of FIG. 28, the function func0 is arranged in the memory B, and the function func1 is arranged in the memory C. Therefore, when the main function funcM calls the function func0, the function func0 calls the function func1, and the function func1 calls the function func3, when the execution of the function func3 is completed and the function func1 returns, the function func1 also includes the memory B. The memory C cannot be in a low voltage state.

  On the other hand, if the main function funcM calls the function func0, the function func0 calls the function func2, and the function func2 calls the function func3, when the execution of the function func3 is completed and the function func2 returns, the memory B Since the function func0 is arranged, the memory B can be in a low voltage state, and since the main function funcM, the function func0, and the function func2 are not arranged in the memory C, the memory C is in the low voltage state. It can be. As described above, when a plurality of memories are assigned to the function, the conditions under which the memory can be brought into the low voltage state are determined independently for each memory.

  FIG. 29 is a flowchart for explaining memory allocation when there are a plurality of memories allocated to a function.

  The processing in step S2901 and step S2902 in FIG. 29 is the same as the processing in step S1401 and step S1402 in FIG.

  When straddling the boundary of the memory in step S2902, the code generation device 100 assigns a function to a plurality of memories (step S2903). For example, the code generation device 100 may assign a function to the memory assigned in step S2901 and the next memory. The processing in step S2904 is the same as the processing in step S1404 in FIG.

  Next, control code insertion according to the present embodiment will be described with reference to FIG. FIG. 30 is a flowchart for explaining insertion of a control code when a plurality of memories are assigned to a function.

  The processing from step S3001 to step S3003 in FIG. 30 is the same as the processing from step S1901 to step S1903 in FIG.

  In step S3004, the code generation device 100 places a set of memories in which the function indicated by the character string variable funcx is placed as Mx, and updates the character string variable func with the character string variable funcx.

  In step S3005, the character string variable func is updated with the function name of the function caller pointed to by the character string variable func. The memory set is updated with the memory set M in which the function indicated by the character string variable func is arranged. Therefore, the memory M in step S3005 indicates a set of memories in which the caller function of the function pointed to by the character string variable func is arranged. And let Mx \ M be Mx. M and Mx are memory sets, and \ is an operator indicating a difference set.

  Here, Mx is a memory in which a function indicated by the character string variable func extracted from the list L2 in step S3003 is arranged. Therefore, Mx \ M is a memory in which a function to be called from the main function to the function calling source of the function extracted in step S3002 among the memory in which the function extracted from the list L2 in step S3002 is allocated. It will not be included.

  Next, the code generation device 100 determines whether or not Mx is an empty set (step S3006). When Mx is an empty set, the memory in which all of the memory in which the function extracted in step S3002 is arranged reaches the function calling source of the function extracted in step S3002 from the main function. It is included in any of the above.

  If it is determined in step S3006 that Mx is an empty set, the code generation device 100 determines whether or not the list L2 is empty (step S3007). If the list L2 is not empty in step S3007, the processing from step S3003 is repeated. If the list L2 is empty in step S3007, the control code insertion is terminated.

  If it is determined in step S3006 that Mx is not an empty set, the code generating device 100 proceeds to step S3008. The processing from step S3008 to step S3010 is the same as the processing from step S1908 to step S1910 in FIG.

  As described above, in the present embodiment, even when the assembly code 55 of the function before the control code is inserted is assigned to a plurality of memories, the same effects as in the first embodiment can be obtained.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. In the following description of the fourth embodiment, only differences from the first embodiment will be described, and those having the same functional configuration as those of the first embodiment are used in the description of the first embodiment. The same reference numerals as the reference numerals are assigned, and the description thereof is omitted.

  In the code generation device 100A of the present embodiment, all the memories are first set to a constant voltage state, and when there is a branch, all the memories other than the memory where the branch destination assembly code 55 is arranged are set to a low voltage state. I do.

  FIG. 31 is a flowchart for explaining the operation of the code generation device of the fourth embodiment. Details of the processing of each step shown in FIG. 31 will be described later.

  The code generation device 100A calculates the insertion position of the control code based on the assembly code 55 included in the assembly 50 and the cycle number 61 (step S3101). When the insertion position of the control code is calculated, the code generation device 100A determines a memory map based on the memory structure information 62 and the control code pattern 63 (step S3102).

  Next, the code generation device 100A determines a parameter to be substituted for the control code pattern 63 and inserts the control code at the position calculated in step S3101 (step S3102). When the control code is inserted, the code generation device 100A assembles and links the assembly 50A after the control code is inserted, and outputs the binary 70 with power control.

  The calculation of the control code insertion position in the present embodiment will be described below. FIG. 32 is a flowchart for explaining the calculation of the insertion position of the control code shown in step S3101 of FIG. 32 is executed for each assembly code 55 of a function included in the assembly 50.

  The code generation device 100A sets the counter value of the counter that counts the number of instructions from the start address x of the assembly code 55 to 0 (step S3201). Next, the code generation device 100A acquires an instruction from the assembly code 55, and sets the counter value as the sum of the count value set in step S3201 and the cycle number of the acquired instruction (step S3202). Since the counter value is 0 in step S3201, the counter value becomes the value of the number of cycles of the acquired instruction in step S3202.

  Subsequently, the code generation device 100A determines whether or not the counter value <2N cycles (step S3203). When the counter value is smaller than 2N cycles, the code generation device 100A determines whether a return instruction is included in the acquired instruction (step S3204). If a return instruction is included in step S3204, the code generation device 100A removes the start address x from the power supply Low insertion position list (step S3205). The power supply low insertion position list is a list showing insertion positions of power supply control codes for shifting the memory from the constant voltage state to the low voltage state.

  Next, the code generation device 100A determines whether or not all instructions included in the assembly code 55 have been scanned (step S3206). If it is determined in step S3206 that all instructions have been scanned, the calculation of the control code insertion position is terminated. If it is determined in step S3206 that all the instructions have not been scanned, the processing from step S3202 is repeated.

  If the counter value is greater than 2N cycles in step S3203, the code generation device 100A determines whether or not a return instruction is included in the acquired instruction (step S3207). When there is a return instruction in step S3207, the code generation device 100A calculates the power supply high insertion position (step S3208). The power high insertion position indicates a position where a power control code for shifting the memory from the low voltage state to the constant voltage state is inserted. Details of the processing in step S3207 will be described later.

  When the power supply high insertion position is calculated in step S3208, the code generating device 100A proceeds to step S3206.

  If it is determined in step S3204 that there is no return instruction, the code generation device 100A determines whether there is a function call instruction (step S3209). If there is a call instruction, the code generation device 100A sets the counter value to 0 (step S3210), and proceeds to step S3205. If there is no call instruction, the code generation device 100A proceeds to step S3206.

  If there is no return instruction in step S3207, the code generation device 100A determines whether there is a calling instruction (step S3211). If there is a call instruction in step S3211, the code generation device 100A sets the counter value to 0 and sets the next address of the call instruction as the start address x. Then, the start address x is added to the power supply Low insertion position list (step S3212). Therefore, the next address of the call instruction is added to the power supply Low insertion position list. The code generating apparatus 100A proceeds to step S3208 following step S3212.

  If the call instruction does not exist in step S3211, the code generation device 100A proceeds to step S3206.

  As described above, according to the present embodiment, as long as there is no call instruction or return instruction within 2N cycles from the start address of the function (branch destination of the call instruction) or the instruction next to the call instruction (branch destination of the return instruction), The insertion position of the control code is calculated so that the memory other than the memory used by the function is in a low voltage state.

  FIG. 33 is a flowchart for explaining the calculation of the insertion position of the control code shown in step S3208 of FIG.

  In step S3208, the code generation device 100A specifies a position before N cycles so that all the memories have a constant voltage state N cycles before the call instruction or the return instruction.

  The code generation device 100A loads the corresponding instruction node included in the assembly code 55 and the number of cycles = 0 in the queue. The code generation device 100A sets the temporary farthest address as the address of the corresponding instruction node (step S3301). Next, the code generation device 100A extracts the instruction node and the cycle number from the queue (step S3302).

  The code generation device 100A determines whether the fetched instruction node is the head of the function or the number of cycles is greater than N (step S3303). When it is determined in step S3303 that the instruction node is not the head of the function or if the number of cycles is smaller than N, the code generation device 100A loads the instruction node immediately before the instruction node extracted in step S3303 in the queue (step S3303). S3304).

  If the code generation device 100A determines in step S3303 that the instruction node is the head of the function or the number of cycles is greater than N, the address of the instruction node extracted in step S3302 is greater than the temporary farthest address. It is determined whether or not it is far from the head (step S3305). If it is determined in step S3305 that the address extracted in step S3302 is farther than the temporary farthest address, the code generation device 100A sets the current address (the address extracted in step S3302) as the farthest address. (Step S3306).

  Next, the code generation device 100A determines whether or not the queue is empty (step S3307). If the queue is not empty in step S3307, the processing from step S3302 is repeated. If the queue is empty in step S3307, the code generation device 100A adds the farthest address to the power supply high insertion position list (step S3308) and ends the process. The power high insertion position list is a list showing insertion positions of power control codes for shifting the memory from the low voltage state to the constant voltage state.

  The code generation device 100A according to the present embodiment generates the power high insertion position list for each function as the list L10 and the power low insertion position list for each function as the list L20 by the processing described with reference to FIGS. 32 and 33. did.

  Next, the determination of the memory map of this embodiment will be described with reference to FIG. FIG. 34 is a flowchart for explaining determination of the memory map shown in step S3102 of FIG.

  The code generation device 100A refers to the assembly code 55 for each function and extracts the number of calls of the function having the low voltage part as the number of calls information (step S3401). Next, the code generation device 100A extracts the code size s_v of the power control code from the power control code pattern 64 (step S3402).

  The code generation device 100A corrects the code size of the assembly 50 based on the code size s_v extracted in step S3402 and the function size information 52 (step S3403). The code generation device 100A of the present embodiment adds the product of the value obtained by adding 1 to the number of function calls and the code size s_v to the size of the assembly code 55 for each assembly code 55 of the function included in the assembly 50. Is the corrected code size.

  The processing in steps S3404 and S3405 is the same as the processing in steps S904 and S905 described with reference to FIG.

  Next, control code insertion according to the present embodiment will be described with reference to FIGS. FIG. 35 is a first flowchart illustrating the insertion of the control code shown in step S3103 of FIG.

  100 A of code generators embed the parameter which makes all the memories a fixed voltage state in the power supply control code pattern 64 contained in the control code pattern 63 (step S3501). Next, the code generation device 100A takes out the power high insertion position list of one function from the list L10 including the power high insertion position list for each function, and sets it as x (step S3502). Next, the code generation device 100A inserts the power control code pattern in which the parameter is embedded in step S3501 into x (step S3503). The code generation device 100A determines whether or not the list L10 is empty (step S3504).

  If the list L10 is empty in step S3504, the code generation device 100A proceeds to the process described with reference to FIG. If the list L10 is not empty in step S3504, the processing from step S3502 is repeated.

  35, the power supply control code for putting the memory in a constant voltage state is inserted into the assembly 50.

  FIG. 36 is a second flowchart for explaining the control code insertion shown in step S3103 of FIG.

  The code generation device 100A extracts the power source Low insertion position list of one function from the list L20 including the power source Low insertion position list for each function, and sets it as x (step S3601). Next, the code generation device 100A embeds a parameter for setting a memory other than the memory MEM (x) in which the function corresponding to x extracted in step S3601 is placed in a low voltage state in the power supply control code pattern 64 (step S3602). .

  The code generation device 100A inserts the power control code in which the parameter is inserted immediately after x (step S3603). Next, the code generation device 100A determines whether or not the list L20 is empty (step S3604). If the list L20 is empty in step S3604, the code generation device 100A ends the insertion of the control code and outputs the assembly 50A. If the list L20 is not empty at step S3604, the processing after step S3601 is repeated.

  As a result of the processing in FIG. 36, a power supply control code for putting unnecessary memory into a low voltage state is inserted into the assembly 50.

  The operation of an LSI or the like on which the power supply controlled binary 70 generated by the code generation device 100A of the present embodiment is mounted will be described below with reference to FIG. FIG. 37 is a diagram for explaining an example of the operation of the semiconductor integrated circuit on which the binary with power supply control generated by the code generation device of the fourth embodiment is mounted.

  In FIG. 37, the execution state of the function arranged in the memory and the state of the power supply voltage of the memory are shown in correspondence with each other. The memory A is always a constant voltage memory, and the memories B, C, and D are constant voltage memories when in use.

  In the example of FIG. 37, the function func1 arranged in the memory B is called by the memory function funcM arranged in the memory A, and all the memories (memory A to D) are set to a constant voltage state before N cycles. In FIG. 37, when the function func1 is called, memories other than the memory B in which the function func1 is arranged are set to a low voltage state. Then, all the memories are set to a constant voltage state again N cycles before the function func3 is called from the function func1.

  Since the function func3 returns to the function func1 within 2N cycles after being called, the memories other than the memory D in which the function func3 is arranged remain in a constant voltage state even after the function func3 is called.

  As described above, according to the present embodiment, it is possible to generate a program code that varies the power supply voltage of the memory at a timing in consideration of the voltage variation time.

(Fifth embodiment)
The fifth embodiment of the present invention will be described below with reference to the drawings. In the following description of the fifth embodiment, only differences from the first embodiment will be described, and those having the same functional configuration as those of the first embodiment are used in the description of the first embodiment. The same reference numerals as the reference numerals are assigned, and the description thereof is omitted.

  In the fifth embodiment of the present invention, a constant voltage memory is always arranged from the main function to a certain level, and a function immediately below the function arranged in the constant voltage memory is always a constant voltage memory and a constant voltage memory in use. Consider the case where they are arranged in

  In this embodiment, in the above case, the same memory as the constant voltage memory in use in which the caller function is arranged is used in a layer below the functions arranged in the constant voltage memory and the constant voltage memory in use in the above case. In addition, it is assumed that the constant voltage memory is not always used when there are a plurality of caller functions that use the same constant voltage memory in use (including the case where there is only one caller function).

  The above assumption will be described below with reference to FIG. FIG. 38 is a diagram for explaining the premise of the fifth embodiment.

  In the arrangement shown in FIG. 38, the main function funcM and the functions funcB1 and funcB2 which are layers below the main function funcM are always arranged in the constant voltage memory A. The functions immediately below the function funcB1 are the function funcC1 and the function funcC2. The function immediately below the function funcB2 is a function funcC3. The function funcC1 is a memory A which is a constant voltage memory at all times and a memory B which is a constant voltage memory when in use, and the function funcC2 is a memory A which is a constant voltage memory at all times and a memory C which is a constant voltage memory when in use. The function funcC3 is arranged in the memory A that is always a constant voltage memory and the memory D that is a constant voltage memory when in use. In the function funcC1, the function funcC2, and the function funcC3, the portion arranged in the memory A is a constant voltage portion of each function.

  In FIG. 38, the constant voltage portion of the function funcC3 is illustrated as C3-1. In the function funcC1, the function funcC2, and the function funcC3, the portions arranged in the memory B, the memory C, and the memory D are the low voltage portions of the respective functions. In FIG. 38, the low voltage part of the function funcC3 is illustrated as C3-2.

  A function funcD1 and a function funcD2 are arranged in the lower layer of the function funcC1, and a function funcE1 and a function funcE2 are arranged in the lower layer. A function funcD3 is arranged below the function funcC2, and a function funcE3 is arranged further below. A function funcD4 is arranged in the lower layer of the function funcC3, and a function funcE4 is arranged in the lower layer.

  The caller functions of the function funcE1 are the function funcD1 and the function funcD2. Therefore, the function funcE1 is arranged only in the memory B that is the constant voltage memory in use, which is the same as the functions funcD1 and funcD2. The caller functions of the function funcE2 are a function funcD2 and a function funcD3. The memories in which these functions are arranged are different from the memory B and the memory C, respectively. Therefore, the function funcE2 is a memory A that is a constant voltage memory at all times and a memory B or a memory C that is a constant voltage memory when in use so that the function call can be normally performed in a state where only either memory is used. Placed in the crab.

  In the example of FIG. 38, the function funcE2 is arranged in the memory A and the memory B, which is the same constant voltage memory in use as the function funcD2. The function funcD1 and the function funcD2 are arranged in the memory B, which is a constant voltage memory in use, which is the same as the function funcC1 that is the caller function.

  Even in the memory C, the function funcE3 and the function funcD3 may be function-called from a function other than the memory C. For this reason, the function funcE3 and the function funcD3 are always arranged in the constant voltage memory A and the same memory C as the respective caller functions. Also in the memory D, the function funcE4 and the function funcD4 are arranged in the memory D at the same position as each caller function.

In the arrangement shown in FIG. 38, for example, the following two routes from the function funcD3 to the return to the main function funcM can be considered.
(1) Function funcD3 (memory C) → function funcC2 (low voltage part) (memory C) → function funcC2 (constant voltage part) (memory A) → function funcB1 (memory A) → main function funcM (memory A)
(2) Function funcD3 (memory C) → function funcC3 (low voltage part C3-2) (memory D) → function funcC3 (constant voltage part C3-1) (memory A) → function funcB2 (memory A) → main function funcM (Memory A)

  Of these, first, consider the case of operating to return to the main function funcM through the path (1).

  The memory C is used by the function funcC2. Therefore, the code generating apparatus 100 according to the first embodiment does not insert a code for setting the memory C in the low voltage state at the position after the return from the function funcD3 in step S53 of FIG. However, since the memory C is not used after the function funcC2, the code generation device 100 according to the first embodiment inserts a code for setting the memory C in a low voltage state at a position after the return from the function funcC2. Therefore, the memory function C returns to the main function funcM after the low voltage state.

  Next, consider a case where the operation is performed so as to return to the main function funcM through the path (2).

  After returning from the function funcD3 to the low voltage part C3-2 of the function funcC3, the memory C is not used. However, a code for setting the memory C to a low voltage state is not inserted in the function funcD3. Further, in the function funcC3, the function funcB2, and the main function funcM, the memory C is not related and is out of control. For this reason, the memory C returns to the main function funcM in a constant voltage state.

  Therefore, in the present embodiment, when returning from the lower layer function to the main function according to the function calling relationship, it can be confirmed that the constant voltage memory is not used after the function placed in the constant voltage memory is used. Only in the case of use, the corresponding constant voltage memory during use is set to a low voltage state. In this embodiment, when returning from the lower layer function to the main function, if the once-used constant voltage memory is used again, the power control is performed so that the corresponding constant voltage memory when used again becomes the constant voltage state. Go through the code. For this reason, in the present embodiment, it is possible to determine whether or not the once-used constant voltage memory is used again.

  In the present embodiment, the constant voltage memory in use that is not used again before returning to the main function is set to a low voltage state in this way, thereby contributing to reduction of power consumption.

  FIG. 39 is a diagram illustrating the functional configuration of the code generation device according to the fifth embodiment. The code generation device 100B of this embodiment includes a code acquisition unit 110, an arrangement determination unit 120, a sleep release code insertion processing unit 130, and a sleep code insertion processing unit 140.

  The code acquisition unit 110 acquires an assembly code of a function from the assembly 50 input to the code generation device 100B of the present embodiment. The arrangement determination unit 120 determines whether or not the assembly code of the acquired function is arranged in both the constant voltage memory in use and the constant voltage memory at all times based on memory map information 57 described later.

  Note that the code generation device 100B of the present embodiment has the physical area shown in FIG. 3 as a table of the memory map information 57 as shown in FIG. FIG. 40 is a diagram illustrating an example of memory map information according to the fifth embodiment.

  The sleep release code insertion processing unit 130 releases the low voltage state of the constant voltage memory during use based on the determination result by the arrangement determination unit 120. For example, the sleep release code insertion processing unit 130 generates a sleep release code so as to change the memory from a low voltage state (hereinafter referred to as a sleep state) to a constant voltage state by the power supply control code, and inserts the sleep release code into the function code. Details of the processing of the sleep release code insertion processing unit 130 will be described later.

  The sleep code insertion processing unit 140 inserts the power control code into the function assembly code based on the memory map information 57 and the power control code pattern 64 so that the constant voltage memory is in a low voltage state when in use. The power supply control code inserted here is a power supply control code (hereinafter referred to as a sleep code) that puts the memory into a sleep state. Details of the processing of the sleep code insertion processing unit 140 will be described later.

  In the code generation device 100B of this embodiment, the assembly code of the function in which the sleep release code and the sleep code are inserted is output as the assembly 50A after the power supply control code is inserted.

  Next, control code insertion by the code generation device 100B of this embodiment will be described with reference to FIG. FIG. 41 is a flowchart for explaining insertion of a control code by the code generation device of the fifth embodiment.

  The process shown in FIG. 41 is a process executed in step S53 of FIG. Note that the code generation device 100B according to the present embodiment starts the processing shown in FIG. 41 after executing the same processing as steps S51 and S52 of FIG. When the process shown in FIG. 41 is completed, the assembly 50A in which the control code is inserted is output. After the assembly 50A is output, the code generation device 100B performs the same processing as step S54 in FIG. 5 and outputs the binary 70 with power control. The code generation device 100B of the present embodiment executes the process shown in FIG. 41 for each function.

  In step S51, the code generation device 100B according to the present embodiment acquires the assembly code 55 for each function by the code acquisition unit 110, and calculates the division position. In the following description, it is assumed that the assembly code of the function funcX has been acquired.

  In step S52, the code generation device 100B determines a memory map for arranging the divided assembly code 55 based on the division position and the structure information 62 of the memory unit 10 included in the parameter 60, and sets the memory map information 57. Output.

  Next, the code generation device 100B proceeds to step S53. Note that the processing from step S 4101 to step S 4106 in FIG. 41 is processing executed by the arrangement determination unit 120 and the sleep release code insertion processing unit 130. The processing from step S4107 to step S4109 is processing executed by the sleep code insertion processing unit 140.

  When the code generation device 100B starts executing step S53, the arrangement determining unit 120 always maintains the constant function voltage memory and the assembly code 55 of the function funcX based on the divided assembly code 55 and the memory map information 57. It is determined whether or not to use both of the voltage memory (step S4101).

  In step S4101, when the function funcX uses only one of the constant voltage memory in use and the constant voltage memory at all times, the process proceeds to step S4106 described below.

  If both the constant voltage memory in use and the constant voltage memory are used in step S4101, the code generation device 100B divides the assembly code 55 of the function funcX according to the division position calculated in step S51 (step S4102). The first half of the divided assembly code 55 is a constant voltage portion Xa, and the second half is a low voltage portion Xb.

  Subsequently, the code generation device 100B embeds parameters in the power control code pattern 64 and the jump control code pattern 65 based on the memory map determined in step S52 (steps S4103 to 4106).

  The sleep release code insertion processing unit 130 uses, as a parameter, a “constant voltage memory in use in which the low voltage part Xb is arranged” that specifies a memory to be in a constant voltage state in the power supply control code pattern 64 at the head of the constant voltage part Xa. Embed (step S4103). In this embodiment, a power control code pattern in which a parameter for setting a constant voltage state is embedded is set as a sleep release code. The sleep release code of the present embodiment sets, for example, a memory in which the low voltage unit Xb is arranged to a constant voltage state (a usable state).

  Next, the code generation device 100B inserts a label funcX_L representing the start address of the low voltage part Xb of the function funcX (step S4104). Further, the code generation device 100B embeds a label funcX_L indicating the start address of the low voltage part of the function funcX in the jump control code pattern 65 (step S4105).

  As described above, the sleep release code is inserted into the assembly code 55 of the function funxX so that the constant voltage memory can be used during use.

  Next, the code generation device 100B executes a process of inserting a sleep code for setting the constant voltage memory in use into a low voltage state for the function call in the function funcX (step S4106). In the process of step S4106, the processes of steps S4107 to 4109 described below are performed.

  The code generation device 100B according to the present embodiment scans each instruction (code) in the function funcX and determines whether the instruction is a call instruction (step S4107). If the instruction is not a call instruction in step S4107, the process of step S4106 is terminated.

  If the instruction is a call instruction in step S4107, the sleep code insertion processing unit 140 determines that the memory in which the call destination function is arranged (hereinafter called the call destination memory) is the same memory as the memory in which the call instruction of the function funcX is arranged. Alternatively, it is determined whether or not the memory is always a constant voltage (step S4108). In step S4108, when the memory in which the callee function is arranged is the same memory as the memory in which the call instruction is arranged or the constant voltage memory, the processing in step S4106 is terminated.

  In step S4108, when the call destination memory is not the same memory as the memory in which the call instruction is arranged or the constant voltage memory, the sleep code insertion processing unit 140 lowers the power of the call destination memory next to the call instruction of the function funcX. A power supply control code for voltage is inserted (step S4109), and the process of step S4106 is terminated.

  For example, consider a case where the code of the low voltage part Xb in the assembly code 55 of the function funxX is arranged in the memory Y and the function funcY arranged in the memory Z is called in the assembly code 55 of the function funcX.

  When the code generating apparatus 100B returns to the function funcX after executing the function funcY, the code generating apparatus 100B sets the memory Z to a low voltage state. In other words, the sleep code insertion processing unit 140 generates a sleep code by embedding “memory Z” that designates a memory to be set in the low voltage state in the power control code pattern 64 as a parameter. Then, the sleep code insertion processing unit 140 inserts the sleep code generated immediately after the function call instruction for calling the function funcY in the assembly code 55 of the function funcX.

  The processing shown in FIG. 41 will be further described below with reference to FIGS.

  FIG. 42 is a diagram for explaining processing of the sleep release code insertion processing unit and the sleep code insertion processing unit.

  In step S4101, the sleep release code insertion processing unit 130 does not insert the sleep release code when the function funcX always uses only the constant voltage memory or the constant voltage memory when in use. When the function funcX always uses a constant voltage memory and a constant voltage memory when in use, the function funcX is divided into a constant voltage part Xa and a low voltage part Xb. The sleep release code insertion processing unit 130 inserts a sleep release code that puts the memory in which the low voltage unit Xb is arranged into a constant voltage state at the head of the constant voltage unit Xa. In FIG. 42, the constant voltage memory in use in which the low voltage portion Xb is arranged is the memory XB.

  When the call instruction is present in the assembly code 55 of the function funcX, the sleep code insertion processing unit 140 determines whether the call destination memory is the same memory as the memory in which the call instruction is arranged or a constant voltage memory at all times. . When the call destination memory is the same memory as the memory in which the call instruction is arranged or the constant voltage memory at all times, the sleep code insertion processing unit 140 does not insert the sleep code.

  When the call destination memory is not the same memory as the memory in which the call instruction is arranged or the constant voltage memory at all times, the sleep code insertion processing unit 140 generates a sleep code for setting the call destination memory to the low voltage state after the call instruction of the function funcX. insert.

  As shown in FIG. 42, when the call instruction of the function funcX is arranged in the memory X and the call destination memory is the memory Y, the sleep code insertion processing unit 140 applies the memory Y to the low voltage next to the call instruction of the function funcX. Insert the sleep code to be in the state.

  By inserting the sleep code in this way, the memory Y can be brought into a low voltage state when returning from the function funcY to the function funcX, which can contribute to a reduction in power consumption.

  Hereinafter, the processes of the sleep release code insertion processing unit 130 and the sleep code insertion processing unit 140 will be further described with reference to FIG. 38 as an example.

  FIG. 43 is a diagram illustrating a case where the function funcX is the main function funcM.

  The main function funcM is always arranged to use only the constant voltage memory, and the jump control code to the constant voltage memory in use to which the low voltage part is assigned and the constant voltage memory in use to which the low voltage part is assigned are constant. It is not necessary to insert a power supply control code to be in a voltage state. Therefore, when the function funcX is the main function funcM, the process proceeds from step S4101 to step S4106 in FIG.

  In step S4107, the main function funcM includes a call instruction for calling the function funcB1. Therefore, the process proceeds to step S4108. In step S4108, the memory in which the function funcB1, which is a call destination function, is always a constant voltage memory. Therefore, it is not necessary to insert a power supply control code for setting the constant voltage memory in a low voltage state when in use, and the process of step S4106 is terminated.

  FIG. 44 is a diagram illustrating a case where the function funcX is the function funcB1.

  Similarly to the main function funcM, the function funcB1 is also always placed in the constant voltage memory, and the power supply that puts the constant voltage memory in use in a constant voltage state to which the jump control code to the constant voltage memory in use and the low voltage part are assigned is used. There is no need to insert a control code.

  Therefore, when the function funcX is the function funcB1, in FIG. 41, the process proceeds from step S4101 to step S4106.

  In step S4107, the function funcB1 includes a call instruction for calling the function funcC1. Therefore, the process proceeds to step S4108. In step S4108, the function funcC1 is placed in the constant voltage memory B when in use. The memory B is not the same as the memory in which the function funcB1 is arranged, and is not always a constant voltage memory. Therefore, the process proceeds to step S4109.

  After the function funcC1 is executed, the memory B is not used before returning to the main function funcM. Therefore, in step S4109, the power supply control code for setting the memory B in the low voltage state is inserted after the call instruction of the function funcB1.

  FIG. 45 is a diagram illustrating a case where the function funcX is the function funcD2.

  The function funcD2 is arranged to use only a constant voltage memory when in use. Therefore, it is not necessary to insert a power supply control code for making the constant voltage memory in a constant voltage state during other use. Therefore, when the function funcX is the function funcD2, in FIG. 41, the process proceeds from step S4101 to step S4106.

  In step S4107, the function funcD2 includes a call instruction that calls the function funcE1, the function funcE2, and the function funcE3. Therefore, the process proceeds to step S4108.

  In step S4108, the function funcE1 and the function funcE2 are placed in the same constant voltage memory B during use as the function funcD2. That is, since the function B is used even after the functions funcE1 and funcE2 return to the function funcD2, the process of step S4106 is terminated without inserting the power supply control code for setting the memory B in the low voltage state into the function funcD2.

  On the other hand, the function funcE3 is arranged in a constant voltage memory C at the time of use different from the function funcD2. Therefore, the process proceeds to step S4109. Since the memory B is used after the function funcE3 returns to the function funcD2, in step S4109, a power supply control code for setting the memory C to a low voltage state is inserted after the call instruction of the function funcE3 in the function funcD2.

  FIG. 46 is a diagram illustrating a case where the function funcX is the function funcC3.

  The function funcC3 is arranged so as to always use the memory A that is a constant voltage memory and the memory D that is a constant voltage memory when in use. Accordingly, the process proceeds from step S4101 to step S4102 and subsequent steps in FIG.

  The function funcC3 is divided into a constant voltage part C3-1 and a low voltage part C3-2 based on the function size information 52. The constant voltage unit C3-1 is allocated to the memory A, and the low voltage unit C3-2 is allocated to the memory D.

  When the function funcC3 is divided, the sleep release code insertion processing unit 130 sets a sleep release code for setting the memory D in which the low voltage unit C3-2 is arranged to a constant voltage state at the head of the constant voltage unit C3-1. insert. The sleep release code insertion processing unit 130 labels the beginning of the low voltage unit C3-2 and inserts the jump control code to the memory D at the end of the constant voltage unit C3-1.

  The function funcC3 includes a call instruction that calls the function funcD3 and the function funcD4. The function funcD4 is arranged in the memory D, which is a constant voltage memo when in use, which is the same as the function funcC3, and the function funcD4 uses the memory D after returning. Therefore, the sleep code insertion processing unit 140 does not insert the sleep code for setting the memory D in the low voltage state after the call instruction of the function funcD4 in the assembly code of the function funcC3.

  On the other hand, the function funcD3 is arranged in a memory C, which is a constant voltage memory when used, different from the function funcC3, and the memory C is not used after returning from the function funcD3 to the function funcC3. Therefore, the sleep code insertion processing unit 140 inserts a sleep code for setting the memory C in a low voltage state immediately after the call instruction of the function funcD3 in the assembly code of the function funcC3.

  As described above, in the present embodiment, the memory in which the caller function is arranged is different from the callee memory in which the callee function is arranged, and the call is made after returning from the callee function to the caller function. When the destination memory is not used again, a sleep code for putting the destination memory in a low voltage state is inserted immediately after the call instruction in the assembly code 55 of the caller function. In the present embodiment, this allows the callee memory to be in a low voltage state when the callee function returns to the caller function, thereby contributing to the reduction of power consumption.

(Sixth embodiment)
The sixth embodiment of the present invention will be described below with reference to the drawings. In the following description of the sixth embodiment, only differences from the fifth embodiment will be described, and those having the same functional configuration as the fifth embodiment were used in the description of the fifth embodiment. The same reference numerals as the reference numerals are assigned, and the description thereof is omitted.

  In the sixth embodiment of the present invention, as in the fifth embodiment, the main function up to a certain level is always placed in a constant voltage memory, and the function directly below the function placed in the constant voltage memory is always a constant voltage. Consider the case where the memory and the constant voltage memory are in use.

  Further, in the above case, in the hierarchy below the functions arranged in the constant voltage memory and the constant voltage memory in use, the same memory as the constant voltage memory in use in which the caller function is arranged is used, and Assuming that the constant voltage memory is not always used when there are a plurality of caller functions that use the same constant voltage memory when used (including the case where there is only one caller function), the same as in the fifth embodiment It is.

  FIG. 47 is a diagram for explaining the premise of the sixth embodiment. FIG. 47A shows a function call relationship in the present embodiment. FIG. 47B shows the result of generating a memory map based on the call relationship shown in FIG. In the state of FIG. 47, when the control code is inserted by the code generation device 100B of the fifth embodiment, the sleep code is inserted so that the memories B and C are in the low voltage state as follows.

When memory B is in a low voltage state:
(1) When returning from function funcA2 to function funcMAIN (2) When returning from function funcA5 to function funcMAIN (3) When returning from function funcB1 to function funcA1 (4) When returning from function funcB2 to function funcA3 (5) ) When returning from function funcD1 to function funcC1 (6) When returning from function funcC2 to function funcB3

When memory C is in a low voltage state:
(1) When returning from function funcA1 to function funcMAIN (2) When returning from function funcA3 to function funcMAIN (3) When returning from function funcA4 to function funcMAIN (4) When returning from function funcC1 to function funcB1 (5) ) When returning from function funcB5 to function funcB4

  Consider a case in which functions are called in the order of function funcMAIN, function funcA1, function funcB1, function funcC1, and function funcD1 in the program in which the control code is inserted so that the memory B and memory C are in a low voltage state at the above timing.

  In this case, when returning from the function funcD1 to the function funcC1, the memory B is in a low voltage state. Subsequently, an attempt is made to return from the function funcC1 to the function funcB1, but at this time, the memory B is already in a low voltage state.

  Therefore, when the processor executing this program tries to execute an instruction to return from the function funcC1 to the function funcB1, the processor cannot access the memory B. As a result, the processor cannot obtain instructions and may not operate correctly.

  In this embodiment, regardless of what memory map is obtained, control code is generated so that the processor can obtain instructions and operate correctly.

  FIG. 48 is a diagram illustrating the functional configuration of the code generation device according to the sixth embodiment. The code generation device 100C of the present embodiment includes a sleepable table creation unit 150 in addition to the units included in the code generation device 100B of the fifth embodiment.

  The code generation device 100C of this embodiment inserts a control code based on the table created by the sleep capable table creation unit 150.

  The sleep capable table creation unit 150 according to the present embodiment is a table indicating a set of all constant voltage memories in use that can be used up to the function f by the function call relation information 58 and the memory map 57, UPFM (f) Create Also, the sleep capable table creation unit 150 of the present embodiment determines whether or not the memory in which the function g is placed may be in a low voltage state when returning from the function g to the function f based on UPFM (f). A PowerOff (f, g), which is a table to be shown, is created. The two created tables are stored in a predetermined area of the auxiliary storage device 104 or the memory device 105 included in the code generation device 100C of the present embodiment. Details of creation of the two tables by the sleep capable table creation unit 150 will be described later.

  Note that the function call relationship information 58 of this embodiment indicates the call relationship in each function included in the assembly 50. The function call relationship information 58 of the present embodiment may be given in advance to the code generation device 100C, or may be generated from the assembly 50 by the code generation device 100C.

  Next, control code insertion by the code generation device 100C of the present embodiment will be described with reference to FIG. FIG. 49 is a flowchart for explaining insertion of a control code by the code generation device of the sixth embodiment.

  The process shown in FIG. 49 is a process executed in step S53 of FIG. Note that the code generation device 100C of the present embodiment starts the processing shown in FIG. 49 after executing the same processing as in steps S51 and S52 of FIG. When the process shown in FIG. 49 is completed, the assembly 50A in which the control code is inserted is output.

  After the assembly 50A is output, the code generation device 100C performs the same processing as step S54 in FIG. 5 and outputs the binary 70 with power control. The code generation device 100C according to the present embodiment executes the processing illustrated in FIG. 49 for each function.

  In step S51, the code generation device 100C of the present embodiment acquires the assembly code 55 for each function by the code acquisition unit 110, and calculates the division position. In the following description, it is assumed that the assembly code of the function funcX has been acquired.

  In step S52, the code generation device 100C determines a memory map for arranging the divided assembly code 55 based on the division position and the structure information 62 of the memory unit 10 included in the parameter 60, and sets the memory map information 57. Output.

  Next, the code generation device 100 </ b> C proceeds to step S <b> 53, and executes the processing after step S <b> 4901. Note that the processing from step S4901 to step S4906 in FIG. 49 is processing executed by the placement determination unit 120, the sleep release code insertion processing unit 130, and the sleep capable table creation unit 150. The processing from step S4908 to step S4910 is processing executed by the sleep code insertion processing unit 140.

  When the code generating device 100C starts executing step S53, the sleep capable table creating unit 150 executes step S50 and creates PowerOff (f, g) (step S4901). Details of step S50 will be described later.

  The processing from step S4902 to step S4907 is the same as the processing from step S4101 to step S4106 in FIG.

  In the process of step S4907, the sleep code insertion processing unit 140 performs the processes of steps S4908 to 4910 described below.

  The code generation device 100C according to the present embodiment scans each instruction (code) in the function funcX and determines whether the instruction is a call instruction (step S4908). If the instruction is not a call instruction in step S4908, the process of step S4907 ends.

  When the instruction is a call instruction in step S4908, the sleep code insertion processing unit 140 refers to PowerOff (f, g) and determines whether or not the sleep code can be inserted (step S4909). If the sleep code cannot be inserted in step S4909, the process of step S4907 ends. If the sleep code can be inserted in step S4909, the sleep code insertion unit 140 inserts a power control code for setting the power of the callee memory to a low voltage next to the call instruction of the function funcX (step S4910). The process of step S4907 ends.

  As described above, in the present embodiment, the sleep code is inserted only when it is determined from the PowerOff (f, g) generated based on UPFM (f) that the sleep code can be inserted.

  Here, creation of UPFM (f) and PowerOff (f, g) by the sleep capable table creation unit 150 will be described. First, UPFM (f) will be described.

  UPFM (f) of this embodiment is a table showing a set of all constant voltage memories in use that can be used up to the function f. UPFM (f) is defined as the following formula (1).

  Here, Usage_PFM (f) is a set of constant voltage memory names in use used by the function f in the memory map information 57.

  For example, when the function f is the function funcMAIN, UPFM (f) is as follows.

  UPFM (funcMAIN): = φ

  That is, the set UPFM (funcMAIN) of all in-use constant voltage memories that can be used up to the function funcMAIN is an empty set.

  When the function f is the function funcA1, UPFM (f) is as follows.

  UPFM (funcA1): = UPFM (funcMAIN) ∪Using_PFM (funcA1) = {C}

  That is, the set UPFM (funcA1) of all in-use constant voltage memories that can be used up to the function funcA1 is only the memory C.

  When the function f is the function funcB1, UPFM (f) is as follows.

  UPFM (funcB1): = UPFM (funcA1) ∪UPFM (funcA2) ∪Using_PFM (funcB1) = {B, C}

  That is, the set UPFM (funcB1) of all the constant voltage memories in use that can be used up to the function funcB1 is the memory B and the memory C.

  When the function f is the function funcC1, UPFM (f) is as follows.

  UPFM (funcC1): = UPFM (funcA1) ∪UPFM (funcB1) ∪Using_PFM (funcC1) = {B, C}

  That is, the set UPFM (funcC1) of all the constant voltage memories that can be used up to the function funcC1 is the memory B and the memory C.

  Next, PowerOff (f, g) will be described. The PowerOff (f, g) of the present embodiment is a table indicating whether or not the memory in which the function g is placed may be put into a low power state when returning from the function g to the function f. It is defined as (2).

In PowerOff (f, g), for example, consider a case where the function f is a function funcA1 and the function g is a function funcB1. In this case, Using_PFM (funcB1) = {B}, UPFM (funcA1) = {C}, and there is no common element between the function funcB1 and the function funcA1. That is,
Using_PFM (funcB1) ∩UPFM (funcA1) = φ
And
PowerOff (funcA1, funcB1): = True
It becomes. Therefore, the function funcB1 can insert a sleep code that puts the memory B in which the function funcB1 is placed into a low voltage state immediately after the call instruction of the function funcA1.

Next, in PowerOff (f, g), for example, consider a case where the function f is a function funcB1 and the function g is a function funcC1. In this case, Using_PFM (funcC1) = {C}, UPFM (funcB1) = {B, C}, and a common element {C} exists between the function funcC1 and the function funcB1. That is,
Using_PFM (funcC1) ∩UPFM (funcB1) ≠ φ
And
PowerOff (funcB1, funcC1): = False
It becomes. Therefore, the function funcC1 cannot insert a sleep code for setting the memory C in which the function funcC1 is placed into a low voltage state immediately after the call instruction of the function funcC1.

  Next, creation of UPFM (f) and PowerOff (f, g) of the sleep capable table creation unit 150 in step S50 of FIG. 49 will be described with reference to FIG. FIG. 50 is a flowchart for explaining table creation by the sleep capable table creation unit of the sixth embodiment. In this embodiment, UPFM (f) and PowerOff (f, g) are created by performing a breadth-first search on the function call relationship diagram. In breadth-first search, the main function is the starting point, all functions of the function one layer below the main function, then all functions of the function two layers below the main function, and so on, are called in order. Refers to the search method to follow.

  The sleep capable table creation unit 150 of the present embodiment first initializes the queue Q (step S5001). The queue Q is a first-in first-out data structure for storing a function name.

  Next, the sleep capable table creation unit 150 sets f_MAIN to the queue Q as the initial data setting (step S5002), and then initializes UPFM (f_MAIN) to the empty set φ (step S5003). The initial value of UPFM (f) other than f = f_MAIN is in an undefined state that is distinguished from the empty set.

  Subsequently, the sleep capable table creation unit 150 determines whether or not the queue Q is empty (step S5004). If the queue Q is not empty in step S5004, the sleep capable table creation unit 150 proceeds to step S5005.

  If the queue Q is not empty in step S5004, the sleep capable table creation unit 150 extracts a function from the queue Q and sets the extracted function as a function f (step S5005). Subsequently, the sleep capable table creating unit 150 refers to the function call relation information 58 and obtains a call destination function (child function) of the function f (step S5006). In step S5006, the call destination function of the function f is assumed to be functions f1, f2,.

  The sleep capable table creation unit 150 performs PowerOff (f, g) and UPFM on the callee functions g = f1, f2,..., Fn obtained in step S5006 by the processing in steps S5007 to S5015 described below. Create (g). In addition, in step S5007 to step S5015, the sleep capable table creating unit 150 loads the call destination functions (child functions) of the functions f1, f2,. Here, the function loaded in the queue Q is taken out in step S5005 via step S5004, and in steps S5007 to S5015, the call destinations of the call destination functions of the functions f1, f2,. Stacks functions (grandchild functions). In this embodiment, by repeating this, UPFM (f) is obtained for all functions f, and PowerOff (f, g) is obtained for calls from all functions f to function g.

  The steps from step S5007 to step S5015 will be described below.

  The sleep capable table creating unit 150 of the present embodiment initializes a counter variable i indicating the functions f1, f2,..., Fn to 1 (step S5007). In the following description, it is assumed that the i-th function fi is selected as the function g. Next, the sleep capable table creation unit 150 calculates the current PowerOff (f, fi) based on the equation (2) (step S5008).

  In step S5008, the sleep capable table creation unit 150 determines whether UPFM (f) and Usage_PFM (fi) have a common part (common element). If there is no common part in step S5008, PowerOff (f, fi): = True is set (step S5009). If there is a common part in step S5008, PowerOff (f, fi): = False is set (step S5010).

  Subsequently, the sleep capable table creating unit 150 updates UPFM (fi) in steps S5011 to S5014. The processing from step S5011 to step S5014 is processing executed when a call relationship exists between functions in the same hierarchy.

  The sleep capable table creating unit 150 calculates a set T: = UPFM (f) ∪Using_PFM (fi) as a temporary value of UPFM (fi) (step S5011).

  Next, the sleep capable table creation unit 150 compares the set T with UPFM (f) (step S5012). If it is determined in step S5012 that the set T is equal to UPFM (f), there is no need to update UPFM (fi), and the process advances to step S5015.

  If the set T and UPFM (f) are not equal in step S5012, UPFM (f) is replaced with the set T and updated (step S5013). In addition, the sleep capable table creation unit 150 loads fi in the queue Q to be included in the recalculation target (step S5014). This is because this update affects PowerOff (f, g).

  Note that the initial value of UPFM (f) other than f = f_MAIN is an undefined state that is distinguished from an empty set, and is always inserted into the queue Q once through steps S5013 and S5014. Therefore, UPFM (f) can be obtained for all functions f, and PowerOff (f, g) can be obtained for calls from all functions f to function g.

  If the counter variable i becomes equal to n in step S5015, the sleep capable table creating unit 150 has executed the processing from step S5008 to step S5014 for the functions f1, f2,..., Fn. Return. If the counter variable i is not equal to n in step S5015, i is incremented (step S5016), and then the process returns to step S5008.

  The sleep capable table creating unit 150 ends the process when it is determined in step S5004 that the queue Q is empty.

  In the present embodiment, with the above configuration, the control code can be generated so that the processor can obtain an instruction and operate correctly. In the present embodiment, since unnecessary control codes are not inserted, the number of control code insertions can be reduced, and power control of each memory can be performed efficiently.

(Seventh embodiment)
The seventh embodiment of the present invention will be described below with reference to the drawings. The code generation device according to the present embodiment determines the memory map so as to reduce the insertion of the control code. In addition, in this embodiment, the code | symbol similar to the code | symbol used in description of 1st thru | or 6th embodiment is used for what has the function structure similar to 1st thru | or 6th embodiment.

  In the seventh embodiment of the present invention, as in the fifth and sixth embodiments, the main function up to a certain level is always placed in the constant voltage memory, and immediately below the function placed in the constant voltage memory at all times. Consider the case where functions are always placed in a constant voltage memory and a constant voltage memory when in use.

  Further, in the above case, in the hierarchy below the functions arranged in the constant voltage memory and the constant voltage memory in use, the same memory as the constant voltage memory in use in which the caller function is arranged is used, and The assumption that the constant voltage memory is not always used when there are a plurality of caller functions that use the same constant voltage memory in use (including the case where there is one caller function) is also the fifth and sixth. This is the same as the embodiment.

  The purpose of this embodiment is to further reduce power consumption. For example, in the sixth embodiment, any memory map can realize the power of the fifth embodiment phase or the like. However, depending on the pattern of function calls, there is room for further power reduction. For example, consider the case of the memory map of FIG.

  In the memory map of FIG. 47B, when each function is called through a path of function funcMAIN, function funcA2, function funcB1, and function funcD1, the memory B is only in a constant voltage state. However, when the function funcMAIN, the function funcA1, the function funcB1, the function funcC1, and the function funcD1 are called in the path, the memory B, Both C are in a constant voltage state. That is, the memory C that is not used at this time is also in a constant voltage state.

  In this way, in the hierarchy below the functions arranged in the constant voltage memory at the time of use and the constant voltage memory at the time of use, only the restriction of using the same memory as the constant voltage memory at the time of use at which the caller function is arranged is used In some cases, a memory map that has room for power consumption reduction is determined.

  Therefore, the code generation device 100D of this embodiment determines a memory map that can further reduce power consumption.

  FIG. 51 is a flowchart for explaining the operation of the code generation device of the seventh embodiment.

  In the code generation device 100D of the present embodiment, when the assembly 50 and the cycle number N included in the parameter 60 are input, the code generation device 100D calculates the division position of the assembly code 55 for each function (step S5101). . In the present embodiment, the division position calculated in step S5101 is the insertion position where the control code is inserted.

  When the division position of the assembly code 55 is calculated in step S5101, the code generation device 100D arranges the assembly code 55 divided based on the division position and the structure information 62 of the memory unit 10 included in the parameter 60. A memory map is determined (step S5102). Details of the determination of the memory map in this embodiment will be described later.

  When the memory map is generated, the code generation device 100 determines a parameter to be substituted for the control code pattern 63 included in the parameter 60, generates a control code, and inserts the control code at the division position of the assembly code 55 (step). S5103). The code generation device 100D assembles and links the assembly 50A including the assembly code 55 into which the control code is inserted (step S5104), and outputs the power-controlled binary 70 including the control code to complete the code generation.

  The determination of the memory map of this embodiment will be described below with reference to FIG. FIG. 52 is a diagram for explaining determination of a memory map in the seventh embodiment.

  The code generation device 100D of this embodiment includes a parent function selection unit 521, a constant voltage memory allocation unit 522, a total code size calculation unit 523, a call frequency calculation unit 524, a constant voltage memory allocation unit 525 in use, an allocation adjustment / address A calculation unit 526 is included. The code generation device 100D determines a memory map by the above-described units.

  The parent function selection unit 521 of the present embodiment creates call frequency information ρ between functions, and specifies one parent function according to the call frequency information. The call frequency information ρ of the present embodiment is created based on the number of calls on the source code, the number of calls on the execution history, or the weighted sum thereof.

  FIG. 53 is a diagram illustrating an example of call frequency information between functions. As shown in FIG. 53, in the call frequency information ρ, the caller function (parent function), the callee function (child function), and the number of times the caller function calls the callee function (score) are associated with each other. Yes. When there are a plurality of parent functions for one child function, the parent function selection unit 521 of the present embodiment selects the function having the highest relationship, that is, the function having the highest score as the parent function.

  The always constant voltage memory allocation unit 522 performs function allocation to the always constant voltage memory. The constant voltage memory allocation unit 522 of the present embodiment determines the number of function hierarchies that allocate the entire constant voltage memory. Next, the constantly constant voltage memory allocation unit 522 determines a memory to be always a constant voltage memory. Next, the constant voltage memory allocation unit 522 extracts function candidates that allocate the constant voltage unit to the constant voltage memory. Then, the constant voltage memory allocation unit 522 determines the memory allocation for the function that allocates the whole to the constant voltage memory and the memory allocation for the function that always allocates the constant voltage unit to the constant voltage memory.

  The total code size calculation unit 523 creates a function group represented by a function that exists in the layer immediately below the function that is always assigned to the constant voltage memory as a whole, and calculates the code amount of the function group based on the function size information 52. .

  FIG. 54 is a diagram illustrating an example of calculation of the code amount of the function group. The calculation result by the total code size calculation unit 523 is output as the output table 54. In the output table 54, a function group represented by the function funcA1, the function funcA2, the function funcA3, the function funcA4, and the function funcA5, which are functions immediately below the function funcMAIN, which is a function that is always arranged in the constant voltage memory, is created. Yes. Each function group is associated with the total code amount of each function group. In this embodiment, this function group includes only the representative function itself and its descendant functions.

  The call frequency calculation unit 524 refers to the output table 54 and the call frequency information ρ, and creates a call frequency table T in which the call frequency Q between the functions assigned to the constant voltage memory in use is calculated. Details of the processing of the call frequency calculation unit 524 of this embodiment will be described later.

  The in-use constant voltage memory allocation unit 525 refers to the function size information 52, the output table 54, and the call frequency Q, and allocates each function set to the in-use constant voltage memory. Details of the processing of the constant voltage memory allocation unit 525 in use will be described later.

  The allocation adjustment / address calculation unit 526 makes corrections such as deleting unnecessary ones by referring to the allocation result by the constant voltage memory allocation unit 525 when in use, and sets the start addresses of the constant voltage unit and the low voltage unit of each function. calculate. The unnecessary ones are, for example, those in which all the caller functions are arranged in the same memory as a result of the assignment by the constant voltage memory assignment unit 525 in use.

  Then, the allocation adjustment / address calculation unit 526 updates the size of the low voltage part of each function. Then, the allocation adjustment / address calculation unit 526 calculates the start address of the constant voltage portion and the low voltage portion of each function.

  The processing of the call frequency calculation unit 524 of this embodiment will be described below with reference to FIG. FIG. 55 is a flowchart for explaining the processing of the call frequency calculation unit of the seventh embodiment.

  In this embodiment, the call frequency Q (f, g) between the function group F represented by the function f and the function group G represented by the function g is given by the following expression (3).

  Here, p (φ, ψ) is the number of calls (score) from the function ψ to the function φ, and is obtained from the call frequency information ρ. In the present embodiment, this call frequency Q (f, g) is calculated for all pairs of function groups represented by the functions of the next layer after the layer always placed in the constant voltage memory. Further, the call frequency calculation unit 524 refers to each value of the function field of the output table 54 (the name of the function of the next layer after the layer always placed at a constant voltage) as f [1],..., F [L_MAX]. To do.

  L_MAX is the number of functions in the next layer of functions that are always placed in the constant voltage memory. The output table 54 is assumed to be stored as a two-dimensional array Q of L_MAX × L_MAX elements. Therefore, in the present embodiment, the functions f and g described above are sequentially selected and scanned with the functions named f [1],..., F [L_MAX] (however, the same applies to f and g). Is not selected).

  The call frequency calculation unit 524 initializes the variable i to 1 (step S5501). Subsequently, the call frequency calculation unit 524 sets the variable j to i + 1 (step S5502). Subsequently, the call frequency calculation unit 524 calculates the call frequency Q (f [i], f [j]) given by Expression (3) (step S5503) and stores it in the two-dimensional array Q [i, j]. (Step S5504). The call frequency calculation unit 524 repeats the processing of step S5503 and step S5504 while i and j are each equal to or less than L_MAX (steps S5505 to S5508). The call frequency calculation unit 524 of the present embodiment calculates the call frequency Q as described above.

  FIG. 56 is a diagram showing an example of the calculated call frequency Q. With reference to FIG. 56, the call frequency Q (F_A3, F_A4) when f [i] is the function group F_A3 of the output table 54 and f [j] is the function group F_A4 of the output table 54 will be described.

  The function group F_A3 = {f_A3, f_B3}, and the function group F_A4 = {f_A4, f_B4}. Note that f_A3 is a function funcA3, f_A4 is a function funcA4, f_B3 is a function funcB3, and f_B4 is a function funcB4.

Therefore, the call frequency Q is based on the call frequency information ρ,
Q (F_A3, F_A4) = {p (f_A3, f_A4) + p (f_A4, f_A3)} + {p (f_A3, f_B4) + p (f_B4, f_A3)} + {p (f_B3, f_A4) + p (f_A4, f_B3) } + {P (f_B3, f_B4) + p (f_B4, f_B3)} = (0 + 0) + (0 + 0) + (0 + 0) + (13 + 0) = 13
Is calculated. Those not included in the call frequency information ρ are calculated as 0. In this way, the call frequency Q between all the function groups in the output table 54 is calculated, and the call frequency table T is created. FIG. 56 is a diagram illustrating an example of a call frequency table.

  Next, the processing of the constant voltage memory allocation unit 525 in use according to this embodiment will be described. The in-use constant voltage memory allocation unit 525 of this embodiment allocates a function to the in-use constant voltage memory with reference to the function size information 52, the output table 54, and the call frequency table T.

  FIG. 57 is a flowchart for explaining processing of the constant voltage memory allocating unit in use according to the seventh embodiment.

  The in-use constant voltage memory allocation unit 525 initializes the array M_rest [m] with the size of the in-use constant voltage memory m (step S5701). Here, m represents the name of the constant voltage memory when in use.

  Subsequently, in-use constant voltage memory allocation unit 525 specifies a memory to which one function group is allocated in steps S5702 to S5704.

  Specifically, the constant voltage memory allocation unit 525 during use scans the output table 54 to obtain a function group having the maximum total code amount (the sum of the sizes of the low voltage parts of all functions included in the function group). Choose. A representative function of the function group is set as a function f_M (step S5702).

  Next, the in-use constant voltage memory allocation unit 525 finds out-of-use constant voltage memory in which a function group having the function f_M as a representative function can be arranged (step S5703). Here, the in-use constant voltage memory allocation unit 525 finds the in-use constant voltage memory m such that the array M_rest [m] is equal to or greater than the total code amount of the function group having the function f_M as a representative function. The memory m found in step S5703 is a memory in which the low voltage part of each function of the function group f_M is arranged.

  In the present embodiment, the size of the constant voltage memory in use may be acquired from the function size information 52 as shown in FIG. FIG. 58 is a diagram showing an example of the size information of the constant voltage memory at the time of use, and the size information S1 of the constant voltage memory at the time of use is shown.

  Next, the in-use constant voltage memory allocation unit 525 reduces the size of the low-voltage part of each function that constitutes a function group having the function M_rest [m] as the representative function for the memory m from the array M_rest [m]. The value is updated (step S5704).

  Next, in-use constant voltage memory allocation unit 525 specifies a function group to be arranged in memory m allocated in steps S5702 to S5704 in steps S5705 to S5710.

  The in-use constant voltage memory allocation unit 525 first calculates a representative function set F = {f | Q (f_M, f)> 0} of the function group (step S5705). The set F is a set of functions that are called from functions belonging to a function group typified by the function f_M or that call a function belonging to a function group typified by the function f_M.

  In use, the constant voltage memory allocation unit 525 determines whether the set F is an empty set (step S5706). If the set F is not an empty set in step S5706, there is a function that is called from a function belonging to a function group represented by the function f_M or a function belonging to a function group represented by the function f_M.

  When the set F is not an empty set, the constant voltage memory allocation unit 525 in use selects a function group represented by the function f having the maximum call frequency Q (f_M, f) (step S5707). However, when there are a plurality of calls having the maximum calling frequency Q (f_M, f), the total size s (f) of the function group represented by the function f (the total size of the low voltage portions of each function) is the maximum. Choose one.

  Next, the in-use constant voltage memory allocation unit 525 determines whether or not the total size s (f) of the function group represented by the function f is equal to or smaller than the array M_rest [m] (step S5708). When the total size s (f) is equal to or smaller than the array M_rest [m] in step S5708, the in-use constant voltage memory allocation unit 525 stores the low voltage portion of each function of the function group represented by the function f. And the array M_rest [m] is updated to a value obtained by subtracting the total size s (f) from the array M_rest [m] (step S5709).

  Then, the constant voltage memory allocation unit 525 in use removes the function f from the set F regardless of whether or not the memory in which the low voltage part of the function group represented by the function f is determined is determined (step S5710). If the size total s (f) is not equal to or smaller than the array M_rest [m] in step S5708, the process proceeds to step S5710. In use, the constant voltage memory allocation unit 525 repeats the processing from step S5706 until the set F becomes an empty set.

  If the set F is an empty set in step S5706, there is a function that is called from a function belonging to a function group represented by the function f_M or a function belonging to a function group represented by the function f_M. do not do. Therefore, the in-use constant voltage memory allocation unit 525 determines whether there is an unallocated function group (step S5711). If there is an unassigned function in step S5711, the constant voltage memory allocating unit 525 during use returns to step S5702, and the assignment is continued from the function group having a large total code amount. If there is no unassigned function group in step S5711, the in-use constant voltage memory allocating unit 525 ends the processing because the memory allocation of all function groups has been completed.

  Hereinafter, the processing of the constant voltage memory allocation unit 525 in use will be described with a specific example.

  In use, the constant voltage memory allocation unit 525 first selects the function group F_A2 (total code amount 4 KB) having the maximum total code amount of the function group from the output table 54. The in-use constant voltage memory allocation unit 525 refers to the size information S1 to find the memory B (size 8 KB) that is the in-use constant voltage memory capable of arranging the function group F_A2, and allocates the function group F_A2 to the memory B. At this time, the remaining memory size of the memory B is 4 KB.

  Here, the function groups having the calling relationship with the function group F_A2 (the function group G satisfying the calling frequency Q (F_A2, G)> 0) are the function group F_A1 and the function group F_A3. Among these, the call frequency Q with the function group F_A2 is larger in the function group F_A1. Since the total code amount (2 KB) of the function group F_A1 is equal to or less than the remaining memory size (4 KB) of the memory B and can be allocated to the memory B, the constant voltage memory allocation unit 525 in use allocates the function group F_A1 to the memory B. .

  Since the function group F_A1 is assigned, the function group F_A3 is the only unassigned function group among the function groups having a calling relationship with the function group F_A2. Since the total code amount of the function group F_A3 is 2 KB, which is the same as the remaining memory size of the memory B, the function group F_A3 can be allocated to the memory B. Therefore, the in-use constant voltage memory allocation unit 525 allocates the function group F_A3 to the memory B. At this time, the remaining memory size of the memory B is 0 KB, and the only memory that can be allocated is the memory C.

  At this time, there is no unassigned function group among the function groups having a calling relationship with the function group F_A2. Accordingly, the constant voltage memory allocation unit 525 in use allocates the function group F_A5 (total code amount 3 KB) having the maximum total code amount to the memory C (memory size 8 KB) among the unassigned function groups F_A4 and F_A5. . At this time, the remaining memory size of the memory C is 5 KB.

  Of the function groups having a calling relationship with the function group F_A5, the unassigned function group is only the function group F_A4. The total code amount of the function group F_A4 is 2 KB and can be assigned to the memory C. Therefore, the in-use constant voltage memory allocation unit 525 allocates the function group F_A4 to the memory C.

  All the function groups are already assigned. FIG. 59 shows the result of assigning the function group to the constant voltage memory during use in this way. FIG. 59 is a diagram illustrating an example of a result of allocation of the constant voltage memory during use.

  In FIG. 59, the function group F_A1, the function group F_A2, and the function group F_A3 are allocated to the memory B that is a constant voltage memory when in use. The function group F_A4 and the function group F_A5 are assigned to the memory C which is a constant voltage memory when in use.

  In the present embodiment, as described above, since the memory map is determined based on the calling frequency between function groups having a calling relationship, it is possible to suppress the function from being arranged across a plurality of memories. . Therefore, in this embodiment, the number of insertions of the control code for setting the memory in the low voltage state can be reduced, and the power supply control of each memory can be performed efficiently. For this reason, in this embodiment, it can contribute to the reduction of the further power consumption.

  Moreover, this embodiment can contribute to further reduction of power consumption by combining with the fifth embodiment, the sixth embodiment, or the like.

In the embodiment of the present invention, the following configurations described below are conceivable.
(Appendix 1)
Insertion position calculating means for calculating an insertion position for inserting a control code for controlling the power supply voltage so that the area can be switched in a state where the power supply voltage is stable in a program code written in a memory having a plurality of areas;
Memory map generating means for creating a memory map based on the structure information of the memory and the insertion position;
A code generation unit configured to generate a program code by inserting the control code into the insertion position;
(Appendix 2)
The insertion position calculating means includes
The code generation device according to appendix 1, wherein the insertion position is calculated by using a time for which a predetermined number of cycles are executed as one instruction code as a time required for fluctuation of the power supply voltage.
(Appendix 3)
The code generation device according to appendix 1 or 2, further comprising link means for linking the program code and outputting a binary including a control code for controlling the power supply voltage.
(Appendix 4)
The code generation device according to any one of appendices 1 to 3, further comprising a dividing unit that divides the program code at the insertion position calculated by the insertion position calculating unit.
(Appendix 5)
The dividing means includes
The program code from the start address of the program code to the insertion position is the first half, and the program code after the insertion position is divided as the second half,
The code generation means includes
The first half portion is always arranged in a region to which a power supply voltage is supplied,
The code generation device according to appendix 4, wherein the second half portion generates a program code so as to be arranged in a region where a power supply voltage is supplied during use.
(Appendix 6)
Code insertion means for inserting the control code into the program code;
The code insertion means includes
The code generation device according to appendix 5, wherein a control code for supplying a power supply voltage to an area where the latter half portion is arranged at the head of the first half portion is inserted.
(Appendix 7)
The code insertion means includes
The code generation device according to appendix 5 or 6, wherein a control code for jumping to a region where the latter half portion is arranged is inserted at the end of the first half portion.
(Appendix 8)
The program code includes an interrupt handler,
The code insertion means includes
Generate a call relationship diagram for the program code, duplicate the function node that can be reached from both the main function and the interrupt handler,
The code generation device according to any one of appendices 1 to 7 associated with the node copied from the interrupt handler.
(Appendix 9)
The code generation device according to any one of appendices 1 to 8, further comprising code size correction means for correcting the code size of the program code to a code size after the control code is inserted based on the code size of the control code. .
(Appendix 10)
The code generation means includes
When the area to which the power supply voltage is supplied once in use is not used again before returning to the main function from the function arranged in the lower layer according to the function calling relationship,
Supplementary note for inserting a control code for setting a voltage in a region to which a power supply voltage is supplied during use to a voltage lower than the power supply voltage in a function code for calling a function arranged in the region to which a power supply voltage is supplied during use The code generation device according to any one of 1 to 9.
(Appendix 11)
The code generation means includes
Code acquisition means for acquiring assembly code for each function;
An arrangement determining means for determining whether the code of the function acquired by the code acquiring means is arranged in a region where a power supply voltage is supplied during use and the region where the power supply voltage is always supplied;
In response to the determination of the arrangement determination means, a sleep release code insertion means for inserting a control code for supplying a power supply voltage to an area where the latter half portion is arranged at the head of the first half portion,
The area where the instruction of the function is a function call instruction and the function called by the function call instruction is arranged is the same area as the area where the function call instruction is arranged or the area where the power supply voltage is always supplied If not, sleep code insertion means for inserting a control code for setting a voltage in a region to which a power supply voltage is supplied at the time of use immediately after the function call command to a voltage lower than the power supply voltage. The code generation device according to claim 1.
(Appendix 12)
The code generation means includes
Code acquisition means for acquiring assembly code for each function;
A first set which is a set of all constant voltage memories in use used from the main function to the function, and a second set which is a set of constant voltage memories in use used by a callee function called by the function Sleep code insertable table creating means for creating a table in which information indicating whether or not a common part exists in a set is stored for each call destination function called by the function;
An arrangement determining means for determining whether the code of the function acquired by the code acquiring means is arranged in a region where a power supply voltage is supplied during use and the region where the power supply voltage is always supplied;
In response to the determination of the arrangement determination means, a sleep release code insertion means for inserting a control code for supplying a power supply voltage to an area where the latter half portion is arranged at the head of the first half portion,
When the instruction of the function is a function call instruction and the common part does not exist between the first set and the second set in the table, a power supply voltage at the time of use immediately after the function call instruction 11. The code generation device according to claim 1, further comprising: a sleep code insertion unit that inserts a control code that sets a voltage in a region to which the voltage is supplied to be lower than a power supply voltage.
(Appendix 13)
The memory map creating means includes
A parent function determining means for specifying one parent function according to the call frequency information;
A constant voltage memory allocation means for performing constant function allocation to a constant voltage memory;
A code amount calculation means for calculating a total code amount of the constant voltage memory when using the function group assigned to the constant voltage memory when using;
A call frequency calculation means for creating a table that calculates a call frequency between function groups assigned to the constant voltage memory in use;
Based on the total amount of code calculated by the code amount calculation means and the table created by the call frequency calculation means, a constant voltage memory allocation unit for use that allocates to a constant voltage memory for usage for each function group;
Allocation adjustment / address calculation means for referring to the result of the constant voltage memory allocation means in use, correcting the allocation by the constant voltage memory allocation means at all times, and calculating the start address of the constant voltage portion and the low voltage portion of each function; The code generation device according to any one of appendices 1 to 12, which includes:
(Appendix 14)
An insertion position calculation procedure for calculating an insertion position for inserting a control code for controlling the power supply voltage so that the area can be switched in a state where the power supply voltage is stable in a program code written in a memory having a plurality of areas;
A memory map generation procedure for creating a memory map based on the structure information of the memory and the insertion position;
A code generation method for executing a code generation procedure for generating a program code by inserting the control code into the insertion position.
(Appendix 15)
A code generation program that is executed in a code generation device that generates a program code to be mounted on a semiconductor integrated circuit,
In the code generator,
An insertion position calculating step for calculating an insertion position for inserting a control code for controlling the power supply voltage so that the area can be switched in a state where the power supply voltage is stable in a program code written in a memory having a plurality of areas;
A memory map generating step of creating a memory map based on the structure information of the memory and the insertion position;
A code generation step of executing a code generation step of generating the program code by inserting the control code into the insertion position.

  The embodiments of the present invention are not limited to the specifically disclosed examples, and various modifications and changes can be made without departing from the scope of the claims.

50 Assembly 52 Function Size Information 55 Assembly Code 60 Parameter 62 Structure Information 63 Control Code Pattern 64 Power Control Code Pattern 70 Power Control Binary 100, 100A, 100B, 100C, 100D Code Generator

Claims (9)

Insertion position calculating means for calculating an insertion position for inserting a control code for controlling the power supply voltage so that the area can be switched in a state where the power supply voltage is stable in a program code written in a memory having a plurality of areas;
Memory map generating means for creating a memory map based on the structure information of the memory and the insertion position;
A code generation unit configured to generate a program code by inserting the control code into the insertion position; The insertion position calculating means includes
2. The code generation device according to claim 1, wherein the insertion position is calculated by taking a time for which a predetermined number of cycles are executed as one instruction code as a time required for fluctuation of the power supply voltage.   3. The code generation apparatus according to claim 1, further comprising a linking unit that links the program code and outputs a binary including a control code for controlling the power supply voltage.   The code generation apparatus according to claim 1, further comprising a dividing unit that divides the program code at the insertion position calculated by the insertion position calculating unit. The code generation means includes
When the area to which the power supply voltage is supplied once in use is not used again before returning to the main function from the function arranged in the lower layer according to the function calling relationship,
A control code for inserting a voltage in a region to which a power supply voltage is supplied during use into a code lower than the power supply voltage is inserted into a function code for calling a function arranged in the region to which the power supply voltage is supplied during use. Item 5. The code generation device according to any one of Items 1 to 4. The code generation means includes
Code acquisition means for acquiring assembly code for each function;
An arrangement determining means for determining whether the code of the function acquired by the code acquiring means is arranged in a region where a power supply voltage is supplied during use and the region where the power supply voltage is always supplied;
In response to the determination of the arrangement determination means, a sleep release code insertion means for inserting a control code for supplying a power supply voltage to an area where the latter half portion is arranged at the head of the first half portion,
The area where the instruction of the function is a function call instruction and the function called by the function call instruction is arranged is the same area as the area where the function call instruction is arranged or the area where the power supply voltage is always supplied If not, sleep code insertion means for inserting a control code for setting a voltage in a region where a power supply voltage is supplied during use immediately after the function call instruction to a voltage lower than the power supply voltage is provided. The code generation device according to any one of the above. The code generation means includes
Code acquisition means for acquiring assembly code for each function;
A first set which is a set of all constant voltage memories in use used from the main function to the function, and a second set which is a set of constant voltage memories in use used by a callee function called by the function Sleep code insertable table creating means for creating a table in which information indicating whether or not a common part exists in a set is stored for each call destination function called by the function;
An arrangement determining means for determining whether the code of the function acquired by the code acquiring means is arranged in a region where a power supply voltage is supplied during use and the region where the power supply voltage is always supplied;
In response to the determination of the arrangement determination means, a sleep release code insertion means for inserting a control code for supplying a power supply voltage to an area where the latter half portion is arranged at the head of the first half portion,
When the instruction of the function is a function call instruction and the common part does not exist between the first set and the second set in the table, a power supply voltage at the time of use immediately after the function call instruction 6. The code generation device according to claim 1, further comprising: a sleep code insertion unit that inserts a control code that sets a voltage in a region to which the voltage is supplied to be lower than a power supply voltage. The memory map creating means includes
A parent function determining means for specifying one parent function according to the call frequency information;
A constant voltage memory allocation means for performing constant function allocation to a constant voltage memory;
A code amount calculation means for calculating a total code amount of the constant voltage memory when using the function group assigned to the constant voltage memory when using;
A call frequency calculation means for creating a table that calculates a call frequency between function groups assigned to the constant voltage memory in use;
Based on the total amount of code calculated by the code amount calculation means and the table created by the call frequency calculation means, a constant voltage memory allocating unit in use for allocating to a constant voltage memory in use for each function group;
Allocation adjustment / address calculation means for referring to the result of the constant voltage memory allocation means in use, correcting the allocation by the constant voltage memory allocation means at all times, and calculating the start address of the constant voltage portion and the low voltage portion of each function; The code generation device according to claim 1, comprising: An insertion position calculation procedure for calculating an insertion position for inserting a control code for controlling the power supply voltage so that the area can be switched in a state where the power supply voltage is stable in a program code written in a memory having a plurality of areas;
A memory map generation procedure for creating a memory map based on the structure information of the memory and the insertion position;
A code generation method for executing a code generation procedure for generating a program code by inserting the control code into the insertion position.

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