JP2011134077A - Clock transmission/reception circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock transmission/reception circuit which suppresses crosstalk from clock wiring. <P>SOLUTION: The clock transmission/reception circuit which transmits a clock and receives the clock which is thus transmitted includes: a pseudo random number bit string generation unit which inputs the input clock and generates a first clock based on a pseudo random number bit string; a transmission unit which has a transmission side exclusive logical computing unit which inputs the first clock and the input clock, performs exclusive logical operation, and generates a second clock; first and second clock wiring which propagate the first and second clocks generated by the transmission unit; and a receiving unit which has a receiving side exclusive logical computing unit which inputs the first and second clocks which have been propagated the first and second clock wiring, performs exclusive logical operation, and generates the output clock. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a clock transmission / reception circuit.

  An integrated circuit (LSI) chip or a motherboard on which the chip is mounted may have a clock wiring in the vicinity of the signal wiring. At this time, crosstalk noise caused by the clock is generated in the signal wiring due to parasitic capacitance and parasitic inductance generated between the clock wiring and the signal wiring.

  When an analog signal propagates through the signal wiring, the SN ratio of the analog signal deteriorates due to such crosstalk noise. In particular, if the frequency band of the analog signal and the frequency band of the crosstalk noise overlap, it is difficult to remove the crosstalk noise by a filter or the like, so that crosstalk becomes a serious problem.

  As a method for suppressing such crosstalk noise, for example, (1) the clock wiring is separated from the signal wiring by a certain distance, (2) the clock wiring or signal wiring is shielded, and (3) the differential clock is crossed. It is generally used to cancel the talk, (4) shift the frequency band of the clock from the signal frequency band, (5) stop the clock as much as possible.

  Further, (6) there is a method of suppressing peak power by intentionally adding jitter to a clock generated by a clock source and spreading its frequency spectrum.

JP 2002-111636 A Japanese National Patent Publication No. 2-501432

  However, the above (4) and (5) may not be adopted, and the above (3) cannot obtain a sufficient effect depending on the position of the clock wiring with respect to the signal wiring. Therefore, there are many suppression means only by adopting the above (1) and (2) based on the experience of the designer. Further, the method of intentionally adding jitter to the clock in (6) is inappropriate for a communication circuit that does not allow jitter.

  Accordingly, an object of the present invention is to provide a clock transmission / reception circuit capable of suppressing crosstalk from the clock wiring.

  According to a first aspect, in a clock transmission / reception circuit that transmits a clock and receives the transmitted clock, a pseudo random number bit string generation unit that inputs an input clock and generates a first clock based on the pseudo random number bit string; A transmission unit having a transmission-side exclusive logic unit that inputs a first clock and an input clock and performs an exclusive logical operation to generate a second clock; and the first and second generated by the transmission unit A first and second clock wiring that propagates the clock and the first and second clocks that have propagated through the first and second clock wirings are input and an exclusive logical operation is performed to generate an output clock. And a receiving unit having a side exclusive logic unit.

  According to the first aspect, since the first and second clocks propagating through the clock wiring are pseudo-random clocks, the frequency spectrum is spread and the peak voltage is reduced.

This is an electronic circuit to which the present embodiment is applied. It is a figure which shows the clock transmission / reception circuit in this Embodiment, and its operation waveform. It is a figure which shows an example of the clock wiring and signal wiring in an LSI chip. It is a figure explaining the crosstalk noise by two clocks. It is a figure which shows the structural example of the electronic circuit in this Embodiment. It is a circuit diagram of the clock transmission / reception circuit in this Embodiment. It is a figure which shows an example of the signal waveform in the clock transmission / reception circuit of FIG. It is a circuit diagram of another clock transmission / reception circuit in this Embodiment. It is a circuit diagram of an M series generator. It is a circuit diagram of a Gold series generator. It is a circuit diagram of a delta-sigma modulator. It is a figure which shows a simulation model. 6 is a diagram illustrating a frequency spectrum of crosstalk that occurs when a transmission unit 10 outputs a differential clock to two clock wirings 21 and 22. FIG. It is a figure which shows the frequency spectrum of the crosstalk in the example in which the exclusive logic unit 12 of the transmission unit 10 shown in FIG. 6 is an ENOR gate. It is a figure which shows the frequency spectrum of the crosstalk in the example in which the exclusive logic unit 12 of the transmission unit 10 shown in FIG. 8 is an ENOR gate.

  FIG. 1 shows an electronic circuit to which this embodiment is applied. This electronic circuit is provided with circuit blocks 41 and 42, and the circuit block 41 supplies an analog signal to the circuit block 42 via an analog signal wiring 44. Further, the clock CLK generated by the clock source 14 is supplied to the circuit blocks 41 and 42 via the clock wiring 20.

  The clock CLK is a signal that repeats the H level and the L level at a predetermined frequency, and generates crosstalk noise NZ in the adjacent signal wiring 44 at its rising edge and falling edge.

  Since the frequency spectrum of the clock CLK has a voltage peak at a higher order frequency such as the third order and the fifth order in addition to the primary frequency, the crosstalk noise NZ similarly has a voltage peak at a higher order frequency band. If the crosstalk noise frequency band overlaps with the analog signal frequency band, it is difficult to remove the crosstalk noise component superimposed on the analog signal by the filter circuit.

  FIG. 2 is a diagram showing a clock transmission / reception circuit and its operation waveform in the present embodiment. The clock transmitting / receiving circuit receives the input clock CLKin generated by the clock source 14 and receives the first random number bit string generator 11 that generates the first clock SA based on the pseudo random number bit string, the first clock SA, and the input clock CLKin. The transmission unit 10 includes a transmission-side exclusive logical operation unit 12 that performs these exclusive logical operations and generates the second clock SB.

  Further, the clock transmission / reception circuit has first and second clock lines 20 for propagating the first and second clocks SA and SB, respectively. The first and second clock wirings 20 are configured, for example, with the same line width, film thickness, and length, and are configured so that the clock propagation times are equal. The clock transmission / reception circuit further receives the first and second clocks SA and SB propagated through the first and second clock wirings 20, performs an exclusive logical operation thereof, and generates an output clock CLKout. A receiving unit 30 including a side exclusive logic unit 31.

  In this example, the exclusive logic units 12 and 31 are EOR (Exclusive OR) gates, which output an H level when the H and L levels of both input clocks are different, and an L level when they are the same.

  As shown in the operation waveform in FIG. 2, the pseudo random number bit string generator 11 generates a pseudo random first clock SA based on an input clock CLKin generated by a clock source 14 such as a crystal oscillator or a PLL synthesizer. . Then, the EOR gate 12 inverts the first clock SA according to the input clock CLKin to generate the second clock SB. Therefore, the second clock SB is also a pseudo-random clock.

  The first and second clocks SA and SB are propagated through the first and second clock wirings 20 and input to the receiving unit 30 in the circuit unit that receives the clock. The reception-side exclusive logic unit 13 in the reception unit 30 inputs the first and second clocks SA and SB propagated through the first and second clock wirings 20 and outputs their EOR signals to the output clock CLKout. Play and output as. The EOR gate 31 inverts the first clock SA according to the second clock SB, and as a result, the output clock CLKout becomes the same as the input clock CLKin generated by the clock source 14.

  In an LSI chip constituting an electronic circuit, there may be a large number of analog signal wirings in the vicinity of the clock wiring 20. Therefore, crosstalk noise in the signal wiring existing in the vicinity of the first and second clock wirings 20 in FIG. 2 will be described.

  FIG. 3 is a diagram showing an example of the clock wiring and signal wiring in the LSI chip, and shows a cross section of the integrated circuit multilayer wiring. The clocks SA and SB are propagated to the two clock wirings 20. Further, it is assumed that signal wirings 44A, 44B, 44C and the like exist around the clock wiring 20. An insulating film and a wiring layer (not shown) are formed between these wirings.

  The crosstalk noise on the signal wiring 44 caused by the clocks SA and SB propagating through the two clock wirings 20 differs depending on the position of the signal wiring 44. For example, in the signal wiring 44A, the influence of crosstalk from the clock wiring 20 that propagates the first clock SA is larger than that in the second clock SB, and in the signal wiring 44C, the clock wiring 20 that propagates the second clock SB. The influence of crosstalk from is larger than that of the first clock SA. Further, since the signal wiring 44 </ b> B is located at approximately the same distance from the two clock wirings 20, it is equally affected by the crosstalk from both clock wirings 20.

  Therefore, the crosstalk noise of the first clock SA is mainly generated in the signal wiring 44A. If the first clock SA is pseudorandom, the crosstalk noise is also pseudorandom. As a result, in the frequency spectrum of the crosstalk noise, power peaks in high-order frequency bands such as the first order, the third order, and the fifth order are suppressed. Similarly, the crosstalk noise of the second clock SB is mainly generated in the signal wiring 44C, and the power peak in the higher frequency band of the crosstalk noise is also suppressed.

  Furthermore, since the crosstalk noise of the first and second clocks SA and SB is equally generated in the signal wiring 44B, the crosstalk noise of the signal wiring 44B is also pseudo-random. Thereby, the power peak in the higher frequency band of the crosstalk noise is also suppressed.

  FIG. 4 is a diagram for explaining crosstalk noise caused by two clocks. FIG. 4 shows the same two clocks SA and SB as in FIG. In the signal wiring 44B, crosstalk noise is generated from these two clocks SA and SB. Since the crosstalk noise voltage in the signal wiring 44 is a linear sum of the crosstalk noise voltages generated from SA and SB, it can be considered to be equal to the crosstalk generated from the sum SA + SB of the clocks SA and SB.

  The clock SB is a clock obtained by inverting the clock SA according to the input clock CLKin as described above. The clock SB is a kind of NRZ (Non-Return to Zero) signal that has only an H level or an L level and does not become an intermediate level (zero level).

  On the other hand, the signal SA + SB changes from the intermediate level (zero level) to H or L when the clock SB changes from L to H or from H to L. Return to level. A signal obtained by correcting the signal SA + SB with a broken line in the figure is a kind of RZ (Return to Zero) signal. Therefore, it can be understood that the signal SA + SB is very similar to the RZ signal of the signal SB.

  In general, if a certain signal is random, the RZ signal of the signal is also random. Therefore, it can be said that the signal SA + SB is also random. As a result, the frequency spectrum of the signal SA + SB becomes very similar to the RZ signal of the clock SB, the frequency is spread and the power peak is suppressed.

  FIG. 4 shows the signal SA + 0.5SB. That is, in FIG. 3, when the signal wiring 44B is arranged at a position closer to the clock wiring that propagates the clock SA, the influence from the clock SA becomes larger than the influence from the clock SB. This signal SA + 0.5SB is only less affected by the clock SB, and the intermediate level (zero level) is only shifted from the intermediate level (zero level) of the signal SA + SB. Therefore, the randomness of the signal SA + 0.5SB is also maintained.

  As described above, according to the clock transmission / reception circuit of FIG. 2, since at least two pseudo-random clocks SA and SB propagate through the clock wirings 21 and 22, the power of a specific frequency in the frequency spectrum of the crosstalk generated thereby. The peak value can be reduced. Moreover, the crosstalk in the signal wiring affected by both of the two pseudo-random clocks SA and SB can similarly reduce the power peak value of the specific frequency in the frequency spectrum, so that the specific frequency does not depend on the position of the signal wiring. The power peak value can be reduced.

  On the other hand, when a differential clock is simply propagated, depending on the position of the signal wiring, the crosstalk from one clock may become too strong, and a power peak at a specific frequency may be generated in the crosstalk. is there. Compared with the case where the spectrum is spread by modulating the clock itself, the clock transmission / reception circuit of the present embodiment can regenerate the non-modulated clock by the receiving unit, and can be used as the clock of the communication circuit. Furthermore, according to the present embodiment, since the power supply noise caused by the operation of the buffer provided in the clock wiring is caused by the pseudo random clock, the frequency spectrum is spread.

  FIG. 5 is a diagram illustrating a configuration example of the electronic circuit in the present embodiment. The electronic circuit of FIG. 5 has three circuit units 41, 42, and 43 to which a clock CLK is supplied. A signal wiring 44 through which an analog signal propagates is provided from the circuit unit 41 to the circuit units 42 and 43. In order to supply the clock, the clock transmission / reception circuit of the present embodiment described with reference to FIG. 2 is provided.

  The clock transmission / reception circuit includes a transmission unit 10, a clock wiring 20, and reception units 31, 32, and 33. The transmission unit 10 generates two pseudo random clocks CLK (SA, SB) from the input clock CLKin generated by the clock source 14 and outputs them to the two clock lines 20. The output pseudo random clock CLK propagates to the receiving unit 31 in the circuit units 41 and 42 and propagates to the receiving unit 33 in the circuit unit 43 via the clock buffer 46. The clock buffer 46 is provided to shape the clock waveform when the clock wiring 20 is long. Then, the receiving units 31, 32, 33 regenerate the original clock CLKin from the two pseudo random clocks CLK (SA, SB) that have propagated.

  FIG. 6 is a circuit diagram of the clock transmission / reception circuit in this embodiment. FIG. 6A is the same as the clock transmission / reception circuit shown in FIG. 2, and FIG.

  The clock transmission / reception circuit in FIG. 6A is as described with reference to FIG. 2. In the transmission unit 10, the pseudo random number bit string generator 11, the transmission side exclusive logical operator 12, Thus, pseudo random clocks SA and SB are generated. In the reception unit 30, the original clock CLKout is regenerated from the clocks SA and SB propagated through the clock wirings 21 and 22 by the reception side exclusive logic unit 31 and output from the output terminal 02.

  In the clock transmission / reception circuit which is a modified example of FIG. 6B, the transmission unit 10 divides the frequency of the input clock CLKin by 1/2 in addition to the pseudo random number bit string generator 11 and the transmission side exclusive logical operator 12. It has a frequency divider 14 and flip-flops or latch circuits 15 and 16 for latching the clocks SA and SB at the rising edge of the input clock CLKin. The latch circuits 15 and 16 are a kind of timing adjustment unit, and are adjusted so that the timings of fluctuations in the H and L levels of the pseudo random clocks SA and SB coincide with each other. Then, both clocks SA and SB propagated through the clock wirings 21 and 22 provided in parallel are input to the reception side exclusive logical arithmetic unit 31 of the reception unit 30 in a timing-aligned state. As a result, the original clock CLKout is accurately reproduced by the receiving unit.

  6A and 6B, the exclusive logic units 12 and 31 in the transmission unit and the reception unit are EOR circuits.

  FIG. 7 is a diagram illustrating an example of signal waveforms in the clock transmission / reception circuit of FIG. In the transmission unit 10, the first pseudo random clock SA (51) is generated from the input clock CLKin (50), and the second pseudo random clock SB ( 52) is generated. In the receiving unit 30, the EOR of these clocks SA and SB is calculated to reproduce the original clock CLKout (57).

  When the crosstalk caused by the clocks SA and SB in the signal wirings arranged in the vicinity of the clock wirings 21 and 22 is affected by both the clocks SA and SB, the crosstalk 53 shown in FIG. In addition, a linear sum of crosstalk generated from the clocks SA and SB is obtained. That is, the crosstalk 53 is the same as the crosstalk 56 generated from the signal SA + SB (55 in the figure) obtained by adding the clocks SA and SB. In the example of FIG. 7, the influence of the clock SA is slightly larger than that of the clock SB.

  This signal SA + SB (55) has the same H and L level transition timing as the signal 54 obtained by converting the clock SB into an RZ (Return-to-Zero) signal. Therefore, the signal SA + SB (55) is a random clock like the clock SB, and the frequency band of the frequency spectrum is spread. Accordingly, the crosstalk 56 by the signal SA + SB (55) and the crosstalk 53 equal thereto are spread in the frequency band of the frequency spectrum, and the power peak value at a specific frequency is reduced.

  FIG. 8 is a circuit diagram of another clock transmission / reception circuit in the present embodiment. In this example, the exclusive logic units 13 and 32 in the transmission unit and the reception unit are ENOR circuits, and the exclusive logic unit 32 in the reception unit inverts and inputs the clock SB. Other configurations are the same as those in FIG. 8B differs from FIG. 8A in that the transmission unit 10 includes a frequency divider 14 and latch circuits or flip-flops 15 and 16 for timing matching.

  By adopting the ENOR circuit as the exclusive logic operation units 13 and 32, the second pseudo random clock SB is merely inverted in logic from the clock SB of FIG. Therefore, the randomness of the clock is the same, and therefore the crosstalk by the first and second pseudo-random clocks SA and SB is also random, the frequency spectrum is spread, and the peak value of the specific frequency is reduced.

  6 and 8 can be realized by any one of an M-sequence (Maximal-length sequence) generator, a Gold sequence generator, and a delta-sigma modulator, for example. Any generator is known to those skilled in the art, but an example of them is given below.

FIG. 9 is a circuit diagram of the M-sequence generator. The M-sequence generator is an exclusive OR of the K (K = 7) D flip-flops 51 to 57 in which the data output Q and the data input D are connected to each other, and the data outputs Q of the D flip-flops 55 and 57. And an EOR gate 58 taking (EOR). The output of the K-th stage D flip-flop 57 and the output of the L-th stage (K> L) D flip-flop 55 are input to the EOR gate 58. The input clock CLKin is supplied to the clock terminal of the D flip-flop, the output of the EOR gate 58 is connected to the data input D of the first stage D flip-flop 51, and the EOR gate 58 outputs the pseudo random clock SA. In the D flip-flops 51 to 57, at the time of reset, at least one D flip-flop is reset to the data output Q = 1, the data output Q is propagated in synchronization with the clock CLKin, and the pseudo-random clock SA is generated from the EOR gate 58. Generated. The pseudo random clock SA is a random bit string clock having a cycle of a bit string of L = 2 ⁷ −1 bits.

  FIG. 10 is a circuit diagram of the Gold series generator. This Gold sequence generator is the same as the M sequence generator of FIG. A generator and an adder 69 for adding the M sequences M1 and M2 generated by the generator and the adder 69 output a pseudo random clock SA. The two M series generators are different from the D flip-flops 55 and 64 in one input of the EOR gates 58 and 68.

  FIG. 11 is a circuit diagram of a first-order delta-sigma modulator. This delta-sigma modulator has an adder / subtractor 70, an integrating circuit 72, a quantizing circuit 74 composed of a comparator, and a delay circuit 76. These circuits operate in synchronization with the input clock CLKin. The quantization circuit 74 compares the input value with the reference value and outputs a 1-level or 0-level pseudo-random clock SB depending on the magnitude relationship. The output is fed back to the input side via the delay circuit 76 and subtracted from the input signal CONT. Then, a 1-level or 0-level pseudo-random signal SB having a ratio corresponding to the value of the control signal CONT is generated.

[simulation]
The frequency spectrum of crosstalk when the clock transmitting / receiving circuit of this embodiment is simulated will be described below.

  FIG. 12 is a diagram illustrating a simulation model. The simulation model, which is a clock transmission / reception circuit of the present embodiment, includes a transmission unit 10, two clock wirings 21, 22, a reception unit 30, a signal line 44 that receives crosstalk from the clock wirings 21, 22, and a signal. And a terminating resistor R for the line 44. The capacitors C1 and C2 are provided between the clock wirings 21 and 22 and the signal line 44.

  In the simulation, the capacitors C1 and C2 were changed from 0 to 10 fF, and the frequency spectrum of crosstalk generated in the signal line 44 with each capacitor was obtained. The amplitude of the clock output from the transmission unit 10 is 1.2 Vpp, the rise time and fall time are 1 ns, the frequency of the input clock is 50 MHz, the wiring 44 is lossless, and the resistance R is 100 kΩ.

  FIG. 13 is a diagram showing a frequency spectrum of crosstalk that occurs when the transmission unit 10 outputs a differential clock to the two clock wirings 21 and 22. This frequency spectrum is the worst case in which the maximum crosstalk voltage is generated when the capacitors C1 and C2 are changed from 0 to 10 fF. The horizontal axis is frequency and the vertical axis is voltage value. In the example of FIG. 13, the differential clock has a high voltage peak value at each of the primary frequency 50 MHz, the third frequency 150 MHz, the fifth frequency 250 MHz, and the seventh frequency 350 MHz. Therefore, when these frequencies overlap with the frequency band of the signal on the signal line 44, it is difficult to remove crosstalk noise generated on the signal line 44.

  FIG. 14 is a diagram showing a frequency spectrum of crosstalk in an example in which the exclusive logic unit 12 of the transmission unit 10 shown in FIG. 6 is an EOR gate. This example is also the worst case in which the maximum crosstalk voltage is generated when the capacitors C1 and C2 are changed in the same manner as described above. At the primary frequency of 50 MHz, the maximum peak voltage is 18.1 mV, which is about 20 dB lower than that of FIG. At other third, fifth, and seventh frequencies, the peak voltage is lower than that in FIG. 13 due to the spread spectrum.

  FIG. 15 is a diagram showing a frequency spectrum of crosstalk in an example in which the exclusive logic unit 12 of the transmission unit 10 shown in FIG. 8 is an ENOR gate. This example is also the worst case in which the maximum crosstalk voltage is generated when the capacitors C1 and C2 are changed in the same manner as described above. At the primary frequency of 50 MHz, the maximum peak voltage is 18.1 mV, which is about 20 dB lower than that of FIG. At other third, fifth, and seventh frequencies, the peak voltage is lower than that in FIG. 13 due to the spread spectrum. From this result, even when the ENOR gate is used, the crosstalk is spread spectrum and the maximum peak value at each frequency is reduced.

  As described above, according to the clock transmission / reception circuit of the present embodiment, the spread spectrum pseudo-random clock can be propagated without modulating the clock phase and frequency of the clock source, and the maximum peak of crosstalk can be transmitted. The voltage can be reduced, and the receiving unit can regenerate the original clock. In addition, the maximum peak voltage of crosstalk can be reduced as compared with the case where a differential clock is propagated. In addition, both the transmission unit and the reception unit can be realized with a small area by merely providing a pseudo random number bit string generator and an exclusive logic gate.

  The clock transmission / reception circuit of the present embodiment can be used as, for example, a clock supply circuit in an LSI chip. Even if a clock wiring is provided in a multilayer wiring structure in an LSI, crosstalk of signal wiring in the vicinity thereof is provided. The peak voltage can be reduced. Furthermore, the clock transmission / reception circuit can be used for a mother board between LSI chips. In that case, the crosstalk peak voltage of the signal wiring near the clock wiring in the mother board can be reduced. Further, the crosstalk peak voltage of the signal wiring can be reduced even when the clock wiring and the signal wiring are provided in the same coaxial cable.

  The above embodiment is summarized as follows.

(Appendix 1)
In a clock transmission / reception circuit that transmits a clock and receives the transmitted clock,
A pseudo random number bit string generation unit that inputs an input clock and generates a first clock based on a pseudo random number bit string, and a transmission that inputs the first clock and the input clock and performs an exclusive logical operation to generate a second clock A transmission unit having a side exclusive logic unit;
First and second clock lines for propagating the first and second clocks generated by the transmission unit;
A clock having a receiving unit having a receiving side exclusive logical operation unit that inputs the first and second clocks propagated through the first and second clock wirings, performs an exclusive logical operation, and generates an output clock. Transmission / reception circuit.

(Appendix 2)
In Appendix 1,
The transmission unit further synchronizes the first clock output from the pseudo random number bit string generation unit and the second clock output from the transmission side exclusive logic unit in synchronization with the input clock. 1. A clock transmission / reception circuit having first and second timing adjustment units that output to a first clock wiring.

(Appendix 3)
In Appendix 1 or 2,
The clock transmission / reception circuit in which the exclusive logical operation of the transmission side and reception side exclusive logical operation units is an EOR operation.

(Appendix 4)
In Appendix 1 or 2,
The exclusive logical operation of the transmitting side and the receiving side exclusive logical operator is an ENOR operation,
A clock transmitting / receiving circuit for inverting and inputting the second clock;

(Appendix 5)
In Appendix 1 or 2,
The clock transmission / reception circuit configured such that the first and second clock wirings have the same propagation time of each clock.

(Appendix 6)
In Appendix 1 or 2,
The pseudo-random bit string generation unit is a clock transmission / reception circuit that is one of an M-sequence generator, a Gold-sequence generator, and a delta-sigma modulator.

(Appendix 7)
In Appendix 6,
The M-sequence generator generates an exclusive OR between a K-stage flip-flop connected in series and a K-stage output and an L-stage output of the K-stage flip-flop. A clock transmission / reception circuit, wherein L is smaller than K, and the gate outputs the first clock.

(Appendix 8)
In Appendix 6,
The Gold sequence generator includes first and second M sequence generators having different configurations, and an adder for adding the outputs of the first and second M sequence generators to output the first clock; A clock transmission / reception circuit.

(Appendix 9)
In Appendix 6,
The delta-sigma modulator compares an adder for adding an input signal and a feedback quantization error, an integration circuit for integrating the output of the adder, and an output of the integration circuit with a predetermined reference value. A clock transmission / reception circuit having a quantization circuit for generating a quantization output and a delay circuit for delaying a quantization error of the quantization circuit and feeding back to the adder, and operating in synchronization with the input clock.

10: Transmitting unit 11: Pseudo random number bit string generation circuit 12: Exclusive logical operation unit SA, SB: First and second clocks 20: Clock wiring 30: Reception unit 31: Exclusive logical operation unit

Claims (5)

In a clock transmission / reception circuit that transmits a clock and receives the transmitted clock,
A pseudo random number bit string generating unit that inputs an input clock and generates a first clock based on a pseudo random number bit string, and a transmission that inputs the first clock and the input clock and performs an exclusive logical operation to generate a second clock A transmission unit having a side exclusive logic unit;
First and second clock lines for propagating the first and second clocks generated by the transmission unit;
A clock having a receiving side unit having a receiving side exclusive logical operation unit that inputs the first and second clocks propagated through the first and second clock lines and performs an exclusive logical operation to generate an output clock. Transmission / reception circuit. In claim 1,
The transmission unit further synchronizes the first clock output from the pseudo random number bit string generation unit and the second clock output from the transmission side exclusive logic unit in synchronization with the input clock. 1. A clock transmission / reception circuit having first and second timing adjustment units that output to a first clock wiring. In claim 1 or 2,
The clock transmission / reception circuit in which the exclusive logical operation of the transmission side and reception side exclusive logical operation units is an EOR operation. In claim 1 or 2,
The exclusive logical operation of the transmitting side and the receiving side exclusive logical operator is an ENOR operation,
A clock transmitting / receiving circuit for inverting and inputting the second clock; In claim 1 or 2,
The clock transmission / reception circuit configured such that the first and second clock wirings have the same propagation time of each clock.

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