JP2011130168A - Voltage controlled oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the increase in circuit scale of a voltage controlled oscillation circuit. <P>SOLUTION: The voltage controlled oscillation circuit includes an oscillation amplifier part 32 for amplifying an oscillation signal, an LC resonance part 33 for controlling the oscillation frequency of the oscillation signal, and a negative resistance part 34 having a negative resistive component. The LC resonance part 33 includes gm cells 25 and 26 connected in a loop and capacities 28 to 31 having one ends connected to nodes on the loop. The oscillation frequency is controlled on the basis of: an inductance value based on the gm cells 25 and 26 and the capacities 28 and 29; and capacity values of the capacities 30 and 31. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a voltage controlled oscillation circuit, and more particularly to an LC resonance type voltage controlled oscillation circuit.

  There are various types of voltage controlled oscillators (VCOs) used in semiconductor integrated circuits, such as emitter-coupled multivibrators, ring oscillators, and LC oscillation types.

  Emitter-coupled multivibrators and ring oscillators are advantageous in that they can be easily integrated and can increase the rate of change of the oscillation frequency, but have a larger jitter (phase noise) than the LC oscillation type. There are drawbacks. On the other hand, the LC oscillation type has an advantage that jitter (phase noise) is small as compared with the emitter-coupled multivibrator and the ring oscillator, but has a disadvantage that the change rate of the oscillation frequency is small.

  A solution to the above-described problem in the LC oscillation type voltage controlled oscillation circuit is disclosed in Patent Document 1. FIG. 9 shows an LC oscillation type voltage controlled oscillation circuit disclosed in Patent Document 1. In FIG. The circuit shown in FIG. 9 includes inductors 11 and 12, capacitors 13, 14, 16 and 17, a MOS transistor 15, bipolar transistors 18 and 19, and a current source 20. The inductors 11 and 12, the capacitors 13, 14, 16 and 17, and the MOS transistor 15 constitute a resonance circuit 21. The bipolar transistors 18 and 19 and the current source 20 constitute a negative resistance circuit 22.

  The circuit shown in FIG. 9 outputs an oscillation signal having a desired oscillation frequency from nodes A and AN. Here, the circuit shown in FIG. 9 controls the oscillation frequency by controlling the voltage VG applied to the gate of the MOS transistor 15.

  Patent Document 2 discloses a gyrator circuit as one of LC resonance circuits. Patent Document 3 discloses a ring oscillator type voltage controlled oscillation circuit of a type different from the LC oscillation type.

JP 2002-158539 A JP-A-8-330903 JP 2007-267410 A

  However, in the case of Patent Document 1, as apparent from FIG. 9, spiral inductance is used for the inductors 11 and 12. This spiral inductance is constituted by distributed constant lines arranged in a spiral. Therefore, the circuit shown in Patent Document 1 has a problem that the circuit scale increases.

  Here, in the case of the circuit shown in Patent Document 1, the oscillation frequency is controlled based on the inductance component and the capacitance component of the resonance circuit 21. That is, in the case of the circuit shown in Patent Document 1, it is necessary to increase the inductors 11 and 12 in order to further reduce the oscillation frequency. Therefore, the circuit shown in Patent Document 1 has a problem that the circuit scale further increases.

  Further, the inductance value of the spiral inductance is determined by many factors. For this reason, the circuit disclosed in Patent Document 1 has a problem that it is difficult to generate an oscillation signal having an oscillation frequency with high accuracy.

  A voltage-controlled oscillation circuit according to the present invention includes an oscillation amplifier unit that amplifies an oscillation signal, an LC resonance unit that controls an oscillation frequency of the oscillation signal, and a negative resistance unit having a negative resistance component, The LC resonating unit includes first and second transconductance amplifiers connected in a loop, and first and second capacitors having one ends connected to nodes on the loop, and the first and second capacitors The oscillation frequency is controlled based on an inductance value based on the second transconductance amplifier and the first capacitor and a capacitance value of the second capacitor.

  With the circuit configuration as described above, it is possible to suppress an increase in circuit scale.

  According to the present invention, it is possible to provide a voltage controlled oscillation circuit capable of suppressing an increase in circuit scale.

1 is a diagram illustrating a voltage controlled oscillation circuit according to a first embodiment of the present invention. It is a circuit diagram of the gm cells 24-26 concerning Embodiment 1 of this invention. It is a circuit diagram of the gm cells 23 and 27 concerning Embodiment 1 of this invention. It is a figure for demonstrating operation | movement of the electric current generation part concerning Embodiment 1 of this invention. It is a figure for demonstrating operation | movement of the gyrator conversion part concerning Embodiment 1 of this invention. It is a figure for demonstrating operation | movement of the negative resistance part 34 concerning Embodiment 1 of this invention. It is a figure which shows the equivalent circuit of the gyrator conversion part concerning Embodiment 1 of this invention. It is a figure which shows the voltage controlled oscillation circuit concerning Embodiment 2 of this invention. 2 is a diagram illustrating a voltage controlled oscillation circuit described in Patent Document 1. FIG.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. For clarity of explanation, duplicate explanation is omitted as necessary.

Embodiment 1
FIG. 1 shows a voltage controlled oscillation circuit according to the first exemplary embodiment of the present invention. The circuit shown in FIG. 1 includes an oscillation amplifier unit 32, an LC resonance unit 33, and a negative resistance unit 34. The oscillation amplifier unit 32 includes a gm cell 23. The LC resonator 33 includes a gm cell (third transconductance amplifier) 24, a gm cell (first transconductance amplifier) 25, a gm cell (second transconductance amplifier) 26, and a capacitor (first transconductance amplifier). Capacity) 28 and 29, and capacity (second capacity) 30 and 31. The negative resistance unit 34 includes a gm cell 27.

  Each of the gm cells 23 to 27 is a fully differential transconductance amplifier having a pair of differential input terminals IN + and IN− and a pair of differential output terminals OUT + and OUT−. Each of the gm cells 23 to 27 outputs a current corresponding to the differential input voltage supplied to the differential input terminals IN + and IN− from the differential output terminals OUT + and OUT−. Although not shown, each gm cell 23 to 27 has a power supply voltage terminal VDD, a ground voltage terminal VSS, a bias voltage terminal Bias, a setting voltage terminal VCM, and a control voltage terminal VG. For convenience, the symbols “VDD”, “VSS”, “Bias”, “VCM”, and “VG” each indicate a terminal name and also a voltage.

  First, the circuit configuration of the circuit shown in FIG. 1 will be described. The inverting output terminal OUT− of the gm cell 23 is connected to the non-inverting input terminal IN + of the gm cell 24. The non-inverting output terminal OUT + of the gm cell 23 is connected to the inverting input terminal IN− of the gm cell 24.

  The inverting output terminal OUT− of the gm cell 24 includes a non-inverting input terminal IN + of the gm cell 24, an inverting output terminal OUT− of the gm cell 25, an inverting input terminal IN− of the gm cell 26, and one end of the capacitor 31. , Gm cell 27 is connected to non-inverting input terminal IN + and gm cell 23 is connected to inverting input terminal IN−. The non-inverting output terminal OUT + of the gm cell 24 includes the inverting input terminal IN− of the gm cell 24, the non-inverting output terminal OUT + of the gm cell 25, the non-inverting input terminal IN + of the gm cell 26, and one end of the capacitor 30. , The inverting input terminal IN− of the gm cell 27 and the non-inverting input terminal IN + of the gm cell 23.

  The non-inverting output terminal OUT + of the gm cell 26 is connected to one end of the capacitor 29 and the inverting input terminal IN− of the gm cell 25. The inverting output terminal OUT− of the gm cell 26 is connected to one end of the capacitor 28 and the non-inverting input terminal IN + of the gm cell 25. The other ends of the capacitors 28 to 31 are connected to the ground voltage terminal VSS. The inverting output terminal OUT− of the gm cell 27 is connected to one external output terminal and also connected to the non-inverting input terminal IN + of the gm cell 23. The non-inverting output terminal OUT + of the gm cell 27 is connected to the other external output terminal and also to the inverting input terminal IN− of the gm cell 23.

  Next, the gm cells 23 to 27 will be described in more detail. FIG. 2 is a circuit diagram of the gm cells 24-26. FIG. 3 is a circuit diagram of the gm cells 23 and 27. The circuit shown in FIG. 2 includes a differential amplifier unit 39 and a common mode feedback unit (CMFB unit) 40. The differential amplifier unit 39 is a circuit that outputs a current corresponding to the differential input voltage from the differential output terminals OUT + and OUT−. The CMFB unit 40 is a circuit that controls the average voltage of the differential output terminals OUT + and OUT− to be the set voltage VCM.

  The differential amplifier unit 39 includes transistors Q1 to Q7. The CMFB unit 40 includes transistors Q8 to Q15, a resistor R10, and a capacitor C10. In the example of FIG. 2, transistors Q1-Q4 and transistors Q7-Q13 are P-channel MOS transistors. Transistors Q5, Q6, Q14, and Q15 are N-channel MOS transistors.

  First, the circuit configuration of the circuit shown in FIG. 2 will be described. In the transistor Q1, the source terminal is connected to the power supply voltage terminal VDD, the drain terminal is connected to the source terminal of the transistor Q3, and the gate terminal is connected to the bias voltage terminal Bias. In the transistor Q2, the source terminal is connected to the power supply voltage terminal VDD, the drain terminal is connected to the source terminal of the transistor Q4, and the gate terminal is connected to the bias voltage terminal Bias together with the gate terminal of the transistor Q1.

  In the transistor Q3, the drain terminal is connected to the drain terminal of the transistor Q5, and the gate terminal is connected to the non-inverting input terminal IN +. In the transistor Q4, the drain terminal is connected to the drain terminal of the transistor Q6, and the gate terminal is connected to the inverting input terminal IN−. In the transistor Q5, the source terminal is connected to the ground voltage terminal VSS, and the gate terminal is connected to the node P. In the transistor Q6, the source terminal is connected to the ground voltage terminal VSS, and the gate terminal is connected to the node P together with the gate terminal of the transistor Q5.

  The source terminal of the transistor Q7 is connected to a node on the signal line that connects the drain terminal of the transistor Q2 and the source terminal of the transistor Q4. The drain terminal of the transistor Q7 is connected to a node on a signal line that connects the drain terminal of the transistor Q1 and the source terminal of the transistor Q3. The gate terminal of the transistor Q7 is connected to the control voltage terminal VG. The inverting output terminal OUT− is connected to a node on a signal line connecting the drain terminal of the transistor Q3 and the drain terminal of the transistor Q5. The non-inverting output terminal OUT + is connected to a node on a signal line that connects the drain terminal of the transistor Q4 and the drain terminal of the transistor Q6.

  In the transistor Q8, the source terminal is connected to the power supply voltage terminal VDD, the drain terminal is connected to each source terminal of the transistors Q11 and Q13, and the gate terminal is connected to the bias voltage terminal Bias. In the transistor Q9, the source terminal is connected to the power supply voltage terminal VDD, the drain terminal is connected to each source terminal of the transistors Q10 and Q12, and the gate terminal is connected to the bias voltage terminal Bias together with the transistor Q8.

  In the transistors Q10 and Q11, the drain terminals are commonly connected to the node P, and the gate terminals are commonly connected to the set voltage terminal VCM. In the transistor Q12, the drain terminal is connected to the node Q, and the gate terminal is connected to the inverting output terminal OUT−. In the transistor Q13, the drain terminal is commonly connected to the node Q, and the gate terminal is connected to the non-inverting output terminal OUT +.

  In the transistor Q14, the source terminal is connected to the ground voltage terminal VSS, the drain terminal is connected to the node P, and the gate terminal is connected to the gate terminal of the transistor Q15 and the node Q. In the transistor Q15, the source terminal is connected to the ground voltage terminal VSS, and the drain terminal is connected to the node Q. One end of a resistor R10 is further connected to the node P. The other end of the resistor R10 is connected to one end of the capacitor C10. The other end of the capacitor C10 is connected to the ground voltage terminal VSS.

  The operation of the circuit shown in FIG. 2 will be described. Transistors Q1 and Q2 constitute a current mirror circuit. The drain currents of the transistors Q1 and Q2 are controlled by the bias voltage Bias. That is, the transistors Q1 and Q2 operate as a DC current source in the differential amplifier unit 39, and supply a DC current to the transistors Q3 to Q7.

  The drain current of the transistor Q3 is controlled by one of the differential input voltages supplied from the outside. The drain current of the transistor Q4 is controlled by the other differential input voltage supplied from the outside. That is, the transistors Q3 and Q4 amplify the current flowing out or flowing into the differential output terminals OUT + and OUT− based on the differential input voltage (AC voltage) supplied from the outside. The drain currents of the transistors Q5 and Q6 are controlled by a feedback voltage 41 from the CMFB unit 40. That is, the transistors Q5 and Q6 operate as a load portion in the differential amplifier section 39, and control the DC voltage at the differential output terminals OUT + and OUT−.

  Transistors Q8 and Q9 form a current mirror circuit in the same manner as transistors Q1 and Q2. The drain currents of the transistors Q8 and Q9 are controlled by the bias voltage Bias. That is, the transistors Q8 and Q9 operate as a DC current source in the CMFB unit 40 and supply a DC current to the transistors Q10 to Q15.

  The drain currents of the transistors Q10 and Q11 are controlled by the set voltage VCM. That is, the transistors Q10 and Q11 convert the set voltage VCM into a current. The drain current of the transistor Q12 is controlled by the voltage of the inverting output terminal OUT−. Further, the drain current of the transistor Q13 is controlled by the voltage of the non-inverting output terminal OUT +. That is, the transistors Q13 and Q12 convert the voltages at the differential output terminals OUT + and OUT− into currents, respectively.

  Transistors Q14 and Q15 constitute a current mirror circuit. The drain currents of the transistors Q14 and Q15 are controlled by the voltage at the node Q. That is, the drain currents of the transistors Q10 and Q11 are controlled by the transistor Q14. Similarly, the drain currents of the transistors Q12 and Q13 are controlled by the transistor Q15.

  The feedback voltage 41 corresponding to the difference between the current converted based on the set voltage VCM and the current converted based on the voltages of the differential output terminals OUT + and OUT− is the gates of the transistors Q5 and Q6. Applied to the terminal. Here, the drain currents of the transistors Q5 and Q6 are controlled so that the set voltage VCM is equal to the average voltage of the differential output terminals OUT + and OUT−. The resistor R10 and the capacitor C10 are provided to prevent oscillation of the feedback loop. With such a circuit configuration, the gm cell can keep the average voltage of the output signal constant. Therefore, multistage connection of gm cells is possible.

  The differential amplifier unit 39 adjusts the negative feedback amount by controlling the on-resistance of the transistor Q7 by the control voltage VG. That is, the differential amplifier unit 39 can adjust the transconductance gm by the control voltage VG.

  Next, the circuit (gm cells 23 and 27) shown in FIG. 3 will be described. The circuit shown in FIG. 3 has a differential amplifier unit 39b having a circuit configuration different from that of the differential amplifier unit 39 as compared with the circuit shown in FIG. 2 (gm cells 24 to 26). Further, the circuit shown in FIG. 3 does not have the CMFB section 40 as compared with the circuit shown in FIG. The gm cells 23 and 27 perform common mode feedback control by inputting the feedback voltage 41 from the gm cell 25 to the feedback voltage terminal FB. Other circuit configurations and operations are the same as those of the circuit shown in FIG. The differential amplifier section 39b may have a circuit configuration that does not include the transistor Q7. In that case, a node on the signal line connecting the drain terminal of the transistor Q1 and the source terminal of the transistor Q3 and a node on the signal line connecting the drain terminal of the transistor Q2 and the source terminal of the transistor Q4 are directly connected. .

  Next, the operation of the voltage controlled oscillation circuit shown in FIG. 1 will be described. In the oscillation amplifier unit 32, the gm cell 23 operates as an oscillation amplifier that amplifies the oscillation signal. In the LC resonance unit 33, the gm cells 25 and 26 and the capacitors 28 and 29 constitute a gyrator conversion unit. The gm cell 24 constitutes a current generation unit that generates a current toward the gyrator conversion unit. Here, the gm cells 24 to 26 gyrate-convert the capacitors 28 and 29 to generate an equivalent inductance. This equivalent inductance forms a parallel resonance circuit together with the capacitors 30 and 31. Thereby, the LC resonance unit 33 controls the oscillation frequency of the oscillation signal output from the oscillation amplifier unit 32. In the negative resistance section 34, the gm cell 27 constitutes a negative resistance. The transconductance gm of the gm cells 23 to 27 can be expressed as gm = (output differential current / input differential voltage).

The gm cell 24 that operates as a current generator will be described with reference to FIG. In the example of FIG. 4, the voltage V <b> 2 is applied to the non-inverting input terminal IN + of the gm cell 24. The voltage V <b> 1 is applied to the inverting input terminal IN− of the gm cell 24. At this time, a current Io flows from the non-inverting input terminal IN + of the gm cell 24 toward the inverting output terminal OUT−. Further, a current Io flows from the non-inverting output terminal OUT + of the gm cell 24 toward the inverting input terminal IN−. This current Io can be expressed as follows.
Io = gm × (V2−V1) (1)

Therefore, the impedance Z24 viewed from the input side of the gm cell 24 can be expressed as follows.
Z24 = (V2-V1) / Io = 1 / gm (2)

  That is, the gm cell 24 is equivalent to the case where the resistor is grounded. Thus, the gm cell 24 generates a current directed to the gyrator conversion unit and determines the impedance of the LC resonance unit 33.

  Next, the gyrator conversion unit will be described with reference to FIG. FIG. 5 shows an example in which the gyrator conversion unit is replaced with a single-ended configuration. The circuit shown in FIG. 5 includes gm cells 25a and 26a and a capacitor 28a. The gm cell 25a corresponds to the gm cell 25 in the gyrator conversion unit, the gm cell 26a corresponds to the gm cell 26, and the capacitor 28a corresponds to the capacitors 28 and 29. The capacitance value of the capacitor 28a is C1.

The gm cell 25a and the gm cell 26a are connected in a loop shape. A node on the signal line connecting the output terminal of the gm cell 26a and the input terminal of the gm cell 25a is referred to as a node N. A node on the signal line connecting the output terminal of the gm cell 25a and the input terminal of the gm cell 26a is referred to as a node M. A capacitor 28a is provided between the node N and the ground voltage terminal VSS. A voltage Vi is applied to the node M and a current Ii flows. A voltage Vo is applied to the node N and a current Io flows. Since the transconductance gm is expressed by gm = (output current / input voltage), the following equation is established in FIG.
Io = gm × Vi (3)
Ii = gm × Vo (4)
Vo = Io / (jωC1) (5)

By substituting Vo in Equation (5) for Vo in Equation (4), the following equation is established.
Ii = gm × Io / (jωC1) (6)

By substituting Io of equation (3) for Io of equation (6), the following equation is established.
Ii = gm ² × Vi / (jωC1) (7)

When the expression (7) is further modified, the following expression is established.
Vi / Ii = jωC1 / gm ² (8)

When L = C1 / gm ² is established, the following equation is established.
Vi / Ii = jωL (9)

  As can be seen from the equations (8) and (9), the capacitance value C1 is converted into the inductance value L. This is the same even in the case of a gyrator conversion unit having a fully differential configuration. That is, the capacitance values C1 of the capacitors 28 and 29 are converted into inductance values L (35 and 36 in FIG. 7) by the gm cells 24-26. Thereby, the gyrator converter becomes equivalent to the circuit shown on the right side of FIG. That is, the LC resonance unit 33 configures an LC resonance circuit by the inductance values of the gm cells 24 to 26 and the capacitors 28 and 29 and the capacitance values of the capacitors 30 and 31, and oscillates an oscillation signal in the voltage controlled oscillation circuit. Determine the frequency.

Next, the gm cell 27 that operates as the negative resistance unit 34 will be described with reference to FIG. In the example of FIG. 6, the voltage V2 is applied to the non-inverting input terminal IN + of the gm cell 27. The voltage V <b> 1 is applied to the inverting input terminal IN− of the gm cell 27. At this time, a current Io flows from the non-inverting output terminal OUT + of the gm cell 27 toward the non-inverting input terminal IN +. Further, a current Io flows from the inverting input terminal IN− of the gm cell 27 toward the inverting output terminal OUT−. Here, the current direction is different between the current Io in FIG. 6 and the current Io in FIG. Therefore, the impedance Z27 viewed from the input side of the gm cell 27 can be expressed as follows.
Z27 = − (V2−V1) / Io = −1 / gm (10)

  That is, the gm cell 27 is equivalent to the case where the negative resistance is grounded. Thus, the gm cell 27 constitutes a negative resistance.

  As described above, the voltage controlled oscillation circuit according to this embodiment controls the oscillation frequency of the oscillation signal by the LC resonance unit 33 including the gm cells 24 to 26 and the capacitors 28 to 31. That is, the voltage controlled oscillation circuit according to the present embodiment does not need to be provided with a spiral inductance, so that an increase in circuit scale can be suppressed.

  As described above, the transconductance gm of the gm cells 24 to 26 can be controlled by the control voltage VG from the outside. When a varicap is used for the capacitors 28 to 32, the capacitance values of the capacitors 28 to 32 can be controlled by an external control voltage. That is, the voltage controlled oscillation circuit according to the present embodiment can control the inductance value and the capacitance value of the LC resonance unit 33 from the outside. In other words, the voltage controlled oscillation circuit according to the present embodiment can control the oscillation frequency of the oscillation signal from the outside.

The inductors 35 and 36 obtained by gyrating the capacitors 28 and 29 can be expressed by L = C1 / gm ² as described above. The capacitance values of the capacitors 28 and 29 are C1, the capacitance values of the capacitors 30 and 31 are C2, and the inductance values of the inductors 35 and 36 are L. Therefore, the oscillation frequency f0 can be expressed by the following equation.
f0 = 1 / (2π√ (L · C1)) = gm / (2π√ (C1 · C2)) (11)

  As described above, the voltage-controlled oscillation circuit according to the present embodiment can be easily designed because the gm cell and the capacitor are used as the LC resonance circuit, and the elements for determining the inductance value are limited. Therefore, the voltage-controlled oscillation circuit according to the present embodiment can easily generate an oscillation signal having a highly accurate oscillation frequency.

  Further, as shown in Expression (11), the transconductance gm and the oscillation frequency f0 are in a linear relationship. That is, the voltage controlled oscillation circuit according to the present embodiment can linearly change the oscillation frequency of the oscillation signal in accordance with the change in transconductance gm. The transconductance gm is controlled by the voltage. Therefore, the voltage controlled oscillation circuit according to the present embodiment can smoothly change the oscillation frequency of the oscillation signal in accordance with the change in voltage. Thereby, the voltage-controlled oscillation circuit according to the present embodiment can finely adjust the oscillation frequency of the oscillation signal.

Further, the voltage controlled oscillation circuit according to the present embodiment uses a gm cell having a fully differential configuration for the LC resonance unit 33. Therefore, it is advantageous in the following points.
1. Strong against common mode noise.
2. The signal amplitude can be increased.
3.1.2. As a result, jitter (phase noise) can be reduced.
4). The even harmonics of the oscillation signal can be reduced.

  Furthermore, since the voltage controlled oscillation circuit according to the present embodiment uses the fully differential gm cell also for the oscillation amplifier unit 32 and the negative resistance unit 34, the relativity of the circuit can be improved.

Embodiment 2
FIG. 8 shows a voltage controlled oscillation circuit according to the second exemplary embodiment of the present invention. The circuit shown in FIG. 8 includes an LC resonance unit 33c having a circuit configuration different from that of the circuit shown in FIG. The LC resonance unit 33 c has variable capacitors 30 c and 31 c instead of the capacitors 30 and 31 as compared with the LC resonance unit 33. The other circuit configuration is the same as that of FIG.

  With such a circuit configuration, the circuit shown in FIG. 8 can control both the inductance values based on the gm cells 24 to 26 and the capacitors 28 and 29 and the capacitance values of the variable capacitors 30c and 31c. Therefore, the circuit shown in FIG. 8 can generate an oscillation signal having a wider range of oscillation frequencies.

  For example, a case where the fluctuation range of the inductance value according to the voltage fluctuation is narrowed and the fluctuation range of the capacitance value according to the voltage fluctuation is widened will be described. In this case, in the circuit shown in FIG. 8, the oscillation frequency can be roughly adjusted by the variable capacitors 30c and 31c and finely adjusted by the gm cells 24 to 26 and the capacitors 28 and 29. The reverse is also true.

  As described above, the voltage-controlled oscillation circuit according to the present embodiment controls the oscillation frequency of the oscillation signal by the LC resonance unit 33 including the gm cells 24 to 26 and the capacitors 28 to 31. That is, the voltage controlled oscillation circuit according to the present embodiment does not need to be provided with a spiral inductance, so that an increase in circuit scale can be suppressed. In addition, since the voltage-controlled oscillation circuit according to the present embodiment uses a gm cell and a capacitor as the LC resonance circuit, the elements that determine the inductance value are limited. Therefore, the voltage-controlled oscillation circuit according to the present embodiment can generate an oscillation signal having a highly accurate oscillation frequency.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

32 Oscillation amplifier part 33, 33c LC resonance part 34 Negative resistance part 23-27 gm cell 25a, 26a gm cell 28-31 capacity 28a capacity 30c, 31c variable capacity 35, 36 inductor 39, 39b differential amplifier part 40 CMFB part Q1 to Q15 Transistor C10 Capacitance R10 Resistance FB Feedback voltage terminal VDD Power supply voltage terminal VSS Ground voltage terminal Bias Bias voltage terminal VG Control voltage terminal VCM Setting voltage terminal

Claims (9)

An oscillation amplifier for amplifying the oscillation signal;
An LC resonance unit for controlling the oscillation frequency of the oscillation signal;
A negative resistance portion having a negative resistance component,
The LC resonance part is
First and second transconductance amplifiers connected in a loop;
First and second capacitors having one end connected to a node on the loop;
A voltage-controlled oscillation circuit that controls the oscillation frequency based on an inductance value based on the first and second transconductance amplifiers and the first capacitance and a capacitance value of the second capacitance. The first and second transconductance amplifiers are:
The voltage controlled oscillation circuit according to claim 1, wherein the voltage controlled oscillation circuit has a fully differential configuration. In the first and second transconductance amplifiers,
3. The voltage controlled oscillation circuit according to claim 1, wherein the transconductance is controlled according to an external voltage. The LC resonance part is
The voltage-controlled oscillation circuit according to claim 1, further comprising a third transconductance amplifier that outputs a current corresponding to the amplified oscillation signal to a node on the loop. The first to third transconductance amplifiers are:
5. The voltage controlled oscillation circuit according to claim 4, wherein the voltage controlled oscillation circuit has a fully differential configuration. In the first to third transconductance amplifiers,
6. The voltage controlled oscillation circuit according to claim 4, wherein the transconductance is controlled according to an external voltage.   The voltage-controlled oscillation circuit according to claim 1, wherein the first capacitor is a varicap.   The voltage-controlled oscillation circuit according to claim 1, wherein the second capacitor is a varicap.   The voltage-controlled oscillation circuit according to claim 1, wherein the second capacitor is a variable capacitor whose capacitance value changes according to an external voltage.

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