JP2011127947A - Failure diagnostic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a failure diagnostic device which reduces a processing load while making the speed of a failure diagnosis high. <P>SOLUTION: The failure diagnostic device includes: a control part having a battery voltage detecting part which detects a voltage of a battery pack and sets a first flag based on the detected voltage; a receiving part which receives the detected voltage and the first flag; a storage part which stores the detected voltage received by the receiving part and the first flag received by the receiving part and a flag setting part which sets a second flag based on the detected voltage stored in the storage part. The control part compares the first flag stored in the storage part with the second flag and diagnoses a failure in the failure diagnostic device from the consistency of the flags. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

    The present invention relates to a failure diagnosis apparatus.

By writing data to a plurality of different addresses on the same bit line or the same word line as the address, and comparing the values stored in the three addresses, A RAM diagnostic device for diagnosing a failure of a bit line or a word line is known (Patent Document 1).

JP 2000-339991 A

  However, when performing a diagnostic method using a conventional RAM diagnostic apparatus, there is a problem in that the processing in the CPU is complicated, a load is applied to the CPU, and the processing time for diagnosis becomes long.

  Therefore, the present invention provides a failure diagnosis apparatus that reduces the processing load while speeding up failure diagnosis.

The present invention detects a voltage of a battery pack, sets a first flag based on the detected voltage, receives the detected voltage and the first flag, and sets a second flag. The above-described problem is solved by diagnosing a failure from the consistency between the first flag and the second flag.

  According to the present invention, the battery voltage detection unit that sets the first flag based on the detection voltage, and the control unit that receives the detection voltage and the first flag and sets the second flag, In order to diagnose a failure based on the consistency between the first flag and the second flag, it is possible to determine a change in detected data due to a garbled value, a communication abnormality, etc. in the storage unit. A failure in the apparatus can be diagnosed while mitigating.

It is a block diagram which shows the assembled battery monitoring apparatus containing the failure diagnosis apparatus which concerns on embodiment of invention. It is a figure which shows the characteristic of the detection voltage and flag signal of a battery cell which are contained in the assembled battery monitoring apparatus of FIG. It is a figure explaining the data of a battery cell and the 1st flag formed by the cell controller etc. which are contained in the assembled battery monitoring apparatus of FIG. It is a figure for demonstrating the transition of the data of RAM, a register | resistor, and ROM contained in the assembled battery monitoring apparatus of FIG. It is a flowchart which shows the control procedure of the assembled battery monitoring apparatus of FIG. It is a flowchart which shows the control procedure of the assembled battery monitoring apparatus of FIG. It is a flowchart which shows the control procedure of the assembled battery monitoring apparatus of FIG. It is a block diagram which shows the other assembled battery monitoring apparatus of this invention. It is a flowchart which shows the other control procedure of the assembled battery monitoring apparatus of FIG.

  Hereinafter, embodiments of the invention will be described with reference to the drawings.

<< First Embodiment >>
As an example of an assembled battery monitoring device including a failure diagnosis device according to an embodiment of the invention, a failure diagnosis device used as a battery for a vehicle such as a hybrid vehicle or an electric vehicle will be described. FIG. 1 is a block diagram showing an assembled battery monitoring device according to the present embodiment. First, a configuration relating to the capacity adjustment function of this example will be described with reference to FIG.

  As shown in FIG. 1, the assembled battery monitoring device according to the present embodiment includes 1 unit of n battery cells 1 (n is an arbitrary positive integer, n = 4 in the example shown in FIG. 1) connected in series. And three cell controllers CC1, CC2, CC3 for monitoring the battery capacities of the battery modules M1, M2, M3 (specifically, the voltages VC1 to VC4 of the individual cells). With. The assembled battery 3 includes battery modules M1, M2, and M3.

  The three battery modules M1 to M3 are connected in series, and a battery load 2 that is a motor such as an electric vehicle is connected to both ends of the battery modules M1 to M3 via a power converter such as an inverter (not shown). The relay switch 4 is turned on and off by an ON / OFF operation, and is connected between the assembled battery 3 and the battery load 2.

  When power is supplied from the three battery modules M1 to M3 to the battery load 2, the battery capacity varies due to individual differences in manufacturing of each battery cell 1 and the like. Therefore, according to the detected voltage of each battery cell 1, the CPU 10 sends a command to the cell controllers CC1, CC2, CC3, closes the switching element (not shown), and converts the power of the battery cell having a high battery capacity to the capacity adjustment resistor. By supplying to 5, the battery capacity is adjusted at a predetermined timing. A series circuit of the capacity adjustment resistor 5 and a switching element (not shown) such as a transistor is connected in parallel to each battery cell 1. The cell controllers CC1 to CC3 adjust the capacity of the battery cell 1 by causing the current from the battery cell 1 to flow through the capacity adjustment resistor by turning the switching element ON.

  The CPU 100 controls the battery load 2 and the battery controller 101, and detects the capacity of the assembled battery 3 from the battery controller 101. When the assembled battery 3 is consumed and the capacity of the assembled battery 3 decreases, the CPU 100 controls the inverter to limit the output torque of the motor and prevent overdischarge of the assembled battery 3. The battery controller 101 includes cell controllers CC1 to CC3 and a CPU 10.

  Each of the cell controllers CC1 to CC3 has input terminals VC1 to VC4 for inputting voltages of the battery cells 1 of the battery modules M1 to M4 including the four battery cells 1 and a ground terminal GND thereof. Each cell controller CC1 to CC3 holds the voltage value input to each input terminal VC1 to VC4 as a detection voltage, generates a flag to be described later based on the detection voltage, and outputs a signal including the detection voltage and the flag. It transmits to CPU10.

  CPU10 transmits the instruction | command which detects the voltage of each battery cell 1 to cell controller CC1-CC3 at a predetermined | prescribed timing, and cell controller CC1-CC3 which received this detects the voltage of each battery cell 1. FIG.

  The output terminals Out1 to Out3 of the cell controllers CC1 to CC3 are connected to the input terminals In1 to In3 of the CPU 10 via communication lines, and the cell controllers CC1 to CC3 and the CPU 10 are connected via the communication lines. Communicate. Referring to FIG. 1, the cell controllers CC1 to CC3 and the CPU 10 are connected by a wired communication line, but may be wireless, and perform communication via, for example, a photocoupler and a photodiode. May be. Moreover, each cell controller CC1-CC3 and CPU10 do not need to be comprised by the control processing apparatus of another structure.

  The CPU 10 writes the data included in the detection voltage and flag signal transmitted from each cell controller CC1 to CC3, and can read the data. The RAM 11 (Random Access Memory), and the ROM 13 (Read Only) in which the data for reading is recorded. Memory) and a register 12 for temporarily recording data.

  Next, the configuration relating to the failure diagnosis function of this example will be described with reference to FIGS. FIG. 2 shows the characteristics of the detection voltage of the battery cell 1 and the flag signal. (A) shows the detection voltage of the battery cell 1, (b) shows the overcharge flag, and (c) shows the overdischarge flag.

  Each cell controller CC1-CC3 detects the voltage of the battery cell 1 from the input terminals VC1-VC4. The detected voltage is converted by an A / D converter (not shown) included in each of the cell controllers CC1 to CC3 and is digitally expressed in 16-bit length. Each cell controller CC1 to CC3 uses an upper limit voltage value (Vmax) and a lower limit voltage value (Vmin) set in advance, and an overdischarge or overcharge flag (hereinafter referred to as a first flag) based on the detected voltage. ) Is set. The upper limit voltage value indicates a voltage value at which the battery cell 1 may be overcharged, and the lower limit voltage value indicates a voltage value at which the battery cell 1 may be overdischarged. Each cell controller CC1 to CC3 compares the detected voltage with the upper limit voltage value (Vmax) or the lower limit voltage value (Vmin), and when the detected voltage is higher than the upper limit voltage value, sets the first flag to 1, When the detected voltage is lower than the lower limit voltage value, the first flag is set to 1. When the detected voltage is between the lower limit voltage value (Vmin) and the upper limit voltage value (Vmax), the first flag is set. Set to 0. Referring to FIG. 2A, for example, in a certain battery cell 1, when the cell controller CC1 detects a detection voltage for a time between 0 and t5, the detection voltage for the time between t1 and t2 is an upper limit voltage value. Since it is higher than (Vmax), the first flag of the time between t1 and t2 is set to 1. In addition, since the detection voltage during the period from t3 to t4 is lower than the lower limit voltage value (Vmin), the first flag during the period from t1 to t2 is set to 0. Then, the set flag is converted by an A / D converter (not shown) included in each of the cell controllers CC1 to CC3 and is digitally expressed with a 16-bit length. And each cell controller CC1-CC3 transmits a detection voltage and a 1st flag to CPU10.

  The CPU 10 stores the received detection voltage and the first flag in the RAM 11. The RAM 11 is assigned an address in association with each battery cell 1, and the received detection voltage and the first flag are stored in a storage area to which an address corresponding to the battery cell to be detected is attached. The Further, the CPU 10 sets a flag (hereinafter referred to as a second flag) based on the detected voltage stored in the RAM 11. The flag setting conditions are set under the same conditions as the cell controllers CC1 to CC3 shown in FIG. Then, the CPU 10 determines whether or not there is a failure portion by comparing the first flag stored in the RAM 11 with the second flag. The CPU 10 determines that there is no failure when the first flag and the second flag match, and determines that there is a failure when the first flag and the second flag do not match. When it is determined that there is a failure, the CPU 10 performs control for specifying the failure location, as will be described later.

  Next, the control part for specifying the failure location by CPU10 is demonstrated using FIG.3 and FIG.4. FIG. 3 is a diagram illustrating data of the battery cell 1 and the first flag formed by the cell controller CC1. In FIG. 3, the cell 1 voltage indicates the detected voltage of the battery cell 1 on the most positive side in the battery module M1, and the cell 2 voltage and subsequent voltages are sequentially repeated from the battery cell 1 on the most positive side in the battery module M1. The detection voltage of the battery cell 1 which falls is shown. FIG. 4 is a diagram illustrating data stored in the RAM 11, the register 12, and the ROM 13 when a failure location is specified. 4A to 4E show data transitions of the RAM 11, the register 12 and the ROM 13 shown in time series, FIG. 4A shows the data at time t, and FIGS. 4B to 4E show. Indicates data at times t + 1 to t + 4.

  As shown in FIG. 3, the cell controller CC1 stores the detected voltage and the first flag data of each battery cell 1 included in the battery module M1, and transmits the data to the CPU 10. Referring to FIG. 4, the RAM 11 is divided into storage areas for each address, and the detection voltage of each battery cell 1 and the data of the first flag are stored in the storage area for each address. Therefore, the data to be transitioned is stored. In this example, at time t, the cell 1 voltage and the first flag data are written to the address A0000, and “00000000” is written to the address C0001. The ROM 13 stores “5555”, “AAAAA”, and “FFFF” in advance with a data length of 16 bits. The failure diagnosis in the CPU 10 is performed as follows. “5555”, “AAAA”, and “FFFF” are in hexadecimal notation.

  4A and 4B, the cell 1 voltage data and the first flag stored in the area A0000 are copied to the address C0000 in the RAM 11 (step S1). When the CPU 10 calls the data stored in the area of address A0000, the CPU 10 writes the data “5555” called from the ROM 13 to the lower bits of the flag part, and stores the cell 1 voltage and the data “5555” in the register 12. (Step S2). Next, the CPU 10 rewrites the RAM 11 by writing the cell 1 voltage and the data “5555” stored in the register 12 to the addresses A0000 and B0000 of the RAM 11 (step S3). When calling the data stored in the area of address A0000, the CPU 10 writes the data “AAAA” called from the ROM 13 to the lower bits of the flag part, and stores the cell 1 voltage and the data “5555” in the register 12. (Step S4). Next, referring to FIG. 4C, the CPU 10 writes the cell 1 voltage and “AAAA” data stored in the register to the addresses A0001 and B0001 of the RAM 11, and rewrites the RAM 11 (step S5). Next, referring to FIG. 4D, the CPU 10 calculates the sum of the data stored at the address A0000 and the data stored at the address A0001, and writes it in the register (step S6). If normal, the lower bit data “5555” at address A0000 and the lower bit data “AAAA” of A0001 are summed, so the lower bit data of the register is “FFFF”. In order to determine whether or not the data corresponding to the first flag is “FFFF”, the CPU 10 calls the data “FFFF” from the ROM 13, and the data stored in the register 12 in step S 6. Compare (step S7). If the lower bit data is the same, the CPU 10 does not write data to the data at the C0001 address. If the lower bit data is different, the CPU 10 adds +1 to the data at the C0001 address, and the data at the C0001 address is “00000001”. Is written. If the RAM 11 and the register 12 are normal for the lower bits of the addresses A0000, A0001, B0000, and B0001 in FIGS. 4D and 4E, the data of the lower bits is “5555”. In this example, it is set to “5554” for explanation. Therefore, in FIG. 4D, the low-order bit of the register 12 is “FFFE” because it is the sum of “5554” at address A0000 and “AAAA” at address A0001.

  Then, referring to FIG. 4E, the CPU 10 calculates the sum of the data stored at the address B0000 and the data stored at the address B0001, and writes it in the register (step S8). Similarly, since the sum of the lower-bit data “5555” at address B0000 and the lower-bit data “AAAA” of B0001 is taken if it is normal, the lower-bit data of the register is “FFFF”. In order to determine whether or not the data corresponding to the first flag is “FFFF”, the CPU 10 calls the data “FFFF” from the ROM 13, and the data stored in the register 12 in step S 6. Compare (step S9). When the lower bit data is the same, the CPU 10 does not write data to the data at the address C0001, and when the lower bit data is different, the CPU 10 adds +1 to the data at the address C0001 and writes the data. In FIG. 4E, the lower bit data at address B0000 is “5554” and the lower bit data at register 12 is “FFFE”. Therefore, the data at address C0001 is written as +1, and the data is written at address C0001. Is “00000002”.

  Next, the data stored at the address C0001 (data “00000002” in FIG. 4E) is read into the register 12 to determine whether the data at the address C0001 is 0, 1, or 2. To do. When the data at address C0001 is 2, this corresponds to the case where the lower-bit data at addresses A0000 and A0001 and the lower-bit data at addresses B0000 and B0001 are different. Since the possibility that a failure such as the value fixing of the address in the RAM 11 will occur at the same time is quite low, it can be estimated that the failure is in the register 12. When the data at the address C0001 is 1, this corresponds to the case where either the data of the lower bits of the addresses A0000 and A0001 or the data of the lower bits of the addresses B0000 and B0001 is equal to “FFFF”. In such a case, it can be estimated that the RAM 11 is malfunctioning due to address value fixation or the like. The case where the data at the address C0001 is 0 corresponds to the case where the data of the lower bits of the addresses A0000 and A0001 and the data of the lower bits of the addresses B0000 and B0001 are equal to “FFFF”. In this case, the RAM 11 and the register 12 correspond to the case where there is no failure. Therefore, since the first flag and the second flag are different and no failure has occurred in the CPU 10, it is determined that there is a communication abnormality such as a signal that is transmitted from the cell controllers CC1 to CC3 to the CPU 10 changes due to noise or the like. Is done. Thereby, CPU10 can pinpoint a failure location.

  Next, a control flow for failure diagnosis of the assembled battery monitoring device of this example will be described with reference to FIGS. FIG. 5 shows a flowchart of a control procedure for confirming the consistency between the flag set by the cell controllers CC1 to CC3 and the flag set by the CPU 10 based on the cell voltage, and FIGS. It is a flowchart which shows the control procedure of the failure diagnosis in CPU10.

  With reference to FIG. 5, in step S51, the CPU 10 transmits the cell voltage (detected voltage) of the battery cell 1 transmitted from the CC1, and the first flag set by the cell controller CC1 based on the cell voltage. Is stored in the RAM 11. In step S52, the CPU 10 calls the cell voltage stored in the RAM 11 to the register 12. In step S53, the cell voltage written in the register 12 is compared with the upper limit voltage value.

  When the cell voltage is higher than the upper limit voltage value, the CPU 10 sets the overcharge flag as the second flag and calls data “0001” indicating the overcharge flag to the register 12 (step S531). The CPU 10 compares the first flag and the second flag (step S532). When the first flag and the second flag match, the CPU 10 notifies the battery cell 1 that it is overcharged with a lamp or the like, and ends the process. When the first flag and the second flag do not match, the CPU 10 performs a control flow for specifying the failure location shown in FIG.

  Returning to step S53, if the cell voltage is lower than the upper limit voltage value, the cell voltage written in the register is compared with the lower limit voltage value in step S54.

When the cell voltage is lower than the lower limit voltage value, the CPU 10 sets the overdischarge flag as the second flag and calls data “0001” indicating the overdischarge flag to the register (step S541). The CPU 10 compares the first flag and the second flag (step S542). When the first flag and the second flag match, the CPU 10 notifies the battery cell 1 that the battery cell 1 is overdischarged with a lamp or the like, and ends the process. When the first flag and the second flag do not match, the CPU 10 performs control for identifying the failure location.

  Returning to step S54, when the cell voltage is higher than the lower limit voltage value and lower than the upper limit voltage value, the CPU 10 sets the normal flag as the second flag and calls the data “0000” indicating the normal flag to the register (step S55). . The CPU 10 compares the first flag and the second flag (step S56). If the first flag matches the second flag, the CPU 10 ends the process. When the first flag and the second flag do not match, the CPU 10 performs a control flow for specifying the failure location shown in FIG.

  Next, with reference to FIGS. 6 and 7, a control procedure for specifying a failure location will be described. Referring to FIG. 6, steps S1 to S7 are the same as steps S1 to S7 in FIG. If the flag portion of the register is “FFFF” in step S7, the CPU 10 does not write the data at the address C0001 and proceeds to step S8. on the other hand. When the flag portion of the register is not “FFFF”, the CPU 10 increments the data at the address C0001 (step S71). Next, in step S8, the CPU 10 writes the data at the address B0000 and the sum of the data at the address B0001 in the register. If the flag portion of the register is “FFFF” in step S9, the CPU 10 does not write the data at the address C0001 and proceeds to the abnormality diagnosis of FIG. on the other hand. If the flag portion of the register is not “FFFF”, the CPU 10 increments the data at address C0001 (step S71), and proceeds to the abnormality diagnosis of FIG.

  Referring to FIG. 7, in step S10, CPU 10 reads the data at address C0001, and determines in step S11 whether the data at address C0001 is “0000”. If the data at address C0001 is “0000”, it is determined that a communication error has occurred. If the data at the address C0001 is not “0000”, it is determined in step S12 whether the data at the address C0001 is “0001”. If the data at the address C0001 is “0001”, it is determined that the RAM is stuck. If the data at the address C0001 is not “0001”, it is determined that the register is stuck. Then, when the above-described control flow is completed for the battery cell 1, the above-described control is performed for the next battery cell 1, and the process continues to the battery cell 1 on the most negative side in the battery module M3.

  As described above, the failure diagnosis apparatus of the present invention receives the first flag set based on the detection voltage of the battery cell 1 by the cell controllers CC1 to CC3 and the CPU 10 that receives the signal including the detection voltage. The consistency with the second flag set based on the detected voltage is confirmed. In this example, if the flag is consistent, the battery controller 101 determines that it is operating normally. If the flag is not consistent, an abnormality has occurred in the battery controller 101. Judge and make a detailed abnormality diagnosis. Thus, in this example, simple failure determination based on flag consistency is performed, and detailed failure determination is performed based on the simple result. Therefore, complicated processing is not required, and the burden on the CPU 10 is reduced. be able to. Further, in this example, since the failure determination is simplified, the processing time can be shortened, and it is not necessary to use the CPU 10 having a high processing capacity, so that the cost can be suppressed. Further, in this example, since it is not necessary to perform complicated processing for failure diagnosis every time the detection voltage of the battery cell 1 included in the assembled battery 3 is transmitted to the CPU 10, the processing time of the CPU 10 is shortened and the processing load is reduced. Reduction and cost reduction can be realized.

  In this example, the first flag and the second flag are set using a voltage value indicating overdischarge or overcharge as a threshold value. Thereby, simple failure diagnosis can be performed using the flag for detecting overdischarge or overdischarge, and it is not necessary to separately use a signal for failure diagnosis.

  In this example, a failure diagnosis of the battery controller 101 can be performed using a capacity adjustment control signal.

  In this example, referring to FIG. 1, the cell controllers CC1 to CC3 and the CPU 10 are connected by a communication line connecting In1 to In3 and Out1 to Out3. Instead of the communication line, as shown in FIG. The CPU 10 and the assembled battery 3 may be connected by the power supply line 30. FIG. 8 is a block diagram showing another assembled battery monitoring apparatus of this example.

One end of the power supply line 30 is connected to the positive terminal side of the assembled battery 3, and the other end is connected to the CPU 10. The power supply line 30 supplies the power of the assembled battery 3 to the CPU 10. The detection voltage and the first flag of the battery cell 1 detected by each cell controller CC1 to CC3 pass through the assembled battery 3 from each cell controller CC1 to CC3, and through the power supply line 30 to the CPU 10 by power line communication. Sent. Moreover, CPU10 transmits the command signal etc. for detecting the voltage of the battery cell 1 with respect to each cell controller CC1-CC3 via the power supply line 30 by power line communication. Then, the CPU 10 performs the failure determination illustrated in FIGS. 4 to 7, but when the communication state is abnormal, the CPU 10 determines that an abnormality has occurred in the communication of the power supply line 30.

  This example transmits and receives the detection voltage and the first flag of the battery cell 1 by power line communication using the power supply line 30, and the second flag is set based on the first flag and the received detection voltage. And the failure of the power line communication, the RAM 11 and the register 12 can be determined based on the determination result.

  Further, in this example, referring to FIG. 5, even when the cell voltage is a normal value, the consistency between the first flag and the second flag is determined and simple failure diagnosis is performed. If the cell voltage is a normal value, failure diagnosis may not be performed. FIG. 9 is a flowchart showing another control procedure of this example.

  Referring to FIG. 9, in step S <b> 91, CPU 10 transmits the cell voltage (detected voltage) of battery cell 1 transmitted from CC <b> 1 and the first flag set by cell controller CC <b> 1 based on the cell voltage. Is stored in the RAM 11. In step S92, it is determined whether or not the first flag stored in the RAM 11 is “0000”. If the first flag is “0000”, the control process is terminated. On the other hand, if the first flag is not “0000”, the CPU 10 calls the cell voltage stored in the RAM 11 to the register 13 in step S93, and the CPU 10 stores the cell voltage stored in the register in step S94. Based on the above, the second flag is set. Next, in step S95, it is determined whether or not the second flag is “0000”. If the second flag is not “0000”, the control processing of this example is terminated because consistency with the first flag is achieved. On the other hand, when the second flag is “0000”, the consistency with the first flag is not achieved, and the characteristics of the failure location are observed.

  In this example, both the overdischarge flag and the overcharge flag are set to 1, but it is not always necessary to use the same flag, and different flags may be assigned.

  The cell controllers CC1 to CC3 in this example correspond to the “detection unit” and “first flag setting unit” of the present invention, and the CPU 10 serves as the “reception unit”, “second flag setting unit”, and “control unit”. The RAM 11 and / or the register 12 correspond to a “storage unit”, and the capacitance adjustment resistor 5 corresponds to a “resistance”.

DESCRIPTION OF SYMBOLS 1 ... Battery cell 2 ... Battery load 3 ... Battery assembly M1-M3 ... Battery module 4 ... Relay switch 5 ... Resistance for capacity adjustment 6 ... Voltage detection circuit 10 ... CPU
11 ... RAM
12 ... Register 13 ... ROM
CC1 to CC3 ... cell controller 30 ... power supply line 100 ... CPU
101 ... Battery controller

Claims (5)

A battery voltage detector that detects the voltage of the assembled battery and sets a first flag based on the detected voltage;
A reception unit that receives the detection voltage and the first flag, a storage unit that stores the detection voltage received by the reception unit and the first flag received by the reception unit, and a storage unit that stores the detection voltage and the first flag. A fault diagnosis apparatus comprising a control unit having a flag setting unit that sets a second flag based on the detected voltage.
The controller is
A failure diagnosis device that compares the first flag stored in the storage unit with the second flag and diagnoses a failure in the failure diagnosis device from the consistency of the flag. The first flag setting unit compares the predetermined threshold voltage with the detection voltage, sets the first flag,
The failure diagnosis apparatus according to claim 1, wherein the second flag setting unit sets the second flag by comparing the predetermined threshold voltage with a detection voltage stored in the storage unit. . A power supply line that is electrically connected to the battery pack and supplies power to the battery load;
The receiver is
The power line communication flowing through the power supply line receives the detection voltage and the first flag,
The storage unit includes a RAM and a register that store a detection voltage received by the reception unit and a first flag received by the reception unit,
The controller is
3. The fault diagnosis apparatus according to claim 1, wherein when the value of the first flag is different from the value of the second flag, a fault of the power line communication, the RAM, and the register is diagnosed. The assembled battery includes a plurality of batteries,
The detection voltage and the first flag are associated with addresses assigned to the plurality of batteries,
The failure according to any one of claims 1 to 3, wherein the storage unit stores the received detection voltage and the received first flag in association with each address. Diagnostic device. The assembled battery includes a plurality of batteries,
A resistor for adjusting the capacity of each of the batteries;
The controller specifies a battery whose capacity is to be adjusted according to the received detection voltage, and controls the resistance connected to the specified battery to adjust the capacity of the battery. The failure diagnosis apparatus according to any one of claims 1 to 3.

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