JP2011119481A - Semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of improving reliability of a semiconductor device. <P>SOLUTION: The semiconductor device has: an interposer 2A; and chips CP1 and CP2 provided on the interposer 2A. The interposer 2A has: a plurality of columnar conductors 10 which extend in a direction of a thickness thereof and are electrically insulated to one another; and a wiring layer 11 interposing the chips CP1 and CP2, and the plurality of columnar conductors 10; wherein air gaps 13 are formed between the plurality of columnar conductors 10 and open to the outside, and respective side faces of the plurality of columnar conductors 10 are covered with insulating films 12. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor package (semiconductor device) mounted on an organic substrate.

  Japanese Unexamined Patent Application Publication No. 2004-42082 (Patent Document 1) discloses a technique related to a multi-chip package in which a plurality of semiconductor chips are mounted. In this multichip package, a plurality of semiconductor chips are mounted via a silicon interposer mounted on a package substrate (organic substrate).

  In addition, this inventor performed prior art search based on the result invented. As a result, JP 2006-216723 A (Patent Document 2) was extracted. In Patent Document 2, for the purpose of effectively suppressing unwanted radiation noise to a high frequency band, a region having a gap is provided between a pair of planar electrodes, and a plurality of columnar or columnar resistors are provided in the region. A technique related to a printed wiring board (organic substrate) sandwiched between layers is disclosed.

JP 2004-42082 A JP 2006-216723 A

  A multichip package (semiconductor package) is a semiconductor device configured by mounting a plurality of semiconductor chips (hereinafter simply referred to as chips) on, for example, an organic substrate (for example, a build-up substrate or a printed wiring board). Such a multichip package is mounted on a substrate (motherboard) made of an organic base material on which an electronic circuit such as a computer is configured.

  By the way, in a multi-chip package using an organic substrate, stress is generated between the chip and the organic substrate due to a mismatch in thermal expansion coefficients between the silicon (Si) -based chip and the organic substrate, resulting in a gap. For example, there is a problem that reliability is lowered. In addition, for example, wiring for electrically connecting a plurality of chips is formed on an organic base material with poor flatness, so that it is difficult to make fine wiring. Further, for example, it is conceivable that the wiring length between chips becomes long, and that the organic substrate itself becomes large due to this.

  For this reason, the present inventor is examining a technology relating to the next generation package in order to meet the recent demands for miniaturization, high performance, and high functionality of semiconductor devices. FIG. 1 schematically shows a semiconductor device 100 studied by the present inventors. A semiconductor device 100 shown in FIG. 1 includes a silicon interposer 110 and chips CP1 and CP2 mounted thereon, and can also be called a semiconductor package. In FIG. 1, the semiconductor device 100 is illustrated as being mounted on an organic substrate 130 (for example, a mother board) together with a heat sink 120 (for example, a heat spreader) that houses the semiconductor device 100 by a cavity.

  Since the silicon interposer 110 is an interposer having silicon as a base material 111, there is no mismatch in thermal expansion coefficient between the chips CP1 and CP2 having the same silicon base material. For this reason, the problem by the stress as mentioned above does not occur, and the reliability of the semiconductor device 100 can be improved. Further, since the silicon interposer 110 uses silicon for the base material 111 and is excellent in planarization as compared with the organic substrate, it is easy to form fine wiring.

  Therefore, the semiconductor device 100 including the silicon interposer 110 can be expected to improve the data transfer speed by shortening the wiring length between chips and increasing the number of bus lines by fine wiring. Further, in order to increase the functionality of the semiconductor device 100, the silicon interposer 110 may be mounted with different types of chips such as a chip formed with logic semiconductor elements and a chip formed with memory semiconductor elements. I can expect.

  However, in the semiconductor device 100 mounted on the organic substrate 130 such as a mother board, for example, stress is generated between the organic substrate 130 and the silicon interposer 110 due to a mismatch of thermal expansion coefficients. For this reason, for example, under an overload condition such as a temperature cycle test, the reliability of the semiconductor device 100 is lowered due to the stress, for example, the organic substrate 130 and the silicon interposer 110 are warped against each other and the bonding property is lowered. In particular, in the case where a plurality of chips including chips CP1 and CP2 are mounted on the silicon interposer 110, the mounting area is also enlarged. Therefore, when the size of the silicon interposer 110 is, for example, 20 mm square or more, a decrease in reliability is remarkable. become.

  Further, in FIG. 1, in order to improve the heat dissipation of the semiconductor device 100, a common heat sink 120 is attached to the chips CP1 and CP2, and the chips CP1 and CP2 are cooled. The chips CP1 and CP2 and the heat sink 120 are bonded via a bonding member 121, and the heat sink 120 and the organic substrate 130 are bonded via a bonding member 122.

  Here, for example, a semiconductor element having a large thermal resistance such as logic and a large amount of heat generated may be formed on the chip CP1, and a semiconductor element having a small thermal resistance such as a memory may be formed on the chip CP2. . In such a case, the heat generated from the chip CP1 is efficiently cooled by the heat sink 120 and the base material 111 (silicon) of the silicon interposer 110, but the heat is conducted to the chip CP2. For this reason, when the temperature of the chip CP2 rises, malfunction or thermal destruction may occur, and the reliability of the semiconductor device 100 is lowered.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  In addition, patent document 2 which this inventor extracted by prior art search is a subject which suppresses noise, Comprising: The package with a space | gap is described for that purpose, In order to improve reliability No description is made regarding the invention disclosed in the present application.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. A semiconductor device according to an embodiment of the present invention includes an interposer and a semiconductor chip provided on the interposer. The interposer includes a plurality of columnar conductors that extend in the thickness direction and are electrically insulated from each other, and a wiring layer that interposes the semiconductor chip and the plurality of columnar conductors. A gap is formed between the columnar conductors, the gap is open to the outside, and each side surface of the plurality of columnar conductors is covered with an insulating film.

  An effect obtained by a representative one of the inventions disclosed in the present application will be briefly described. The reliability of the semiconductor device can be improved by the one embodiment.

It is explanatory drawing which shows typically the semiconductor device which this inventor is examining. It is sectional drawing which shows typically the semiconductor device in one Embodiment of this invention. FIG. 3 is a plan view schematically showing the semiconductor device shown in FIG. 2. It is sectional drawing which shows typically the state which mounted the semiconductor device shown in FIG. 1, FIG. 2 on the organic substrate. It is sectional drawing which shows typically the semiconductor device in the manufacturing process in one Embodiment of this invention. FIG. 6 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 5. FIG. 7 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 6. FIG. 8 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 7. FIG. 9 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 8. FIG. 10 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 9. It is sectional drawing which shows typically the semiconductor device in other embodiment of this invention. It is sectional drawing which shows typically the semiconductor device in the manufacturing process in other embodiment of this invention. It is sectional drawing which shows typically the semiconductor device in other embodiment of this invention. It is sectional drawing which shows typically the semiconductor device in the manufacturing process in other embodiment of this invention. It is sectional drawing which shows typically the semiconductor device in other embodiment of this invention. It is sectional drawing which shows typically the semiconductor device in the manufacturing process in other embodiment of this invention. It is sectional drawing which shows typically the semiconductor device in other embodiment of this invention. It is sectional drawing which shows the principal part of a semiconductor device typically. It is sectional drawing which shows the principal part of a semiconductor device typically. It is sectional drawing which shows typically the semiconductor device in other embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof may be omitted.

(Embodiment 1)
First, the structure of the semiconductor device according to the present embodiment will be described with reference to FIGS. FIG. 2 is a cross-sectional view schematically showing the semiconductor device 1A in the present embodiment, and FIG. 3 is a plan view schematically showing the semiconductor device 1A. 2 shows a cross section of the semiconductor device 1A taken along line AA of FIG. Further, FIG. 3 shows a plane viewed from the back side of the semiconductor device 1A, and chips CP1, CP2, CP3, CP4 (shown by broken lines) mounted on the device surface opposite to the back side are seen through. It is shown. In FIG. 3, the columnar conductor 10 and the frame body 20 are hatched for easy understanding.

  The semiconductor device 1A includes an interposer 2A and chips CP1 to CP4 provided on the interposer 2A. The chip CP1 is, for example, a CPU, and a logic semiconductor element is formed on the chip CP1. The chips CP2 to CP4 are, for example, DRAMs or flash memories, and the semiconductor elements for memory are formed on the chips CP2 to CP4. Using these chips CP1 to CP4, the semiconductor device 1A can perform a predetermined operation.

  The interposer 2A has a plurality of columnar conductors 10 extending in the thickness direction and electrically insulated from each other, and a wiring layer 11 having the chips CP1 to CP4 and the plurality of columnar conductors 10 interposed therebetween. . Each side surface of the plurality of columnar conductors 10 is covered with an insulating film 12, and a gap 13 is provided between the plurality of columnar conductors 10. The gap 13 is open to the outside of the interposer 2A (semiconductor device 1A). The interposer 2 </ b> A has a frame 20 that surrounds the plurality of columnar conductors 10 on the outer periphery.

  The wiring layer 11 of the interposer 2A includes a first layer (lowermost layer) wiring layer 14a, a second layer (uppermost layer) wiring layer 14b, an interlayer insulating layer 15 between the wiring layers 14a and 14b, and a wiring layer 14b. And a passivation film 16 having an opening formed at a desired position. For example, the wiring layers 14a and 14b include copper (Cu), the interlayer insulating layer 15 includes silicon oxide or an organic resin, and the passivation film 16 includes an organic resin. The passivation film 16 serves as a surface protective film for the interposer 2A, and protects the uppermost wiring layer 14b. On the other hand, in the lowermost wiring layer 14a, the insulating film 12 covering the side surface of the columnar conductor 10 is formed so as to be related to the wiring layer 14a, and is protected by the insulating film 12 made of, for example, a silicon oxide film. The total thickness of the wiring layer 11 composed of these is formed to be about 15 μm, for example.

  The wiring layer 14b exposed from the opening of the passivation film 16 serves as an external electrode pad of the interposer 2A, and the chips CP1 to CP4 and the wiring layer 11 are electrically connected through the external electrode pad. In the wiring layer 11, the wiring layer 14 b serving as the external electrode pad and the wiring layer 14 a are connected to each other through a via 17. The wiring layer 14 a (wiring layer 11) is electrically connected to the columnar conductor 10.

  On the interposer 2A (wiring layer 11), chips CP1 to CP4 are mounted and provided. External connection terminals (not shown) are formed on the main surfaces (element formation surfaces) of the chips CP1 to CP4, and are flip-chip connected to the electrode pads (wiring layer 14b) of the interposer 2A via the electrode bumps 18. ing. An underfill resin 19 is filled between the chips CP1 to CP4 and the interposer 2A (wiring layer 11). The underfill resin 19 prevents mismatch between the thermal expansion coefficients of the interposer 2A and the chips CP1 to CP4, and improves the connectivity between the interposer 2A and the chips CP1 to CP4.

  The columnar conductor 10 is made of, for example, a conductor containing copper (Cu), and is formed in a columnar shape having a diameter of about 60 μm and a length (height) of about 300 μm. The plurality of columnar conductors 10 are erected from the wiring layer 11, and a gap 13 is opened between them. For this reason, when the columnar conductor 10 is exposed, the conductor (for example, copper) may be corroded to deteriorate the electrical characteristics.

  Therefore, in this embodiment, the columnar conductor 10 is prevented from corroding by covering the side surface of the columnar conductor 10 with the insulating film 12 such as a silicon oxide film. The semiconductor device 1A is particularly effective because it has a structure in which the gap 13 is open to the outside. The reliability of the semiconductor device 1A can be improved by preventing the deterioration of the electrical characteristics by preventing the columnar conductor 10 from being corroded. The tip of the columnar conductor 10 is exposed without being covered like the insulating film 12 on the side surface in order to ensure electrical connection with the outside. Even in this state, after connection, the tip of the columnar conductor 10 is not corroded because it is protected by, for example, solder.

  Similarly, the surface of the wiring layer 14a on the gap 13 side is also covered with the insulating film 12 to prevent the wiring layer 14a from being corroded. By preventing the corrosion of the wiring layer 14a, the reliability of the semiconductor device 1A can be improved by preventing the deterioration of the electrical characteristics.

  Such a semiconductor device 1A is configured to include chips CP1 to CP4 provided on the interposer 2A, and is a semiconductor package (multi-chip package). The semiconductor device 1A is formed with a size of about 11 mm square, for example.

  Incidentally, the semiconductor device 100 described with reference to FIG. 1 is also a semiconductor package because it includes the chips CP1 and CP2. In the semiconductor device 100, chips CP1 and CP2 are provided on an interposer (silicon interposer 110) using silicon as a base material, that is, a support. On the other hand, there is no interposer 2A of the semiconductor device 1A corresponding to such a base material (support). Therefore, the semiconductor device 1A can also be referred to as a substrate-less package, and the interposer 2A can be said to be a flexible substrate because the wiring layer 11 is in the form of a film (for example, a thickness of 15 μm and a size of 11 mm square).

  FIG. 4 shows a state where the semiconductor device 1A is mounted on an organic substrate 130 (for example, a mother board). For example, the columnar conductor 10 (for example, copper) and the pattern 131 (for example, copper) are provided on the tip of each of the plurality of columnar conductors 10 of the semiconductor device 1A via solder balls 21 having a diameter of, for example, about 70 μm. The semiconductor device 1A is mounted on the organic substrate 130. As described above, the semiconductor device 1 </ b> A has a structure in which the plurality of columnar conductors 10 are connected.

  The semiconductor device 1 </ b> A has a plurality of columnar conductors 10 provided so as to stand upright from the wiring layer 11, and the plurality of columnar conductors 10 are mounted on the organic substrate 130 as legs. Since there are gaps 13 between the plurality of columnar conductors 10, the stress generated between the organic substrate 130 and the interposer 2A can be relaxed. Moreover, since the wiring layer 11 of the interposer 2A is in the form of a film, the stress generated between the interposer 2A and the chips CP1 to CP4 can be relaxed. For this reason, for example, even in an overload condition such as a temperature cycle test, warpage between the semiconductor device 1A and the organic substrate 130 is suppressed, and the reliability as the semiconductor device 1A can be improved.

  In the semiconductor device 1A, a plurality of chips CP1 to CP4 are mixedly mounted on the same surface of the interposer 2A on the wiring layer 11 side. These chips CP1 to CP4 may have different thermal resistances depending on their functions such as logic and memory and the size of the chip. For example, on the interposer 2A, a chip CP1 (for example, a logic) having a high thermal resistance and a high calorific value and chips CP2 to CP4 (for example, a memory) having a low thermal resistance and heat resistance may be mounted. In such a case, it is effective to have a structure in which heat conduction is separated between a chip that generates a large amount of heat and a chip that is weak against heat.

  Therefore, the semiconductor device 1A (interposer 2A) has a structure having a gap 13 between the chips CP1 to CP4 so that the base material of the substrate 23 serving as a heat path is not provided. For example, the base material (silicon silicon) when using a silicon interposer ) Is interrupted. Silicon has a very high thermal conductivity, and when a plurality of chips with different calorific values are mounted, problems due to heat transfer occur. Therefore, it is possible to prevent malfunctions and thermal destruction due to the temperature of the chip that is weak against heat being excessively increased due to the influence of the chip that generates a large amount of heat, and the reliability of the semiconductor device 1A can be improved.

  Further, although the semiconductor device 1A is a substrate-less package, it does not simply have a substrate, but has a structure in which a plurality of columnar conductors 10 are provided and gaps 13 are provided between the columnar conductors 10. For this reason, heat dissipation can also be improved by using the air gap 13 as a cooling path and flowing air, water, or the like through the cooling path. As a result, it is possible to further prevent malfunctions and thermal destruction due to the temperature of the heat-sensitive chip being excessively increased due to the influence of the chip having a high calorific value, and to further improve the reliability of the semiconductor device 1A. Can do.

  Further, since the gap 13 is provided between the plurality of columnar conductors 10, the capacitance between the columnar conductors 10 can be reduced as compared with, for example, silicon. Therefore, the data transfer rate can be improved.

  In addition, a frame 20 is provided on the outer periphery of the interposer 2A of the semiconductor device 1A. The presence or absence of the frame body 20 can be selected as appropriate, but in this embodiment, the case where the frame body 20 is provided is described.

  The interposer 2A includes a plurality of columnar conductors 10 and a wiring layer 11, and the wiring layer 11 has a film shape (for example, a thickness of about 15 μm). Therefore, the interposer 2A is handled. It may be difficult to do this. Therefore, handling property can be improved by providing the frame 20 surrounding the plurality of columnar conductors 10 on the outer periphery of the interposer 2A. Thereby, the semiconductor device 1 </ b> A can be easily mounted on the organic substrate 130.

  The frame 20 of the semiconductor device 1A may be in a free state without being bonded to the organic substrate 130, but in FIG. 4, the frame 20 (for example, copper) is the bonding member 22 (for example, solder). It is bonded to the pattern 132 (for example, copper foil) of the organic substrate 130 via Since the semiconductor device 1A is a base material-less package, it is considered that deformation of the outer shape (form) becomes a problem during actual use after being mounted on the organic substrate 130. Therefore, the frame body 20 is provided, and the frame body 20 is also bonded to the organic substrate 130, thereby preventing the semiconductor device 1A from being deformed.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings. First, as shown in FIG. 5, a substrate 23 having a predetermined thickness having a first surface 23a and a second surface 23b opposite to the first surface 23a is prepared. In the present embodiment, the base material of the substrate 23 is silicon. Next, after forming a resist on one surface of the substrate 23, a desired pattern 24 is formed by using a photolithography technique.

  Subsequently, by using dry etching using the pattern 24 as a mask, as shown in FIG. 6, a plurality of through holes 25 extending in the thickness direction of the substrate 23 and a through groove 26 surrounding the through holes 25 are formed. . In FIG. 6, the pattern 24 is removed after the through holes 25 and the through grooves 26 are formed. Further, in a later manufacturing process, the columnar conductor 10 is formed in the through hole 25 and the frame body 20 is formed in the through groove 26.

  In this manufacturing process, the through groove 26 is formed, but the through groove 26 may be left. As will be described later, the silicon frame may be formed by leaving the base material (silicon) in a shape similar to the frame 20 by patterning.

  Subsequently, as shown in FIG. 7, the insulating film 12 is formed on the inner walls of the plurality of through holes 25. Further, the insulating film 12 is formed on the inner wall of the through groove 26. Specifically, since silicon is used as the substrate 23, the insulating film 12 made of a silicon oxide film can be formed by thermally oxidizing the surface of the substrate 23.

  Subsequently, as shown in FIG. 8, each of the plurality of through holes 25 is filled with a conductor (for example, copper), thereby extending a plurality of the substrates 23 extending in the thickness direction of the substrate 23 and electrically insulated from each other. The columnar conductor 10 is formed. Moreover, the frame 20 surrounding the plurality of columnar conductors 10 is formed by filling the through grooves 26 with a conductor (for example, copper). Specifically, a conductive plate is attached to the second surface 23b of the substrate 23, and the through hole 25 and the through groove 26 are filled with a conductor (for example, copper) by electrolytic plating using the conductive plate as a seed. Thereafter, the columnar conductor 10 and the through-groove 20 are formed by performing flat processing on the first surface 23a side of the substrate 23, removing the conductive plate, and performing flat processing on the second surface 23b side of the substrate 23.

  Subsequently, as illustrated in FIG. 9, the wiring layer 11 that is electrically connected to the plurality of columnar conductors 10 is formed on the first surface 23 a of the substrate 23. For example, the wiring layer 14a, the interlayer insulating layer 15, and the wiring layer 14b are formed by a semi-additive method. When the wiring layer 14b is formed, a via 17 that electrically connects the wiring layer 14a and the wiring layer 14b is formed. Further, the passivation layer 16 is coated and patterned on the wiring layer 14b to form the wiring layer 11.

  Subsequently, as shown in FIG. 10, chips CP <b> 1 to CP <b> 4 that are electrically connected to the wiring layer 11 are mounted on the wiring layer 11. Specifically, external connection terminals (not shown) formed on the main surfaces (element formation surfaces) of the chips CP1 to CP4 are flip-chip connected to the wiring layer 14b via the electrode bumps 18. Thereafter, an underfill resin 19 is filled between the chips CP1 to CP4 and the wiring layer 11.

  Next, the base material of the substrate 23 is removed from the second surface 23b side of the substrate 23 opposite to the first surface 23a on which the chips CP1 to CP4 are mounted. Specifically, silicon serving as a base material is removed by dry etching from the second surface 23b side of the substrate 23. At this time, the base material is removed by the selection ratio of copper (columnar conductor 10, frame body 20) or silicon oxide (insulating film 12) with respect to silicon (base material), and the columnar conductor 10, frame body 20, and insulation of the side surfaces thereof are removed. The film 12 will remain.

  In this way, the semiconductor device 1A (baseless package) shown in FIG. 2 is completed. In addition, an interposer 2A having a plurality of columnar conductors 10 and a wiring layer 11 is also completed.

  In this embodiment, after mounting the chips CP1 to CP4 on the wiring layer 11, the base material of the substrate 23 is removed to complete the semiconductor device 1A. Not limited to this, the chip mounting process can be selected as appropriate. For example, after removing the base material of the substrate 23, the chips CP1 to CP4 can be mounted on the wiring layer 11 to complete the semiconductor device 1A.

  However, since the wiring layer 11 becomes a film by removing the base material of the substrate 23, it is difficult to mount the chips CP1 to CP4 on the film-like wiring layer 11. Therefore, as in this embodiment, by mounting the chips CP1 to CP4 on the wiring layer 11, the manufacturing yield is improved when the base material of the substrate 23 is removed using the chips CP1 to CP4 as a support. be able to.

  Moreover, in this embodiment, the case where the frame 20 of the interposer 2A was formed in the same manufacturing process as the columnar conductor 10 was demonstrated. That is, after forming the through groove 26 together with the through hole 25 in the manufacturing process described with reference to FIG. 6, the columnar conductor 10 is formed in the through hole 25 in the manufacturing process described with reference to FIG. A frame 20 was formed in the groove 26.

  Here, when only the through hole 25 is formed and the through groove 26 is not formed in the manufacturing process described with reference to FIG. 6, the frame body 20 is not formed in the state shown in FIG. 9, for example. In such a case, a resist pattern surrounding the plurality of columnar conductors 10 is formed on the second surface 23b of the substrate 23, and then the etching process described with reference to FIG. A frame body made of the base material (silicon) of the substrate 23 can be formed.

  Further, when there is no frame 20 of the interposer 2A, it is advantageous to mount the chip first. FIG. 17 shows an interposer 2A ′ when the frame body 20 is not provided in the interposer 2A, and a semiconductor device 1A ′ having the same. When there is no frame in this way, the interposer 2A 'becomes a film, and it is difficult to mount the chips CP1 to CP4 in this film state. For this reason, when the frame 20 is not provided, it is desirable to remove the base material of the substrate 23 after mounting the chips CP1 to CP4 first.

  Further, in this embodiment, as shown in FIG. 2, the end of the columnar conductor 10 is exposed without being covered like the insulating film 12 on the side surface in order to ensure electrical connection with the outside. Yes. A structure when the tip of the columnar conductor 10 is exposed will be described with reference to FIGS.

  In FIG. 18, for example, the insulating film 12 on the side surface of the columnar conductor 10 shown in FIG. 2 is partially retracted from the tip side. For example, when connecting to a joining member 22 such as a solder bump, the contact area between the columnar conductor 10 and the conductor is increased, and the conductor (eg, copper) is better in wettability than the insulating film 12 (eg, silicon oxide film). This is advantageous for holding the bonding member 22 and can improve the reliability of the semiconductor device. The structure as shown in FIG. 18 can be formed, for example, by adjusting the etching strength in the etching process described with reference to FIG.

  On the other hand, in FIG. 19, for example, the columnar conductor 10 shown in FIG. 2 is partially retracted from the tip side. For example, when connecting to the joining member 22 such as a solder bump, the contact area between the solder and the conductor of the columnar conductor 10 is reduced, which is advantageous for reducing the diameter of the solder bump (joining member 22). For example, with the miniaturization of a semiconductor device, the reliability of a semiconductor device having a solder bump with a reduced diameter can be improved. The structure as shown in FIG. 19 can be formed, for example, by etching the columnar conductor 10 (for example, copper) (for example, using a cupric chloride solution) after the etching step described in FIG. .

(Embodiment 2)
The structure of the semiconductor device in this embodiment will be described with reference to FIG. FIG. 11 is a cross-sectional view schematically showing the semiconductor device 1B in the present embodiment. In the semiconductor device 1A described in the first embodiment, the insulating film 12 is provided on the space 13 side of the wiring layer 14a. However, the present embodiment is different in that the reinforcing material 30 is provided. Therefore, it demonstrates centering on the point and description of another structure may be abbreviate | omitted.

  In the interposer 2 </ b> B of the semiconductor device 1 </ b> B, a reinforcing material 30 that covers the roots of the plurality of columnar conductors 10 extending from the wiring layer 11 and reinforces the standing of the plurality of columnar conductors 10 is provided. The reinforcing material 30 is, for example, insulative and rigid, and is made of, for example, a glass material. For this reason, since generation | occurrence | production of malfunctions, such as the columnar conductor 10 falling from the wiring layer 11, for example, can be suppressed, the reliability of the semiconductor device 1B can be improved.

  Further, in the semiconductor device 1B, a gap 13 is provided between the chips CP1 to CP4 so that the base material of the substrate 23 serving as a heat path is not provided. For example, heat conduction by the base material (silicon) when a silicon interposer is used. Is shut off. Therefore, it is possible to prevent malfunctions and thermal destruction due to the temperature of the chip that is weak against heat being excessively increased due to the influence of the chip that generates a large amount of heat, and the reliability of the semiconductor device 1B can be improved.

  In addition, by providing the reinforcing material 30 on the side of the gap 13 of the wiring layer 11, handling properties can be improved. Therefore, the semiconductor device 1B can be easily mounted on the organic substrate 130 described with reference to FIG.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings. After the manufacturing process described with reference to FIG. 6 in the first embodiment, as shown in FIG. 12, the reinforcing member 30 having openings for opening the through holes 25 and the through grooves 26 is used as the first surface 23 a of the substrate 23. To form. Specifically, for example, a glass plate is used as the reinforcing member 30, and after the glass plate is joined to the first surface 23a of the substrate 23, the openings corresponding to the through holes 25 and the through grooves 26 are removed by, for example, etching. To do.

  Alternatively, after preparing the substrate 23 in the manufacturing process described with reference to FIG. 5, a reinforcing material is formed on the first surface 23 a of the substrate 23. After that, the pattern 24 as shown in FIG. 5 is formed on the reinforcing material, and the through hole 25 and the through groove 26 are opened together with the through hole 25 and the through groove 26 by the etching process described with reference to FIG. You may form the reinforcing material 30 which has an opening part to do.

  Thereafter, after the manufacturing steps described with reference to FIGS. 7 to 10 in the first embodiment, the semiconductor device 1B shown in FIG. 11 is completed. In addition, an interposer 2B having a plurality of columnar conductors 10 and a wiring layer 11 is also completed.

(Embodiment 3)
The structure of the semiconductor device in this embodiment will be described with reference to FIG. FIG. 13 is a cross-sectional view schematically showing a semiconductor device 1C in the present embodiment. In the semiconductor device 1A described in the first embodiment, the insulating film 12 is provided on the side surface (air gap 13 side) of the columnar conductor 10, but in the present embodiment, the outer side of the insulating film 12 (air gap 13 side). The difference is that the reinforcing material 31 is provided. Therefore, it demonstrates centering on the point and description of another structure may be abbreviate | omitted.

  In the interposer 2 </ b> C of the semiconductor device 1 </ b> C, a reinforcing material 31 that reinforces the standing of the plurality of columnar conductors 10 is provided on each side surface of the plurality of columnar conductors 10 via the insulating film 12. The reinforcing material 31 has rigidity, for example, and is made of a base material (for example, silicon) of the substrate 23, for example. For this reason, since generation | occurrence | production of malfunctions, such as the columnar conductor 10 falling from the wiring layer 11, for example, can be suppressed, the reliability of 1 C of semiconductor devices can be improved.

  Further, the semiconductor device 1C has a structure having a gap 13 between the chips CP1 to CP4 so that the base material of the substrate 23 serving as a heat path is not provided. For example, heat conduction by the base material (silicon) when using a silicon interposer Is shut off. Therefore, it is possible to prevent malfunction or thermal destruction due to the temperature of the chip that is weak against heat being excessively increased due to the influence of the chip that generates a large amount of heat, and the reliability of the semiconductor device 1C can be improved.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings. After the manufacturing process described with reference to FIG. 8 in the first embodiment, as shown in FIG. 14, the diameter of the columnar conductor 10 is set on each of the end portions of the plurality of columnar conductors 10 on the second surface 23b side of the substrate 23. A larger pattern 32 is formed. Specifically, for example, after a layer made of copper is formed on the second surface 23b of the substrate 23, the copper layer is patterned by anisotropic etching or the like to form the pattern 32. As a result, the pattern 32 is provided at the end of the plurality of columnar conductors 10 on the second surface 23b side.

  Thereafter, after the manufacturing process described with reference to FIGS. 9 to 10 in the first embodiment, the semiconductor device 1C shown in FIG. 13 is completed. In addition, an interposer 2C having a plurality of columnar conductors 10 and a wiring layer 11 is also completed.

  The base material of the substrate 23 is etched using the pattern 32 as a mask, with reference to FIG. 10, so that the plurality of columnar conductors 10 stand on the side surfaces of the columnar conductors 10 via the insulating films 12. The reinforcing material 31 that reinforces the installation is formed. Thereafter, the pattern 32 may be removed, but in this embodiment, the pattern 32 is formed of the same material as the columnar conductor 10 and is larger than the diameter of the columnar conductor 10. For this reason, the pattern 32 is left to effectively use the pattern 32 as an external connection terminal.

(Embodiment 4)
The structure of the semiconductor device in this embodiment will be described with reference to FIG. FIG. 15 is a cross-sectional view schematically showing the semiconductor device 1D in the present embodiment. In the semiconductor device 1A described in the first embodiment, the gap 13 is formed between all the columnar conductors 10, but in this embodiment, the gap 13 that blocks the heat path between the chips CP1 to CP4. Is different. Therefore, it demonstrates centering on the point and description of another structure may be abbreviate | omitted.

  In the interposer 2D of the semiconductor device 1D, almost the base material of the substrate 23 remains, and the slit-shaped gap 13 is formed at a position where the heat path is blocked between the chips CP1 to CP4. In the plane of the semiconductor device 1D as shown in FIG. 3, a cross-shaped slit (gap 13) is formed so as to block the heat path between the chips CP1 to CP.

  In the semiconductor device 1D, the gap 13 is not provided between the chips CP1 to CP4 so that the base material of the substrate 23 serving as a heat path is not provided. For example, the heat conduction by the base material (silicon) when using a silicon interposer, It is shut off. Therefore, it is possible to prevent malfunction and thermal destruction due to the temperature of the chip that is weak against heat being excessively increased due to the influence of the chip having a high calorific value, and the reliability of the semiconductor device 1D can be improved.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings. After the manufacturing process described with reference to FIG. 9 in the first embodiment, chips CP1 to CP4 electrically connected to the wiring layer 11 are mounted on the wiring layer 11 as shown in FIG. An underfill resin 19 is filled between the CP 4 and the wiring layer 11.

  Subsequently, as shown in FIG. 16, a slit (gap 13) is formed between the columnar conductors 10 from the second surface 23b side opposite to the first surface 23a on which the chips CP1 to CP4 are mounted on the substrate 23. The base material of the substrate 23 is removed so as to form. Specifically, a slit (gap 13) is formed at a position where the blade 33 cuts off the heat path between the chips CP1 to CP4. Such a slit is not limited to being formed using the blade 33 but may be formed using etching or the like.

  Thereby, the semiconductor device 1D shown in FIG. 15 is completed. In addition, an interposer 2D having a plurality of columnar conductors 10 and a wiring layer 11 is also completed.

  Further, like the reinforcing material 30 shown in FIG. 11, such a reinforcing material may be constituted by the base material (silicon) of the substrate 23 in order to prevent problems such as the columnar conductor 10 falling. In FIG. 20, in the interposer 2D, the interposer 2D ′ when a part of the substrate 23 is left so as to cover the roots of the plurality of columnar conductors 10 extending from the wiring layer 11, and the semiconductor device 1D ′ having the interposer 2D ′ are shown. Show. Thus, even when the reinforcing material 34 made of the base material (silicon) of the substrate 23 is provided, the slit (gap 13) is indispensable in order to prevent heat transfer.

  In the interposer 2D ', the etching process described with reference to FIG. 10 is applied after the slit process described with reference to FIG. Alternatively, in the interposer 2D ', the etching process described with reference to FIG. 16 is applied after the slit process described with reference to FIG.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Not too long.

  For example, although the case where a plurality of semiconductor chips having different thermal resistances are mounted on the same surface of the interposer has been described in the above embodiment, they may be mounted on both the upper and lower surfaces of the interposer. Specifically, a semiconductor chip having a high thermal resistance can be mounted on the upper surface of the interposer, and a semiconductor chip lower than that can be mounted on the lower surface of the interposer. Thereby, the semiconductor chip having a high thermal resistance and a high calorific value can be separated from the semiconductor chip having a low thermal resistance and weak against heat by the thickness of the interposer, so that the cooling effect can be enhanced.

1A, 1A ′, 1B, 1C, 1D, 1D ′ Semiconductor device 2A, 2A ′, 2B, 2C, 2D, 2D ′ Interposer 10 Columnar conductor 11 Wiring layer 12 Insulating film 13 Voids 14a, 14b Wiring layer 15 Interlayer insulating layer 16 Passivation film 17 Via 18 Electrode bump 19 Underfill resin 20 Frame body 21 Solder ball 22 Joining member 23 Substrate 24 Pattern 25 Through hole 26 Through groove 30, 31 Reinforcement material 32 Pattern 33 Blade 34 Reinforcement material 100 Semiconductor device 110 Silicon interposer 111 Base Material 120 Heat radiation plate 121, 122 Joining member 130 Organic substrate 131, 132 Pattern CP1, CP2, CP3, CP4 Chip

Claims (10)

A semiconductor device having an interposer and a semiconductor chip provided on the interposer,
The interposer includes a plurality of columnar conductors that extend in the thickness direction and are electrically insulated from each other, and a wiring layer that interposes the semiconductor chip and the plurality of columnar conductors,
Having a gap between the plurality of columnar conductors, the gap is open to the outside,
A side surface of each of the plurality of columnar conductors is covered with an insulating film. The semiconductor device according to claim 1,
A semiconductor device comprising a frame surrounding the plurality of columnar conductors. The semiconductor device according to claim 1 or 2,
A semiconductor device, wherein a reinforcing material that covers the base of the plurality of columnar conductors extending from the wiring layer and reinforces the standing of the plurality of columnar conductors is provided. The semiconductor device according to claim 1, 2 or 3.
A semiconductor device, wherein a reinforcing material for reinforcing standing of the plurality of columnar conductors is provided on each side surface of the plurality of columnar conductors via the insulating film. In the semiconductor device according to any one of claims 1 to 4,
As the semiconductor chip, a plurality of semiconductor chips having different calorific values are provided on the interposer. (A) forming a plurality of through holes extending in the thickness direction in a substrate having a first surface and a second surface opposite to the first surface;
(B) forming an insulating film on the inner walls of the plurality of through holes;
(C) After the step (b), by filling each of the plurality of through holes with a conductor, a plurality of columnar conductors extending in the thickness direction of the substrate and electrically insulated from each other are formed. Process,
(D) after the step (c), forming a wiring layer electrically connected to the plurality of columnar conductors on the first surface of the substrate;
(E) etching the base material of the substrate from the second surface side of the substrate;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 6.
After forming the through groove surrounding the plurality of through holes in the step (a), filling the through groove with a conductor in the step (c), or
After the step (d), after forming a resist pattern on the second surface of the substrate, etching the base material of the substrate in the step (e),
A method for manufacturing a semiconductor device, comprising: forming a frame surrounding the plurality of columnar conductors. In the manufacturing method of the semiconductor device of Claim 6 or 7,
Arranging the reinforcing material on the second surface of the substrate before the step (a), or
After the step (a), disposing a reinforcing material on which a through hole leading to the plurality of through holes is formed on the second surface of the substrate;
A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device of Claim 6 or 7,
(F) After the step (d), including a step of forming a pattern larger than the diameter of the columnar conductor on each of the second surface side end portions of the plurality of columnar conductors,
In the step (e), the base material of the substrate is etched using the pattern as a mask, thereby reinforcing the standing of the plurality of columnar conductors via the insulating film on each side surface of the plurality of columnar conductors. A method of manufacturing a semiconductor device, comprising forming a reinforcing material to be manufactured. In the manufacturing method of the semiconductor device of Claim 6 or 7,
In the step (e), the base material is removed so that a slit is formed between the plurality of columnar conductors.

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