JP2011119467A - Display device and method of manufacturing display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce effect due to hydrogen in carrying out hydrogen plasma treatment in the thin-film transistor substrate of a display device. <P>SOLUTION: Copper wiring formed on an amorphous silicon layer formed of an amorphous silicon film is provided with a thin-film transistor substrate having a copper alloy layer 107A formed of alloy with copper, as main components, which contains elements in which the generation energy of hydride is negative as first additional elements and second additional elements, and a pure copper layer 107B formed of pure copper on the copper alloy layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device and a method for manufacturing the display device, and more particularly to a display device using a thin film transistor substrate and a method for manufacturing the display device.

  A liquid crystal panel provided with a TFT (Thin Film Transistor) substrate is applied to a thin TV having a large screen size. In recent years, the driving frequency has been increased in order to improve the moving image quality, and accordingly, the resistance of the signal line needs to be lowered. Research and development of flat-screen televisions using organic EL (Electro Luminescence) devices are also active, but it is also necessary to reduce the resistance of the signal lines of the TFT substrate because of the need to drive the elements with current. Flat-screen TVs are also exposed to intense price competition. Therefore, cost reduction is indispensable to meet market demands, and thin film materials and process chemicals with good cost performance are also required in the signal line forming process.

  Conventionally, in order to construct a signal line of a low-resistance TFT substrate, a Mo / Al / Mo laminated film using aluminum having a resistivity of about 3 μΩcm as a main conductor material (where / represents the interface of the lamination, and the right side of / Is the lower layer, and the left side of / is the upper layer. In order to further reduce the resistance of the signal line of this laminated film, the Al layer must be thickened. However, since the deposition time of the Mo / Al / Mo laminated film becomes longer, the productivity is deteriorated and the manufacturing process is also reduced. Problems such as a dramatic increase in the frequency of hillocks that cause yield deterioration occur.

  Copper is an example of a signal line material having a low resistivity lower than that of aluminum and a reasonable material cost. Copper has a feature that the resistivity of a thin film is as low as about 2 μΩcm, and it can be in direct electrical contact with a transparent conductive film (generally an oxide containing indium as a main component). .

  However, there are drawbacks in that the adhesion to the base is weak and that transistor characteristics are easily deteriorated by diffusion into silicon, which is a semiconductor layer of the thin film transistor.

  Patent Document 1 discloses 0.1 to 20 at. With respect to copper (Cu) containing inevitable impurities. % Of a copper alloy to which an additive element that is a solid solution is added, and the additive element is a copper whose oxide formation free energy is smaller than Cu and the diffusion coefficient of the additive element in Cu is larger than the self-diffusion coefficient of Cu. Disclosure of employing an alloy.

International Publication No. 2006/025347

  An object of the present invention is to reduce the influence of hydrogen plasma. Other novel objects and configurations will be clarified in the specification and drawings.

  The display device of the present invention is a display device using a thin film transistor, and the thin film transistor includes an amorphous silicon layer formed of an amorphous silicon film, and a copper wiring formed on the amorphous silicon layer. And the copper wiring has a first copper alloy layer formed of an alloy containing copper as a main component and containing at least one element selected from lithium, palladium, and yttrium as a first additive element. This is a characteristic display device.

  Further, the first copper alloy layer is at least one element selected from aluminum, beryllium, hafnium, lithium, magnesium, manganese, silicon, scandium, titanium, zirconium, vanadium, and zinc, and is other than the first additive element. An element is included as the second additive element. Here, the first additive element may be at least one of lithium and yttrium.

  The display device of the present invention further includes a pure copper layer that is the copper wiring and is formed of pure copper on the first copper alloy layer, and the first copper alloy layer includes the amorphous silicon layer. The pure copper layer may be formed on the first copper alloy layer. Here, “pure copper” means that containing 99.90% or more of copper.

  The copper wiring includes a second copper alloy layer formed of an alloy containing copper as a main component on the amorphous silicon layer, and a pure copper layer formed of pure copper on the second copper alloy layer. In the case of a first copper alloy layer to which at least one of aluminum, beryllium, manganese, vanadium, and zinc is added as a second additive element, it may be formed on the pure copper layer.

  The display device manufacturing method of the present invention is a method for manufacturing a display device using a thin film transistor, and includes an amorphous silicon film forming step of forming a doped amorphous silicon film, and the doped amorphous silicon After the step of oxidizing the surface of the film, at least one element selected from lithium, palladium and yttrium is included as the first additive element, and further aluminum, beryllium, hafnium, lithium, magnesium, manganese, silicon, scandium, titanium, zirconium A copper alloy film for forming a copper alloy film formed of an alloy containing at least one element of vanadium and zinc and containing as a second additive element an element other than the first additive element A film forming step, a pure copper film forming step of forming a pure copper film formed of pure copper, the copper alloy film and the pure copper And a copper wiring forming step of forming a copper wiring, and a hydrogen plasma irradiation step of irradiating a hydrogen plasma after removing the doped amorphous silicon film at a portion where the copper wiring was not formed. It is a manufacturing method of the display apparatus provided.

1 is a diagram schematically showing a liquid crystal display device according to a first embodiment. It is a figure which shows the structure of the liquid crystal display panel of FIG. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 1st photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows a 1st photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 2nd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows a 2nd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 3rd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows a 3rd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 4th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows a 4th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 5th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows a 5th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows roughly the partial cross section of the liquid crystal panel using the TFT substrate of the liquid crystal display device which concerns on 1st Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 1st photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows a 1st photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 2nd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows a 2nd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 3rd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows a 3rd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 4th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows a 4th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 5th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows a 5th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows roughly the partial cross section of the liquid crystal panel using the TFT substrate of the liquid crystal display device which concerns on 2nd Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 1st photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows a 1st photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed by a 2nd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows a 2nd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed by the modification of a 2nd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows the modification of a 2nd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 3rd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows a 3rd photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows roughly the partial cross section of the TFT substrate formed of a 4th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows a 4th photolithography process among the manufacturing processes of the liquid crystal display device which concerns on 3rd Embodiment. It is a figure which shows roughly the partial cross section of the liquid crystal panel using the TFT substrate of the liquid crystal display device which concerns on 3rd Embodiment.

  In a thin film transistor manufacturing process, it is known to form a source / drain electrode and perform a hydrogen plasma treatment after etching a doped contact layer. Since copper is a material that easily diffuses hydrogen, it has the disadvantage that hydrogen plasma treatment causes hydrogen to penetrate to the vicinity of the interface with the contact layer, greatly reducing the adhesion between the contact layer and the source / drain electrodes. Yes.

  In the conventional example, the oxide of the additive element is formed at the interface with the underlying silicon oxide to ensure the adhesion, but the oxide layer is reduced by the hydrogen diffused by the hydrogen plasma treatment, and the adhesion is lowered. There is a possibility. Hereinafter, a display device using a thin film transistor in which the influence of hydrogen plasma is reduced will be described.

  First, the reason for determining the additive element of the copper alloy used for the wiring of the thin film transistor substrate according to the display device of the present invention will be described.

  As a requirement of the first additive element, there is a requirement that “the free energy of formation of hydride is negative”. This requirement is an important requirement for trapping hydrogen generated by the hydrogen plasma treatment as an additive element.

  As a further requirement, “the solid solubility limit in copper is greater than 0.1 atomic%”. This requirement is a requirement for the additive element not to precipitate in the alloy containing copper as a main component, but to be dissolved and uniformly dispersed in the copper alloy crystal.

  The requirements as the second additive element differ depending on the function fulfilled.

  The first requirement is that “the equilibrium oxygen potential of the oxidation reaction is lower than the equilibrium oxygen potential of the oxidation reaction of silicon”. This requirement is a requirement for the second additive element to oxidize by taking oxygen from the oxide film formed on the surface of the doped amorphous silicon film by oxidation treatment.

  The second requirement is that “the solid solubility limit in copper is greater than 0.1 atomic%”. This requirement is a requirement for the additive element to effectively contribute to the oxidation reaction at the interface without being precipitated in the alloy containing copper as a main component. Therefore, by satisfying the first requirement and the second requirement at the same time, when an oxygen-containing insulator (silicon oxide) or a pre-oxidized semiconductor layer contact layer is used as a base, an alloy containing copper as a main component and the base The oxide of the additive element can be deposited at the interface with the substrate. Alternatively, it is possible to impart affinity that expresses adhesiveness at the interface between the alloy containing copper as a main component and the base.

The third requirement is that “the diffusion constant in copper at 230 ° C. is smaller than 10 ⁻²¹ m ² / s”. This requirement is a requirement to prevent the additive element from diffusing into copper having a purity of 99.9% or higher, thereby preventing the resistivity of pure copper from increasing and obtaining a low-resistance video signal line. It becomes possible.

  By satisfying all of the above first to third requirements, the source electrode and the drain electrode can be formed on the contact layer of the preliminarily oxidized semiconductor layer, and a low-resistance video signal line can also be formed. .

  The fourth requirement is a requirement that “it is a metal element that forms a metal element oxide having a higher solubility in an etchant than copper oxide and has better corrosion resistance than copper”. The shape of the cross section of the wiring pattern is preferably a forward tapered shape. Copper with low resistivity needs to be further reduced in resistance with higher performance such as improvement of moving picture quality. In such a case, it is conceivable to increase the thickness of the pure copper layer. When the film thickness is increased, one of the problems is that the cross-sectional shape after etching tends to be vertical. When the cross-sectional shape is vertical, the coverage of the insulating film laminated on the upper layer is poor, and there is a possibility of inducing a defect such as an interlayer short circuit. Therefore, in order to make it easier to obtain a tapered shape, it is a requirement that a tapered shape can be easily obtained by adding a metal element having high oxide solubility and disposing it in an upper layer of pure copper.

  Examples of the additive element that satisfies the requirements of the first additive element in the present invention include at least one element among lithium, palladium, and yttrium. By adding one or more of the above elements to copper, it is possible to form hydrogen and hydride generated by hydrogen plasma treatment and prevent entry to the base.

  On the other hand, in the second additive element, as an element satisfying the first to third requirements, at least one of aluminum, beryllium, hafnium, lithium, magnesium, manganese, scandium, titanium, and zirconium can be cited.

  In addition, examples of the element that satisfies the fourth requirement include at least one of aluminum, beryllium, manganese, vanadium, and zinc.

  In the second additive element in the present invention, the element satisfying the first requirement to the third requirement is preferably disposed below the pure copper layer because it contributes to adhesion. In addition, in the case of an element that satisfies the fourth requirement, it is desirable that the element be disposed in the upper layer of the pure copper layer so that the taper shape of the copper wiring can be obtained more easily.

  The addition amount of the first additive element in the copper alloy is desirably larger than 0.1 atomic%. Furthermore, it is desirable that it is below the solid solubility limit in copper. Further, the content of the second additive element is desirably larger than 0.1 atomic%. Furthermore, it is desirable that it is below the solid solubility limit in copper. Here, the equilibrium oxygen potential of the oxidation reaction is defined by the left side or the right side of the following equation.

  In the above equation, R is a gas constant, T is an absolute temperature, p is an equilibrium oxygen partial pressure, n is a stoichiometric number of oxide oxygen, and ΔG is a free energy of formation of the oxide. The value of the free energy of formation of the oxide is described in databases such as “Ihsan Barin, THERMOCHEMICAL DATA OF PURE SUBSTANCES, VHC (1993)”.

  The solid solubility limit of the metal element in copper can be read from a binary alloy phase diagram described in, for example, “ASM HANDBOOK Volume 3, Alloy Phase Diagrams”.

Further, if the time of the thermal process is t, the diffusion distance is given as the square root of πDt. If the diffusion coefficient D is smaller than 10 ⁻²¹ (m ² / s), the time of the thermal process is estimated to be 30 minutes. The diffusion distance is about several nm. Therefore, the diffusion distance of the Cu alloy-added element into the upper layer Cu of the Cu / Cu alloy can be limited to a level that can be ignored with respect to the film thickness (from 100 nm). The value of the diffusion constant can be obtained by using the Arrhenius equation from the frequency factor and activation energy database described in “Metal Data Book” edited by the Japan Metallurgy Society.

  Hereinafter, first to third embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent elements are denoted by the same reference numerals, and redundant description is omitted. In the first to third embodiments, a method for manufacturing a TFT substrate of an in-plane switching type liquid crystal display device is described. In each embodiment, a partial cross-sectional view and a process diagram are shown for each photolithography process, and the partial cross-sectional view shows a stage where the photoresist is removed. In the following description, resist pattern formation refers to a series of steps from application of a photoresist to selective exposure using a mask until development and baking, and repeated description is avoided.

[First Embodiment]
FIG. 1 is a diagram schematically showing a liquid crystal display device 10 according to an embodiment of the liquid crystal display device of the present invention. As shown in this figure, the liquid crystal display device 10 includes a liquid crystal panel 20 fixed so as to be sandwiched between an upper frame 11 and a lower frame 12, a backlight device (not shown), and the like.

  FIG. 2 shows the configuration of the liquid crystal panel 20 of FIG. The liquid crystal panel 20 has two substrates, a TFT substrate 100 and a color filter substrate 21 manufactured by the manufacturing method of the first embodiment, and a liquid crystal composition is sealed between these substrates. A gate signal line 24 controlled by the drive circuit 22 and a drain signal line 25 controlled by the drive circuit 23 are stretched over the TFT substrate 100, and these signal lines function as one pixel of the liquid crystal display device 10. A cell 26 is formed. The liquid crystal panel 20 has the number of cells 26 corresponding to the display resolution, but is simplified in FIG. 2 so as not to complicate the figure.

  FIG. 3 schematically shows a cross section of the TFT substrate 100 formed by the first photolithography process 171 in the manufacturing process of the TFT substrate 100. FIG. 4 shows a first photolithography step 171. As shown in these drawings, in the first photolithography step 171, first, a transparent conductive film 102 made of indium tin oxide is formed on a glass substrate 101 made of alkali-free glass by sputtering (step S 111). Here, the transparent conductive film 102 may be indium zinc oxide or indium tin zinc oxide. The film thickness is about 10 nm to 150 nm, and preferably about 20 nm to 50 nm. Subsequently, a Cu / CuX alloy 103 is formed by magnetron sputtering (step S111). The film thickness of the Cu / CuX alloy 103 is preferably about 200 nm to 400 nm for Cu, and 10 nm to 100 nm for the CuX alloy. In this example, the CuX alloy X was made of manganese. Other aluminum or magnesium may be used.

  Next, a resist pattern is formed using a half exposure mask (step S112). Here, the resist is formed thick without exposing the portions constituting the scanning signal line and the common signal line, and the resist is formed thinly as the half exposure for the portion where the common (transparent) electrode is formed. Thereafter, the Cu / CuX alloy 103 is selectively etched away (step S113), and then the transparent conductive film is selectively etched away (step S114). Next, the resist in the half exposure portion is removed by ashing (step S115). After ashing, the Cu / CuX alloy 103 in the half-exposure part is selectively removed by etching (step S116), and the resist is peeled off (step S117).

  FIG. 5 schematically shows a cross section of the TFT substrate 100 formed by the second photolithography process 172 in the manufacturing process of the TFT substrate 100. FIG. 6 shows a second photolithography step 172. As shown in these drawings, in the second photolithography step 172, first, a gate insulating film 104 made of silicon nitride, a semiconductor layer 105 made of amorphous silicon, and doped amorphous silicon (n + type). The contact layer 106 made of is continuously formed by plasma chemical vapor deposition (step S121), and the surface of the contact layer is pre-oxidized by oxygen plasma (step S122).

  After the resist pattern is formed using the binary exposure mask (step S123), the contact layer 106 and the semiconductor layer 105 are selectively removed by etching (step S124). When the resist is removed, a so-called island pattern is formed (step S125). . Through the above steps, scanning signal lines (including gate electrodes and scanning signal line terminals), common signal lines (including common signal line terminals), and common (transparent) electrodes are formed.

  FIG. 7 schematically shows a cross section of the TFT substrate 100 formed by the third photolithography process 173 in the manufacturing process of the TFT substrate 100. FIG. 8 shows a third photolithography step 173. As shown in these drawings, in the third photolithography step 173, first, from an alloy containing copper as a main component to which 5 atomic% of lithium is added as a first additive element and 5 atomic% of manganese is added as a second additive element. A copper alloy layer 107A and a pure copper layer 107B made of 99.99% pure copper are continuously formed by magnetron sputtering (step S131). The thickness of the copper alloy layer 107A made of an alloy containing copper as a main component is about 10 nm to 100 nm, and preferably about 20 nm to 50 nm. The thickness of the pure copper layer 107B is about 100 nm to 1000 nm, preferably about 200 nm to 500 nm.

  Of the additive elements of the copper alloy, first, the first additive element is preferably palladium or yttrium in addition to lithium in this embodiment. Among them, yttrium is particularly good.

  As the second additive element, aluminum, beryllium, hafnium, lithium, magnesium, scandium, titanium, and zirconium are suitable in addition to the manganese of this embodiment.

  After forming a resist pattern using a binary exposure mask (step S132), the pure copper layer and the copper alloy layer are selectively removed by etching (step S133), the contact layer is selectively removed by etching (step S134), and the resist is peeled off. Then (step S135), a drain electrode (including a video signal line and a video signal line terminal) and a source electrode are formed.

  Here, hydrogen plasma treatment is performed for the purpose of improving the characteristics such as reducing the leakage current of the TFT substrate and increasing the mobility. This is a method of terminating dangling bonds in silicon by hydrogenation with hydrogen. The substrate subjected to the above-described process was subjected to hydrogen plasma treatment using a plasma CVD apparatus. The substrate temperature was 100 ° C. and the processing time was 120 seconds.

  When the wiring pattern after the hydrogen plasma treatment was observed, it was confirmed that the copper wiring on the contact layer had no defects such as peeling and had good adhesion. Moreover, when hydrogen plasma processing was performed at 230 degreeC higher than 100 degreeC, it confirmed that it had favorable adhesiveness.

  FIG. 9 schematically shows a cross section of the TFT substrate 100 formed by the fourth photolithography process 174 in the manufacturing process of the TFT substrate 100. FIG. 10 shows a fourth photolithography step 174. As shown in these drawings, in the fourth photolithography step 174, first, a protective insulating film 108 made of silicon nitride is formed by plasma chemical vapor deposition (step S141). The deposition temperature of the protective insulating film 108 is about 230 ° C. At this time, an additive element of the copper alloy layer 107A is formed at the interface between the pre-oxidized contact layer 106 and the copper alloy layer 107A formed in the third photolithography step 173. Oxidation reaction of manganese occurs, and a thin manganese oxide layer 110 is formed. The manganese oxide of the oxide layer 110 serves as a barrier layer that blocks diffusion of the pure copper layer 107B and the copper alloy layer 107A into the copper contact layer 106 and the semiconductor layer 105 and silicon from the contact layer 106, or an adhesion layer. Function as. In this embodiment, the oxide layer is formed when the protective insulating film is formed. However, the oxide layer may be formed by performing heat treatment or the like in advance before the hydrogen plasma treatment.

  Here, the oxide layer thickness of the additive element of the copper alloy layer 107A is 0.5 nm to 5 nm, preferably about 1 nm to 2 nm.

  After forming a resist pattern using a binary exposure mask (step S142), a through hole 109 is opened in the protective insulating film on the source electrode, and at the same time, a through hole (not shown) is formed in the protective insulating film on the video signal line terminal (not shown). At the same time, a through hole (not shown) is opened in the protective insulating film and the gate insulating film on the scanning signal line terminal (not shown) (step S143), and the resist is peeled off (step S144).

  FIG. 11 schematically shows a cross section of the TFT substrate 100 formed by the fifth photolithography process 175 in the manufacturing process of the TFT substrate 100. FIG. 12 shows a fifth photolithography step 175. As shown in these drawings, in the fifth photolithography step 175, first, a transparent conductive film 111 made of indium tin oxide is formed by sputtering (step S151). First, after forming a resist pattern using a binary exposure mask (step S152), the transparent conductive film 111 is selectively etched away except for the pixel electrode, the scanning signal line terminal, the common signal line terminal, and the video signal line terminal ( Step S153), the resist is peeled off (Step S154). Through the above steps, the TFT substrate 100 of the liquid crystal display device is completed.

  FIG. 13 schematically shows a partial cross section of a liquid crystal panel 150 using the TFT substrate 100 of the liquid crystal display device manufactured by the above process. The liquid crystal panel includes the TFT substrate 100 manufactured by the first photolithography process 171 to the fifth photolithography process 175 described above, the liquid crystal 120, and the color filter substrate 21. As shown in this figure, the drain line, the source electrode, and the common electrode which are video signal lines of the TFT substrate 100 are wired with copper.

  As described above, according to the present embodiment, even in the hydrogen plasma treatment, the oxide layer 110 is suppressed from being reduced due to the presence of the copper alloy layer 107A, and the adhesion between the copper wiring and the contact layer 106 is suppressed. Can keep.

  Further, since the TFT substrate 100 is wired with pure copper, the power consumption of the TFT substrate 100 can be reduced.

[Second Embodiment]
A TFT substrate 200 of a liquid crystal display device according to a second embodiment of the present invention will be described. The configuration of the liquid crystal display device in which the TFT substrate 200 is used is the same as the configuration of the liquid crystal display device 10 of FIG. 1 and the liquid crystal panel 20 of FIG. 2 in the first embodiment. Is omitted.

  FIG. 14 schematically shows a cross section of the TFT substrate 200 formed by the first photolithography process 271 in the manufacturing process of the TFT substrate 200. FIG. 15 shows a first photolithography step 271. As shown in these drawings, in the first photolithography step 271, first, a transparent conductive film 202 made of indium tin oxide is formed on a glass substrate 201 made of alkali-free glass by sputtering (step S211). Here, the transparent conductive film 202 may be indium zinc oxide or indium tin zinc oxide. The film thickness is about 10 nm to 150 nm, and preferably about 20 nm to 50 nm. Subsequently, a Cu / CuX alloy 203 is formed by magnetron sputtering (step S211). The film thickness of the Cu / CuX alloy 203 is preferably about 200 nm to 400 nm for Cu, and 10 nm to 100 nm for the CuX alloy. In this example, the CuX alloy X was made of manganese. Other aluminum or magnesium may be used.

  Next, a resist pattern is formed using a half exposure mask (step S212). Here, the resist is formed thick without exposing the portions constituting the scanning signal line and the common signal line, and the resist is formed thinly as the half exposure for the portion where the common (transparent) electrode is formed. Thereafter, the Cu / CuX alloy 203 is selectively removed by etching (step S213), and then the transparent conductive film 202 is selectively removed by etching (step S214). Next, the resist in the half exposure portion is removed by ashing (step S215). After ashing, CuX in the half-exposure portion is selectively removed by etching (step S216), and the resist is peeled off (step S217).

  FIG. 16 schematically shows a cross section of the TFT substrate 200 formed by the second photolithography process 272 in the manufacturing process of the TFT substrate 200. FIG. 17 shows a second photolithography step 272. As shown in these drawings, in the second photolithography step 272, first, a gate insulating film 204 made of silicon nitride, a semiconductor layer 205 made of amorphous silicon, and doped amorphous silicon (n + type). The contact layer 206 made of is continuously formed by plasma chemical vapor deposition (step S221), and the surface of the contact layer 206 is pre-oxidized by oxygen plasma (step S222).

  After the resist pattern is formed using the binary exposure mask (step S223), the contact layer 206 and the semiconductor layer 205 are selectively removed by etching (step S224), and the resist is peeled off (step S225) to form a so-called island pattern. . Through the above steps, scanning signal lines (including gate electrodes and scanning signal line terminals), common signal lines (including common signal line terminals), and common (transparent) electrodes are formed.

  FIG. 18 schematically shows a cross section of the TFT substrate 200 formed by the third photolithography process 273 in the manufacturing process of the TFT substrate 200. FIG. 19 shows a third photolithography step 273. As shown in these drawings, in the third photolithography step 273, first, a CuMn alloy layer 207A is formed as a first layer with a thickness of 40 nm, and then a pure copper layer 207B made of 99.99% purity pure copper is formed with a thickness of 600 nm. Further, a copper alloy layer 207C made of an alloy containing copper as a main component and containing 3 atomic% of yttrium as the first additive element and 5 atomic% of aluminum as the second additive element is continuously formed by 60 nm magnetron sputtering (step) S231). The film thickness of the copper alloy layer 207C made of an alloy containing copper as a main component is about 10 nm to 100 nm, and preferably about 20 nm to 60 nm. The thickness of the pure copper layer 207B is about 100 nm to 1000 nm, preferably about 200 nm to 600 nm.

  Of the additive elements of the copper alloy of the copper alloy layer 207C, first, the first additive element is preferably lithium or palladium in addition to yttrium in this embodiment. Of these, lithium is particularly good.

  The second additive element is preferably beryllium, manganese, vanadium, or zinc in addition to the aluminum of this embodiment.

  After the resist pattern is formed using the binary exposure mask (step S232), the copper alloy layer 207C, the pure copper layer 207B, and the CuMn alloy layer 207A are selectively etched away (step S233), and the contact layer 206 is selectively etched away. (Step S234) When the resist is removed (Step S235), a drain electrode (including a video signal line and a video signal line terminal) and a source electrode are formed.

  As a result of observing the shape of the side surfaces of the drain electrode and the source electrode after etching, it was confirmed that the thick copper (600 nm) pure copper layer 207B has a forward taper shape.

  Here, hydrogen plasma treatment is performed for the purpose of improving characteristics such as reduction of leakage current of TFT substrate 200 and increase of mobility. This is a method of terminating dangling bonds in silicon by hydrogenation with hydrogen. The substrate subjected to the above-described process was subjected to hydrogen plasma treatment using a plasma CVD apparatus. The substrate temperature was 100 ° C. and the processing time was 120 seconds.

  When the wiring pattern after the hydrogen plasma treatment was observed, it was confirmed that the copper wiring on the contact layer 206 had no defects such as peeling and had good adhesion. Moreover, when hydrogen plasma processing was performed at 230 degreeC higher than 100 degreeC, it confirmed that it had favorable adhesiveness.

  FIG. 20 schematically shows a cross section of the TFT substrate 200 formed by the fourth photolithography process 274 in the manufacturing process of the TFT substrate 200. FIG. 21 shows a fourth photolithography step 274. As shown in these drawings, in the fourth photolithography step 274, first, a protective insulating film 208 made of silicon nitride is formed by plasma chemical vapor deposition (step S241). The deposition temperature of the protective insulating film 208 is about 230 ° C. At this time, an oxidation reaction of the additive element occurs at the interface between the pre-oxidized contact layer 206 formed in the third photolithography step 273 and the CuMn alloy layer 207A. As a result, an oxide layer 210 of a thin additive element oxide is formed. This oxide functions as a barrier layer that blocks diffusion of the pure copper layer 207B and the copper alloy layer 207C into the copper contact layer 206 and the semiconductor layer 205 and silicon from the contact layer 206, or as an adhesion layer.

  Here, the oxide layer thickness of the additive element of the copper alloy layer is 0.5 nm to 5 nm, and preferably about 1 nm to 2 nm.

  After forming a resist pattern using a binary exposure mask (step S242), a through hole is opened in the protective insulating film on the source electrode, and at the same time, a through hole (not shown) is formed in the protective insulating film on the video signal line terminal (not shown). At the same time, a through hole (not shown) is opened in the protective insulating film and the gate insulating film on the scanning signal line terminal (not shown) (step S243), and the resist is peeled off (step S244).

  FIG. 22 schematically shows a cross section of the TFT substrate 200 formed by the fifth photolithography process 275 in the manufacturing process of the TFT substrate 200. FIG. 23 shows a fifth photolithography step 275. As shown in these drawings, in the fifth photolithography step 275, first, a transparent conductive film 211 made of indium tin oxide is formed by sputtering (step S251). First, after forming a resist pattern with a binary exposure mask (step S252), the transparent conductive film is selectively etched away except for the pixel electrode, the scanning signal line terminal, the common signal line terminal, and the video signal line terminal (step S252). S253), the resist is peeled off (step S254). The TFT substrate 200 of the liquid crystal display device is completed through the above steps.

  FIG. 24 schematically shows a partial cross section of a liquid crystal panel 250 using the TFT substrate 200 of the liquid crystal display device manufactured by the above process. The liquid crystal panel 250 includes the TFT substrate 200 manufactured by the first photolithography process 271 to the fifth photolithography process 275 described above, the liquid crystal 213, and the color filter substrate 21. As shown in this figure, the drain line, the source electrode, and the common electrode which are video signal lines of the TFT substrate 200 are wired with copper.

  As described above, according to the present embodiment, even in the hydrogen plasma treatment, the oxide layer 210 is suppressed from being reduced due to the presence of the copper alloy layer 207C, and the adhesion between the copper wiring and the contact layer 206 is suppressed. Can keep.

  Further, according to the present embodiment, a good taper shape can be obtained even in the pure copper layer 207B that is thickened by the presence of the copper alloy layer 207C.

  Further, since the TFT substrate 200 is wired with pure copper, the power consumption of the TFT substrate 200 can be reduced.

[Third Embodiment]
A TFT substrate 300 of a liquid crystal display device according to a third embodiment of the present invention will be described. The configuration of the liquid crystal display device using the TFT substrate 300 is the same as the configuration of the liquid crystal display device 10 of FIG. 1 and the liquid crystal panel 20 of FIG. 2 in the first embodiment. Is omitted.

  In the first embodiment, five times of photolithography are used, but in this embodiment, four times of photolithography are used. As in the first embodiment, in each of FIGS. 25 to 34, FIGS. 25, 27, 29, 31 and 33 are the thin film transistor portions, and FIGS. 26, 28, 30, 32 and 32. Reference numeral 34 denotes a process flow. 29 and 30 show a process for substituting the processes of FIGS. 27 and 28. The following explanation is based on the divided steps.

  FIG. 25 schematically shows a cross section of the TFT substrate 300 formed by the first photolithography process 371 in the manufacturing process of the TFT substrate 300. FIG. 26 shows a first photolithography step 371. As shown in these drawings, first, a transparent conductive film 302 made of indium tin oxide is formed on a substrate 301 made of alkali-free glass by sputtering. Here, the transparent conductive film may be either indium zinc oxide or indium tin zinc oxide. The film thickness is about 10 nm to 150 nm, and about 50 nm is preferable. Subsequently, as in the first embodiment, a Cu / CuX alloy 303 is continuously formed by magnetron sputtering (step S311).

  Next, a resist pattern is formed by photolithography using a half exposure mask (step S312). Here, a thick resist is formed on the portions constituting the scanning signal line and the common signal line without exposure, and a thin resist is formed on the portion where the common (transparent) electrode is formed as half exposure. After photolithography, the Cu / CuX alloy 303 is etched (step S313), and then the transparent conductive film 302 is etched (step S314). Here, the resist in the half exposure portion is removed by ashing (step S315). After ashing, the Cu / CuX alloy 303 in the half-exposure portion is etched, and then the resist is peeled off (step S317).

  Through the above steps, scanning signal lines (including gate electrodes and scanning signal line terminals), common signal lines (including common signal line terminals), and common (transparent) electrodes are formed.

  FIG. 27 schematically shows a cross section of the TFT substrate 300 formed by the second photolithography process 372a in the manufacturing process of the TFT substrate 300. FIG. 28 shows a second photolithography step 372a. As shown in these drawings, first, plasma chemistry is performed on a gate insulating film 304 made of silicon nitride, a semiconductor layer 305 made of amorphous silicon, and a contact layer 306 made of doped amorphous silicon (n + type). Films are continuously formed by vapor deposition (step S321a), and the surface of the contact layer 306 is pre-oxidized with oxygen plasma (step S322a).

  Subsequently, a first alloy layer 307A containing 4 atomic% of yttrium and 3 atomic% of manganese and containing copper as a main component and a pure copper layer 307B of 99.99% purity are continuously formed by magnetron sputtering (step S323a). ). The film thickness of the first alloy layer 307A is about 10 nm to 100 nm, and preferably about 20 nm to 50 nm. The film thickness of pure copper is about 100 nm to 1000 nm, preferably about 200 nm to 500 nm.

  Next, a resist pattern is formed by photolithography using a half exposure mask (step S324a). Here, the drain electrode (including the video signal line and the video signal line terminal) and the portion constituting the source electrode are not exposed and the resist is formed thick, and the portion of the semiconductor layer 305 where the island pattern is formed is half exposed. The resist is formed thinly. After photolithography, the pure copper layer 307B and the first alloy layer 307A are etched (step S325a), and then the doped amorphous silicon (n + type) layer 306 and the semiconductor layer 305 are etched (step S326a). Here, the resist in the half exposure portion is removed by ashing (step S327a). After the ashing, the pure copper / first alloy layer laminated film in the half-exposed portion is etched (step S328a), and then the doped amorphous silicon (n + type) layer 306 is etched to separate the channel of the thin film transistor. (Step S329a), the resist is removed (Step S330a). Through the above steps, the drain electrode (including the video signal line and the video signal line terminal), the source electrode, and the island pattern of the semiconductor layer 305 are formed.

  29 and 30 show a second photolithography step 372b that is a modification of the second photolithography step 372a shown in FIGS. As shown in these drawings, first, a gate insulating film 304 made of silicon nitride, a semiconductor layer 305 made of amorphous silicon, and a doped amorphous silicon (n + type) layer 306 are formed by plasma chemical vapor deposition. Films are continuously formed (step S321b), and the surface of the contact layer 306 is pre-oxidized with oxygen plasma (step S322b). Subsequently, the first alloy layer 307A and the pure copper layer 307B are continuously formed (step S323b).

  Next, a resist pattern is formed by photolithography using a half exposure mask (step S324b). Here, the resist pattern is formed in a portion constituting a drain electrode (including a video signal line and a video signal line terminal) and a source electrode, and a resist is formed thickly around the channel of the thin film transistor without being exposed, In other parts, a resist is thinly formed as half exposure. After photolithography, the stacked film of the first alloy layer 307A and the pure copper layer 307B is etched to form a drain electrode (including a video signal line and a video signal line terminal) and a source electrode, and amorphous silicon (n + type) ) The channel of the thin film transistor is separated by etching the layer 306 (step S325b).

  Subsequently, the resist in the half exposure portion is removed by ashing (step S326b). In addition, the resist removal process of this half exposure part is omissible. Subsequently, the remaining resist is reflowed to fill the channel portion of the thin film transistor with the resist (step S327b). Subsequently, the semiconductor layer 305 is etched (step S328b), and the resist pattern is removed to form an island pattern of the semiconductor layer 305 (step S329b).

  Here, hydrogen plasma treatment was performed as in the first embodiment. As a result of observing the channel portion after the hydrogen plasma treatment, no peeling of the copper wiring was observed.

  FIG. 31 schematically shows a cross section of the TFT substrate 300 formed by the third photolithography process 373 in the manufacturing process of the TFT substrate 300. FIG. 32 shows a third photolithography step 373. As shown in these drawings, first, a protective insulating film 308 made of silicon nitride is formed by plasma chemical vapor deposition (step S331). The film forming temperature is about 230 ° C. At this time, the oxidation of the additive element is performed at the interface between the contact layer 306 that has been pre-oxidized (step S322a) formed in the second photolithography step 372a and the first alloy layer 307A containing yttrium-manganese and containing copper as a main component. Reaction occurs, and an oxide layer 310 of a thin additive element oxide (manganese oxide in this embodiment) is generated. This oxide layer functions as a barrier layer that blocks diffusion of the pure copper layer 307B and the first alloy layer 307A into the copper contact layer 306 and the semiconductor layer 305, or as an adhesion layer. After photolithography using a binary exposure mask (step S332), a through hole 309 is opened in the protective insulating film 308 on the source electrode and the video signal line terminal (not shown), and at the same time, a scanning signal line terminal (not shown). A through hole 309 is opened in the upper protective insulating film 308 and the gate insulating film 304 (step S333), and the resist is removed (step S334).

  FIG. 33 schematically shows a cross section of the TFT substrate 300 formed by the fourth photolithography step 374 in the manufacturing process of the TFT substrate 300. FIG. 34 shows a fourth photolithography step 374. As shown in these drawings, a transparent conductive film 311 made of indium tin oxide is formed by sputtering (step S341). First, after photolithography using a binary exposure mask (step S342), the pixel electrode 311, the scanning signal line terminal (not shown), the common signal line terminal (not shown), and the video signal line terminal (not shown) are patterned. Is etched (step S343), and the resist is removed (step S344). The TFT substrate 300 of the liquid crystal display device can be manufactured even if photolithography is performed four times through the above steps.

  FIG. 35 schematically shows a partial cross section of a liquid crystal panel 350 using the TFT substrate 300 of the liquid crystal display device manufactured by the above process. As shown in this figure, the drain line, the source electrode and the common electrode which are video signal lines of the TFT substrate 300 are wired with copper.

  In the first to third embodiments, a TFT substrate of an IPS (In Plane Switching) type liquid crystal display device is used. Of the TN (Twisted Nematic) type and VA (Vertical Alignment) type Either type of TFT substrate may be used.

  In the first embodiment and the third embodiment, the copper alloy layer 107A and the copper alloy layer 307A are arranged in the lower layer of the copper wiring. In the second embodiment, the copper alloy layer 207C is arranged in the upper layer of the copper wiring. did. Depending on the requirements of the additive element, the copper alloy layer is disposed on the upper layer and the lower layer of the pure copper layer.

  In the above embodiment, the liquid crystal display device is used. However, the copper wiring on the amorphous silicon film formed on the glass substrate such as the TFT substrate of the organic EL display device using the self-luminous element, It may be a copper wiring on an amorphous silicon film formed on another substrate.

  10 liquid crystal display device, 11 upper frame, 12 lower frame, 20 liquid crystal panel, 21 color filter substrate, 22 drive circuit, 23 drive circuit, 24 gate signal line, 25 drain signal line, 26 cell, 100 TFT substrate, 101 glass substrate , 102 transparent conductive film, 103 copper / copper alloy, 104 gate insulating film, 105 semiconductor layer, 106 contact layer, 107A copper alloy layer, 107B pure copper layer, 108 protective insulating film, 109 through hole, 110 oxide layer, 111 transparent Conductive film, 120 liquid crystal, 150 liquid crystal panel, 200 TFT substrate, 201 glass substrate, 202 transparent conductive film, 203 copper / copper alloy, 204 gate insulating film, 205 semiconductor layer, 206 contact layer, 207A copper alloy layer, 207B pure copper layer 207C Copper alloy layer 208 Insulating film, 210 oxide layer, 211 transparent conductive film, 213 liquid crystal, 250 liquid crystal panel, 300 TFT substrate, 301 glass substrate, 302 transparent conductive film, 303 pure copper / copper alloy, 304 gate insulating film, 305 semiconductor layer, 306 contact Layer, 307A copper alloy layer, 307B pure copper layer, 308 protective insulating film, 309 through hole, 310 oxide layer, 311 transparent conductive film, 350 liquid crystal panel, 313 liquid crystal.

Claims (4)

A display device using a thin film transistor,
The thin film transistor
An amorphous silicon layer formed by an amorphous silicon film;
A copper wiring formed on the amorphous silicon layer,
The copper wiring includes at least one element selected from lithium, palladium and yttrium as a first additive element, and further includes aluminum, beryllium, hafnium, lithium, magnesium, manganese, silicon, scandium, titanium, zirconium, vanadium and zinc. It has a first copper alloy layer formed of an alloy containing copper as a main component, which is at least one kind of element and includes an element other than the first additive element as a second additive element. Display device. The copper wiring further includes a pure copper layer formed of pure copper on the first copper alloy layer,
The first copper alloy layer is formed on the amorphous silicon layer;
The display device according to claim 1, wherein the pure copper layer is formed on the first copper alloy layer. The copper wiring is
A second copper alloy layer formed of an alloy containing copper as a main component on the amorphous silicon layer;
A pure copper layer formed of pure copper on the second copper alloy layer;
Further comprising
The first copper alloy layer is formed on the pure copper layer,
The display device according to claim 1, wherein the second additive element of the first copper alloy layer is at least one element selected from aluminum, beryllium, manganese, vanadium, and zinc. A method of manufacturing a display device using a thin film transistor,
An amorphous silicon film forming step of forming a doped amorphous silicon film;
After the step of oxidizing the surface of the doped amorphous silicon film, at least one element selected from lithium, palladium, and yttrium is included as a first additive element, and aluminum, beryllium, hafnium, lithium, magnesium, manganese, A copper alloy film formed of an alloy containing, as a main component, copper, which is at least one element of silicon, scandium, titanium, zirconium, vanadium, and zinc and contains an element other than the first additive element as a second additive element A copper alloy film forming step of forming a film;
A pure copper film forming step of forming a pure copper film formed of pure copper after the copper alloy film forming step;
Etching the copper alloy film and the pure copper film to form a copper wiring, and a copper wiring forming step,
A hydrogen plasma irradiation step of irradiating the copper wiring with hydrogen plasma after the step of removing the doped amorphous silicon film at the location where the copper wiring is not formed.

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