JP2011114330A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having higher flexibility, in the selection of a bottom electrode material of a ferroelectric capacitor and having less via-processing, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device includes switching transistors 301A and 301B formed on a substrate 101; a diffusion layer 121; an interlayer insulating film 131 formed on the transistor 301; ferroelectric capacitors 201A and 201B including a bottom electrode 211, a ferroelectric film 212 and a top electrode 213; a wiring layer 141, formed above the top electrode 213; a first plug TW that conducts electricity between the top electrode 213 and the wiring layer 141; second plugs V1A and V1B that conduct electricity between the diffusion layer 121 and the wiring layer 141; and a third plug CSF; disposed to the side of the bottom electrode 211 for making electrical continuity established between the bottom electrode 211 and the diffusion layer 121. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and is applied to, for example, a ferroelectric memory device (FeRAM) having a ferroelectric capacitor.

  Currently, application of FeRAM devices to RFID, microcomputers, and the like is progressing, and further performance improvement and cost reduction are desired.

  As an example of FeRAM, Chain type FeRAM which has a TC (Transistor Capacitor) parallel unit serial connection type structure is mentioned. In Chain-type FeRAM, memory cells including capacitors and transistors connected in parallel are connected in series with each other to form a Chain unit.

  In the Chain type FeRAM, for example, a COP (Capacitor On Plug) structure is adopted, and a capacitor is disposed on a W (tungsten) plug. At this time, in order to suppress oxidation of the W plug, an Ir (iridium) layer and a barrier metal layer (TiAlN, TiN, WN, etc.) having a thickness of 100 nm or more are required as the lower electrode material of the capacitor. There are many restrictions.

  Further, when the FeRAM structure is formed by a conventional method, four via processes (CS, CSM, V1, TW) are required before the M1 wiring process. Here, TW constitutes a plug that conducts the upper electrode of the capacitor and the wiring layer, and CS and CSM constitute a plug that conducts the lower electrode of the capacitor and the diffusion layer, and the wiring layer and the diffusion layer V1 constitutes the upper part of the plug that conducts the wiring layer and the diffusion layer. In the conventional method, an increase in cost and a decrease in yield due to as many as four via processes are problematic.

  Patent Document 1 describes an example of a semiconductor memory device corresponding to a chain type FeRAM.

JP 2001-319472 A

  It is an object of the present invention to provide a semiconductor device having a high degree of freedom in selecting a lower electrode material for a ferroelectric capacitor and having a small number of via processes, and a method for manufacturing the same.

  One aspect of the present invention is, for example, a switching transistor formed on a substrate, first and second diffusion layers formed so as to sandwich the transistor in the substrate, and interlayer insulation formed on the transistor. A ferroelectric capacitor including a film, a lower electrode, a ferroelectric film, and an upper electrode sequentially formed on the interlayer insulating film; a wiring layer formed above the upper electrode; and the upper electrode A first plug formed and electrically connected between the upper electrode and the wiring layer; and formed on the first diffusion layer and electrically connected between the first diffusion layer and the wiring layer. A second plug that is formed on the second diffusion layer and disposed on a side of the lower electrode, and electrically connects the lower electrode and the second diffusion layer. Semiconductor characterized by comprising a plug It is a device.

  Another aspect of the present invention is, for example, a switching transistor formed on a substrate, first and second diffusion layers formed so as to sandwich the transistor in the substrate, and interlayer insulation formed on the transistor. A ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode sequentially formed on the interlayer insulating film; a first wiring layer formed above the upper electrode; and the lower part A second wiring layer formed between an electrode and the transistor; a first plug formed on the upper electrode and electrically conducting the upper electrode and the first wiring layer; A second plug formed on the first diffusion layer and electrically connecting the first diffusion layer and the second wiring layer; and formed on the second diffusion layer; and the lower electrode Arranged on the side of the lower electrode A semiconductor device characterized by comprising a third plug for electrically connecting and said second diffusion layer.

  In another aspect of the present invention, for example, a switching transistor is formed on a substrate, first and second diffusion layers are formed so as to sandwich the transistor in the substrate, an interlayer insulating film is formed on the transistor, A lower electrode, a ferroelectric film, and an upper electrode are sequentially formed on the interlayer insulating film to form a ferroelectric capacitor including the lower electrode, the ferroelectric film, and the upper electrode, and the upper electrode A first plug is formed on the first diffusion layer, a second plug is formed on the first diffusion layer, and the lower electrode and the second plug are formed on a side of the lower electrode on the second diffusion layer. 3. A semiconductor device comprising: a third plug electrically connected to the diffusion layer; and a wiring layer electrically connected to the first and second plugs formed above the upper electrode. It is a manufacturing method.

  According to the present invention, it is possible to provide a semiconductor device having a high degree of freedom in selecting a lower electrode material of a ferroelectric capacitor and having a small number of via processes, and a manufacturing method thereof.

It is the top view and side sectional view showing the composition of the semiconductor device of a 1st embodiment. It is the top view and side sectional view which show the structure of the semiconductor device of a comparative example. 2 is a circuit diagram and a graph for explaining the operation of the semiconductor device of FIG. FIG. 2 is a side sectional view showing a configuration of a Chain unit in the semiconductor device of FIG. 1. FIG. 6 is a side cross-sectional view (1/2) illustrating the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a side cross-sectional view (2/2) illustrating the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a plan view and a side cross-sectional view showing a modification of the configuration of the semiconductor device of FIG. 1. It is a sectional side view (1/2) which shows the manufacturing method of the semiconductor device of a comparative example. FIG. 4 is a side cross-sectional view (2/2) illustrating the method for manufacturing the semiconductor device of the comparative example. It is the top view and side sectional view showing the composition of the semiconductor device of a 2nd embodiment. It is a sectional side view (1/2) which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a side sectional view (2/2) showing a manufacturing method of a semiconductor device of a 2nd embodiment. It is the top view and side sectional view showing the composition of the semiconductor device of a 3rd embodiment. It is the top view and side sectional view which show the structure of the semiconductor device of 4th Embodiment. It is the top view and side sectional view showing the composition of the semiconductor device of a 5th embodiment.

  Embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1A and 1B are a plan view and a side sectional view showing the configuration of the semiconductor device of the first embodiment. 1A corresponds to a plan view of the semiconductor device, and FIGS. 1B and 1C are side views taken along lines XX ′ and YY ′ shown in FIG. 1A, respectively. It corresponds to a sectional view.

  FIG. 1A shows an STI (Shallow Trench Isolation) layer 111 and a diffusion layer 121 formed on the substrate 101. FIG. 1A further shows a ferroelectric capacitor 201 (201A to 201D) and a gate conductive film GC constituting a switching transistor 301 described later.

  The semiconductor device of this embodiment is a ferroelectric memory device (FeRAM) including a memory cell composed of the ferroelectric capacitor 201 and the switching transistor 301. FIG. 1A also shows various plugs TW, V1, and CSF.

  FIG. 1B shows capacitors 201A and 201B shown in FIG. 1A and transistors 301A and B that constitute memory cells together with the capacitors 201A and 201B. On the other hand, FIG. 1C shows capacitors 201A and C shown in FIG. 1A and transistors 301A and C that constitute memory cells together with the capacitors 201A and C. 1B and 1C, subscripts A to C are added to reference numerals of components corresponding to the capacitors 201A to 201C and the transistors 301A to 301C.

  Hereinafter, the structure of each memory cell will be described with reference to FIG. 1B and the capacitor 201A and the transistor 301A as examples. However, the following description also applies to other ferroelectric capacitors 201 and switching transistors 301 in the semiconductor device of this embodiment, such as capacitors 201B and C and transistors 301B and 301C. In the following description, FIGS. 1A and 1C are referred to as appropriate in addition to FIG.

  In FIG. 1B, a transistor 301A formed over the substrate 101 is illustrated. The transistor 301A includes a gate insulating film 311A and a gate electrode 312A which are sequentially formed over the substrate 101. In the present embodiment, the substrate 101 is a semiconductor substrate, for example, a silicon substrate. The gate insulating film 311A is, for example, a silicon oxide film, and the gate electrode 312A is, for example, a polysilicon layer.

FIG. 1B further shows diffusion layers 121 ₁ and 121 ₂ formed in the substrate 101 so as to sandwich the transistor 301A. One of the diffusion layers 121 ₁ and 121 ₂ functions as a source diffusion layer, and the other functions as a drain diffusion layer. The diffusion layers 121 ₁ and 121 ₂ are examples of the first and second diffusion layers of the present invention, respectively.

FIG. 1B further shows a diffusion layer 121 ₃ formed in the substrate 101. The transistor 301A is sandwiched between the diffusion layers 121 ₁ and 121 ₂ , and the transistor 301B is sandwiched between the diffusion layers 121 ₂ and 121 ₃ . Thus, the diffusion layer 121 ₂ is shared by the transistors 301A and B.

  FIG. 1B further shows a first interlayer insulating film 131 formed on the substrate 101 so as to cover the transistor 301A, and a capacitor 201A formed on the first interlayer insulating film 131. The first interlayer insulating film 131 is an example of the interlayer insulating film of the present invention. The capacitor 201A includes a lower electrode (BE: Bottom Electrode) 211A, a ferroelectric film (FE: Ferroelectric Film) 212A, and an upper electrode (TE: Top Electrode) 213A that are sequentially formed on the first interlayer insulating film 131. Contains.

In the present embodiment, the lower electrode 211A is a laminated film in which a barrier metal TiAlN film having a thickness of 30 nm and an Ir film having a thickness of 120 nm are sequentially laminated. The ferroelectric film 212A is a Pb (Zr _x Ti _1-x ) O ₃ film having a thickness of 100 nm. Further, the upper electrode 213A is a laminated film in which a 10 nm thick SrRuO ₃ film and a 70 nm thick IrO ₂ film are sequentially laminated (the SrRuO ₃ film is not shown).

FIG. 1B further shows a hydrogen protective film 151 and a second interlayer insulating film 132 formed in this order on the first interlayer insulating film 131 so as to cover the capacitor 201A. Examples of the hydrogen protective film 151 include a SiO _x film (silicon oxide film) such as a SiO ₂ film, an Al _x O _y film (aluminum oxide film) such as an Al ₂ O ₃ film, and a SiAl _x O _y film such as a SiAlO film ( Silicon aluminum oxide film), ZrO _x film (zirconium oxide film) such as ZrO ₂ film, Si _x N _y film (silicon nitride film) such as Si ₃ N ₄ film, or a combination of two or more of these films A membrane is suitable.

FIG. 1B further shows a wiring layer 141 formed above the upper electrode 213A of the capacitor 201A with a hydrogen protective film 151 and a second interlayer insulating film 132 interposed therebetween. In FIG. 1B, a portion of the wiring layer 141 that is electrically connected to the upper electrode 213A of the capacitor 201A is denoted by reference numeral 141 ₁ and is electrically connected to the upper electrode 201B of the capacitor 201B. The part is indicated by reference numeral 141 ₂ . The wiring layer 141 corresponds to the M1 wiring, and is an Al (aluminum) layer in the present embodiment. FIG. 1B further shows a third interlayer insulating film 133 formed on the second interlayer insulating film 132 so as to cover the wiring layer 141.

FIG. 1B further shows three types of plugs TW _A , V 1 _A and CSF _A. As is clear from FIG. 1A, among these plugs, the plugs V1 _A and CSF _A are plugs that do not originally appear in the cross section of FIG. However, in the present embodiment, for convenience of explanation, indicated by broken lines in FIG. 1 (B) also plug V1 _A and CSF _A. In the drawings described later, plugs that do not originally appear in the cross section are indicated by broken lines.

Plug TW _A, as shown in FIG. 1 (B), (see FIG. 1 (A) also) which are formed on the upper electrode 213A, and electrically conductive is not the upper electrode 213A and the wiring layer 141 _1. Plug TW _A is an example of the first plug of the present invention. In this embodiment, the plug TW _A is, W (tungsten) and has a plug.

Also, the plug V1 _A, as shown in FIG. 1 (B), is formed on the diffusion layer 121 ₁ is electrically conductive is not the diffusion layer 121 ₁ and the wiring layer 141 ₁ (FIG. 1 (A) See also). Plug V1 _A is an example of a second plug of the present invention. In this embodiment, the plug V1 _A also has a W (tungsten) plug.

Also, the plug CSF _A, as shown in FIG. 1 (B), is formed on the diffusion layer 121 _2, it is electrically conducted to thereby a diffusion layer 121 ₂ and the lower electrode 211A. More specifically, the plug CSF _A, as shown in FIG. 1 (C), is arranged on the side of the lower electrode 211A, by contact with the side surface and the upper surface of the diffusion layer 121 _{and second} lower electrode 211A, and electrically conductive is not the the lower electrode 211A and the diffusion layer 121 ₂ (see FIG. 1 (a) also). Plug CSF _A is an example of a third plug of the present invention. In the present embodiment, the plug CSF _A is also a W (tungsten) plug. Thus, in the present embodiment, the plugs TW _A , V1 _A , and CSF _A are formed of the same material. The plugs TW _A , V1 _A , and CSF _A may all be Al (aluminum) plugs.

As described above, the semiconductor device of this embodiment includes the plugs TW _A , V1 _A , and CSF _A as plugs for the capacitor 201A and the transistor 301A. On the other hand, the semiconductor device shown in FIG. 2 includes plugs TW _A , V 1 _A , CS _A , and CSM _A as plugs for the capacitor 201A and the transistor 301A. Hereinafter, the configuration of the semiconductor device illustrated in FIG. 2 will be described.

  2A and 2B are a plan view and a side sectional view showing a configuration of a semiconductor device of a comparative example. 2A corresponds to a plan view of the semiconductor device, and FIGS. 2B and 2C are side views taken along lines XX ′ and YY ′ shown in FIG. 2A, respectively. It corresponds to a sectional view.

FIG. 2B shows four types of plugs TW _A , V 1 _A , CS _A , and CSM _A.

As shown in FIG. 2B, the plug TW _A is formed on the upper electrode 213A and electrically connects the upper electrode 213A and the wiring layer 141 ₁ (see also FIG. 2A). In this comparative example, the plug TW _A is, Al (aluminum) has a plug.

In FIG. 2B, two plugs CS _A are shown. One plug CS _A is formed on the diffusion layer 121 ₁ , and the other plug CS _A is formed on the diffusion layer 121 ₂ . Is formed. In this comparative example, these plugs CS _A has a polysilicon plug.

Further, in FIG. 2 (B), it is shown two plugs CSM _A is one of the plug CSM _A is formed on the plug CS _A on the diffusion layer 121 ₁ and the other plug CSM _A, diffusion It is formed on the plug CS _a on layer 121 _2. In this comparative example, these plugs CSM _A is, W (tungsten) and has a plug.

Also, the plug V1 _A, as shown in FIG. 2 (B), are formed on the plug CS _A and CSM _A on the diffusion layer 121 _1. In this comparative example, the plug V1 _A is, W (tungsten) and has a plug.

As a result, the plug CS _A on the diffusion layer 121 _1, CSM _A, and V1 _A, as shown in FIG. 2 (B), are electrically connected to not the diffusion layer 121 ₁ and the wiring layer 141 ₁ ( (See also FIG. 2 (A)).

Also, the plug CS _A and CSM _A on the diffusion layer 121 _2, as shown in FIG. 2 (B), are electrically connected to thereby a diffusion layer 121 ₂ and the lower electrode 211A. More particularly, plug CS _A and CSM _A on the diffusion layer 121 _2, FIG. 2 (B), the as shown in (C), is disposed below the lower electrode 211A, and the lower surface of the lower electrode 211A by contact with the upper surface of the diffusion layer 121 _2, are electrically conducted to thereby the the lower electrode 211A and the diffusion layer 121 _2.

In this comparative example, the lower electrode 211A is a laminated film in which a barrier metal TiAlN film and an Ir film are laminated in order. The ferroelectric film 212A is a Pb (Zr _x Ti _1-x ) O ₃ film. The upper electrode 213A is a laminated film in which an SrRuO ₃ film and an IrO ₂ film are laminated in order.

  Hereinafter, the advantages of the semiconductor device of this embodiment will be described with reference to FIG. At that time, the semiconductor device of the comparative example shown in FIG.

As shown in FIG. 2, the semiconductor device of the comparative example includes plugs TW _A , V1 _A , CS _A , CSM _A as plugs for the capacitor 201A and the transistor 301A, and the plugs TW _A , V1 _A , CS _A , CSM _A Are respectively an Al plug, a W plug, a polysilicon plug, and a W plug. Therefore, in the comparative example, the step of forming these plugs (vias steps), the formation process of TW _A, the formation process of V1 _A process of forming the CS _A, 4 processings of formation of CSM _A is also required. Therefore, in the comparative example, an increase in cost and a decrease in yield due to the via process as many as four processes become problems.

On the other hand, the semiconductor device of the present embodiment includes plugs TW _A , V1 _A , and CSF _A as plugs for the capacitor 201A and the transistor 301A as shown in FIG. Thereby, in the present embodiment, it is possible to reduce the number of via processes for forming plugs for the capacitor 201A and the transistor 301A as described below.

First, in the comparative example, the plug CS _A and CSM _A on the diffusion layer 121 ₂ is disposed below the lower electrode 211A. Therefore, the plugs CS _A and CSM _A need to be formed before the capacitor 201A is manufactured. On the other hand, the plug V1 _A is for implantation in the second interlayer insulating film 132, it is necessary to form after making a capacitor 201A. Therefore, in the comparative example, in order to form the plugs on the diffusion layers 121 ₁ and 121 ₂ , three steps of a CS _A forming step, a CSM _A forming step, and a V1 _A forming step are required.

In contrast, in the present embodiment, the plug CSF _A on the diffusion layer 121 ₂ is disposed on the side of the lower electrode 211A. Thus, the plug CSF _A, similar to the plug V1 _A, can be formed after production of a capacitor 201A. Therefore, in this embodiment, the material of the plug V1 _A on the diffusion layer 121 ₁ and the material of the plug CSF _A on the diffusion layer 121 ₂ are made the same, thereby forming these plugs in the same process, The number of steps for forming these plugs can be reduced. In fact, in the present embodiment, materials of the plug CSF _A plug V1 _A are both has a W (tungsten), those plugs, as will be described later, are formed by the same embedding process.

Second, in the comparative example, the plugs TW _A and V1 _A are Al plugs and W plugs, respectively, and are formed of different materials. Therefore, in the comparative example, in order to form the plugs TW _A and V1 _A , two steps of forming the TW _A and forming the V1 _A are necessary.

On the other hand, in this embodiment, the plugs TW _A and V1 _A are both W plugs and are formed of the same material. Therefore, in the present embodiment, the step of forming the plug TW _A, by a process of forming the plugs V1 _A and the same process, it is possible to reduce the number of steps of the plug formation process.

In particular, in this embodiment, the plugs TW _A , V1 _A , and CSF _A are all W plugs, and all are formed of the same material. Therefore, in the present embodiment, the step of forming the plug TW _A, the step of forming the plugs V1 _A, by a process of forming the plugs CSF _A and the same process, the plug TW _A, V1 _A, the CSF _A 1 step Can be formed. As described above, in this embodiment, the plugs TW _A , V1 _A , and CSF _A are made of the same material, so that these plugs can be formed in one step.

In the present embodiment, at least the uppermost layer of the upper electrode 213A is preferably a noble metal layer such as a Pt (platinum) layer or a noble metal-containing layer such as an IrO ₂ layer. First, the upper electrode 213A has an advantage that the etching rate is slow, and it becomes easy to simultaneously form the via hole for the plug TW _A and the via holes for the plugs V1 _A and CSF _A. . Second, during RIE (Reactive Ion Etching) processing of the capacitor 201A, the capacitor 201A is easily processed into a tapered shape, and it is easy to form a via hole for the plug CSF _A so that the side surface of the lower electrode 211A is exposed. There is an advantage of becoming.

  As described above, this embodiment has an advantage that the number of via steps for forming the plug for the capacitor 201A and the transistor 301A can be reduced. The present embodiment further has the advantage that the degree of freedom in selecting the lower electrode material of the capacitor 201A is increased as follows.

In the semiconductor device of the comparative example, the COP structure is adopted, and the lower electrode 211A is disposed on the plug CSM _A that is a W plug. In this case, the problem is that the plug CSM _A which is a W plug expands due to oxidation. Therefore, in the comparative example, in order to suppress the oxidation of the plug CSM _A, as a lower electrode material of the capacitor 201A, the thickness 100nm or more Ir layer and the barrier metal layer (TiAlN, etc.) is required. Thus, in the comparative example, the lower electrode material is limited to a specific material.

On the other hand, the COP structure is not adopted in the semiconductor device of this embodiment, and the lower electrode 211A is disposed on the side of the plug CSF _A. Therefore, in this embodiment, the lower electrode material is not limited to a specific material as in the comparative example, and various materials can be employed. In the present embodiment, for example, it is possible to improve the characteristics of the ferroelectric film 212A by adopting a Pt layer as the lower electrode 211A or by reducing the thickness of the lower electrode 211A. For example, the lower electrode 211A is a laminated film in which a Ti (titanium) film having a thickness of 5 nm and an Ir film having a thickness of 100 nm are sequentially laminated, or a Ti film having a thickness of 5 nm and a Pt film having a thickness of 100 nm are sequentially arranged. By forming a laminated film and using the ferroelectric film 212A as a PZT film, the crystallinity of the PZT film can be improved and the polarization characteristics thereof can be improved.

  In this embodiment, the lower electrode 211A is a laminated film in which a barrier metal TiAlN film and an Ir film are sequentially laminated, and the main body portion (Ir film) of the lower electrode 211A is a barrier metal layer (TiAlN film). Is formed on the first interlayer insulating film 131. However, the lower electrode 211A does not include the barrier metal layer, and may be formed directly on the first interlayer insulating film 131.

  As described above, this embodiment has an advantage that the degree of freedom in selecting the lower electrode material of the capacitor 201A is increased, and the characteristics of the capacitor 201A can be improved. This embodiment is effective for reducing the cost of a low-capacity FeRAM mixed device, for example.

  Hereinafter, the operation and configuration of the semiconductor device of the first embodiment will be described in more detail.

  FIG. 3 is a circuit diagram and a graph for explaining the operation of the semiconductor device of the first embodiment.

  As shown in FIG. 3A, the semiconductor device of this embodiment is a Chain type FeRAM having a TC parallel unit series connection type structure. FIG. 3A shows four memory cells each including four sets of capacitors 201 and transistors 301. In each cell, the capacitors 201 and the transistors 301 are connected in parallel.

  These four cells constitute a Chain unit and are connected in series with each other. The Chain unit is composed of two or more sets (for example, eight sets) of capacitors 201 and transistors 301, and the capacitors 201 and transistors 301 in each cell are connected in series with other capacitors 201 and transistors 301 that constitute the same Chain unit. ing.

  In FIG. 3A, one end of the Chain unit is connected to the plate line PL, and the other end is connected to the bit line BL via the selection transistor X. Further, the word lines WL0 to WL3 are connected to the gates of the four transistors 301, respectively, and the selection line BS is connected to the gate of the selection transistor X.

  3A and 3B are a circuit diagram and a graph for explaining the operation of the semiconductor device in the standby state. FIG. 3B is a PV diagram showing the state of hysteresis of the ferroelectric film 212 in the standby state, where P and V represent polarization and voltage, respectively.

  In the standby state, each transistor 301 is in an ON state. Therefore, both electrodes (211 and 213) of each capacitor 201 are electrically short-circuited, and no voltage is applied between these electrodes. Further, the selection transistor X is in an OFF state.

  FIGS. 3C and 3D are a circuit diagram and a graph for explaining the operation of the semiconductor device in the active state. FIG. 3D is a PV diagram showing the state of hysteresis of the ferroelectric film 212 in the operating state.

  In the operating state, the transistor 301 and the capacitor 201 (indicated by Y and Z, respectively) of the selected cell are turned off, and the voltage Vint is applied to the plate line PL. As a result, a voltage is applied to the capacitor Z, and the signal flows to the bit line BL. Note that the selection transistor X is in an ON state.

  FIG. 4 is a side sectional view showing the configuration of the Chain unit in the semiconductor device of the first embodiment.

  In FIG. 4, eight memory cells including eight sets of capacitors 201 and transistors 301 are connected in a chain form, and constitute one Chain unit.

  FIG. 4 further shows wiring layers M1 to M3. The wiring layer M3 is provided with plate lines PL, word lines WL0 to WL7, selection lines BS, and the like, and the wiring layer M2 is provided with bit lines BL.

The plate line PL is electrically connected to the wiring layer M1 via the plug _PPL , and the bit line BL is electrically connected to the wiring layer M1 via the plug _PBL and the block selection unit. In the present embodiment, the signal in the above operation state is extracted to the bit line BL via the block selection unit and the plug _PBL . Note that the wiring layer 141 shown in FIG. 1 is provided in the wiring layer M1.

  As described above, in the present embodiment, the TC parallel unit series connection structure is adopted, and the semiconductor device of the present embodiment is a Chain-type FeRAM. However, the present embodiment is also effective for semiconductor devices other than Chain type FeRAM, and the semiconductor device of this embodiment may be a device other than Chain type FeRAM.

FIG. 4 is a side sectional view along the line XX ′ shown in FIG. Therefore, in FIG. 1A, the capacitors 201A and B and the transistors 301A and B constitute one Chain unit, and the capacitors 201C and D and the transistors 301C and D constitute another Chain unit. In FIG. 1B, a capacitor 201A and a transistor 301A are connected in parallel to each other by a wiring layer 141 ₁ , diffusion layers 121 ₁ and 122 ₂ , and plugs TW _A , V1 _A , and CSF _A.

  Hereinafter, the manufacturing method of the semiconductor device of 1st Embodiment and a comparative example is demonstrated.

  5 and 6 are side sectional views showing the method for manufacturing the semiconductor device of the first embodiment. Each of the drawings shown in FIGS. 5 and 6 is a side sectional view taken along line X-X ′ shown in FIG.

  First, as shown in FIG. 5A, a switching transistor 301 including a gate insulating film 311, a gate electrode 312, and the like is formed over a substrate 101. Next, as illustrated in FIG. 5A, the diffusion layer 121 is formed in the substrate 101. Next, as shown in FIG. 5A, a first interlayer insulating film 131 is deposited over the substrate 101 so as to cover the transistor 301, and then the first interlayer insulating film is formed by CMP (chemical mechanical polishing). 131 is flattened. Next, as shown in FIG. 5A, a lower electrode material 401 for forming the lower electrode 211 and a ferroelectric for forming the ferroelectric film 212 on the first interlayer insulating film 131. A material 402 and an upper electrode material 403 for forming the upper electrode 213 are sequentially deposited.

  Note that the STI layer 111 illustrated in FIGS. 1A and 1C is formed over the substrate 101 before the transistor 301 is formed.

  Next, as shown in FIG. 5B, a capacitor processing mask layer 411 is formed over the upper electrode material 403. The mask layer 411 is formed by depositing a mask material on the upper electrode material 403 and patterning the mask material into a shape for capacitor processing.

Here, the mask layer 411 is a hard mask layer. Examples of the mask layer 411 include an SiO ₂ film and a laminated film in which a TiAlN film and an SiO ₂ film are laminated in order. Other examples of the mask layer 411 include SiO _x films (silicon oxide films) such as SiO ₂ films, Al _x O _y films (aluminum oxide films) such as Al ₂ O ₃ films, and SiAl _x O _y films such as SiAlO films. Film (silicon aluminum oxide film), ZrO _x film (zirconium oxide film) such as ZrO ₂ film, Si _x N _y film (silicon nitride film) such as Si ₃ N ₄ film, TiAl _x N such as TiAl _0.5 N _0.5 film Examples thereof include a _Y film (titanium aluminum oxide film) or a laminated film in which two or more of these films are combined.

  Next, as shown in FIG. 5C, the lower electrode material 401, the ferroelectric material 402, and the upper electrode material 403 are etched by high temperature RIE, so that the lower electrode 211, the ferroelectric film 212, and A ferroelectric capacitor 201 including the upper electrode 213 is formed. The capacitor 201 is processed into a tapered shape by the RIE.

  Note that when the high temperature RIE is performed at 300 ° C. or higher, the mask layer 411 is preferably a hard mask layer. When the mask layer 411 is a hard mask layer, the mask layer 411 may be removed after the capacitor is formed or may be left. In this embodiment, the mask layer 411 is removed after the capacitor is formed (see FIG. 6A).

  Next, as shown in FIG. 6A, a hydrogen protective film 151 and a second interlayer insulating film 132 are sequentially deposited on the first interlayer insulating film 131 so as to cover the capacitor 201, and then CMP is performed. Thus, the second interlayer insulating film 132 is planarized.

  Next, as shown in FIG. 6A, via holes for the plugs TW, V1, and CSF are formed by PEP (Photo Engraving Process) and RIE. The via hole for the plug TW is formed so as to penetrate the second interlayer insulating film 132 and the hydrogen protective film 151 and expose the upper electrode 213. The via holes for the plugs V1 and CSF are formed so as to penetrate the second interlayer insulating film 132, the hydrogen protective film 151, and the first interlayer insulating film 131 and to expose the diffusion layer 121. In particular, the via hole for the plug CSF is formed so that the side surface of the lower electrode 211 is exposed.

  From the viewpoint of process shortening, the via holes for the plugs TW, V1, and CSF are preferably formed by the same PEP process and the same RIE process. However, when the RIE etching rate of the hydrogen protective film 151 is smaller than the RIE etching rate of the first and second interlayer insulating films 131 and 132 (for example, 1/4 or less), the PEP process of these plugs is performed. The RIE process may be a separate process.

  Next, as shown in FIG. 6A, a W (tungsten) material is deposited on the second interlayer insulating film 132 by W-CVD (chemical vapor deposition), and the plugs TW, V1, and CSF are used. The same plug material is embedded in the via hole. Next, the W material is flattened by CMP to form plugs TW, V1, and CSF as shown in FIG.

  Thus, in this embodiment, the plugs TW, V1, and CSF are formed by the same embedding process. As a result, in this embodiment, the plug material can be embedded in the via holes for the plugs TW, V1, and CSF in one step. In the step of FIG. 6A, an Al (aluminum) material may be employed as the plug material for the plugs TW, V1, and CSF.

  In the present embodiment, the heights of the upper surfaces of the plugs TW, V1, and CSF are the same as shown in FIG. 6A by the above-described planarization process, and all of them are the second interlayer insulating film. It becomes the same height as the upper surface of 132.

  Further, in the present embodiment, the via hole for the plug CSF is formed so that the side surface of the lower electrode 211 is exposed, so that the shape of the plug CSF narrows from the upper side to the lower side of the lower electrode 211. (See FIG. 1C). That is, the planar shape of the plug CSF decreases from the upper side to the lower side of the lower electrode 211.

  Next, as illustrated in FIG. 6B, a wiring layer 141 corresponding to the M1 wiring is formed over the second interlayer insulating film 132. Here, the wiring layer 141 is an Al (aluminum) layer. Next, as shown in FIG. 6B, a third interlayer insulating film 133 is formed on the second interlayer insulating film 132 so as to cover the wiring layer 141. When the wiring layer 141 is formed by the damascene method, the wiring layer 141 is formed after the third interlayer insulating film 133 is formed.

  In this way, as shown in FIG. 6B, the ferroelectric capacitor 201 and the switching transistor 301 that constitute the memory cell are formed over the substrate 101. FIG. 6B further shows a peripheral transistor 501 formed on the substrate 101 by the same manufacturing process. The peripheral transistor 501 includes a gate insulating film 511 and a gate electrode 512 that are sequentially formed on the substrate 101.

  In the present embodiment, the plug TW and the plug V1 for the same memory cell are electrically connected by the wiring layer 141 (see FIG. 1A). On the other hand, the wiring layer 141 that conducts the plug TW and the plug V1 is not electrically connected to the plug CSF for the same memory cell, but is electrically insulated by the third interlayer insulating film 133 (FIG. (See A) and (C)). Thus, in this embodiment, the plug CSF is electrically insulated from the plugs TW and V1 for the same memory cell.

  In FIG. 6B, the third interlayer insulating film 133 is formed on the plug CSF. However, if the cell size allows, the wiring layer 141 may be disposed on the plug CSF. However, in this case, when patterning the wiring layer 141, the wiring portion arranged on the plug CSF and the wiring portion arranged on the same memory cell plugs TW, V1 are separated, and these are separated. It is necessary to electrically insulate the wiring portions.

  An example of the wiring layer 141 having such a structure is shown in FIG. 7A and 7B are a plan view and a side sectional view showing a modification of the configuration of the semiconductor device of FIG.

In FIG. 7 (B) and (C), the wiring layer 141 is disposed on the plug TW _A and V1 _A, the portion 141 ₁ for electrically connecting the plug TW _A and the plug V1 _A, on the plug CSF _A And includes a portion 141 ₃ electrically connected to the plug CSF _A , and the portion 141 ₁ and the portion 141 ₃ are separated from each other (see also FIG. 7A). The portion 141 ₁ is an example of the first portion of the present invention, and the portion 141 ₃ is an example of the second portion of the present invention.

  In the case of FIG. 1, when the wiring layer 141 is etched, only the wiring layer 141 on the plug CSF is removed from the wiring layers 141 on the plugs TW, V1, and CSF. As a result, the plug CSF is exposed. It will be. At this time, the plug CSF may be over-etched by about 1 to 20 nm.

  On the other hand, in the case of FIG. 7, when the wiring layer 141 is etched, none of the wiring layers 141 on the plugs TW, V1, and CSF are removed. Therefore, all of the plugs TW, V1, and CSF need not be over-etched.

  In FIGS. 1 and 7, due to the flattening process of the plug material (FIG. 6A), the height of the upper surface of the plug CSF is substantially the same as the height of the upper surfaces of the plugs TW and V1. . However, in FIG. 1, due to the above-described over-etching, the height of the upper surface of the plug CSF is generally not exactly equal to the height of the upper surface of the plugs TW and V1, and the height of the upper surface of the plugs TW and V1. It is slightly lower than this. Therefore, in the case of FIG. 7, the height of the upper surface of the plug CSF is relatively strictly equal to the height of the upper surfaces of the plugs TW and V1, whereas in the case of FIG. Remains substantially equal to the height of the upper surface of the plugs TW, V1.

  Then, the manufacturing method of the semiconductor device of a comparative example is demonstrated.

  8 and 9 are side sectional views showing a method for manufacturing a semiconductor device of a comparative example. Each of the drawings shown in FIGS. 8 and 9 is a side sectional view taken along line X-X ′ shown in FIG.

  First, the difference between the first embodiment and the comparative example is that plugs CS and CSM are formed in the first interlayer insulating film 131 at the stage shown in FIG. The plug CS is here a polysilicon plug, and the plug CSM is here a W plug.

  Note that the lower electrode material 401, the ferroelectric material 402, and the upper electrode material 403 are deposited after the formation of the plugs CS and CSM in the stage shown in FIG. As a result, the capacitor 201 can be formed on the plugs CS and CSM as shown in FIG.

  Second, the difference between the first embodiment and the comparative example is that, as shown in FIGS. 9A and 9B, the plug V1 and the plug TW are formed by separate embedding processes. The plug V1 is a W plug here, and the plug TW is an Al plug here.

  As a result, in the comparative example, the plugs TW, V1, CS, and CSM are formed by four embedding processes. On the other hand, in the first embodiment, the plugs TW, V1, and CSF are formed by one embedding process. From this, the advantage of 1st Embodiment compared with a comparative example is understood.

  Finally, with reference to FIG. 1, the operation effect of the semiconductor device and the manufacturing method thereof according to the present embodiment will be described.

  As described above, in this embodiment, the plugs TW, V1, and CSF are employed as the plugs for the ferroelectric capacitor 201 and the switching transistor 301. The plug TW is formed on the upper electrode 213 and electrically connects the upper electrode 213 and the wiring layer 141. The plug V1 is formed on the first diffusion layer 121 and electrically connects the first diffusion layer 121 and the wiring layer 141. The plug CSF is formed on the second diffusion layer 121 and is disposed on the side of the lower electrode 211 to electrically connect the lower electrode 211 and the second diffusion layer 121.

  Thereby, in the present embodiment, it is possible to reduce the number of steps for forming the ferroelectric capacitor 201 and the plug for the switching transistor 301. Furthermore, the degree of freedom in selecting the lower electrode material of the ferroelectric capacitor 201 is increased, and the characteristics of the ferroelectric capacitor 201 can be improved.

  Note that the plug CSF of the present embodiment is provided for the purpose of electrically connecting the lower electrode 211 and the second diffusion layer 121. Therefore, a portion of the plug CSF located above the upper surface of the lower electrode 211 is not necessary for achieving this purpose. However, in this embodiment, the height of the upper surface of the plug CSF is equal to the upper surface of the lower electrode 211 because the plug CSF is formed after the ferroelectric capacitor 201 and the second interlayer insulating film 132 are formed. It is higher and is almost the same height as the upper surface of the second interlayer insulating film 132.

  Hereinafter, second to fifth embodiments of the present invention will be described. These embodiments are modifications of the first embodiment, and these embodiments will be described with a focus on differences from the first embodiment.

(Second Embodiment)
FIG. 10 is a plan view and a side sectional view showing the configuration of the semiconductor device of the second embodiment.

  In the first embodiment (FIG. 1), the plugs TW, V1, and CSF are all W plugs. On the other hand, in the second embodiment (FIG. 10), the plug V1 and the plug CSF are W plugs, but the plug TW is an Al plug. In the second embodiment, one of W (tungsten) and Al (aluminum) is an example of the first material of the present invention, and the other is an example of the second material of the present invention.

  In FIG. 1 and FIG. 10, the plug TW shown in FIG. 1 is distinguished from the W plug, and the plug TW shown in FIG. The plug TW shown in FIG. 10 is indicated by the symbol “TW ′”. However, in the following description, for the sake of brevity, both plugs are referred to as “plug TW”.

  As described above, in the second embodiment, the plugs V1 and CSF are W plugs, and the plug TW is an Al plug. Therefore, in the second embodiment, the number of steps for forming the plugs TW, V1, and CSF is increased as compared with the first embodiment. However, in the second embodiment, the plugs V1 and CSF and the plug TW are formed by separate embedding processes, so that damage to the capacitor 201 due to embedding of the plug material for the plug TW can be suppressed.

  Note that the Al material is preferably embedded in forming the plug TW by an Al reflow method with little damage to the capacitor 201. In addition, the plug and the wiring layer are formed by opening the via hole for the plug V1 and CSF, embedding the W material in the via hole for the plug V1 and CSF, CMP for the W material, opening the via hole for the plug TW, and for the plug TW. It is desirable to bury the Al material in the via hole, perform CMP of the Al material, and form the wiring layer 141 in this order.

  In the second embodiment, only the plug V1 may be a W plug, and the plugs TW and CSF may be Al plugs. The reason is that the embedding of the plug material for the plug TW may damage the upper electrode 213 of the capacitor 201, and the embedding of the plug material for the plug CSF may damage the lower electrode 211 of the capacitor 201. Because there is. In the second embodiment, the plug V1 is a W plug, and the plugs TW and CSF are Al plugs, so that it is possible to suppress damage to the capacitor 201 due to embedding the plug material for the plug TW and CSF.

  In this case, it is desirable that the Al material for the plug CSF is embedded by the Al reflow method as in the case of the Al material for the plug TW. At this time, it is desirable to perform the embedding by the same embedding process. Also, the plug and wiring layer are formed by opening a via hole for the plug V1, embedding a W material in the via hole for the plug V1, CMP for the W material, opening a via hole for the plug TW and CSF, and for the plug TW and CSF. It is desirable to bury the Al material in the via hole, perform CMP of the Al material, and form the wiring layer 141 in this order.

  11 and 12 are side sectional views showing the method for manufacturing the semiconductor device of the second embodiment.

  In the present embodiment, the steps shown in FIGS. 11A to 11C are performed in the same manner as the steps shown in FIGS. 6A to 6C.

  In this embodiment, next, as shown in FIG. 12A, a hydrogen protective film 151 and a second interlayer insulating film 132 are sequentially deposited on the first interlayer insulating film 131 so as to cover the capacitor 201. Thereafter, the second interlayer insulating film 132 is planarized by CMP.

  Next, as shown in FIG. 12A, via holes for the plugs V1 and CSF are formed by PEP and RIE. The via holes for the plugs V1 and CSF may be formed at the same time or separately, but from the viewpoint of shortening the process, it is desirable to form them simultaneously by the same PEP process and the same RIE process.

  Next, as shown in FIG. 12A, a W material is deposited on the second interlayer insulating film 132 by W-CVD, and the same plug material is embedded in the via holes for the plugs V1 and CSF. Next, the W material is flattened by CMP to form plugs V1 and CSF as shown in FIG. Thus, in this embodiment, the plugs V1 and CSF are formed by the same embedding process.

  Next, as shown in FIG. 12B, a via hole for the plug TW is formed by PEP and RIE.

  Next, as shown in FIG. 12B, an Al material is deposited on the second interlayer insulating film 132 by an Al reflow method, and the plug material is embedded in the via hole for the plug TW. Next, the Al material is planarized by CMP to form a plug TW as shown in FIG. Thus, in the present embodiment, the plug TW is formed by a filling process different from the plugs V1 and CSF.

  Next, in the present embodiment, the process shown in FIG. 12C is performed in the same manner as the process shown in FIG. In this manner, as shown in FIG. 12C, the ferroelectric capacitor 201 and the switching transistor 301 that constitute the memory cell are formed on the substrate 101.

  As described above, in this embodiment, the plugs TW, V1, and CSF are employed as the plugs for the ferroelectric capacitor 201 and the switching transistor 301. The plug TW is formed on the upper electrode 213 and electrically connects the upper electrode 213 and the wiring layer 141. The plug V1 is formed on the first diffusion layer 121 and electrically connects the first diffusion layer 121 and the wiring layer 141. The plug CSF is formed on the second diffusion layer 121 and is disposed on the side of the lower electrode 211 to electrically connect the lower electrode 211 and the second diffusion layer 121.

  Thereby, in this embodiment, it is possible to reduce the number of steps of forming the ferroelectric capacitor 201 and the plug for the switching transistor 301 as in the first embodiment. Furthermore, the degree of freedom in selecting the lower electrode material of the ferroelectric capacitor 201 is increased, and the characteristics of the ferroelectric capacitor 201 can be improved.

  In the first embodiment, the plugs TW, V1, and CSF are all W plugs. In the present embodiment, the plugs V1 and CSF are W plugs, and the plug TW is an Al plug. Alternatively, in the present embodiment, the plug V1 is a W plug, and the plugs TW and CSF are Al plugs. Thereby, in this embodiment, it is possible to suppress damage to the ferroelectric capacitor 201 due to the plug material for the plug TW or the plug material for the plug TW and CSF.

  In this embodiment, one of W (tungsten) and Al (aluminum) is an example of the first material of the present invention, and the other is an example of the second material of the present invention. The material of 2 may be a material other than W (tungsten) or Al (aluminum). The material of the plugs TW, V1, and CSF in the first embodiment may also be a material other than W (tungsten).

(Third embodiment)
FIG. 13 is a plan view and a side sectional view showing the configuration of the semiconductor device of the third embodiment.

  As shown in FIG. 1B, in the first embodiment, the capacitor 201A forms a capacitor pair with another adjacent capacitor 201B. The lower electrode 211A of the capacitor 201A, the lower electrode 211B of the capacitor 201B, Is short-circuited. More specifically, in the capacitor pair, the lower electrode 211A of the capacitor 201A and the lower electrode 211B of the capacitor 201B are integrated.

Further, as shown in FIG. 1B, in the first embodiment, the plug CSF has a one-to-one correspondence with the capacitor 201. For example, the plug CSF _A has a one-to-one correspondence with the capacitor 201A and is electrically connected to the lower electrode 211A. Similarly, the plug CSF _B has a one-to-one correspondence with the capacitor 201B and is electrically connected to the lower electrode 211B. In the first embodiment, as shown in FIG. 1A, four plugs CSF are provided for four memory cells.

  In the third embodiment, as in the first embodiment, as shown in FIG. 13B, the capacitor 201A forms a capacitor pair with another adjacent capacitor 201B, and the lower electrode 211A of the capacitor 201A is formed. And the lower electrode 211B of the capacitor 201B are short-circuited.

However, in the third embodiment, unlike the first embodiment, as shown in FIG. 13B, the plug CSF is shared by the two capacitors 201 constituting the capacitor pair. For example, the plug CSF _AB is shared by the capacitors 201A and 201B, and is electrically connected to the lower electrodes 211A and 211B. In the third embodiment, as shown in FIG. 13A, two plugs CSF are provided for four memory cells.

  In FIG. 13B, the boundary between the capacitor 201A and the capacitor 201B is indicated by B. As shown in FIG. 13B, the common CSF for the capacitors 201A and 201B is disposed in the vicinity of the boundary B. More specifically, the CSF is disposed in the vicinity of the end of the boundary B so as to be in contact with the lower electrodes 211A, B of the capacitors 201A, B. In FIG. 14B, an interval between the plug TW and the plug CSF for the same memory cell is indicated by an arrow A.

  Here, the first embodiment and the third embodiment are compared.

  In the first embodiment, since the plugs TW and CSF are formed at the same time, the interval between the plug TW and the plug CSF can be narrowed only to the interval of the minimum design rule. On the other hand, in the third embodiment, since the plug CSF is disposed in the vicinity of the boundary between the capacitors 201 constituting the capacitor pair, the size of each memory cell in the Y-Y ′ line direction can be reduced. Thereby, in the third embodiment, the chip size of the semiconductor device can be reduced, and the cost of the semiconductor device can be reduced.

  As described above, in the present embodiment, the plug CSF is shared by the capacitors 201 constituting the capacitor pair, and is disposed in the vicinity of the boundary between these capacitors 201. Thereby, in the present embodiment, the chip size of the semiconductor area can be reduced as compared with the first embodiment, and the cost of the semiconductor device can be reduced.

(Fourth embodiment)
FIG. 14 is a plan view and a side sectional view showing the configuration of the semiconductor device of the fourth embodiment.

  In the third embodiment, as shown in FIG. 13B, the capacitor 201A forms a capacitor pair with another adjacent capacitor 201B. The lower electrode 211A of the capacitor 201A, the lower electrode 211B of the capacitor 201B, Is short-circuited. More specifically, in the capacitor pair, the lower electrode 211A of the capacitor 201A and the lower electrode 211B of the capacitor 201B are integrated.

  Similarly, in the fourth embodiment, as shown in FIG. 14B, the capacitor 201A forms a capacitor pair with another adjacent capacitor 201B, and the lower electrode 211A of the capacitor 201A and the lower part of the capacitor 201B are formed. The electrode 211B is short-circuited.

  However, in the fourth embodiment, unlike the third embodiment, as shown in FIG. 14B, in the capacitor pair, the lower electrode 211A of the capacitor 201A and the lower electrode 211B of the capacitor 201B are separated. Yes.

However, in the fourth embodiment, as shown in FIGS. 14A and 14B, the plug CSF _AB is disposed between the capacitor 201A and the capacitor 201B, and the lower electrode 211A and the capacitor 201B of the capacitor 201A are disposed. The lower electrode 211B is electrically connected. Thereby, in the fourth embodiment, the lower electrode 211A of the capacitor 201A and the lower electrode 211B of the capacitor 201B are short-circuited.

  In the fourth embodiment, the plug CSF is disposed between the capacitors constituting the capacitor pair. This increases the size of each memory cell in the X-X ′ line direction. However, in the fourth embodiment, as shown in FIG. 14A, in addition to the plug CSF, the plug V1 is also arranged between capacitors adjacent in the XX ′ line direction, so that the Y− The size in the Y ′ line direction can be reduced. Thus, in the fourth embodiment, it is possible to reduce the chip size of the semiconductor device and reduce the cost of the semiconductor device.

  As described above, in the present embodiment, the plug CSF is shared by the capacitors 201 constituting the capacitor pair, and is disposed between these capacitors 201. Thereby, in the present embodiment, the chip size of the semiconductor area can be reduced as compared with the first embodiment, and the cost of the semiconductor device can be reduced.

(Fifth embodiment)
FIG. 15 is a plan view and a side sectional view showing a configuration of the semiconductor device of the fifth embodiment.

  The semiconductor device of the first to fourth embodiments is a Chain type FeRAM, whereas the semiconductor device of the fifth embodiment is a non-Chain type FeRAM. Thus, the present invention is effective not only for Chain type FeRAM but also for non-Chain type FeRAM.

FIG. 15B shows a first wiring layer 161 corresponding to the plate line PL and a second wiring layer 162 corresponding to the bit line BL. In FIG. 15 (B), the first wiring layer 161 electrically connected to the capacitor 201A is shown by reference numeral 161 _1, the second wiring layer 162 electrically connected to the transistor 301A is, reference numeral 162 Shown in ₁ .

As shown in FIG. 15B, the first wiring layer 161 ₁ is formed above the upper electrode 213A. The plug TW _A is formed on the upper electrode 213A, and electrically connects the upper electrode 213A and the first wiring layer 161 ₁ . In this embodiment, the plug TW _A is, W (tungsten) and has a plug.

Further, as shown in FIG. 15B, the second wiring layer 162 ₁ is formed below the lower electrode 211A, specifically, between the lower electrode 211A and the transistor 301A. Then, the plug V1 _A is formed on the diffusion layer 121 ₁ is electrically conductive is not a diffusion layer 121 ₁ and ₁ second wiring layer 162. In this embodiment, the plug V1 _A also has a W (tungsten) plug.

Further, the plug CSF _A is formed on the diffusion layer 121 ₂ as shown in FIG. 15B, and electrically connects the diffusion layer 121 ₂ and the lower electrode 211A. More specifically, the plug CSF _A, as shown in FIG. 15 (C), is arranged on the side of the lower electrode 211A, by contact with the side surface and the upper surface of the diffusion layer 121 _{and second} lower electrode 211A, and electrically conductive is not the the lower electrode 211A and the diffusion layer 121 ₂ (see FIG. 15 (a) also). In the present embodiment, the plug CSF _A is also a W (tungsten) plug.

In the present embodiment, the capacitor 201A and the transistor 301A include the first wiring layer 161 ₁ , the second wiring layer 161 _2, and the diffusion layers 121 ₁ and 122 ₂ , the plugs TW _A , V1 _A , and CSF _A. Are connected in series.

  In this embodiment, the plugs CSF correspond to the capacitors 201 on a one-to-one basis. In FIG. 15A, two plugs CSF are provided for two memory cells.

  As described above, in this embodiment, the plugs TW, V1, and CSF are employed as the plugs for the ferroelectric capacitor 201 and the switching transistor 301. The plug TW is formed on the upper electrode 213 and electrically connects the upper electrode 213 and the first wiring layer 161. The plug V1 is formed on the first diffusion layer 121 and electrically connects the first diffusion layer 121 and the second wiring layer 162. The plug CSF is formed on the second diffusion layer 121 and is disposed on the side of the lower electrode 211 to electrically connect the lower electrode 211 and the second diffusion layer 121.

  Thereby, in this embodiment, it is possible to reduce the number of steps of forming the ferroelectric capacitor 201 and the plug for the switching transistor 301 as in the first embodiment. Furthermore, the degree of freedom in selecting the lower electrode material of the ferroelectric capacitor 201 is increased, and the characteristics of the ferroelectric capacitor 201 can be improved.

  In the third to fifth embodiments, as in the second embodiment, the plug TW and the plug CSF may be Al plugs.

  In the second to fifth embodiments, the wiring layer 141 may be disposed on the plug CSF as in the modification of the first embodiment (FIG. 7).

  As mentioned above, although the example of the specific aspect of this invention was demonstrated by 1st-5th embodiment, this invention is not limited to these embodiment.

DESCRIPTION OF SYMBOLS 101 Substrate 111 STI layer 121 Diffusion layer 131 1st interlayer insulation film 132 2nd interlayer insulation film 133 3rd interlayer insulation film 141 Wiring layer 151 Hydrogen protective film 161 1st wiring layer 162 2nd wiring layer 201 Strong Dielectric capacitor 211 Lower electrode 212 Ferroelectric film 213 Upper electrode 301 Switching transistor 311 Gate insulating film 312 Gate electrode 401 Lower electrode material 402 Ferroelectric material 403 Upper electrode material 411 Mask layer 501 Peripheral transistor 511 Gate insulating film 512 Gate electrode TW, V1, CSF, CS, CSM Plug GC Gate conductive film

Claims (5)

A switching transistor formed on the substrate;
First and second diffusion layers formed to sandwich the transistor in the substrate;
An interlayer insulating film formed on the transistor;
A ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode sequentially formed on the interlayer insulating film;
A wiring layer formed above the upper electrode;
A first plug formed on the upper electrode and electrically conducting the upper electrode and the wiring layer;
A second plug formed on the first diffusion layer and electrically conducting the first diffusion layer and the wiring layer;
A third plug formed on the second diffusion layer, disposed on a side of the lower electrode, and electrically conducting the lower electrode and the second diffusion layer;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the capacitor and the transistor are connected in parallel to each other, and are connected in series to one or more other sets of capacitors and transistors connected in parallel to each other. A switching transistor formed on the substrate;
First and second diffusion layers formed to sandwich the transistor in the substrate;
An interlayer insulating film formed on the transistor;
A ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode sequentially formed on the interlayer insulating film;
A first wiring layer formed above the upper electrode;
A second wiring layer formed between the lower electrode and the transistor;
A first plug formed on the upper electrode and electrically conducting the upper electrode and the first wiring layer;
A second plug formed on the first diffusion layer and electrically conducting the first diffusion layer and the second wiring layer;
A third plug formed on the second diffusion layer, disposed on a side of the lower electrode, and electrically conducting the lower electrode and the second diffusion layer;
A semiconductor device comprising:   The semiconductor device according to claim 3, wherein the capacitor and the transistor are connected in series to each other. Forming a switching transistor on the substrate,
Forming first and second diffusion layers to sandwich the transistor in the substrate;
Forming an interlayer insulating film on the transistor;
A lower electrode, a ferroelectric film, and an upper electrode are sequentially formed on the interlayer insulating film to form a ferroelectric capacitor including the lower electrode, the ferroelectric film, and the upper electrode;
Forming a first plug on the upper electrode;
Forming a second plug on the first diffusion layer;
Forming a third plug electrically connecting the lower electrode and the second diffusion layer to a side of the lower electrode on the second diffusion layer;
A method of manufacturing a semiconductor device, comprising: forming a wiring layer electrically connected to the first and second plugs above the upper electrode.

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