JP2011114156A - Single-electron-turnstyle device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To fabricate a smaller single-electron island, and to arrange a top gate without requiring high precision. <P>SOLUTION: Two groove portions 105 which are arranged opposite each other are formed at two places across an opening portion 104 orthogonally to an extension direction of a thin line to be formed. The groove portions 105 are formed until reaching an insulating layer 101. Then an upper-layer portion of a silicon layer 102 is thermally oxidized through a silicon oxide layer 103 to make the silicon layer 102 thinner. In this oxidizing process, constriction portions 107 which are constricted in a layer thickness direction are formed nearby the inside of curved line-shaped border portions corresponding to two opposite curved line-shaped edges of the opening 104, and at the constriction portions 107, the silicon layer 102 becomes less in film thickness to form a tunnel barrier through quantum size effect in the layer thickness direction. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a single-electron turn style device capable of transferring one electron and a method for manufacturing the same.

  When considered as an electronic device, the single-electron turn-style device can achieve the ultimate low power consumption and can reliably transmit one electron. By connecting multiple single-electron turn-style devices, for example, sending one electron and judging the logic when it is sent, or determining the memory state when there is one electron, etc. Conceivable. Note that the number of electrons to be sent is not limited to one, and a plurality of electrons can be sent.

  In addition, the single-electron turn style device can be integrated because it is a requirement that the device be a small size device. Further, since the power consumption is low, the degree of integration is not limited by the power consumption. Moreover, since electrons can be sent one by one in one transfer process, if the number of transfers in one second is increased, a current that can be read as a current using a commercially available ammeter can be passed. At present, there is no stable and accurate standard current source, but this can be realized by a single-electron turn-style device.

  By the way, at present, the size of the manufactured single-electron turn-style device is determined by the lithography technique and cannot be made very small. For this reason, it can be operated only at an extremely low temperature of 1 K or less in absolute temperature (see Non-Patent Document 1).

  Here, the example of the manufacturing method of the present main single electron turn style device is demonstrated using FIG. 13A-FIG. 13F. 13A, 13C, and 13E schematically show a cross-section during manufacture, and FIGS. 13B, 13D, and 13F show a plane during manufacture. 13A, 13C, and 13E are cross-sectional views taken along line XX 'of FIGS. 13B, 13D, and 13F.

  First, a well-known SOI (Silicon on Insulator) substrate is prepared. 13A (13B) shows a buried insulating layer 1301 and a surface silicon layer 1302 of the SOI substrate. Here, a case where silicon is used will be described. Although turn-style devices using other materials have also been proposed, the use of silicon as the material enables the use of cutting-edge microfabrication technology, which makes it possible to manufacture devices with relatively good reproducibility. is there.

  Next, by processing the surface silicon layer 1302, as shown in FIGS. 13C and 13D, a pattern layer 1302a in which three island regions are connected in series is formed. Each of the three island regions becomes a single electron island. Single electron islands are small conductor islands that can store charge.

  Next, the surface of the pattern layer 1302a is oxidized to form a surface oxide layer 1303 as shown in FIGS. 13E and 13F, and a top gate electrode 1304 disposed in a region corresponding to the upper portion of the central single electron island is formed. Form. Oxidation for forming the surface oxide layer 1303 makes the narrow portions between the three single electron islands and the thin portions connecting the single electron islands at both ends and the electrode portions thinner. Thereby, in a thin part, a quantum size effect arises, potential becomes high, an electron becomes difficult to pass, and a potential barrier can be made. This works as a tunnel barrier.

  Therefore, as shown in the equivalent circuit of FIG. 14, three single electron islands 1401 are connected in series between the wide electrode portions at both ends of the patterned layer 1302a made of silicon, and the tunnel capacitor 1402 is connected between the single electron islands 1401. Are connected. Further, a top gate electrode 1403 is provided on the central single electron island 1401.

  By the way, the size of the thin portion that becomes the above-described tunnel capacitor or the like is the smallest pattern size that can be produced by the current lithography technique. For this reason, the size of the single electron island is always larger than this. In the conventional technique described above, a single electron island cannot be produced with the minimum dimension of lithography, and the single electron island size is limited to 100 nm to several 100 nm.

  It is the size of the single-electron island that determines the upper limit temperature at which the single-electron turn-style device operates, and the smaller the single-electron island, the higher the temperature that can be operated. Thus, it can be operated only at an extremely low temperature of 1 K or less in absolute temperature.

  Further, the equivalent circuit shown in FIG. 14 shows that there is no capacitive coupling between the top gate 1403 and the two left and right single electron islands 1401. However, as is apparent from the actual structure shown in FIG. 13F and the like, as shown in FIG. 15, the top gate 1403 and the two left and right single electron islands 1401 should also have a coupling capacitance. Since these coupling capacitors are separated from the top gate 1403, the capacitances C1 and C3 in FIG. 15 are smaller than the capacitance C2. Thus, since it is also necessary that the conditions of C2> C1 and C3 are satisfied, the top gate 1403 is formed only on the center single-electron island 1401 and is disposed on the single-electron island 1401 on both ends. It is important not to be done.

  For this purpose, the accuracy of pattern alignment between lithography for forming single electron islands and lithography for forming top gates is increased, and lithography for forming top gates is also as small as lithography for forming single electron islands. It is necessary to be able to form a pattern.

T, Altebaemer, and H, Ahmed, "Characteristics of Electron Pump Circuit Using Silicon Multiple Tunnel Junction", Jpn. J. Apple. Phys., Vol.40, pp.80-82, 2001. S. Horiguchi, et al., "Mechanism of Potential Profile Formation in Silicon Single-Electron Transistor Fabricated Using Pattern-Dependent Oxidation", Jpn. J. Apple. Phys., Vol.40, pp.L29-L32, 2001. Y. Takahashi, et al., "Silicon single-electron devices", JOURNAL OF PHYSICS: CONDENSED MATTER, vpl.14, pp.R995-R1033, 2002.

  As explained above, current single-electron turn-style devices cannot make small single-electron islands that are close to the limits of lithography, and top gates can be placed with high accuracy on single-electron islands. There is a problem that it is not easy.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to make it possible to produce a smaller single-electron island and to arrange a top gate without requiring high accuracy. And

  The method for manufacturing a single-electron turn-style device according to the present invention includes a first step of forming a silicon layer on an insulating layer, and forming at least a silicon oxide layer on the silicon layer, and a layer above the silicon layer. A second step of forming the opening, a third step of reducing the layer thickness of the silicon layer in the region of the opening, and facing each other in the center of the opening, leaving two opposite ends of the opening A fourth step of forming two groove portions that reach the insulating layer and forming a thin line portion in the silicon layer sandwiched between the two groove portions; and oxidizing the silicon layer by thermal oxidation to reduce the layer thickness The silicon layer under the outer edge of the end portion is formed with two constricted portions that are thinner than the other regions, and a tunnel barrier is formed at both ends of the thin line portion and the silicon layers of the two constricted portions. Between the two ends of the The central portion of each and fine line portions of the con layer, a fifth step of forming a single-electron island, on the fine line portion comprises at least a sixth step of forming a gate electrode.

  In the method for manufacturing a single-electron turnstyle device, in the first step, a silicon layer and a silicon oxide layer are formed on the insulating layer, and in addition, a silicon nitride layer is formed on the silicon oxide layer. Then, an opening that penetrates may be formed in the silicon nitride layer.

  In the method for manufacturing a single-electron turn-style device, in the third step, the upper layer of the silicon layer may be oxidized by thermal oxidation to reduce the thickness of the silicon layer in the region of the opening.

  In the method for manufacturing a single-electron turnstyle device, an opening having a depth reaching the silicon layer may be formed in the second step. In the second step, an opening having a depth up to the middle of the silicon layer may be formed.

  In the method for manufacturing a single-electron turn-style device, in the third step, the upper layer of the silicon layer may be etched through the opening to reduce the thickness of the silicon layer in the region of the opening.

  In the method for manufacturing a single-electron turn-style device described above, the outer edge portion of the end portion may be formed in a curved shape in plan view.

  The single-electron turnstyle device according to the present invention includes a silicon layer formed on an insulating layer, a silicon oxide layer formed on the silicon layer, and a silicon layer facing the planar direction of the silicon layer. The two constricted portions thinner than the other regions formed in this manner, and the two groove portions that are arranged to face each other in the region between the two constricted portions perpendicular to the arrangement direction of the two constricted portions and reach the insulating layer And a thin line portion formed in the silicon layer sandwiched between the two groove portions, and a gate electrode formed on the thin line portion, the constricted portion corresponding to the constricted portion formed in the upper layer of the silicon layer Formed by oxidizing the upper layer of the silicon layer by thermal oxidation through an opening having at least two opposing edges, and forming the constricted portion after forming the groove portion. Silicon layer is the layer thickness of the quantum size effect.

  In the single-electron turn style device, the two opposing edges may be formed in a curved shape in plan view.

  As described above, according to the present invention, the two constricted portions thinner than the other regions formed in the silicon layer so as to face the planar direction of the silicon layer are the constricted portions formed in the upper layer of the silicon layer. The silicon in the constricted part is formed by oxidizing the upper layer of the silicon layer by thermal oxidation through an opening having at least two corresponding opposing edges, and forming the constricted part after forming the groove part. Since the layers are made to have a layer thickness that produces a quantum size effect, it is possible to produce smaller single electron islands and to have an excellent effect that a top gate can be arranged without requiring high accuracy. can get.

It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention (plane). It is explanatory drawing for demonstrating the structure of the single electron turnstyle device in Embodiment 1 of this invention. It is explanatory drawing for demonstrating the structure of the single electron turnstyle device in Embodiment 1 of this invention (plane). It is explanatory drawing for demonstrating the structure of the single electron turnstyle device in Embodiment 1 of this invention (cross section). It is a circuit diagram which shows the equivalent circuit of a single electron turn style device. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention (plane). It is explanatory drawing for demonstrating the structure of the single electron turnstyle device in Embodiment 4 of this invention. It is explanatory drawing for demonstrating the structure of the single electron turnstyle device in Embodiment 4 of this invention (plane). It is explanatory drawing for demonstrating the structure of the single electron turnstyle device in Embodiment 4 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 5 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 5 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 5 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 5 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 5 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 5 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 6 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 6 of this invention (cross section). It is process drawing for demonstrating the manufacturing method in Embodiment 6 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 6 of this invention (plane). It is process drawing for demonstrating the manufacturing method in Embodiment 6 of this invention (cross section). It is process drawing for demonstrating the single electron turn style device manufacturing method (cross section). It is process drawing for demonstrating the single electron turn style device manufacturing method (plane). It is process drawing for demonstrating the single electron turn style device manufacturing method (cross section). It is process drawing for demonstrating the single electron turn style device manufacturing method (plane). It is process drawing for demonstrating the single electron turn style device manufacturing method (cross section). It is process drawing for demonstrating the single electron turn style device manufacturing method (plane). It is a circuit diagram which shows the equivalent circuit of a single electron turn style device. It is a circuit diagram which shows the equivalent circuit of a single electron turn style device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described together with a manufacturing method. First, as shown in FIG. 1A, a substrate including an insulating layer 101 and a silicon layer 102 is prepared. For example, an SOI substrate can be used. The buried insulating layer (silicon oxide layer) of the SOI substrate becomes the insulating layer 101, and the surface silicon layer becomes the silicon layer 102. When such a substrate is prepared, a silicon oxide layer 103 is formed on the silicon layer 102. For example, the silicon oxide layer 103 may be formed by thermally oxidizing the surface of the silicon layer 102. Alternatively, silicon oxide may be deposited on the silicon layer 102 by a well-known chemical vapor deposition (CVD) method. The silicon layer 102 may have a thickness of about 10 to 50 nm, and the silicon oxide layer 103 may have a thickness of about 10 to 30 nm.

  Next, as shown in FIGS. 1B and 1C, an opening 104 is formed in the silicon oxide layer 103 in a region including a portion where a thin line portion to be described later is formed. FIG. 1B shows a cross section taken along line XX ′ of FIG. 1C. Here, the planar shape of the two edge portions sandwiching the region where the thin line portion described later is formed is preferably composed of semicircles having the same diameter. Moreover, you may be comprised by a part of circular arc. For example, a resist pattern having an opening corresponding to the opening 104 may be formed by a well-known lithography technique, and the silicon oxide layer 103 may be selectively removed by a known etching technique using the resist pattern as a mask. The opening 104 may be formed partway through the silicon oxide layer 103. Note that the opening 104 may be formed until the silicon layer 102 is reached.

  The dimension of the planar shape of the opening 104 is about several tens to several hundreds of nanometers in the left-right direction (direction in which the thin line extends) in FIGS. 1B and 1C. This dimension defines the length in the extending direction of the thin wire described later. Since three single electron islands are arranged in the extending direction of the thin wire, the length of the extending direction of the thin wire may be determined in consideration of this. Further, the vertical dimension in FIGS. 1B and 1C may be about several times the desired width of the thin line.

  Next, after removing the resist pattern described above, the upper layer portion of the silicon layer 102 is thermally oxidized through the silicon oxide layer 103 to thin the silicon layer 102 as shown in FIG. 1D. This oxidation is caused by the fact that an oxidizing substance such as oxygen diffuses in the silicon oxide layer 103 and reacts with silicon in the silicon layer 102. For this reason, in the region of the opening 104 where the silicon oxide layer 103 is thin, the lower silicon layer 102 has a faster oxidation rate than other regions and becomes thinner. As a result, a thin line forming region 106 having a thinner thickness than other regions is formed in the silicon layer 102 in the region below the opening 104.

  By the way, the opening 104 is formed until reaching the silicon layer 102, and the opening 104 is formed to a depth halfway through the silicon layer 102, whereby the silicon layer 102 layer in the region of the opening 104 is formed. The thickness can be made thinner compared to other areas.

  Next, as shown in FIG. 1E and FIG. 1F, they are arranged opposite to each other at two positions sandwiching the fine wire forming region 106 (opening 104) perpendicular to the extending direction of the fine wire to be formed. Two groove portions 105 are formed. FIG. 1F shows a cross section taken along line XX ′ of FIG. 1E. The groove 105 is formed until it reaches the insulating layer 101. Further, the groove portion 105 is formed so as to enter the central portion of the fine line forming region 106 while leaving two opposing end portions. By forming these two groove portions 105, the thin line portion 106 a is formed by the silicon layer 102 between the opposed groove portions 105. The width of the thin line portion 106a is defined by the distance between the two groove portions 105 facing each other. In FIG. 1E, reference numeral 104 ′ is an imaginary line that virtually indicates the outer edge of the two opposing ends in the opening 104, and is hereinafter referred to as the edge 104 ′.

  In the formation of the groove 105, for example, a resist pattern having an opening corresponding to the groove 105 is formed by a well-known lithography technique, and the silicon oxide layer 103 and the silicon layer 102 are formed by a known etching technique using this resist pattern as a mask. It may be selectively removed by etching. In FIG. 1E, the groove 105 extends in the vertical direction (the direction away from the thin line portion 106a) in FIG. 1E beyond the range shown in the drawing, but the present invention is not limited to this. The length in the direction away from the thin wire portion 106a may be shorter than the length in the extending direction of the thin wire portion 106a.

  Next, after removing the resist pattern described above, the upper layer portion of the silicon layer 102 is thermally oxidized again through the silicon oxide layer 103 to make the silicon layer 102 thinner as shown in FIG. 1G. For example, thermal oxidation may be performed under a temperature condition of about 800 ° C. to 1200 ° C.

  By this oxidation step, a constriction 107 constricted in the layer thickness direction is formed in the vicinity of the inside of the region under the two curved edges 104 ′ of the opening 104, as shown in FIGS. 1G and 1H. In the portion 107, the thickness of the silicon layer 102 becomes thinner, and a tunnel barrier is formed by the quantum size effect in the layer thickness direction. FIG. 1G shows a cross section taken along line XX ′ of FIG. 1H.

  Further, in the oxidation step, two groove portions 105 that are opposed to each other with the fine wire portion 106a interposed therebetween are formed, so that a tunnel barrier is also formed at the end of the region of the fine wire portion 106a that is sandwiched between the two groove portions 105. Will come to be.

  As described above, one single electron island is formed in the region of the thin wire portion 106 a sandwiched between the two groove portions 105, and each single region is formed in the two regions between the both ends of the thin wire portion 106 a and the two constricted portions 107. An electronic island is formed. Three single electron islands are formed in total.

  Next, as shown in FIGS. 1I and 1J, the gate electrode 109 is formed so as to cover at least the region of the thin line portion 106a sandwiched between the two groove portions 105. FIG. 1I shows a cross section XX ′ of FIG. 1J. Here, the gate electrode 109 is formed in a state in which the entire thin line portion 106a is covered. The gate electrode 109 becomes a top gate. By forming the gate electrode 109 in this manner, a single electron turn style device can be obtained.

  Next, it will be described in more detail that the above-described three single electron islands are formed in two regions between the narrow wire portion 106a and both ends of the thin wire portion 106a and the two constricted portions 107, respectively.

  First, in the oxidation step after forming the two groove portions 105, there are two groove portions 105 facing each other with the fine wire portion 106a interposed therebetween. Therefore, this oxidation is equivalent to a known pattern-dependent oxidation method (PADOX method). (See Non-Patent Documents 2 and 3). As a result, a tunnel barrier is formed at the end of the region of the fine line portion 106 a sandwiched between the two groove portions 105.

  The above-described formation of the two tunnel barriers by pattern-dependent oxidation will be described in more detail. First, in the fine line portion 106a, the potential energy is increased by the quantum size effect due to the fine line width (the size of the fine line in the direction perpendicular to the extending direction in the plane of the silicon layer 102). However, in the region of the fine wire portion 106a sandwiched between the two groove portions 105, more oxidation occurs due to the presence of the groove portion 105, and a strong compressive stress acts due to this oxidation.

  Due to this compressive stress, as shown in FIG. 2C, in the region 201 of the thin wire portion 106a sandwiched between the two groove portions 105, the band gap in the central portion decreases, and the potential energy also decreases accordingly. . As a result, in the region 201 of the thin wire portion 106a sandwiched between the two groove portions 105, a structure in which a potential barrier is left is formed at both ends on the constricted portion 107 side, and the region in which this potential barrier remains is used as a tunnel barrier. Become functional. As a result, a single electron island is formed at the center of the region 201 where the potential energy is reduced.

  Next, the formation of a tunnel barrier at the constricted portion 107 will be described. In the oxidation process after forming the two groove portions 105, the silicon layer 102 is thinner than the silicon layer 102 in the other region due to the oxidation process performed previously. In this oxidation step, since the two groove portions 105 are formed, the insulating layer 101 is exposed at this portion. For this reason, in the oxidation step, an oxidizing substance such as oxygen diffuses in the insulating layer 101 in addition to the silicon oxide layer 103 to oxidize the silicon layer 102.

  When oxidized in this manner, in the region close to the two edge portions 104 ′ constituted by the curve of the region of the opening 104 that is thinner than the other regions, the closer to the end of the region of the thin line portion 106a, Oxidation does not proceed due to the stress accompanying the increase in volume due to oxidation, and oxidation proceeds more as the distance from the end portion increases. As a result, as shown in FIG. 2A, a constricted portion 107 constricted in the layer thickness direction is formed, and in the constricted portion 107, the silicon layer 102 becomes thinner. In the formation of the constricted portion 107, it is important to ensure a difference in oxidation rate to the extent that a level difference of the constricted portion 107 can be obtained in the oxidation after forming the groove portion 105 and forming the thin wire portion 106a. In this embodiment, by forming the opening 104, a difference is formed in the layer thickness of the silicon oxide layer 103, and the above-described difference in oxidation rate is obtained.

  The constricted portion 107 formed in this manner functions as a tunnel barrier by forming a region 202 having an increased potential energy as shown in FIG. 2C due to the quantum size effect in the layer thickness direction. As a result, the regions with low potential energy between both ends of the region 201 and the two regions 202 are sandwiched by the potential barriers, and single electron islands are formed in each region. Since the tunnel barrier in the region 202 can be controlled by controlling the thickness direction of the silicon layer by oxidation, etching, or the like, the tunnel barrier can be formed without being limited by the minimum dimension by the lithography technique.

  As described above, according to the present embodiment, as shown in FIGS. 3A and 3B, the single electron island 301 is formed at the center of the thin wire portion 106a, and the thin wire portion 106a and the two constricted portions 107 are formed. Single electron islands 302 are formed in the regions of the silicon layer 102 sandwiched between the layers. The single electron island 301 and the single electron island 302 are connected and arranged in series on a straight line with the single electron island 301 as the center. FIG. 3B shows a partial cross section of XX ′ of FIG. 3A.

  By the way, in the single-electron turn-style device according to the present embodiment described above, the gate electrode 109 is preferably formed so as to cover the center single-electron island, but overlaps the two single-electron islands on both sides. May be. This will be described below.

  The left and right single electron islands are capacitively coupled to the outer silicon layer 102 through a tunnel barrier formed by the constricted portion 107. On the other hand, the single-electron islands in the central part and the left and right single-electron islands are capacitively coupled via a tunnel barrier in a region where a potential barrier remains between them. As is clear from the plan view of FIG. 3A, the constricted portion 107 is longer than the boundary between the single-electron island in the center and the left and right single-electron islands, and the capacitance formed in the constricted portion 107 is greater. growing.

  For this reason, even if the gate electrode 109 is formed so as to cover three single electron islands, the left and right single electron islands are more strongly coupled to the outer silicon layer 102. Therefore, as shown in the equivalent circuit of FIG. 4, the coupling capacitance between the gate electrode and the left and right single electron islands is small, and the coupling capacitance between the gate electrode and the central single electron island is larger. Thus, according to the present embodiment, even when the gate electrode is formed so as to cover three single electron islands, a configuration in which capacitive coupling with the central single electron island is further strengthened is automatically formed. Will come to be. For this reason, according to the present embodiment, high dimensional accuracy and positional accuracy are not required even in the production of the gate electrode.

  By the way, if the groove part 105 is formed in the central part as far as possible with respect to the direction of the both edges constituted by the curve of the opening part 104, a central single electron island is formed corresponding to the formation position of the groove part 105. As a result, the left and right single-electron islands can be formed uniformly. In this way, by making the left and right single electron islands equal, electrons can be transferred in the same way in either direction.

  On the other hand, when single-electron islands of different sizes are formed on the left and right, when operating a single-electron turnstyle device, a difference occurs in the direction of sending electrons, resulting in a difference in operating margin. In this way, electrons can be selectively transferred in one direction.

  As described above, in this embodiment, a planar opening having curved edges at both edges is formed in the silicon oxide layer formed on the silicon layer, and, for example, by thermal oxidation. The thickness of the silicon layer in the opening is made thinner than other regions, and two groove portions facing each other so as to sandwich the opening are formed until the side portion of the silicon layer is exposed, and the thermal oxidation after forming the groove portion This is characterized in that the silicon layer is made thinner.

  Therefore, the single-electron turnstyle device of this embodiment includes a silicon layer 102 formed on the insulating layer 101, a silicon oxide layer 103 formed on the silicon layer 102, and a silicon layer 102 on the silicon layer 102. Two constricted portions 107 thinner than other regions formed opposite to each other in the plane direction, and disposed opposite to the region between the two constricted portions 107 perpendicular to the arrangement direction of the two constricted portions 107, The constricted portion includes at least two groove portions 105 reaching the insulating layer 101, a thin wire portion 106a formed in a silicon layer sandwiched between the two groove portions 105, and a gate electrode 109 formed on the thin wire portion 106a. 107 is an opening having at least two opposing edges corresponding to the constricted portion 107 formed in the upper layer of the silicon layer 102 after the groove portion 105 is formed. It is formed by oxidizing the upper layer of the silicon layer 102 by thermal oxidation through the portion 104, and the silicon layer 102 in the constricted portion 107 is made to have a layer thickness that causes a quantum size effect by thermal oxidation to form the constricted portion 107. Yes.

  As a result, first, a constricted portion with a thinner layer thickness is formed in the silicon layer at a location corresponding to both curved edges of the opening, and a tunnel barrier is formed here. . In addition, tunnel barriers are formed at both ends of the fine wire portion on both sides of the fine wire portion formed in the silicon layer sandwiched between the groove portions due to a decrease in potential energy at the central portion of the fine wire portion due to oxidation in the presence of the groove portion. Will come to be. As a result, in this embodiment, two single-electron islands are formed between the tunnel barriers of the two constricted portions and the tunnel barriers at both ends of the thin wire portion, and one is also formed in the central portion of the thin wire portion. Single-electron islands are formed. Further, these three single electron islands are connected in series on a straight line.

[Embodiment 2]
Next, a second embodiment of the present invention will be described.

  First, as shown in FIGS. 5A and 5B, a substrate including an insulating layer 501 and a silicon layer 502 is prepared. FIG. 5A shows a cross section taken along line XX ′ of FIG. 5B. For example, an SOI substrate can be used. The buried insulating layer (silicon oxide layer) of the SOI substrate becomes the insulating layer 501 and the surface silicon layer becomes the silicon layer 502. When such a substrate is prepared, a silicon oxide layer 503 is formed on the silicon layer 502. The silicon oxide layer 503 may be formed by thermally oxidizing the surface of the silicon layer 502, for example. Alternatively, silicon oxide may be deposited on the silicon layer 502 by a well-known chemical vapor deposition (CVD) method. The silicon layer 502 may have a thickness of about 10 nm, and the silicon oxide layer 503 may have a thickness of about 10 nm.

  Next, as shown in FIGS. 5A and 5B, an opening 504 in which at least both edges in the direction in which the thin line is extended is formed in a curved line is formed in the silicon oxide layer 503 at the position where the thin line to be described later is formed. To do. For example, a resist pattern having an opening corresponding to the opening 504 may be formed by a well-known lithography technique, and the silicon oxide layer 503 may be selectively removed by a known etching technique using the resist pattern as a mask. The opening 504 is formed partway through the silicon layer 502. The resist pattern is removed after the opening 504 is formed.

  First, the dimension of the planar shape of the opening 504 is about several tens to several hundreds of nanometers in the left-right direction in FIG. 5B (the direction in which the thin line extends). This dimension defines the length in the extending direction of the thin wire described later. Since three single electron islands are arranged in the extending direction of the thin wire, the length of the extending direction of the thin wire may be determined in consideration of this. Further, the vertical dimension in FIG. 5B may be about several times the desired width of the thin line.

  Next, as shown in FIGS. 5C and 5D, two groove portions 505 that are arranged to face each other are formed at two locations that sandwich the opening portion 504 perpendicular to the extending direction of the thin wire to be formed. To do. FIG. 5C shows a cross section taken along line XX ′ of FIG. 5D. The groove portion 505 is formed until the insulating layer 501 is reached. The groove portion 505 is formed so as to enter the central portion of the opening portion 504 while leaving the region of the silicon layer 502 exposed at the ends of both edge portions formed by the curve of the opening portion 504. By forming these two groove portions 505, a thin line portion 506 is formed by the silicon layer 502 between the facing groove portions 505. The width of the thin line portion 506 is defined by the distance between the two groove portions 505 facing each other.

  In the formation of the groove portion 505, for example, a resist pattern having an opening corresponding to the groove portion 505 is formed by a well-known lithography technique, and the silicon oxide layer 503 and the silicon layer 502 are formed by a known etching technique using this resist pattern as a mask. It may be selectively removed by etching. In FIG. 5C, the groove portion 505 extends in the vertical direction (the direction away from the thin wire portion 506) in FIG. 5C beyond the range shown in the figure, but is not limited thereto. The length in the direction away from the thin wire portion 506 may be shorter than the length in the extending direction of the thin wire portion 506.

  Next, after removing the resist pattern described above, the upper layer portion of the silicon layer 502 is thermally oxidized through the silicon oxide layer 503 to thin the silicon layer 502 as shown in FIG. 5E. For example, thermal oxidation may be performed under a temperature condition of about 800 ° C. to 1200 ° C.

  By this oxidation step, a constricted portion 507 constricted in the layer thickness direction is formed in the vicinity of the inside of the curved boundary corresponding to both curved edges of the opening 504, and the silicon layer 502 is formed in the constricted portion 507. It becomes thinner and a tunnel barrier is formed.

  In the oxidation step, since the two groove portions 505 that face each other with the fine wire portion 506 interposed therebetween are formed, a tunnel barrier is also formed at the end portion of the region of the fine wire portion 506.

  As described above, one single electron island is formed in the region of the thin wire portion 506 sandwiched between the two groove portions 505, and each of the two regions between the both ends of the thin wire portion 506 and the two constricted portions 507 is single. An electronic island is formed. Three single electron islands are formed in total.

  As described above, after the formation of the three single electron islands, the region of the single electron island in the central part formed in at least the thin line portion 506 is covered by the same process as in the first embodiment. If a gate electrode is formed, a single-electron turn-style device can be obtained.

  In the present embodiment, a planar opening having curved edges at opposite edges is formed in the silicon oxide layer formed on the silicon layer, and by forming this opening, the silicon layer in the opening is formed. The layer thickness is made thinner than other regions, and two groove portions facing each other so as to sandwich this opening are formed until the side portion of the silicon layer is exposed, and the silicon layer is formed by thermal oxidation after forming the groove portions. It is characterized by making it thinner.

  Also in this embodiment, by forming the opening (opening 504), a difference is formed in the thickness of the silicon oxide layer over the silicon layer, and a difference in oxidation rate for forming the constricted portion is obtained. I have to. In this embodiment, since the thickness of the silicon layer is reduced by forming the opening, the thermal oxidation process is performed once, and the thermal oxidation process is reduced as compared with the first embodiment described above. be able to.

[Embodiment 3]
In the above description, the opening is formed partway through the silicon layer. However, the opening may be formed in the silicon oxide layer until the surface of the silicon layer is exposed.

  For example, first, as shown in FIG. 6A, a substrate including an insulating layer 601 and a silicon layer 602 is prepared. When such a substrate is prepared, a silicon oxide layer 603 is formed on the silicon layer 602. Next, as shown in FIGS. 6B and 6C, in the silicon oxide layer 603, an opening 604 in which both edges in the direction in which the fine line is extended is configured with a curve is formed at a position where the fine line is to be formed. The opening 604 is formed until the surface of the silicon layer 602 is exposed. FIG. 6B shows a cross section XX ′ of FIG. 6C.

  Next, as shown in FIG. 6D, two groove portions 605 arranged opposite to each other are formed at two locations sandwiching the opening 604 perpendicular to the extending direction of the thin wire to be formed. The groove portion 605 is formed until reaching the insulating layer 601. The groove portion 605 is formed so as to enter the central portion of the opening portion 604 while leaving the silicon layer 602 exposed at the ends of both edge portions formed by the curve of the opening portion 604. By forming these two groove portions 605, a thin line portion 606 is formed by the silicon layer 602 between the groove portions 605 facing each other. The width of the thin line portion 606 is defined by the distance between the two groove portions 605 facing each other.

  After forming the groove portion 605 and the thin wire portion 606 as described above, the upper layer portion of the silicon layer 602 is thermally oxidized through the silicon oxide layer 603 to reduce the thickness of the silicon layer 602, as in the second embodiment. . By this oxidation process, a constricted portion constricted in the layer thickness direction is formed in the vicinity of the inside of the curved boundary corresponding to both edges of the opening 604, and the silicon layer 602 becomes thinner in the constricted portion, and the tunnel A barrier is formed.

  In the oxidation step, since the two groove portions 605 that are opposed to each other with the fine wire portion 606 interposed therebetween are formed, a tunnel barrier is also formed at the end portion of the region of the fine wire portion 606.

  As described above, one single electron island is formed in the region of the thin wire portion 606 sandwiched between the two groove portions 605, and each single electron is formed in the two regions between the both ends of the thin wire portion 606 and the two constricted portions. An island is formed. Three single electron islands are formed in total.

  In the present embodiment, by controlling the amount of thermal oxidation described above, the layer thickness of the fine line portion 606 and the step amount of the constricted portion are controlled. Also in this embodiment, since the opening 604 is formed, a step is formed in the silicon oxide layer 603 and a difference can be formed in the oxidation rate of the silicon layer 602 in the thermal oxidation. Similar results are obtained.

[Embodiment 4]
Next, a fourth embodiment of the present invention will be described. First, as shown in FIG. 7A, a substrate including an insulating layer 701 and a silicon layer 702 is prepared. For example, an SOI substrate can be used. The buried insulating layer (silicon oxide layer) of the SOI substrate becomes the insulating layer 701 and the surface silicon layer becomes the silicon layer 702. When such a substrate is prepared, a silicon oxide layer 703 and a silicon nitride layer 704 are formed over the silicon layer 702. For example, the silicon oxide layer 703 may be formed by thermally oxidizing the surface of the silicon layer 702.

Alternatively, silicon oxide may be deposited on the silicon layer 702 by a well-known chemical vapor deposition (CVD) method. The silicon nitride layer 704 can be formed by a CVD method using a nitrogen-based gas and a silane-based gas. The silicon nitride is Si ₃ N ₄ stoichiometrically, but may be a silicon nitride layer 704 having a composition deviating from this. The silicon layer 702 may have a thickness of about 10 nm, the silicon oxide layer 703 may have a thickness of about 10 nm, and the silicon nitride layer 704 may have a thickness of about 10 nm.

  Next, as shown in FIGS. 7B and 7C, an opening 705 in which at least both edges in the direction in which the thin line is extended is formed in the silicon nitride layer 704 at a position where the thin line to be described later is formed is formed. To do. FIG. 7B shows a cross section taken along line XX ′ of FIG. 7C. For example, a resist pattern having an opening corresponding to the opening 705 may be formed by a well-known lithography technique, and the silicon nitride layer 704 may be selectively removed by a known etching technique using the resist pattern as a mask. The opening 705 is formed until the surface of the silicon oxide layer 703 is exposed.

  The dimension of the planar shape of the opening 705 is about several tens to several hundreds of nanometers in the left-right direction (direction in which the thin line extends) in FIGS. 7B and 7C. This dimension defines the length in the extending direction of the thin wire described later. Since three single electron islands are arranged in the extending direction of the thin wire, the length of the extending direction of the thin wire may be determined in consideration of this. Further, the vertical dimension in FIGS. 7B and 7C may be about several times the desired width of the thin line.

  Next, after removing the resist pattern described above, the upper layer portion of the silicon layer 702 is thermally oxidized through the silicon oxide layer 703 exposed in the opening portion 705, and as shown in FIG. 7D, silicon in the region of the opening portion 705 is obtained. Layer 702 is thinned. This oxidation is caused by diffusion of an oxidizing substance such as oxygen in the silicon oxide layer 703 and reaction with silicon in the silicon layer 702. For this reason, in the region of the opening 705 where the silicon oxide layer 703 is exposed, the lower silicon layer 702 has a faster oxidation rate and is thinner than the other regions. On the other hand, since the silicon nitride layer 704 hardly transmits an oxidizing substance, the silicon layer 702 in the region covered with the silicon nitride layer 704 is substantially suppressed from being oxidized. These are the same as the well-known LOCOS (LoCal Oxidation of Silicon) technique.

  As a result, a thin line forming region 707 having a thinner layer thickness than other regions is formed in the silicon layer 702 in the region below the opening 705. Note that the silicon oxide layer 703 becomes thicker in the opening 705. As a result, a step is formed in the silicon oxide layer 703 between the region of the opening 705 and the periphery thereof.

  Next, as shown in FIG. 7E, two groove portions disposed opposite to each other at two locations sandwiching the fine wire forming region 707 (opening portion 705) perpendicular to the extending direction of the fine wire to be formed. 706 is formed. The groove 706 is formed until it reaches the insulating layer 701. Further, the groove portion 706 is formed so as to enter the central portion of the fine line forming region 707 while leaving two oppositely arranged edge portions 705 ′ configured by curves of the fine line forming region 707. By forming these two groove portions 706, a thin line portion 707a is formed by the silicon layer 702 between the opposed groove portions 706. The width of the thin line portion 707a is defined by the distance between the two groove portions 706 facing each other.

  In the formation of the groove 706, for example, a resist pattern having an opening corresponding to the groove 706 is formed by a well-known lithography technique, and the silicon nitride layer 704 and the silicon oxide layer 703 are formed by a known etching technique using this resist pattern as a mask. , And the silicon layer 702 may be selectively removed by etching. In FIG. 7E, the groove portion 706 extends beyond the range shown in the vertical direction of FIG. 7E (a direction away from the thin line portion 707a), but the present invention is not limited to this. The length in the direction away from the thin wire portion 707a may be shorter than the length in the extending direction of the thin wire portion 707a.

  Next, after removing the resist pattern described above, the upper layer portion of the silicon layer 702 is thermally oxidized again through the silicon oxide layer 703, so that the silicon layer 702 is made thinner as shown in FIG. 7F. For example, thermal oxidation may be performed under a temperature condition of about 800 ° C. to 1200 ° C.

  By this oxidation step, a constricted portion 708 constricted in the layer thickness direction is formed in the vicinity of the inner side corresponding to the curved edge portion 705 ′ of the silicon layer 702, as shown in FIGS. 7F and 7G. The layer thickness of the silicon layer 702 becomes thinner, and a tunnel barrier is formed by the quantum size effect in the layer thickness direction. FIG. 7F shows a cross section XX ′ of FIG. 7G.

  Further, in the oxidation step, two groove portions 706 that are opposed to each other with the fine wire portion 707a interposed therebetween are formed, so that a tunnel barrier is also formed at the end of the region of the fine wire portion 707a sandwiched between the two groove portions 706. Will come to be.

  As described above, one single electron island is formed in the region of the thin wire portion 707a sandwiched between the two groove portions 706, and each of the two regions between the both ends of the thin wire portion 707a and the two constricted portions 708 is single. An electronic island is formed. Three single electron islands are formed in total.

  Here, it will be described in more detail that the above-described three single electron islands are formed in two regions between the narrow wire portion 707a and both ends of the thin wire portion 707a and the two constricted portions 708, respectively.

  First, in the oxidation step after the formation of the two groove portions 706, there are two groove portions 706 that are opposed to each other with the fine wire portion 707a interposed therebetween. Therefore, this oxidation is equivalent to a known pattern-dependent oxidation method (PADOX method). (See Non-Patent Documents 2 and 3). As a result, a tunnel barrier is formed at the end of the region of the thin line portion 707a sandwiched between the two groove portions 706.

  The above-described formation of the two tunnel barriers by pattern-dependent oxidation will be described in more detail. First, in the fine line portion 707a, the potential energy is increased by the quantum size effect due to the fine line width (the size of the fine line in the direction perpendicular to the extending direction in the plane of the silicon layer 102) being thin. However, in the region of the thin wire portion 707a sandwiched between the two groove portions 706, more oxidation is caused by the presence of the groove portion 706, and a strong compressive stress is caused by this oxidation.

  Due to this compressive stress, as shown in FIG. 8C, in the region 801 of the thin wire portion 707a sandwiched between the two groove portions 706, the band gap in the central portion is reduced, and accordingly, the potential energy is also reduced. . As a result, in the region 801 of the thin wire portion 707a sandwiched between the two groove portions 706, a structure in which a potential barrier is left is formed at both ends on the constricted portion 708 side, and the region in which this potential barrier remains is used as a tunnel barrier. Become functional. As a result, a single electron island is formed at the center of the region 801 where the potential energy is reduced.

  Next, the formation of a tunnel barrier at the constricted portion 708 will be described. In the oxidation process after forming the two groove portions 706, the silicon layer 702 is thinner than the silicon layer 702 in other regions due to the oxidation process performed previously. In this oxidation step, since the two groove portions 706 are formed, the insulating layer 701 is exposed in this portion. For this reason, in the oxidation step, in addition to the silicon oxide layer 703 exposed between the facing edge portions 705 ′, the insulating layer 701 exposed in the groove portion 706 contains an oxidizing substance such as oxygen. Will diffuse and oxidize the silicon layer 702.

  When oxidized in this way, in the region near the edge portion 705 ′ that is thinner than the other regions, the oxidation does not proceed due to the stress accompanying the increase in volume due to the oxidation, as it approaches the end of the thin line portion 707a. The further the oxidation is, the further away from the end. As a result, as shown in FIG. 8A, a constricted portion 708 narrowed in the layer thickness direction is formed, and the silicon layer 702 becomes thinner in the constricted portion 708. In the formation of the constricted portion 708, it is important to secure a difference in oxidation rate to the extent that a level difference of the constricted portion 708 can be obtained in the oxidation after forming the groove portion 706 and forming the thin wire portion 707a. In this embodiment, the above-described difference in oxidation rate is obtained by performing thermal oxidation in a state where the silicon nitride layer 704 including the opening 705 (edge 705 ′) and the groove 706 is used as a mask.

  The constricted portion 708 formed in this way functions as a tunnel barrier by forming a region 802 with increased potential energy as shown in FIG. 8C due to the quantum size effect in the layer thickness direction. As a result, a region having a low potential energy between both ends of the region 801 and the two regions 802 is sandwiched between potential barriers, and single electron islands are formed in each region. Since the tunnel barrier in the region 802 can be formed by controlling the thickness direction of the silicon layer by oxidation, etching, or the like, the tunnel barrier can be formed without being limited by the minimum dimension by the lithography technique.

  As described above, according to the present embodiment, as shown in FIGS. 9A and 9B, the single electron island 901 is formed at the center of the thin wire portion 707a, and the thin wire portion 707a and the two constricted portions 708 are formed. Single-electron islands 902 are formed in the region of the silicon layer 702 sandwiched between the layers. The single electron island 901 and the single electron island 902 are connected in series on a straight line with the single electron island 901 as the center. FIG. 9B shows a partial cross section of XX ′ of FIG. 9A.

  As described above, after the three single-electron islands are formed, as shown in FIGS. 10A and 10B, at least the region of the thin line portion 707a sandwiched between the two groove portions 706 is covered. A gate electrode 709 is formed. FIG. 10A shows a cross section XX ′ of FIG. 10B. Here, the gate electrode 709 is formed in a state where the entire area of the thin line portion 707a is covered. The gate electrode 709 becomes a top gate. By forming the gate electrode 709 in this way, a single-electron turn style device is obtained.

  By the way, in the single-electron turn-style device in this embodiment described above, the gate electrode 709 is preferably formed so as to cover the center single-electron island, but overlaps the two single-electron islands on both sides. May be. This will be described below.

  The left and right single electron islands are capacitively coupled to the outer silicon layer 702 through a tunnel barrier formed by the constricted portion 708. On the other hand, the single-electron islands in the central part and the left and right single-electron islands are capacitively coupled via a tunnel barrier in a region where a potential barrier remains between them. As is clear from the plan view of FIG. 9A, the constricted portion 708 is longer than the boundary between the single-electron island in the central portion and the left and right single-electron islands, and the capacitance formed in the constricted portion 708 is greater. growing.

  For this reason, even if the gate electrode 709 is formed so as to cover three single electron islands, the left and right single electron islands are more strongly coupled to the outer silicon layer 702. Therefore, as shown in the equivalent circuit of FIG. 4, the coupling capacitance between the gate electrode and the left and right single-electron islands is small, and the coupling capacitance between the gate electrode and the central single-electron island is larger. Thus, according to the present embodiment, even when the gate electrode is formed so as to cover three single electron islands, a configuration in which capacitive coupling with the central single electron island is further strengthened is automatically formed. Will come to be. For this reason, according to the present embodiment, high dimensional accuracy and positional accuracy are not required even in the production of the gate electrode.

  By the way, when the groove 706 is formed in the center as far as possible with respect to the direction of the edge formed by the curve of the opening 705, a central single electron island is formed corresponding to the position where the groove 706 is formed. As a result, the left and right single electron islands can be formed uniformly. In this way, by making the left and right single electron islands equal, electrons can be transferred in the same way in either direction.

  On the other hand, when single-electron islands of different sizes are formed on the left and right, when operating a single-electron turnstyle device, a difference occurs in the direction of sending electrons, resulting in a difference in operating margin. In this way, electrons can be selectively transferred in one direction.

  As described above, in the present embodiment, a planar opening having a curved edge is formed in the silicon nitride layer formed on the silicon oxide layer on the silicon layer, and For example, the thickness of the silicon layer in the opening is made thinner than other regions by, for example, thermal oxidation, and two grooves facing each other so as to sandwich the opening are formed until the side of the silicon layer is exposed, thereby forming the groove. It is characterized in that the silicon layer is made thinner by thermal oxidation after being performed.

  Therefore, the single-electron turnstyle device of this embodiment mode includes a silicon layer 702 formed on the insulating layer 701, a silicon oxide layer 703 formed on the silicon layer 702, and a silicon layer 702 on the silicon layer 702. Two constricted portions 708 thinner than other regions formed opposite to each other in the plane direction, and disposed opposite to the region between the two constricted portions 708 perpendicular to the arrangement direction of the two constricted portions 708, The constricted portion includes at least two groove portions 706 reaching the insulating layer 701, a thin wire portion 707a formed in a silicon layer sandwiched between the two groove portions 706, and a gate electrode 709 formed on the thin wire portion 707a. 708 includes at least two opposing edges 705 ′ corresponding to the constricted portion 708 formed in the upper layer of the silicon layer 702 after forming the groove 706. The silicon layer 702 in the constricted portion 708 is formed to have a layer thickness causing a quantum size effect by oxidizing the upper layer of the silicon layer 702 by thermal oxidation through the opening 705. Has been.

  As a result, a constricted portion having a thinner layer thickness is first formed in the silicon layer at a location corresponding to the two curved edges of the opening, and a tunnel barrier is formed here. Become. In addition, tunnel barriers are formed at both ends of the fine wire portion on both sides of the fine wire portion formed in the silicon layer sandwiched between the groove portions due to a decrease in potential energy in the central portion of the fine wire portion due to oxidation in the presence of the groove portion. Will come to be. As a result, in this embodiment, two single-electron islands are formed between the tunnel barriers of the two constricted portions and the tunnel barriers at both ends of the thin wire portion, and one is also formed in the central portion of the thin wire portion. Single-electron islands are formed. Further, these three single electron islands are connected in series on a straight line.

[Embodiment 5]
Next, a fifth embodiment of the present invention will be described. First, as shown in FIG. 11A, a substrate including an insulating layer 1101 and a silicon layer 1102 is prepared. When such a substrate is prepared, a silicon oxide layer 1103 and a silicon nitride layer 1104 are formed over the silicon layer 1102. These are the same as in the above-described embodiment.

  Next, as shown in FIG. 11B and FIG. 11C, at the portions where the fine lines are formed in the silicon nitride layer 1104 and the silicon oxide layer 1103, at least both edges in the direction in which the fine lines extend are configured by curves. 1105 and an opening 1106 are formed. FIG. 11B shows a cross section taken along line XX ′ of FIG. 11C. For example, a resist pattern having an opening corresponding to the opening 1105 is formed by a well-known lithography technique, and the silicon nitride layer 1104 and the silicon oxide layer are selectively removed by a known etching technique using the resist pattern as a mask. do it. The opening 1105 is formed until the surface of the silicon layer 1102 is exposed. The planar shape of the opening 1105 is the same as the opening 705 in the fourth embodiment described above. Here, the silicon layer 1102 may be thinned by thermal oxidation before forming a groove 1107 described later.

  Next, as shown in FIG. 11D, two groove portions 1107 disposed opposite to each other at two positions sandwiching the opening portion 1105 (opening portion 1106) perpendicular to the extending direction of the thin wire to be formed. Form. The groove 1107 is formed until the insulating layer 1101 is reached. Further, the groove portion 1107 is formed so as to enter the central portion of the opening portion 1105, leaving two edge portions 1105 ′ arranged to face each other, which are configured by the curve of the opening portion 1105. By forming these two groove portions 1107, a thin line portion 1108 is formed by the silicon layer 1102 between the opposite groove portions 1107. The width of the thin line portion 1108 is defined by the interval between the two groove portions 1107 facing each other. The formation of the groove 1107 is the same as the formation of the opening 705 in Embodiment 4 described above.

  Next, the upper layer portion of the silicon layer 1102 is thermally oxidized through the silicon oxide layer 1103 through the opening region including the groove portion 1107 formed in the silicon nitride layer 1104. As shown in FIGS. 11E and 11F, the fine line portion 1108 is obtained. The silicon layer 1102 containing is thinned. In this thermal oxidation, the exposed silicon layer 1102 in the region sandwiched between the two edges 1105 ′ is oxidized. The oxidized portion becomes a silicon oxide layer continuous with the silicon oxide layer 1103. FIG. 11E shows a cross section taken along line XX ′ of FIG. 11F.

  As a result of this oxidation step, a constricted portion 1109 constricted in the layer thickness direction is formed in the silicon layer 1102 near the inside corresponding to the curved edge portion 1105 ′, as shown in FIGS. 11E and 11F. The layer thickness of the silicon layer 1102 becomes thinner and a tunnel barrier is formed.

  Further, in the oxidation step, two groove portions 1107 that are opposed to each other with the fine wire portion 1108 interposed therebetween are formed. Therefore, a tunnel barrier is also formed at the end of the region of the fine wire portion 1108 that is sandwiched between the two groove portions 1107. Will come to be. In the present embodiment, the layer thickness of the thin line portion 1108 and the step amount of the constricted portion 1109 are controlled by controlling the amount of thermal oxidation described above. In the present embodiment, a difference can be formed in the oxidation rate of the silicon layer 1102 in the thermal oxidation due to the presence of the silicon nitride layer 1104 having each opening, and the same result as in the above-described fourth embodiment can be obtained.

  As described above, one single electron island is formed in the region of the thin wire portion 1108 sandwiched between the two groove portions 1107, and each single region is formed in each of the two regions between the both ends of the thin wire portion 1108 and the two constricted portions 1109. An electronic island is formed. Three single electron islands are formed in total.

  Next, when the gate electrode is formed so as to cover at least the region of the thin line portion 1108 sandwiched between the two groove portions 1107, a single-electron turnstyle device can be obtained.

  As described above, in the present embodiment, planar openings having curved edges are formed in the silicon oxide layer on the silicon layer and the silicon nitride layer on the silicon layer. Two groove portions opposed to each other with the opening interposed therebetween are formed until the side portion of the silicon layer is exposed, and the silicon layer is thinned and a constricted portion is formed by thermal oxidation after the groove portion is formed.

  As a result, first, a constricted portion with a thinner layer thickness is formed in the silicon layer at a location corresponding to both curved edges of the opening, and a tunnel barrier is formed here. . In addition, tunnel barriers are formed at both ends of the fine wire portion on both sides of the fine wire portion formed in the silicon layer sandwiched between the groove portions due to a decrease in potential energy in the central portion of the fine wire portion due to oxidation in the presence of the groove portion. Will come to be. As a result, also in this embodiment, two single-electron islands are formed between the tunnel barriers of the two constricted portions and the tunnel barriers at both ends of the thin wire portion, and one is also formed in the central portion of the thin wire portion. Single-electron islands are formed. Further, these three single electron islands are connected in series on a straight line.

[Embodiment 6]
Next, a sixth embodiment of the present invention will be described. First, as shown in FIG. 12A, a substrate including an insulating layer 1201 and a silicon layer 1202 is prepared. When such a substrate is prepared, a silicon oxide layer 1203 and a silicon nitride layer 1204 are formed over the silicon layer 1202. These are the same as in the above-described embodiment.

  Next, as shown in FIG. 12B and FIG. 12C, at the portions where the fine lines are formed in the silicon nitride layer 1204 and the silicon oxide layer 1203, at least both edges in the direction in which the fine lines extend are formed by curves. 1205 and opening 1206 are formed. FIG. 12B shows a cross section taken along line XX ′ of FIG. 12C. For example, a resist pattern having an opening corresponding to the opening 1205 is formed by a well-known lithography technique, and the silicon nitride layer 1204 and the silicon oxide layer are selectively removed by a known etching technique using the resist pattern as a mask. do it. The opening 1205 is formed up to a part of the silicon layer 1202 in the layer thickness direction, and the thickness of the silicon layer 1202 in the region of the opening 1205 is made thinner than the other regions. The planar shape of the opening 1205 is the same as that of the opening 705 in the fourth embodiment described above. Here, the silicon layer 1202 may be thinned by thermal oxidation before forming a groove 1207 described later.

  Next, as shown in FIG. 12D, two groove portions 1207 disposed opposite to each other at two positions sandwiching the opening 1205 (opening 1206) perpendicular to the extending direction of the thin wire to be formed. Form. The groove 1207 is formed until the insulating layer 1201 is reached. Further, the groove portion 1207 is formed so as to enter the center portion of the opening portion 1205 while leaving two edge portions 1205 ′ arranged in a curved shape of the opening portion 1205 so as to face each other. By forming these two groove portions 1207, a thin line portion 1208 is formed by the silicon layer 1202 between the opposite groove portions 1207. The width of the thin line portion 1208 is defined by the distance between the two groove portions 1207 facing each other. The formation of the groove 1207 is the same as the formation of the opening 705 in Embodiment 4 described above.

  Next, the exposed upper layer portion of the silicon layer 1202 is thermally oxidized through the opening region including the groove portion 1207 formed in the silicon nitride layer 1204. As shown in FIG. 12E, the silicon layer 1202 including the thin wire portion 1208 is formed. make it thin. In this thermal oxidation, the exposed silicon layer 1202 in the region sandwiched between the two edges 1205 'is oxidized. The oxidized portion becomes a silicon oxide layer continuous to the silicon oxide layer 1203.

  By this oxidation step, a constricted portion 1209 constricted in the layer thickness direction is formed in the silicon layer 1202 near the inside corresponding to the curved edge portion 1205 ′, as shown in FIG. 12E. In the constricted portion 1209, the silicon layer The layer thickness of 1202 becomes thinner and a tunnel barrier is formed.

  Further, in the oxidation step, two groove portions 1207 that are opposed to each other with the fine wire portion 1208 interposed therebetween are formed. Therefore, a tunnel barrier is also formed at the end of the region of the fine wire portion 1208 that is sandwiched between the two groove portions 1207. Will come to be. In this embodiment mode, by etching the silicon layer 1202 in the formation of the opening 1205, the layer thickness of the thin line portion 1208 is controlled to control the amount of step difference, and the amount of thermal oxidation described above is controlled, so that the thin line portion 1208 is controlled. The constricted portion 1209 is formed while reducing the layer thickness of the first layer. Also in this embodiment, a difference can be formed in the oxidation rate of the silicon layer 1202 in the thermal oxidation due to the presence of the silicon nitride layer 1204 having each opening.

  As described above, one single electron island is formed in the region of the thin wire portion 1208 sandwiched between the two groove portions 1207, and each of the two regions between the both ends of the thin wire portion 1208 and the two constricted portions 1209 is single. An electronic island is formed. Three single electron islands are formed in total.

  Next, when the gate electrode is formed so as to cover at least the region of the thin line portion 1208 sandwiched between the two groove portions 1207, a single electron turnstyle device can be obtained.

  As described above, in the present embodiment, planar openings having curved edges are formed in the silicon oxide layer on the silicon layer and the silicon nitride layer on the silicon layer. In forming the portion, the thickness of the silicon layer in this region is also reduced. Next, two grooves facing each other so as to sandwich the opening are formed until the side portion of the silicon layer is exposed, and the silicon layer is further thinned and a constricted portion is formed by thermal oxidation after forming the groove. There is.

  As a result, also in the present embodiment, first, a constricted portion having a thinner layer thickness is formed in the silicon layer at a location corresponding to the two curved edges of the opening. A barrier is formed. In addition, tunnel barriers are formed at both ends of the fine wire portion on both sides of the fine wire portion formed in the silicon layer sandwiched between the groove portions due to a decrease in potential energy in the central portion of the fine wire portion due to oxidation in the presence of the groove portion. Will come to be. As a result, also in this embodiment, two single-electron islands are formed between the tunnel barriers of the two constricted portions and the tunnel barriers at both ends of the thin wire portion, and one is also formed in the central portion of the thin wire portion. Single-electron islands are formed. Further, these three single electron islands are connected in series on a straight line.

  It should be noted that the present invention is not limited to the embodiment described above, and that many modifications can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, the opening formed in the upper layer of the silicon layer is provided with curved edges arranged opposite to each other. However, the present invention is not limited to this, and a shape close to a square or a triangle may be used. Even if it comprises in this way, although it is non-uniform | heterogenous, a tunnel barrier can be formed. However, in order to uniformly form the tunnel barrier due to the constriction in the planar direction of the silicon layer, it is better to configure it with a convex curve in the position direction, such as a part of an arc.

  DESCRIPTION OF SYMBOLS 101 ... Insulating layer, 102 ... Silicon layer, 103 ... Silicon oxide layer, 104 ... Opening part, 104 '... Edge part, 105 ... Opening part (groove part), 106 ... Fine wire formation area, 106a ... Fine wire part, 107 ... Constriction part 109: Gate electrodes.

Claims (9)

A first step of forming a silicon layer on the insulating layer and forming at least a silicon oxide layer on the silicon layer;
A second step of forming an opening in the upper layer of the silicon layer;
A third step of reducing the thickness of the silicon layer in the region of the opening;
The silicon sandwiched between the two groove portions, the two groove portions reaching the insulating layer are formed to be opposed to each other in the central portion of the opening portion, leaving two opposite ends of the opening portion. A fourth step of forming a thin line portion in the layer;
The silicon layer is oxidized by thermal oxidation to reduce the layer thickness to form two constricted portions where the silicon layer under the outer edge of the end portion becomes thinner than other regions, Tunnel barriers are formed in the silicon layers at both ends and the two constricted portions, and single electron islands are formed in each of the silicon layers between the both ends of the fine wire portions and the constricted portions and in the central portion of the narrow wire portions. And a fifth step to
And a sixth step of forming a gate electrode on the thin wire portion. A method of manufacturing a single-electron turnstyle device, comprising: In the manufacturing method of the single-electron turn style device of Claim 1,
In the first step, a silicon layer and a silicon oxide layer are formed on the insulating layer, and in addition, a silicon nitride layer is formed on the silicon oxide layer,
In the second step, the penetrating opening is formed in the silicon nitride layer. A method of manufacturing a single-electron turnstyle device. In the manufacturing method of the single-electron turn style device of Claim 1 or 2,
In the third step, the upper layer of the silicon layer is oxidized by thermal oxidation to reduce the layer thickness of the silicon layer in the region of the opening. In the manufacturing method of the single electron turn-style device according to claim 3,
In the second step, the opening having a depth reaching the silicon layer is formed. A method of manufacturing a single-electron turn-style device. In the manufacturing method of the single electron turn-style device according to claim 3,
In the second step, the opening having a depth halfway through the silicon layer is formed. A method of manufacturing a single-electron turnstyle device. In the manufacturing method of the single-electron turn style device of Claim 1 or 2,
In the third step, the upper layer of the silicon layer is etched through the opening to reduce the layer thickness of the silicon layer in the region of the opening. In the manufacturing method of the single-electron turn style device of any one of Claims 1-6,
The manufacturing method of a single-electron turnstyle device, wherein the edge portion outside the end portion is formed in a curved shape in plan view. A silicon layer formed on the insulating layer;
A silicon oxide layer formed on the silicon layer;
Two constricted portions thinner than other regions formed on the silicon layer so as to face the planar direction of the silicon layer;
Two groove portions that are arranged to face each other in a region between the two constricted portions perpendicular to the arrangement direction of the two constricted portions and reach the insulating layer;
A thin line portion formed in the silicon layer sandwiched between the two groove portions;
And at least a gate electrode formed on the thin wire portion,
The constricted portion is formed by oxidizing the upper layer of the silicon layer by thermal oxidation through an opening having at least two opposing edges corresponding to the constricted portion formed in the upper layer of the silicon layer,
The single-electron turn-style device, wherein the silicon layer of the constricted portion has a thickness that causes a quantum size effect by the thermal oxidation that forms the constricted portion after forming the groove portion. The single-electron turnstyle device according to claim 8,
The two edge portions facing each other are formed in a curved shape in a plan view.

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