JP2011109515A - Two-wire type serial data transfer control method, program, and two-wire type serial data transfer controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a two-wire type serial data transfer method that suppresses an increase of processor processing time and an increase of storage device for preparation of software, and provide a program and a two-wire type serial data transfer controller. <P>SOLUTION: The two-wire type serial data transfer control system includes one or more slave devices that are connected with a master device through a two-wire type serial data transfer means, and address spaces comprised of one or more slave devices as one address. In the two-wire type serial data transfer control method for this system, a slave address as a transfer partner is created from the address for starting access. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a two-wire serial data transfer control method, a program, and a two-wire serial data transfer control device.

In recent years, various techniques relating to data transfer means have been developed.
For example, in the invention described in Patent Document 1, a master device connected to a plurality of slave devices has a control line (chip select signal: CS: Chip Selector) individually connected to each slave device (RAM: Random Access Memory). CS switching means in a high-speed communication system that uses differential signals for a common data line between a plurality of slave devices and a master device. Is performed by comparing the number of transmission / reception data with the number of data stored in advance for transmission / reception. The transfer is performed by DMA (Direct Memory Access) transfer. Invention of patent document 1 These things reduce the load of a master apparatus.

  The invention described in Patent Document 2 relates to a microcomputer control system, which connects a microcomputer and an external circuit via a control data communication bus, and authenticates with ID data on the control data communication bus. In the microcomputer control system, when the microcomputer sends out the ID data of the external circuit via the control data communication bus at the time of reset and the ACK signal is returned, the external circuit is attached. This is the initial setting. That is, the slave address (ID) is transmitted by microcomputer control. Accordingly, the invention described in Patent Document 2 can reduce the labor of wiring work without consuming the port.

  In a system (001 in FIG. 10) that transfers data using 2-wire serial data transfer (I2C (Inter-Integrated Circuit) specification proposed by Philips), the master device M001 and one or more slave devices S001 to S00n It is connected to one clock line 002 (SCL) and one data line 003 (SDA).

FIG. 10 shows a commonly used two-wire serial data transfer device.
10, M001 is a master device, S001, S002, S003,..., S00n are slave devices, 002 and 003 are clock lines and serial data lines, and 004 is a pull-up element.

  The master device M001 sends the clock and slave address to the serial data line to the slave devices S001 to S00n to be transferred. The slave devices S001 to S00n send their own slave address and the slave address sent by the master device M001. If they match, communication is established by returning an acknowledge signal to the master device M001, and serial data transfer is performed by the subsequent communication protocol.

  In addition, on the communication protocol, the specification clearly indicates from which address the data is transferred to the storage device (not shown) of the slave devices S001 to S00n.

  Generally, a master device can arbitrarily set and send a slave address by software processing via a processor built in an LSI device including a microcomputer device and an I2C controller. For example, the invention described in Patent Document 2 is a device for sending a slave address (ID) through microcomputer control.

  In addition, it is a common technique that an address for a storage device of a slave device can be transmitted by the same microcomputer control.

  In the two-wire serial data transfer system as shown in FIG. 1, the slave device 1 (S001), slave device 2 (S002),..., Slave device n (S00n) are switched by issuing a slave address from the master device M001. However, it is well known that this issuance is performed by microcomputer device or processor control, that is, software processing, and issuance of addresses to the storage devices of the slave devices S001 to S00n is also performed by microcomputer device or processor control, that is, software processing. Technology.

For example, in the serial transfer from the master device M001 to the slave device 1 (S001), the slave address of the slave device 1 (S001) is prepared on the software, and then the serial transfer with the slave device 2 (S002) is performed. Also, the slave address of slave device 2 (S002) is prepared in software, and the slave address of slave device 3 (S003) is also prepared in software when serial transfer is performed with slave device 3 (S003). It becomes.
In this way, it is necessary to prepare on the software the slave addresses for the slave devices S001 to S00n that are transfer partners.

  As a further example, in the case of a system configuration in which the storage areas of the slave devices 1 to 3 (S001 to S003) can be handled as a continuous address space, similarly, for each slave device 1 to 3 (S001 to S003) It is necessary to prepare corresponding software.

  As described above, performing serial transfer control by microcomputer device or processor control is concerned about an increase in processor processing time and an increase in storage devices for software preparation.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a two-wire serial data transfer control method, a program, and a two-wire serial data transfer control device that suppress an increase in processor processing time and an increase in storage devices for software preparation. .

  In order to solve the above-mentioned problem, the invention according to claim 1 of the present invention includes one or more slave devices connected to a master device by a two-wire serial data transfer means, and is composed of the one or more slave devices. A linear serial data transfer control method for a two-wire serial data transfer control system apparatus using an address space as one address space, wherein a slave address serving as a transfer partner is generated from an access start address. .

  According to a second aspect of the present invention, in the first aspect of the present invention, when the upper limit of the memory address space of the slave device is exceeded during serial data transfer between the master device and the slave device, two-wire serial data transfer is performed. Is completed, a slave address as the next transfer partner is generated from the memory address, and serial data transfer from the continuous address space is resumed.

  According to a third aspect of the present invention, in the first aspect of the present invention, when the upper limit of the memory address space of the slave device is exceeded or less than the lower limit during serial data transfer between the master device and the slave device. It has a sequence device that terminates the two-wire serial data transfer, generates a slave address as the next transfer partner from the memory address, and resumes the serial data transfer from the continuous address space.

  The invention according to claim 4 includes one or more slave devices connected to the master device by a two-wire serial data transfer means, and an address space composed of the one or more slave devices is defined as 2 address spaces. A program for controlling the two-wire serial data transfer of the linear serial data transfer control system device, wherein the master device is connected to the master in order to generate a slave address as a transfer partner from the address at which access is started. A procedure for determining whether or not the upper limit of the memory address space of the slave device has been exceeded during serial data transfer between the device and the slave device, and when the master device exceeds the upper limit, the two-wire serial data transfer is performed. A procedure for ending, the master device from the memory address, the slave address to be the next transfer partner Procedure to generate the master device, characterized in that to perform the procedure, to restart the serial data transfer from the continuous address space.

  The invention described in claim 5 includes a master device and one or more slave devices connected to the master device by a two-wire serial data transfer means, and an address space composed of the one or more slave devices is defined as one. A two-wire serial data transfer control device used in a two-wire serial data transfer control system device having one address space, wherein the master device includes the two-wire serial data transfer control device, The serial data transfer control device includes a generation device that generates a slave address as a transfer partner from an address at which access is started.

  According to a sixth aspect of the present invention, in the fourth aspect of the present invention, when the master device exceeds the upper limit of the memory address space of the slave device during serial data transfer with the slave device, the two-wire serial data It has a sequence device that terminates transfer, generates a slave address as a next transfer partner from the memory address, and resumes serial data transfer from a continuous address space.

  The invention according to claim 7 is the invention according to claim 4, wherein the master device exceeds or exceeds the lower limit of the memory address space of the slave device during serial data transfer with the slave device. It has a sequence device that terminates the two-wire serial data transfer, generates a slave address as the next transfer partner from the memory address, and resumes the serial data transfer from the continuous address space.

  The invention according to claim 8 is the invention according to claim 6 or 7, wherein the master device sets an arbitrary address from a memory address setting device for setting a memory address and a memory address in a continuous address space. And a slave address selection device that determines a slave device to which data is to be transferred.

  According to a ninth aspect of the present invention, in the eighth aspect of the invention, the slave address selecting device includes a setting device for setting an upper address limit and an lower address limit, an address setting value from the setting device, an upper limit address setting value, and an address. An arithmetic unit that detects whether the set value and the lower limit address set value are within or out of the range, and whether the address set value is within the range of the upper limit address set value to the lower limit address set value from the detection results of both arithmetic units. And a logic circuit for generating a slave address selection signal.

  According to the present invention, when the storage area of the slave device is a continuous address space, the slave address and data transfer with the slave device are started even when the slave device is crossed by preparing an address to start the transfer. Since it is not necessary to prepare the address of the storage area on software, an increase in the number of storage devices for software preparation can be suppressed. In addition, since no other software is prepared on the software, the processor processing time is reduced, the processing time can be shortened, and other processing can be performed, thereby improving efficiency.

It is a structural example of the master apparatus used for the 2-wire type serial data transfer control apparatus which concerns on this invention. (A), (b) is a configuration example of a system that performs data transfer by two-wire serial data transfer (I2C specification proposed by Philips). It is an example of a structure of the slave address generation apparatus used for the 2-wire type serial data transfer control apparatus concerning this invention. FIG. 4 is an explanatory diagram for explaining an operation of a slave address generation device 608 shown in FIG. 3. It is explanatory drawing explaining operation | movement of the slave address generation apparatus 712 used for the 2-wire type serial data transfer control apparatus based on this invention. It is another example of a structure of the master apparatus used for the 2-wire type serial data transfer control apparatus which concerns on this invention. It is another example of a structure of the master apparatus used for the 2-wire type serial data transfer control apparatus which concerns on this invention. It is a figure which shows the operation example of the 2-wire type serial data transfer control apparatus which concerns on this invention. It is an example of the flowchart for demonstrating the 2-wire type serial data transfer control method which concerns on this invention. This is a two-wire serial data transfer device generally used. This is a configuration example of a system for transferring data by two-wire serial data transfer (I2C specification proposed by Philips). It is a general structural example of a master apparatus.

Embodiments of the present invention will be described with reference to the drawings.
FIG. 11 shows a configuration example of a system that performs data transfer by two-wire serial data transfer (I2C specification proposed by Philips), FIG. 12 shows a general configuration example of a master device, and FIG. An embodiment of a master device used in such a two-wire serial data transfer control device is shown.

<Configuration>
In FIG. 11, M201 indicates a master device, S201 to S203 indicate slave devices 1 to 3, and each of the devices M201 and S201 to S203 includes a clock line indicated by 201 (SCL) and 202 (SDA), and a serial number. Connected by data line.

  In this configuration example, the storage devices of the slave devices 1 to 3 (S201 to S203) have an address space (32k words) of 0000h to 7FFFh, and the storage devices (not shown) of the slave devices 1 to 3 (S201 to S203). System configuration that can be handled in a continuous address space (00000h to 07FFFh, 08000h to 0FFFFh, 10000h to 17FFFh).

  Note that the address space of the storage device unit of each of the slave devices 1 to 3 (S201 to S203) and the total number of slave devices are not limited.

FIG. 12 shows an example of a commonly used configuration of the master device, which includes a 301 processor, a 302 program memory, and a 303 2-wire serial data transfer control device as main components.
The two-wire serial data transfer control device 303 includes a transmission / reception setting device 304, a memory address setting device 305, and a slave address setting device 306.
Reference numeral 307 denotes a two-wire serial data transfer sequence device, which starts a serial data transfer protocol by self-running without processing from the processor 301 (after reset release, etc.), starts a serial data transfer protocol via the processor 301, It is a device that can be terminated. Instructions 308 (SCL) and 309 (SDA) from the processor 301 indicate a clock line and a serial data line in 2-wire serial data transfer.

<Comparative example>
In the following, description will be made using a general technique.
The master device shown in FIG. 12 uses a program stored in the program memory 302 to send / receive settings, memory address settings, and information to the 2-wire serial data transfer sequence device 307 at the start of transfer. Set the slave address. Based on this setting, serial data transfer is started.

For example, when performing the following data transfer:
(1) Receive data from memory address 0010h of slave device 1 (slave address “0000001b”)
(2) Receive data from memory address 0020h of slave device 2 (slave address is “0000010b”)
(3) Data reception from memory address 0030h of slave device 3 (slave address is “0000011b”)
(4) Receive data from memory address 0110h of slave device 1 (slave address is “0000001b”)
(5) Receive data from memory address 0120h of slave device 2 (slave address is “0000010b”)

(6) Receive data from memory address 0130h of slave device 3 (slave address is “0000011b”)
(7) Receive data from memory address 0210h of slave device 1 (slave address is “0000001b”)
(8) Receive data from memory address 0220h of slave device 2 (slave address “0000010b”)
(9) Receive data from memory address 0230h of slave device 3 (slave address “0000011b”)
(10) Receive data from memory address 0310h of slave device 1 (slave address “0000001b”)

(11) Receive data from memory address 0320h of slave device 2 (slave address is “0000010b”)
(12) Receive data from memory address 0330h of slave device 3 (slave address “0000011b”)
(13) Receive data from memory address 0410h of slave device 1 (slave address “0000001b”)
(14) Receive data from memory address 0420h of slave device 2 (slave address “0000010b”)
(15) Receive data from memory address 0430h of slave device 3 (slave address “0000011b”)

(16) Receive data from memory address 0510h of slave device 1 (slave address “0000001b”)
(17) Receive data from memory address 0520h of slave device 2 (slave address “0000010b”)
(18) Data reception from memory address 0530h of slave device 3 (slave address is “0000011b”)

As processing of the processor, it is necessary to store the following 54 instructions in the program memory.
(1-1): Performs reception settings on the transmission / reception setting device via the processor.
(1-2): Set “0010h” to the memory address setting device via the processor
(1-3): Set "0000001b" to the slave address setting device via the processor

(2-1): Perform reception settings on the transmission / reception setting device via the processor
(2-2): “0020h” is set in the memory address setting device via the processor.
(2-3): Set “0000010b” to the slave address setting device via the processor

(3-1): Perform reception settings on the transmission / reception setting device via the processor
(3-2): Set “0030h” to the memory address setting device via the processor
(3-3): Set “0000011b” to the slave address setting device via the processor

(4-1): Perform reception settings on the transmission / reception setting device via the processor
(4-2): Set “0110h” to the memory address setting device via the processor.
(4-3): Set "0000001b" to the slave address setting device via the processor

(5-1): Perform reception settings on the transmission / reception setting device via the processor
(5-2): Set “0120h” to the memory address setting device via the processor.
(5-3): Set “0000010b” to the slave address setting device via the processor.

(6-1): Perform reception setting to the transmission / reception setting device via the processor
(6-2): Set “0130h” to the memory address setting device via the processor.
(6-3): Set “0000011b” to the slave address setting device via the processor.

(7-1): Set the reception to the transmission / reception setting device via the processor.
(7-2): Set “0210h” to the memory address setting device via the processor.
(7-3): Set "0000001b" to the slave address setting device via the processor

(8-1): Perform reception setting to the transmission / reception setting device via the processor
(8-2): Set “0220h” to the memory address setting device via the processor.
(8-3): Set “0000010b” to the slave address setting device via the processor

(9-1): Perform reception settings on the transmission / reception setting device via the processor
(9-2): Set “0230h” to the memory address setting device via the processor.
(9-3): Set “0000011b” to the slave address setting device via the processor

(10-1): Performs reception settings on the transmission / reception setting device via the processor
(10-2): “0310h” is set in the memory address setting device via the processor.
(10-3): Set "0000001b" to the slave address setting device via the processor

(11-1): Sets reception to the transmission / reception setting device via the processor
(11-2): Set “0320h” to the memory address setting device via the processor.
(11-3): Set “0000010b” to the slave address setting device via the processor

(12-1): Sets reception to the transmission / reception setting device via the processor
(12-2): Set “0330h” to the memory address setting device via the processor.
(12-3): Sets “0000011b” to the slave address setting device via the processor

(13-1): Sets the reception setting to the transmission / reception setting device via the processor.
(13-2): “0410h” is set in the memory address setting device via the processor.
(13-3): Set "0000001b" to the slave address setting device via the processor

(14-1): Sets the reception setting to the transmission / reception setting device via the processor.
(14-2): “0420h” is set in the memory address setting device via the processor.
(14-3): Set “0000010b” to the slave address setting device via the processor

(15-1): Sets the reception setting to the transmission / reception setting device via the processor.
(15-2): Sets “0430h” to the memory address setting device via the processor.
(15-3): Set "0000011b" to the slave address setting device via the processor

(16-1): Sets reception to the transmission / reception setting device via the processor
(16-2): “0510h” is set in the memory address setting device via the processor.
(16-3): Set "0000001b" to the slave address setting device via the processor

(17-1): Sets reception to the transmission / reception setting device via the processor
(17-2): “0520h” is set in the memory address setting device via the processor.
(17-3): Set “0000010b” to the slave address setting device via the processor

(18-1): Sets reception to the transmission / reception setting device via the processor
(18-2): Sets “0530h” to the memory address setting device via the processor.
(18-3): Set "0000011b" to the slave address setting device via the processor

<Configuration>
Next, an embodiment according to the present invention will be described.
FIG. 1 shows a configuration example of a master device used in a two-wire serial data transfer control device according to the present invention, and includes a processor 401, a program memory 402, and a two-wire serial data transfer control device 403 as main components. . The two-wire serial data transfer control device 403 includes a transmission / reception setting device 404, a memory address setting device 405, and a slave address selection device 406. Reference numerals 408 (SCL) and 409 (SDA) denote a clock line and a serial data line in two-wire serial data transfer.

  The master device shown in FIG. 1 performs transmission / reception settings and memory address settings via a program stored in the program memory 402 in order to give information at the start of transfer to the 2-wire serial data transfer sequence device. . As for the slave address setting, information from the slave address selection device 406 is given to the two-wire serial data transfer sequence device.

<Slave address selection device>
Here, the slave address selection device 406 will be described.
As described in the system configuration of FIG. 11, the slave address selection device 406 has a continuous address space because the address space of the storage device units of the plurality of slave devices S201 to S203 is a continuous space. This is a device that can determine a slave device as a data transfer target by setting an arbitrary address from the memory addresses.
That means
If the memory address is “00000h to 07FFFh”, the slave address “0000001b”, which is the slave device 1,
If the memory address is “08000h to 0FFFFh”, the slave address “0000010b”, which is the slave device 2,
If the memory address is “10000h to 17FFFh”, the slave address “0000011b” that is the slave device 3
Can be selectively supplied to the two-wire serial data transfer sequence device.

  For example, a specific technical example of the present invention in the case of performing the following data transfer will be described with reference to FIGS. 2 (a), 2 (b), and 3. FIG.

(1) 'Receive data from memory address'00010h'
(2) 'Receive data from memory address "08020h"
(3) 'Data received from memory address "10030h"
(4) 'Receive data from memory address "00110h"
(5) 'Data received from memory address "08120h"

(6) 'Data received from memory address "10130h"
(7) 'Data received from memory address "00210h"
(8) 'Receive data from memory address "08220h"
(9) 'Data received from memory address "10230h"
(10) 'Receive data from memory address "00310h"

(11) 'Data received from memory address "08320h"
(12) 'Receive data from memory address "10330h"
(13) 'Data received from memory address "00410h"
(14) 'Receive data from memory address "08420h"
(15) 'Data received from memory address "10430h"

(16) 'Data received from memory address "00510h"
(17) 'Data received from memory address "08520h"
(18) 'Data received from memory address "10530h"

<Slave address selection signal generator>
The slave address selection signal generator (507) is shown in FIGS.
A memory address setting device 501 is the same as the memory address setting device 405 in FIG. Reference numerals 502 and 503 are devices for setting a lower limit address and an upper limit address in a continuous address space of the storage unit of one slave device. Reference numerals 504 and 505 denote arithmetic units that detect whether the address setting value and the upper limit address setting value, and the address setting value and the lower limit address setting value are within or outside the range, respectively. Further, the logic circuit 506 detects whether the address setting value is within the range of the upper limit address setting value to the lower limit address setting value from the detection results of both, and outputs the result as a slave address selection signal.

  For example, if the upper limit address setting value is “07FFFh” and the lower limit address setting value is “00000h”, the address setting value is “00010h”, so the slave address selection signal output is “1”. When the address set value is “08020h”, the upper limit address set value is exceeded and the output of the slave address selection signal is “0”. It is obvious that the arithmetic unit does not need to use all bits of the address, and it is possible to determine the slave address selection signal by calculating only the necessary bits, that is, in this example, by targeting the upper 2 effective bits. .

FIG. 2B shows an embodiment in this case.
Although the configuration is the same as in FIG. 2A, the address upper / lower limit device (502b) has the functions of the upper limit address setting device (502) and the lower limit address setting device (503) in FIG. 2 (a).

<Slave address generator>
FIG. 3 shows a configuration example of the slave address generation device (608) used in the two-wire serial data transfer control device according to the present invention.
Reference numeral 601 denotes a memory address setting device similar to the memory address setting device 405 shown in FIG. 602, 603, and 604 are the same devices as the slave address selection signal generation device 507 shown in FIG. Reference numerals 605, 606, and 607 are slave address setting devices of the respective slave devices. A selector 607 selectively outputs a slave address from a slave address selection signal. A more specific example will be described with reference to FIG.

<Operation 1>
FIG. 4 is an explanatory diagram for explaining the operation of the slave address generation device 608 shown in FIG.
4, reference numeral 712 denotes a slave address generation device similar to the slave address generation device 608 shown in FIG.
Reference numeral 701 denotes an address setting device, and the upper 2 bits thereof are used by the slave address selection signal generation device 604.
Reference numerals 702, 703, and 704 denote address upper / lower limit setting values, and reference numerals 705, 706, and 707 denote slave address selection signal generation devices having the same functions as the address setting device 501 in FIG. 708, 709, and 710 are slave address setting values corresponding to slave devices 1 to 3 (S201 to S203), 711, 712, and 713 are slave address selection signal outputs from 705, 706, and 707, and 714 is shown in FIG. The selector has the same function as the selector 607, and the slave address is selected and output (715).

<Operation 2>
FIG. 5 is an explanatory diagram for explaining the operation of the slave address generation device 712 used in the two-wire serial data transfer control device according to the present invention.
The upper 2 bits of the address set value indicate in which address upper / lower limit set value, and the slave address selected and output at that time outputs any slave address of the slave devices 1 to 3 (S201 to S203) It was described. For example, if the address setting value (all 13 bits) = 00010h, the upper 2 bits are “00b”, so both the upper and lower limits apply to “00b”. The slave address output from 714 is “0000001b” which is the slave address of the slave device 1.

With this technology, the processor processing for (1) to (18) above is

(A-1): Set "0000001b" to the slave address setting device (708) via the processor
(A-2): Set "0000010b" to the slave address setting device (709) via the processor
(A-3): Set "0000011b" to the slave address setting device (710) via the processor

(B-1): “00b” is set to the address upper / lower limit setting device (702) via the processor.
(B-2): “01b” is set to the address upper / lower limit setting device (703) via the processor.
(B-3): “10b” is set in the address upper / lower limit setting device (704) via the processor.

(1-1): Performs reception settings on the transmission / reception setting device via the processor.
(1-2): Set “00010h” to the memory address setting device via the processor

(2-1): Perform reception settings on the transmission / reception setting device via the processor
(2-2): Set “08020h” to the memory address setting device via the processor.

(3-1): Perform reception settings on the transmission / reception setting device via the processor
(3-2): Set “10030h” to the memory address setting device via the processor

(4-1): Perform reception settings on the transmission / reception setting device via the processor
(4-2): Set “00110h” to the memory address setting device via the processor.

(5-1): Perform reception settings on the transmission / reception setting device via the processor
(5-2): “08120h” is set in the memory address setting device via the processor.

(6-1): Perform reception setting to the transmission / reception setting device via the processor
(6-2): Set “10130h” to the memory address setting device via the processor

(7-1): Set the reception to the transmission / reception setting device via the processor.
(7-2): Set “00210h” to the memory address setting device via the processor.

(8-1): Perform reception setting to the transmission / reception setting device via the processor
(8-2): Set “08220h” to the memory address setting device via the processor.

(9-1): Perform reception settings on the transmission / reception setting device via the processor
(9-2): Set “10230h” to the memory address setting device via the processor

(10-1): Performs reception settings on the transmission / reception setting device via the processor
(10-2): Set “00310h” to the memory address setting device via the processor

(11-1): Sets reception to the transmission / reception setting device via the processor
(11-2): “08320h” is set in the memory address setting device via the processor.

(12-1): Sets reception to the transmission / reception setting device via the processor
(12-2): Set “10330h” to the memory address setting device via the processor

(13-1): Sets the reception setting to the transmission / reception setting device via the processor.
(13-2): Set “00410h” to the memory address setting device via the processor.

(14-1): Sets the reception setting to the transmission / reception setting device via the processor.
(14-2): “08420h” is set in the memory address setting device via the processor.

(15-1): Sets the reception setting to the transmission / reception setting device via the processor.
(15-2): “10430h” is set to the memory address setting device via the processor.

(16-1): Sets reception to the transmission / reception setting device via the processor
(16-2): Set “00510h” to the memory address setting device via the processor

(17-1): Sets reception to the transmission / reception setting device via the processor
(17-2): “08520h” is set in the memory address setting device via the processor.

(18-1): Sets reception to the transmission / reception setting device via the processor
(18-2): Set “10530h” to the memory address setting device via the processor

From the above, it is necessary to store 42 instructions in the program memory as the processing of the processor.
As a result, it can be seen that the number of programs to be stored in the program memory is smaller than that in the general technical example. This technology eliminates the need for a program preparation for slave address setting that is required every time 2-wire serial data transfer, which has been required in general techniques, is started. The time required for processor processing is also reduced.

  Subsequently, when the upper limit of the memory address space of the slave device is exceeded during serial data transfer with the slave device, means for terminating the two-wire serial data transfer (sequence device 908), and from the memory address to the next transfer partner FIGS. 6 and 7 show an embodiment of means (sequence device 908) for generating a slave address and resuming serial data transfer from a continuous address space.

FIG. 6 shows another configuration example of the master device used in the two-wire serial data transfer control device according to the present invention.
In FIG. 6, 903 is a two-wire serial data transfer control device, and 901 is a processor. Reference numeral 902 denotes a program memory, and reference numeral 904 denotes a memory address setting device. 905 is a transfer number counter, and 906 is an upper limit address setting value. Reference numeral 907 denotes a comparator, and reference numeral 908 denotes a two-wire serial data transfer sequence device. Reference numerals 909 and 910 denote a clock line (SCL) and a serial data line (SDA) for two-wire serial transfer.

  Setting to the upper limit address setting device is performed via a processor. For example, since the address space of the slave device 1 (S201) is “00000-07FFFh”, the set value is “07FFFh”. Since this setting does not change the system configuration, it can be set once.

Setting to the memory address setting device is also performed via the processor, but this setting is required every time the transfer protocol is started.
As an example, it is assumed that the memory address setting value is “00010h”.

  Before the two-wire serial data transfer is started, the memory address setting value is loaded into the transfer number counter 905. This load value or counter value is used by the sequence device 908 as the memory address 912.

  In general, when the two-wire serial data transfer is started, the sequence device 908 transmits the data of a certain bit in one byte, which is a unit of transfer data, for serial data transmission and reception operations. Means for notifying the processor that one-byte data has been transmitted, that a certain bit in one byte has been received, and that one-byte data has been received.

  Based on this notification, preparation of transmission data and saving of received data are performed via the processor. A signal for counting up the transfer number counter every time one byte is transferred using this means is shown as a transfer data detection clock 911. The count value and the upper limit address set value 906 are compared by the comparator 907. If they match, the transfer up to the upper limit address is completed, and the sequence device 908 is notified as a transfer protocol end signal 913. The sequence device 908 is circuitized so as to perform an operation for ending the current transfer protocol from this signal.

  Note that even if the transfer protocol end signal is sent to the sequence device after the data transfer with the upper limit address is completed, if the sequence device 908 shifts to the control to start the next data transfer, the counter value or the address setting value By having means for making a change, it is possible to generate a transfer protocol end signal in accordance with the control of the sequence device 908.

  After receiving the transfer protocol end signal, the sequence device is circuitized to end the current protocol, and is configured to start the transfer protocol as an operation included in this sequence.

  When “00010h” as the address setting value 904 is loaded into the transfer number counter 905, “00010h” is input to the sequence device 908. It is assumed that the slave address is generated by the operation shown in FIG.

  The slave address and memory address at the start of serial data transfer are based on this means. When the transfer is started, a transfer data detection clock 911 is issued at a certain timing, and the transfer counter 905 is counted up. The count-up value indicates the address being transferred or transferred, and the counter value (address value) and the upper limit address value are compared by the comparator 907. If the counter value reaches the upper limit address value “07FFFh”, the comparator 907 notifies the sequence device 908 of a transfer protocol end signal, and the sequencer device 908 moves to an operation of ending the transfer protocol based on this signal.

FIG. 7 shows another configuration example of the master device used in the two-wire serial data transfer control device according to the present invention.
In FIG. 7, reference numeral 1003 denotes a two-wire serial data transfer control device, and reference numeral 1001 denotes a processor. Reference numeral 1002 denotes a program memory, and reference numeral 1004 denotes a memory address setting device. Reference numeral 1005 denotes a transfer number counter, and reference numeral 1006 denotes a transfer data detection clock signal. Reference numeral 1007 denotes a memory address, and reference numeral 1008 denotes a two-wire serial data transfer sequence device. Reference numerals 1009 and 1010 denote a two-line serial transfer clock line (SCL) and serial data line (SDA).

  1020, 1021, and 1022 have the same configuration as 705, 708, and 711 shown in FIG. 4, and 1030, 1031, and 1032 show the same configuration as 706, 709, and 711 shown in FIG. 1040, 1041, and 1042 have the same configuration as 707, 710, and 713 shown in FIG. 4, and 1023, 1024, 1025, (1033, 1034, and 1035) and (1043, 1044, and 1045) are shown in FIG. A configuration similar to 906, 907, and 913 is shown.

<Operation 3>
Next, the operation will be described.
Assume that the sequence device is sequence-controlled so as to shift to the next protocol start operation after the end of the transfer protocol according to the operation description of FIG.
Before starting this protocol, preparation for issuing slave addresses and memory addresses is necessary. However, in the present invention, not using software, but using the value from the counter used in the previous protocol termination determination, The address and slave address will be prepared.

FIG. 8 is a diagram showing an operation example of the two-wire serial data transfer control device according to the present invention.
In FIG. 8, the serial data transfer continues and the counter value reaches “07FFFh”, which matches the upper limit address setting value. A transfer protocol end signal is notified to the sequence device, and the serial data transfer ends.
Here, at the start of the next slave device, the sequence device counts up the counter value by one and becomes “08000h”. This value is the start memory address of the slave device that performs the next serial data transfer (the address as a continuous address space, and the memory address on the transfer protocol is “0000h” in this case).

  Similarly to the description of FIG. 4, the slave address is determined by using the memory address, so that the slave address and the memory address are prepared, and serial data transfer to the slave device 2 is started. Is done. Further, the serial data transfer continues and the counter value reaches “0FFFFh”, which coincides with the upper limit address setting value. A transfer protocol end signal is notified to the sequence device, and the serial data transfer ends.

  Here, at the start of the next slave device, the sequence device increments the counter value by one to “10000h”. This value is the start memory address of the slave device that performs the next serial data transfer (the address as a continuous address space, and the memory address on the transfer protocol is “0000h” in this case). Similarly, since the memory address is used to determine the slave address, the slave address and the memory address are prepared, and serial data transfer to the slave device 3 is started.

  In addition, by setting the initial value of the address setting value to be 0 address and making the circuit so that the initial value of the upper limit memory address setting value becomes the upper limit address of the slave device used in the system, Transfer from the slave device can be continuously performed without processing.

This is the case when, for example, a general I2C-EEPROM is configured as a boot device for a slave device, and the processor processing program used in the system requires a program that exceeds the capacity of one I2C-EEPROM, that is, a plurality of I2C-EEPROMs Therefore, boot software is required, and boot software is required in addition to the original system software. In this example, the capacity of the boot device (I2C-EEPROM) increases.
However, since the two-wire serial data transfer control device according to the present invention can continuously transfer data from a plurality of slave devices without using a processor, no dedicated boot software is required, and the increase in boot devices It will not occur.

FIG. 9 is an example of a flowchart for explaining the two-wire serial data transfer control method according to the present invention.
The subject of operation is a master device (substantially a sequence device).
First, the master device determines whether or not serial data is being transferred (step S1). If it is determined that serial data is not being transferred, it waits (step S1 / No), and if it is determined that serial data is being transferred. Advances to step S2 (step S1 / Yes).
In step S2, the master device determines whether the upper limit of the memory address space of the slave device has been exceeded during the transfer of serial data. If the master device determines that the transfer amount of the serial data does not exceed the upper limit of the memory address space, the master device transfers it as it is (step S2 / No), and determines that the transfer amount of the serial data exceeds the upper limit of the memory address space. If so (step S2 / Yes), the two-wire serial data transfer is terminated (step S3).
The master device generates a slave address as the next transfer partner from the memory address of the slave device (step S4).
The master device resumes serial data transfer from the continuous address space (step S4).

<Program>
The two-wire serial data transfer control device according to the present invention described above is realized by a program that causes a computer to execute processing. Examples of the computer include general-purpose computers such as personal computers and workstations, but the present invention is not limited to this. Therefore, as an example, a case where the present invention is realized by a program will be described below.

For example, in the flowcharts shown in FIGS.
A two-wire serial data transfer control system device including one or more slave devices connected to a master device by a two-wire serial data transfer means and having an address space composed of one or more slave devices as one address space 2-wire serial data transfer control program,
In order to generate a slave address as a transfer partner from the address where access starts,
On the computer,
(a) a procedure for determining whether or not the master device has exceeded the upper limit of the memory address space of the slave device during serial data transfer between the master device and the slave device;
(b) The procedure for the master device to end 2-wire serial data transfer when the upper limit is exceeded,
(c) a procedure for the master device to generate a slave address as the next transfer partner from the memory address;
(d) a procedure for the master device to resume serial data transfer from a continuous address space;
A program that executes
Thus, the apparatus according to the present invention can be realized anywhere as long as there is a computer environment capable of executing the program.
Such a program may be stored in a computer-readable storage medium.

<Storage medium>
Here, examples of the storage medium include computer-readable storage media such as CD-ROM (Compact Disc Read Only Memory), flexible disk (FD), and CD-R (CD Recordable), flash memory, and RAM (Random Examples thereof include semiconductor memories such as Access Memory (ROM), ROM (Read Only Memory), and FeRAM (ferroelectric memory), and HDD (Hard Disc Drive).

<Effect>
According to the present embodiment, a serial data transfer system device composed of a master device and one or more slave devices connected by a two-wire serial data transfer means, and an address space comprising one or more slave devices Since the master device has a means for generating a slave address as a transfer partner from the address at which access is started, the slave device has a necessary slave address value on the 2-wire serial data transfer protocol. Software preparation for issuing is unnecessary, and the software storage device can be reduced. This also reduces the processor processing load and shortens the processor processing time.

  Further, according to the present embodiment, when the upper limit of the memory address space of the slave device is exceeded during serial data transfer with the slave device, the two-wire serial data transfer is terminated (sequence device). From the memory address, it has a means (sequence device) for generating a slave address as the next transfer partner and resuming serial data transfer from the continuous address space. Since the process can be terminated and the start of transfer to the next slave device is automated, the series of processes applied to the processor can be reduced and the processor processing time can be shortened.

  Further, it becomes unnecessary to prepare software for the processor processing, and the software storage device for the processor can be reduced.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.

401 processor 402 program memory 403 2-wire serial data transfer control device 404 transmission / reception setting device 406 slave address selection device 407 2-wire serial data transfer sequence device 408 clock line 409 serial data line

JP 2008-135840 A Japanese Patent Laid-Open No. 11-126178

Claims (9)

A two-wire serial data transfer control system device including one or more slave devices connected to a master device by a two-wire serial data transfer means, and having an address space made up of the one or more slave devices as one address space The wire serial data transfer control method of
A two-wire serial data transfer control method, wherein a slave address as a transfer partner is generated from an address at which access is started.   If the upper limit of the memory address space of the slave device is exceeded during serial data transfer between the master device and the slave device, the two-wire serial data transfer is terminated, and the slave to be the next transfer partner from the memory address 2. The two-wire serial data transfer control method according to claim 1, wherein an address is generated and serial data transfer from a continuous address space is resumed.   When the upper limit of the memory address space of the slave device is exceeded or the lower limit is not reached during the serial data transfer between the master device and the slave device, the two-wire serial data transfer is terminated, 2. The two-wire serial data transfer control method according to claim 1, further comprising a sequence device for generating a slave address to be a transfer partner of the second address and resuming serial data transfer from a continuous address space. A two-wire serial data transfer control system device including one or more slave devices connected to a master device by a two-wire serial data transfer means, and having an address space made up of the one or more slave devices as one address space 2 wire serial data transfer control program,
In order to generate a slave address as a transfer partner from the address where access starts,
On the computer,
A procedure for determining whether the master device has exceeded the upper limit of the memory address space of the slave device during serial data transfer between the master device and the slave device;
A procedure for ending the two-wire serial data transfer when the master device exceeds the upper limit;
The master device generates a slave address as a next transfer partner from the memory address,
A procedure for the master device to resume serial data transfer from a continuous address space;
A program characterized by having executed. A two-wire system including a master device and one or more slave devices connected to the master device by a two-wire serial data transfer unit, and an address space composed of the one or more slave devices as one address space A two-wire serial data transfer control device used in a serial data transfer control system device,
The master device includes the two-wire serial data transfer control device, and the two-wire serial data transfer control device includes a generation device that generates a slave address serving as a transfer partner from an address at which access is started. A two-wire serial data transfer control device. The master device is
If the upper limit of the memory address space of the slave device is exceeded during serial data transfer with the slave device, the 2-wire serial data transfer is terminated and a slave address to be the next transfer partner is generated from the memory address. 5. The two-wire serial data transfer control device according to claim 4, further comprising a sequence device for resuming serial data transfer from a continuous address space. The master device is
When the upper limit of the memory address space of the slave device is exceeded or less than the lower limit during serial data transfer with the slave device, the two-wire serial data transfer is terminated, and the next transfer partner is transferred from the memory address. 5. The two-wire serial data transfer control device according to claim 4, further comprising a sequence device for generating a slave address and restarting serial data transfer from a continuous address space.   The master device includes a memory address setting device that sets a memory address, and a slave address selection device that determines a slave device that is a target of data transfer by setting an arbitrary address from memory addresses in a continuous address space. 8. The two-wire serial data transfer control device according to claim 6, further comprising:   The slave address selection device includes a setting device for setting an upper address limit and an address lower limit, an address setting value and an upper limit address setting value from the setting device, and an address setting value and a lower limit address setting value that are within or out of range, respectively. And a logic circuit that detects whether the address set value is within the range of the upper limit address set value to the lower limit address set value and generates a slave address selection signal from the detection results of both the arithmetic units. The two-wire serial data transfer control device according to claim 8.

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