JP2011103608A - Packet forwarding apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To overcome the problem with an apparatus for forwarding packets, wherein a latency to BANK active, read command input, and data output, and a BANK precharge after data transfer are required for accessing data when the apparatus uses a versatile DRAM memory of low bit unit price and large capacity for achieving high-speed access of forwarding information stored in a storage apparatus, and as a result, the transfer efficiency of data is not raised. <P>SOLUTION: By continuously allocating a plurality of input physical ports to a memory BANK, and continuously repeating BANK interleave access to raise the data transfer efficiency of a memory, and a memory band required for reading out forwarding information of the input physical ports is assured. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to memory access in packet transfer processing.

Communication devices such as bridges and routers have a plurality of data input / output interfaces (ports) called a packet. For each packet, these devices search and refer to a large number of databases in the device based on the information attached to the port from which the packet was received and the control information attached to the packet. Determine the processing method. The processing includes operations such as changing or processing packet control information, discarding packets based on the inflow or outflow amount of packets, or sending to specific ports based on database search results. . In these processes, it is necessary to search a large number of databases. When the communication interface becomes high speed, the storage device (memory) in the apparatus storing the database becomes a bottleneck, and the processing speed is limited. The transmission speed is not completely used up.
For this reason, in the conventional apparatus, the database search result is stored in a temporary information storage area called a cache, and forwarding processing is realized at high speed for packets that arrive frequently (see, for example, Patent Document 1).

JP2009-17439

  There are high-speed accessible memories for storing forwarding information, such as CAM and clock-synchronized SRAM, but they have a small capacity and a large current consumption. Therefore, when large capacity is required, DRAM is generally used. However, DRAM access has a problem that the latency from the command input to the start of data transfer and the precharge period after the data transfer are required, and the data transfer efficiency is low.

In order to solve the above problems, a packet transfer apparatus according to an aspect of the present invention includes an input / output port that is an input / output interface of a packet, a packet processing block that performs processing related to packet forwarding, and various forwarding information related to forwarding. It consists of DRAM to store. The packet processing block includes a field extraction unit that extracts a field related to forwarding, an index calculation unit that calculates an address in which forwarding information related to the packet is stored from the extracted field, and a packet from which physical port A physical line number extraction unit that extracts whether the input has been performed; a DRAM access unit that performs reading, writing, and refreshing to the DRAM; a control unit that performs writing and maintenance of forwarding information to the DRAM access unit; A forwarding unit that performs packet forwarding processing, a BANK mapping unit that allocates a physical address from a physical line to a BANK address in the DRAM, and a DRAM address from a field extracted from the packet. An address mapping unit that allocates the scan, characterized by comprising a data input-output unit for performing temporary storage of the write and read data forwarding information. In order to process the packet input by the packet transfer device, read access to the related forwarding information is executed in a time-sharing manner for the BANK in the DRAM fixedly allocated in advance for each physical port input by the packet. Thus, the delay factor associated with the read operation from the DRAM is eliminated.

  A DRAM access means for ensuring the data transfer efficiency for reading the aforementioned forwarding information by configuring the storage device of the cache information necessary for forwarding with DRAM memory and allocating the input physical port to the BANK of the DRAM is provided. , Improve packet processing speed

Functional block diagram showing the configuration of the packet transfer apparatus of the present embodiment The timing of conventional DRAM burst read access is shown. The access timing of BANK interleaving in a basic 1RANK DIMM configuration is shown. The access timing in 2RANK DIMM structure in the embodiment is shown. The block diagram which shows the allocation to the physical port and BANK interleave in this invention. The block diagram which shows the memory cycle structure of this invention in the minimum packet receiving period in Ethernet of 1GBit rate. The block diagram which shows the minimum packet receiving period in Ethernet of 1GBit rate.

  FIG. 1 is a functional block diagram showing the configuration of the packet transfer apparatus of this embodiment. The packet transfer device 20 includes an input / output port 1, a packet processing block 2, and a DRAM 3. The packet processing block 2 includes a field extraction unit 10, an index calculation unit 11, a physical line number extraction unit 12, a DRAM access unit 13, a control unit 16, a forwarding unit 15, and a BANK inside the DRAM access unit. A mapping unit 13-1, an address mapping unit 13-2, and a data input / output unit 13-3 are provided.

  The DRAM 3 stores forwarding information that is information necessary for packet transfer. Types of forwarding information include a port database that stores information related to ports, a forwarding database that stores Ethernet (registered trademark) addresses (Forwarding DataBase, FDB), and a virtual local area network (VLAN). Virtual local area network table that stores information on the port, port virtual local area network table that stores information retrieved using the port and virtual local area network as a key, packet forwarding service Quality of Service (QoS) parameters that store level information . The DRAM 3 has a plurality of forwarding information entries. These pieces of information are recorded in the DRAM 3 in a boundary based on certain data bytes such as 64 bytes and 128 bytes.

The field extraction unit 10 extracts a field related to forwarding included in the transfer target packet received by the input / output port unit 1. A field related to forwarding is included in a part (header) of a packet, and is a part of control information including a source address, a destination address, quality of service (QoS), and the like. The index calculation unit 11 calculates a hash value of a field related to forwarding extracted by the field extraction unit 10, calculates an index based on the calculated hash value, and converts the index value into an address mapping unit 13-in the DRAM access unit 13. 2 is notified. The physical number extraction unit 12 extracts the physical number of the input / output port from the received packet and notifies the BANK mapping unit 13-1 in the DRAM access unit 13. The DRAM access unit 13 includes the BANK mapping unit 13-1, the address mapping unit 13-2, and the data input / output unit 13-3, and is based on a field related to forwarding included in a received packet and a physical line number. DRAM address information is generated, and data information of the DRAM 3 is input and output by the data input / output unit 13-3. Here, the input indicates read data from the DRAM 3 and the output indicates write data to the DRAM 3. The DRAM 3 stores forwarding information entries, and outputs the forwarding information to the data input / output unit 13-3 based on the address information. The forwarding unit 15 processes the packet received from the input / output port 1 based on the forwarding information referred to by the DRAM access unit 13 and transfers the packet to the designated input / output port 1 based on the forwarding information. It has a function to perform.

  The control unit 16 is a control module for controlling the DRAM access unit 13 from the CPU, and has a function related to storing forwarding information entries in the DRAM 3 and maintenance of forwarding information.

An embodiment of the invention in the DRAM access unit 13 will be described. Note that the DRAM 3 is mounted in a DIMM. Since DRAMs and DIMMs are general devices, basic items in device access are omitted as known ones. Regarding the DIMM, the embodiment will be described based on the registered DIMM. Further, in the description of the present invention, a DDR2 800 (operating frequency 400 MHz) 64-bit size registered DIMM is taken as an example.
FIG. 2 shows the timing of burst read in a conventional DRAM. Here, the DRAM operates in synchronization with the memory operation clock CK100. After BANK is activated by the BANK active command 101-1 at the rising edge of the clock timing 100-1, CL (cass) from the read command input to the read data output is executed by executing the read command 101-2 after tRCD = 6CK104. Read data is output from the DIMM after (latency) = 6CK + 1CK106. The DRAM has a function called AL (additive latency). This is a function capable of issuing a command without waiting for a command executed after the tRCD time 104 in the memory. In FIG. 2, the timing for issuing a read command with AL = 4 103 is shown. After reading the data 102-1 from the activated BANK memory, BANK is precharged 101-3 after tRAS = 18CK105, and the next BANK active 101-4 is possible after waiting for tRP = 6CK109 to complete the precharge. It becomes. The basic unit of the read data 102-1 is burst access (maximum 8 cycles). If the read command and address are continuously input within the active BANK page range, data can be read continuously. This continuous data reading is a mechanism provided in the DRAM as a burst read.

  By performing the burst read, the forwarding information read time from the DRAM can be shortened. However, since the time from the BANK active to the newly active becomes = 24CK108, the read data 102− The transfer time 4CK required for 1 is a data transfer ratio of 16.6% with respect to the number of 24CK in the basic cycle.

FIG. 3 shows the burst read timing in the BANK interleaving of the DRAM. This is a general method for increasing the data transfer ratio in which data from each BANK is made continuous by continuously activating each BANK of the memory configured in a divided manner. AL = 4 1
Using the function 03, BANK0 to BANK3 are activated continuously to generate a read command (111-1 to 111-7). At this time, continuous BANK active inputs are subject to the time constraint of tRRD = 6CK113. In continuous access with BANK interleave, the output data is a continuous byte string (116 to 119). In this case, BANK0 active 111-9 can be input at a CK timing of 110-4 after tFAW = 14CK115 hours from BANK3 active 111-7 without waiting for completion of data transfer. In this case, the time tRAS = 18CK105 and tRP = 6CK109 necessary for precharging BANK0 are included in the timing constraint time of tFAW = 14CK115. In FIG. 3, the data transfer time for 4 BANKs when BANK interleaving is 16 CK, and the read data transfer rate increases to 55% with respect to 29 CK until the completion of the data transfer of CK110-5.

FIG. 4 shows the access timing of BANK interleaving in the 2RANK DIMM configuration according to the present invention. In the case of this configuration, by issuing a BANK active and read command (132-1 to 132-4) of RANK2 during a burst read of RANK1 (133-1 to 133-4), 1CK is used to switch the data read to RANK. (140
And 141) can be added to enable continuous burst read cycles.
In the case of the 2RANK DIMM in the present invention, the forwarding information to be written to the memory by making use of the configuration of the DIMM sharing the signal line on the bus is simultaneously written in each of the memory devices RANK1 and RANK2, and the read cycle is performed by RANK. Separation enables continuous BANK access. In this case, the data transfer time in the basic read cycle = 47CK137 is 34CK139, and the data transfer ratio increases to 72% with respect to 47CK. In addition, after the start 13CK of the read cycle, BANK access becomes possible as a continuous data read cycle. TRP = 6CK109 and tFAW = 14CK115 for each RANK can earn necessary time by straddling RANK, and this time correspondence can be ignored in the timing design.

  As described above, it is possible to improve the data transfer ratio of the DRAM by using the BANK interleave access of the DRAM, but the DRAM address calculated from the field included in the received packet from each physical port has a unique value. 2 cannot be simply replaced with BANK interleaved continuous access, and the timing shown in FIG. 2 hinders the transfer ratio of interrupt data.

In order to solve this problem and to make BANK interleave access in which the DRAM read cycle of the forwarding information of the received packet is fixed, in this proposal, forwarding information for one packet received from the physical port is stored in one burst access of the DRAM. As a result, information necessary for forwarding one packet is read from the DRAM by one burst access (maximum 8 cycles) of BANK. Furthermore, by assigning the physical port continuously and fixedly to the BANK divided into DRAMs, the DRAM read cycle of forwarding information corresponding to the physical port is fixed to the continuous burst access by the BANK interleave in which the time division is fixed. It can be replaced. This makes it possible to design the DRAM timing as the continuous timing of the cycle shown in FIG.

FIG. 5 is a block diagram showing an access method in BANK interleaving according to the present invention. By mapping a plurality of input physical ports 140 to continuous memory BANK 141, it is possible to read forwarding information by BANK interleaving shown in FIG. The forwarding information stored in the DRAM 3 is determined by the physical line number extraction unit 12 and the BANK mapping unit 13-1 from each physical port (140-1 to 140-8), and the address information included in the received packet is indexed. The unit 11 and the address mapping unit 13-2 perform mapping to the address in BANK.

  The present invention repeats sequential BANK access in units of physical ports, resulting in a BANK read cycle in which forwarding information cached in a burst read size boundary necessary for forwarding received packets is time-divided in the order of physical ports. By providing this, high-speed access to the memory is realized.

In the present invention, writing of forwarding information is performed at the time of initial setting at the time of starting the apparatus and at the time of receiving a new packet outside the initial setting, and is not accompanied by immediacy. Further, the DRAM refresh is generally performed once every 78 μS. FIG. 7 is a diagram showing a trial calculation of the number of physical ports that can be accommodated at the time of implementation of the present invention in the minimum packet cycle of a physical port of 1 Gbit rate. A memory read is assigned a time 149 obtained by subtracting a refresh or memory write period 150 after the end of reading and 13CK148 from the generation of a BANK active command accompanying the start of reading of the DRAM to the start of read data transfer.
As shown in FIG. 6, the minimum received packet size 143 at the 1 Gbit rate is 84 bytes = 672 bits = 672 nS by taking an Ethernet packet as an example. Operating frequency 400M
In the DDR2 DRAM clock period of 2.5 nS, 268.8CK147 of FIG. 7 is obtained. The time allocated to burst read is 170CK149, and the continuous data read cycle of RANK1 and RANK2 at the time of BANK interleaving in FIG. The calculation can handle 40 ports as the number of physical ports.
In this case, the data transfer time related to the read is 160CK by subtracting 1CK (140 and 141) of data switching between the data transfer period 170CK and RANK, which is a data transfer ratio of 87% with respect to the total 183CK of 13CK148 and 170CK149. become.

1: I / O port 2: Packet processing block 3: DRAM
10: Field extraction unit 11: Index calculation unit 12: Physical line number extraction unit 13: DRAM access unit 13-1: BANK mapping unit 13-2: Address mapping unit 13-3: Data input / output unit 15: Forwarding unit 16: Control unit 20: Packet transfer device 100: DRAM operation clock 100-1: ACT input timing 100-2: READ input timing 100-3: READ execution timing 100-4: Precharge (precharge execution timing)
100-5: ACT input timing (after precharge execution)
101: Command 101-1: ACT (BANK active command)
101-2: READ (read command)
102: Data 102-1: Burst data output 103: AL (additive latency)
104: tRCD = 6CK
105: tRAS = 18CK
106: CL = 6CK + 1CK
107: Time from BANK active to data output = tRCD + CL + 1CK =
13CK
108: Time from BANK active until new BANK active becomes possible = 24
CK
109: tRP = 6CK
110: DRAM operation clock 111: Command 111-1: BANK0 ACT command 111-2: BANK0 READ command 111-3: BANK1 ACT command 111-4: BANK1 READ command 111-5: BANK2 ACT command 111-6: BANK2 READ command 111-7: BANK3 ACT command 111-8: BANK3 READ command 111-9: BANK0 ACT command 112: Data 114: Basic read cycle = 29 CK
115: tFAW = 14CK
116: BANK0 read data 4CK
117: BANK1 read data 4CK
118: BANK2 read data 4CK
119: BANK3 read data 4CK
120: BANK0 read data 121: 10CK
122: 13CK
130: DRAM operation clock 130-1: RANK1 BANK0 ACT command input timing 130-2: RANK1 BANK1 ACT command input timing 130-3: RANK2 BANK0 ACT command input timing 130-4: RANK1 BANK0 ACT command input timing 130-5: RANK1 BANK0 read data output timing 131: RANK1 command 131-1: RANK1 BANK0 ACT and READ command 131-2: RANK1 BANK1 ACT and READ command 131-3: RANK1 BANK2 ACT and READ command 131-4: RANK1 BANK3 ACT and READ command 132 : RANK2 command 131-1: RANK2 BA K0 ACT and READ command 131-2: RANK2 BANK1 ACT and READ command 131-3: RANK2 BANK2 ACT and READ command 131-4: RANK2 BANK3 ACT and READ command

133: RANK1 data 133-1. RANK1 BANK0 read data 133-2: RANK1 BANK1 read data 133-3: RANK1 BANK2 read data 133-4: RANK1 BANK3 read data 133-5: RANK1 BANK0 read data 134: RANK2 data 134- 1: RANK2 BANK0 Read data 134-2: RANK2 BANK3 Read data 137: Basic read cycle = 47CK
139: RANK1 and RANK2 continuous data read cycle = 34CK
140: 1CK
141: 1CK
143: 84 Byte = 672 BIT (672 nS 1 Gbit / S conversion)
144: Preamble + SFD (8 bytes)
145: Minimum packet (64 bytes)
146: Inter-frame gap (12 bytes)
147: 1 packet interval 672nS = 268.8CK (CK = 400MHz = 2.5
nS)
148: From 1ST command generation to read data generation 13CK
149: BANK interleaved burst read cycle in 2RANK configuration
34CK (8 Port min) x 5 cycles = 170CK
149-1: BANK0 physical port 1 Burst access 150: Refresh or random burst write cycle to BANK

Claims (6)

An input / output port that is an input / output interface of a packet, a packet processing block that performs processing related to forwarding of the packet, and a DRAM that stores various forwarding information related to the forwarding,
The packet processing block includes a field extraction unit that extracts a field related to the forwarding;
An index calculator that calculates an address in which the forwarding information related to the packet is stored from the extracted field;
A physical line number extraction unit for extracting from which physical port the packet is input;
A DRAM access unit for performing read, write, and refresh on the DRAM;
Writing the forwarding information to the DRAM access unit, and a control unit for performing maintenance;
A forwarding unit that performs the forwarding process of the packet;
A BANK mapping unit for assigning a BANK address in the DRAM from the physical port in the DRAM access unit;
An address mapping unit that assigns a DRAM address from the field extracted from the packet;
A data input / output unit for temporarily writing the forwarding information and storing read data;
A packet transfer apparatus comprising: A packet transfer method comprising: an input / output port that is an input / output interface of a packet; a packet processing block that performs processing related to forwarding of the packet; and a DRAM that stores various forwarding information related to the forwarding;
A field extraction step for extracting fields related to the forwarding from the packet;
An index calculating step for calculating an address in which the forwarding information related to the packet is stored from the field;
A physical line number extracting step for extracting from which physical port the packet is input;
Assigning the physical port number of the packet extracted in the physical line extraction step to a BANK address of the DRAM;
Outputting the BANK address cyclically in parallel;
Outputting the address where the forwarding information is stored in the index calculation step;
Reading the forwarding information about the packet from the BANK address and the address where the forwarding information is stored;
Performing the forwarding process of the packet from the forwarding information read from the DRAM;
A packet transfer method comprising: Fixedly assigning a physical number of an input / output port, which is an input / output interface of a packet, to a BANK address of a DRAM storing forwarding information of the packet;
Interleaving the BANK access of DRAM in a cyclic parallel manner;
The packet transfer method according to claim 2, further comprising:   3. The packet transfer method according to claim 2, wherein the read cycle time to each BANK of the DRAM is fixed at each round by fixing the amount of forwarding information necessary for packet forwarding processing to a fixed length. .   3. The packet transfer method according to claim 2, wherein the DRAM read cycle is separated from a DRAM refresh cycle or a DRAM write cycle.   3. The packet transfer method according to claim 2, wherein a write cycle is simultaneously performed in a 2RANK DRAM in a 2RANK DIMM, and read access is divided by RANK1 and RANK2.

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