JP2011103554A - Fifo buffer, and method of discarding data of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of selectively and efficiently discarding a packet stored in an FIFO buffer. <P>SOLUTION: The FIFO buffer for sequentially reading data in order of writing includes a reading data designation part 109 for rewriting reading address data representing the top address of a packet to be discarded to data representing the top address of a packet next to the packet to be discarded before discarding the packet to be read next. The packet can be selectively discarded by rewriting the reading address data representing the top address of the packet to be discarded to the data representing the top address of the packet next to the packet to be discarded before discarding the packet to be read next. The packet can be efficiently discarded by only rewriting the reading address data representing the top address of the packet to be discarded. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a first-in first-out (FIFO First In First Out) buffer capable of selectively discarding data and a data discarding method of a first-in first-out buffer.

  In a data transfer system that performs data transfer, a unit of data to be transferred is called a packet. A FIFO buffer for storing a packet is generally used at a transmission / reception end of the data transfer system. Packets are read from the FIFO buffer in the order in which the packets are written.

  In a data processing system including a data transfer system, a packet held in the FIFO buffer of the data transfer system may become unnecessary during processing. As an example, when a control processor transfers data to a plurality of arithmetic processors and causes a plurality of arithmetic processors to perform an operation within a slice that is a unit time of arithmetic processing, the operation is not completed at the end of the slice. For example, the processing of the processor may be aborted.

  The conventional FIFO buffer has a reset function that initializes all addresses to be written to the FIFO buffer and addresses to be read from the FIFO buffer. By using the FIFO buffer reset function, all the packets stored in the FIFO buffer are discarded.

  However, when there is a possibility that a packet that should not be discarded is included in the FIFO buffer, the above-described reset function cannot be used. In such a case, in the conventional system, after reading the packet from the FIFO buffer, a method of leaving the packet determined to be discarded as it is (for example, the 13th to 19th patent documents 1). Paragraph).

  However, in the above conventional method, considerable processing recycling is required for the operation of reading the packet in the FIFO buffer. This consumes processing cycles to process packets that are not needed, resulting in reduced system efficiency.

  As described above, a FIFO buffer having a function capable of selectively discarding a stored packet and a packet discarding method capable of selectively and efficiently discarding a packet stored in the FIFO buffer have been developed. Not.

JP-A-7-262151

  Accordingly, there is a need for a first-in first-out buffer having a function capable of selectively discarding stored packets and a packet discarding method capable of selectively and efficiently discarding the packets stored in the first-in first-out buffer.

  According to the present invention, the first-in first-out buffer for reading out data in the order written is read address data indicating the head address of the packet to be discarded, and the head address of the packet next to the packet to be discarded before discarding the next packet to be read. A read data instruction unit for rewriting data to be shown is provided.

  According to the present invention, in the first-in first-out buffer for reading out data in the order written, the method for discarding the packet is to read the read address data indicating the head address of the packet to be discarded before discarding the next packet to be read. The packet is discarded by rewriting the data indicating the head address of the next packet.

  According to the present invention, before discarding the next packet to be read, the read address data indicating the head address of the packet to be discarded is rewritten to data indicating the head address of the packet next to the packet to be discarded. Packets can be discarded. Further, the packet can be efficiently discarded by simply rewriting the read address data indicating the start address of the packet to be discarded.

  According to the embodiment of the present invention, the packet data length included in the header of the packet to be discarded is added to the read address data indicating the head address of the packet to be discarded, and the packet next to the packet to be discarded Data indicating the start address of is obtained.

  According to the present embodiment, by using the packet data length included in the header of the packet to be discarded, data indicating the start address of the packet next to the packet to be discarded is not required without using a complicated mechanism. Obtainable.

  According to the embodiment of the present invention, a packet in which the packet data length field is located at the head of the header information is handled.

  According to this embodiment, it is convenient when the packet data length is extracted from the header information.

FIG. 3 is a diagram illustrating input / output signals of a FIFO buffer that can selectively discard data according to an exemplary embodiment of the present invention. It is a figure which shows an example of a structure of the FIFO buffer which can selectively discard the data by one Embodiment of this invention. It is a figure for demonstrating the data structure of a packet. 3 is a flowchart illustrating a packet discarding method according to an embodiment of the present invention. It is a figure which shows the state of the packet memorize | stored in the FIFO buffer. 1 is a diagram illustrating an entire configuration of a network using a FIFO buffer capable of selectively discarding data according to an embodiment of the present invention. FIG. It is a figure which shows the structure of the node containing the FIFO buffer used for the network shown in FIG. It is a figure for demonstrating a packet discard process. It is a flowchart which shows the above-mentioned packet discard method by a control circuit. It is a figure which shows the input / output signal of the conventional FIFO buffer. It is a figure which shows an example of a structure of the conventional FIFO buffer.

  FIG. 1 is a diagram illustrating input / output signals of a FIFO (First In First Out) buffer 100 that can selectively discard a packet according to an embodiment of the present invention. The FIFO buffer 100 receives received data from the outside and sends the received data to the internal bus. The FIFO buffer 100 further receives a reset signal and a packet discard signal. When receiving the reset signal, the FIFO buffer 100 discards all the stored packets as in the conventional FIFO buffer. When receiving the packet discard signal, the FIFO buffer 100 selectively discards the next packet to be transferred.

  FIG. 10 is a diagram showing input / output signals of the conventional FIFO buffer 150. In the conventional FIFO buffer 150, there is no packet discard signal.

  FIG. 2 is a diagram illustrating an example of the configuration of the FIFO buffer 100 that can selectively discard data according to an embodiment of the present invention. The FIFO buffer 100 includes a 2-port memory 101, a write data register 103, a write address instruction unit 105, a read data register 107, a read address instruction unit 109, and an adder 111.

  FIG. 11 is a diagram illustrating an example of the configuration of a conventional FIFO buffer 150. The FIFO buffer 150 includes a 2-port memory 151, a write data register 153, a write address instruction unit 155, a read data register 157, and a read address instruction unit 159. The conventional FIFO buffer 150 does not handle a packet discard signal.

  Returning to FIG. 2, when the write address instruction unit 105 receives the write command wr_A, it sends a write command to the write data register 103, and the write data register 103 changes the contents of the write data register 103 to the port A of the 2-port memory 101. Send to. Further, the write address instruction unit 105 sends a write command and an address of the 2-port memory 101 to which data is to be written to the port A of the 2-port memory 101. The 2-port memory 101 writes the received data to the received address. The write address instruction unit 105 increments the stored address to indicate the address to which data is to be written next.

  When receiving the read command rd_B, the read address instruction unit 109 sends the read command and the address of the 2-port memory 101 from which data is to be read to the port B of the 2-port memory 101. The 2-port memory 101 sends the data read from the received address to the read data register 107. The read address instruction unit 109 increments the stored address and indicates the address from which data is to be read next.

  When the reset signal is received, all data in the write data register 103, the write address instruction unit 105, the read data register 107, and the read address instruction unit 109 are cleared. As a result, all data in the 2-port memory 101 is discarded.

  When receiving the packet discard signal, the read address instruction unit 109 receives the output of the adder 111. One input terminal of the adder 111 is connected to the head address of the next packet to be read, which is held by the read address instruction unit 109. The other input terminal of the adder 111 is connected to the packet data length of the header information of the next packet to be read, which is stored in the read data register 107. Therefore, the output of the adder 111, that is, the data received by the read address instruction unit 109 from the adder 111 is data indicating the head address of the next packet to be read next. In this state, when the read command rd_B is received, the read address instruction unit 109 sends the read command and data indicating the next address of the next packet to be read and the data indicating the head address of the next packet to the 2-port memory 101. As a result, the packet scheduled to be read next is discarded. As described above, according to the present embodiment, the packet that was scheduled to be read next is discarded by one cycle of processing.

  FIG. 3 is a diagram for explaining the data structure of a packet. In order to connect the packet data length of the header information of the packet to be read next to the input terminal of the adder 111, it is preferable that the packet data length field is located at the head of the packet header information. In the data structure shown in FIG. 3, the packet data length field is located at 16 bits (from the 48th bit to the 63rd bit) of the header position of the packet header information.

  FIG. 4 is a flowchart illustrating a packet discarding method according to an embodiment of the present invention.

  In step S1010 of FIG. 4, the read address instruction unit 109 receives a “packet discard signal”. The “packet discard signal” is output by the control circuit as will be described later.

  In step S1020 of FIG. 4, the read address instruction unit 109 determines whether there is a valid entry to be discarded in the 2-port memory 101. Here, the read address instruction unit 109 may determine whether there is a valid entry to be discarded by the Rd_valid signal output from the 2-port memory 101 and shown in FIG. If there is a valid entry, the process proceeds to step S1030. If there is no valid entry, the process ends.

  In step S1030 of FIG. 4, the read address instruction unit 109 stores the start address of the next packet to be read held by the read address instruction unit 109 and the header information of the next packet to be read stored in the read data register 107. Is received from the adder.

  In step S1040 of FIG. 4, the read address instruction unit 109 newly stores the output of the adder 111 as a new head address of the next packet to be read.

  FIG. 5 is a diagram illustrating a state of a packet stored in the 2-port memory 101. In FIG. 5, it is assumed that the address has the largest head. In FIG. 5, the 2-port memory 101 includes four packets from packet m to packet m + 3. The write address of port A is the address next to the last address of packet m + 3. The read address of the port B before executing the packet discard is the head address of the packet m. When the packet discard signal is output and the read address instruction unit 109 executes the packet discard process, the read address of the port B is a value obtained by adding the packet data length of the packet m to the head address of the packet m, that is, the packet m + 1. This is the start address.

  In general, the write address and the read address are incremented by the write address instruction unit 105 and the read address instruction unit 109, respectively, and become zero when the upper limit value (capacity of the two-port memory 101) is reached. When the write address catches up with the read address, the 2-port memory 101 becomes full. When the read address catches up with the write address, the 2-port memory 101 becomes empty. The Rd_valid signal in FIG. 2 is output when the write address is larger than the read address, and indicates that valid data exists in the 2-port memory 101.

  Next, an example of the configuration of a data processing system using the FIFO buffer 100 capable of selectively discarding data according to an embodiment of the present invention will be described.

  FIG. 6 is a diagram illustrating an entire configuration of a network using a FIFO buffer capable of selectively discarding data according to an embodiment of the present invention. The network includes a switch 303 and a node 0 (301), a node 1 (305), a node 2 (307), a node 3 (309), and a node 4 (311) connected to the switch 303. Node 0 (301) functions as a system master. Node 1 (305) to node 4 (311) function as operation nodes. The switch 303 has a function of transferring packet data between the five nodes.

  Node 0 (301) transmits parameters for computation to each computation node and controls the entire system. As an example, the node 0 (301) transmits the packet data of the synchronization signal indicating the start of the slice, which is the basic unit time of the arithmetic processing, and the packet data of the parameters necessary for the arithmetic to each arithmetic node.

  The operation nodes 1 (305) to 4 (311) execute the job instructed by the node 0 (301), which is the system master, and send the result back to the node 0 (301). The contents of the job include numerical calculation execution, collection of measurement information, audio information, image information, etc. from the devices 313 to 319 connected to the operation nodes 1 (305) to 44 (311), and the devices 313 to 319. Control, output of audio information, image information, and the like to the devices 313 to 319. As an example, in the operation node 1 (305), information may be periodically collected from a measuring instrument, and motor control may be performed in combination with parameters sent from the node 0 (301). The basic period of motor control is set to the same time as the slice, which is the basic unit time of the arithmetic processing, for example, 1 millisecond.

  Here, it is assumed that each computation node cannot continue the computation beyond the slice time. That is, each time an arithmetic node receives a synchronization signal indicating the start of a slice from node 0 (301), if there is an ongoing process, it stops that process and starts a new process. For example, in the case of the motor control described above, processing for a new basic cycle is started.

  FIG. 7 is a diagram showing a configuration of the node 1 (305) including the FIFO buffer used in the network shown in FIG. The node 1 (305) includes a digital reception interface 201, a frame data reception FIFO buffer 100A, a control data reception FIFO buffer 150A, an internal computing unit 203, a packet management unit 205, a control circuit 207, a frame data transmission FIFO buffer 150B, A control data transmission FIFO buffer 150C and a digital transmission interface 209 are included. The digital reception interface 201 and the digital transmission interface 209 are high-speed digital communication interfaces using differential signals such as LVDS (Low Voltage Differential Signaling).

  In the following, assuming that the frame data receiving FIFO buffer 100A has the packet discarding function shown in FIG. 2, the normal processing and packet discarding processing of the FIFO buffer 100A will be described.

  The synchronization signal described in the network of FIG. 6 is handled as control data, and parameter information for calculation is handled as frame data. The control data receiving FIFO buffer 150A is a conventional FIFO buffer. The control data reception FIFO buffer 150 </ b> A receives a read command from the control circuit 207 and sends reception control data to the control circuit 207. The control circuit 207 is informed of the reception of the control data from the control data reception FIFO buffer 150A, and appropriately outputs a read command. As described above, the frame data reception FIFO buffer 100A has the packet discard function shown in FIG. The frame data receiving FIFO buffer 100A receives a read command from the control circuit 207, and sends the received frame data held in the frame data receiving FIFO buffer 100A to the internal computing unit 203. The control circuit 207 is informed of reception of frame data from the frame data reception FIFO buffer 100A, and informed of the processing state from the internal arithmetic unit 203, and appropriately outputs a read command.

  Assuming that the number of packets scheduled to be received during a slice is known, it is set in advance in the packet management unit 205. The packet management unit 205 includes a packet counter (not shown), and the packet counter is set to zero when the communication channel is reset, for example, at the start of a slice. The packet counter counts the number of packets read using the data information received by the internal arithmetic unit 203.

  FIG. 8 is a diagram for explaining the packet discarding process. The horizontal axis in FIG. 8 shows the passage of time. A packet including a synchronization signal notifying the start of the slice is received by the FIFO buffer 150A and sent to the control circuit 207. The time at this time is t1. At this time, the internal computing unit 203 is processing the packet (S1 + M−3). At this time, the read pointer of the FIFO buffer 100A points to the position of the head address of the packet (S1 + M-3). Here, the read pointer is a register that holds data indicating the read address described with reference to FIG.

  In this state, for example, all data in the FIFO buffer 100A cannot be discarded by a reset signal. The reason is as follows. First, the data of the packet (S1 + M−3) is being read at time t1. Second, at time t2, the packet (S2 + 0) used in the next slice has already been received. Third, there is no time to reset all at once.

  Therefore, the control circuit 207 discards subsequent packets after processing up to the packet (S1 + M−3). The control circuit 207 reads data using a normal rd_b read signal until time t2. Based on information from the packet management unit 205, the control circuit 207 recognizes that the number of unprocessed packets is three. In this embodiment, there are three unprocessed packets that should be specifically discarded (S1 + M−2), (S1 + M−1), and (S1 + M). The control circuit 207 outputs a read signal of rd_b according to a normal process at time t2. As a result, the read pointer of the FIFO buffer 100A points to the position of the head address of the packet (S1 + M-2). The read data register 107 shown in FIG. 2 holds the top data of the packet (S1 + M−2). In this state, at time t3, the control circuit 207 outputs a first packet discard signal. Then, the FIFO buffer 100A performs the processing shown in FIG. 4, and the read pointer of the FIFO buffer 100A indicates the position of the head address of the packet (S1 + M−1). Also, the read data register 107 shown in FIG. 2 holds the top data of the packet (S1 + M−1). In this state, at time t4, the control circuit 207 outputs a second packet discard signal. Then, the FIFO buffer 100A performs the processing shown in FIG. 4, and the read pointer of the FIFO buffer 100A indicates the position of the head address of the packet (S1 + M). The read data register 107 shown in FIG. 2 holds the top data of the packet (S1 + M). In this state, at time t5, the control circuit 207 outputs a third packet discard signal. Then, the FIFO buffer 100A performs the processing shown in FIG. 4, and the read pointer of the FIFO buffer 100A indicates the position of the head address of the head packet (S2 + 0) of the next slice. Also, the read data register 107 shown in FIG. 2 holds the top data of the packet (S2 + 0). By outputting three packet discard signals in this way, three packets (S1 + M−2), (S1 + M−1), and (S1 + M) are discarded. Thus, the processing cycle consumed for discarding one packet is 1, and the packet can be processed efficiently.

  FIG. 9 is a flowchart showing the packet discarding method described above by the control circuit.

  In step S2010 of FIG. 9, the control circuit 207 receives the synchronization signal from the FIFO buffer 150A.

  In step S2020 of FIG. 9, the control circuit 207 receives the number of unprocessed packets from the packet management unit 205.

  In step S2030 of FIG. 9, the control circuit 207 determines whether or not the processing of the in-process packet has been completed using the information from the internal arithmetic unit. If the in-process packet processing has been completed, the process proceeds to step S2050. If the in-process packet processing has not ended, the process advances to step S2040.

  In step S2040 of FIG. 9, after waiting for a predetermined time, the control circuit 207 proceeds to step S2030.

  In step S2050 of FIG. 9, the control circuit 207 outputs a packet discard command for the number of unprocessed packets.

  Note that it has been described that the read address instruction unit 109 determines whether there is a valid entry to be discarded in the 2-port memory 101 in step S1020 of FIG. In place of or in addition to this step, whether or not there is a valid entry to be discarded by the control circuit 207 in the 2-port memory 101 between step S2010 and step S2010 in FIG. If it exists, the process proceeds to step S2020 if it exists, and the process may end if it does not exist.

  According to the above-described embodiment, the FIFO buffer packet can be selectively and efficiently discarded by one cycle of processing.

DESCRIPTION OF SYMBOLS 100 ... FIFO buffer, 101 ... Two port memory, 103 ... Write data register, 105 ... Write address instruction | indication part, 107 ... Read data register, 109 ... Read address instruction | indication part

Claims (6)

  A first-in first-out buffer that reads data in the order in which it was written. Before discarding the next packet to be read, read address data indicating the start address of the packet to be discarded, and data indicating the start address of the packet next to the packet to be discarded A first-in first-out buffer having a read data instructing unit for rewriting data.   Addition that obtains data indicating the start address of the packet next to the discarded packet by adding the packet data length included in the header of the discarded packet to the read address data indicating the start address of the discarded packet The first-in first-out buffer of claim 1, further comprising a vessel.   The first-in first-out buffer according to claim 1 or 2, which handles a packet in which a field of packet data length is located at the head of header information.   A method of discarding a packet in a first-in first-out buffer that reads data in the order of writing. Before discarding the next packet to be read, the read address data indicating the head address of the packet to be discarded is the next to the packet to be discarded. A packet discard method for discarding a packet by rewriting the data to indicate the start address of the packet.   A data indicating a head address of a packet next to the discarded packet is obtained by adding a packet data length included in a header of the discarded packet to read address data indicating the head address of the discarded packet. Item 5. The packet discarding method according to Item 4.   6. The packet discarding method according to claim 4, wherein a packet in which a packet data length field is located at the head of the header information is handled.

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