JP2011100761A - Semiconductor device, semiconductor integrated circuit device, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a high breakdown voltage and low on-resistance, and a semiconductor integrated circuit device including the same in good yield at low cost. <P>SOLUTION: The semiconductor device includes: a semiconductor substrate (1) of a first conductivity type; a source region (11) of a second conductivity type opposite to the first conductivity type and formed on a surface side of the semiconductor substrate; a low-concentration drain region (12) and a high-concentration drain region (14); a gate insulating film (14) formed on the semiconductor substrate; and a gate electrode formed on the gate insulating film, wherein the gate electrode is formed so as to cover at least a part of the low-concentration drain region and has an opening (16) over the low-concentration drain region. It is preferred that the low-concentration drain region and high-density drain region adjoin each other. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a semiconductor device, a semiconductor integrated circuit device, and a manufacturing method of the semiconductor device, and more particularly to a semiconductor device having a GOLD (Gate Overlapped Lightly Doped Drain) structure, a semiconductor integrated circuit device, and a manufacturing method thereof.

An LDD (Lightly Doped Drain) type MOSFET is known as a high breakdown voltage semiconductor device, and particularly a semiconductor integrated circuit device in which a low breakdown voltage logic MOSFET and a high breakdown voltage power MOSFET are formed on the same semiconductor substrate. Used for. In the LDD type MOSFET, a high withstand voltage is achieved because the low concentration region formed in the drain region relaxes the electric field between the gate and the drain. A MOSFET having a GOLD structure is known as a semiconductor device having a high breakdown voltage and a low on-resistance. The GOLD type MOSFET has a region where the low concentration region overlaps the gate electrode. By controlling this region, high breakdown voltage and low on-resistance can be obtained at the same time.

Patent Document 1 discloses that a positive chemically amplified resist is used as a resist mask for patterning polysilicon in a step of forming a gate electrode of a MOSFET. By etching polysilicon using the positive chemically amplified resist as a mask, a gate electrode having a convex shape as viewed in cross section is formed. By ion implantation using the convex gate electrode as a mask, a low concentration region overlapping with the gate electrode can be obtained.

Patent Document 2 discloses the use of an oxide film and a resist pattern stacked on a gate electrode of a MOSFET. The oxide film is etched to be narrower than the gate electrode, and the resist pattern is formed to have a width equal to that of the gate electrode furnace. A high concentration region is formed by ion implantation using the resist pattern as a mask, and after removing the resist pattern, a low concentration region overlapping with the gate electrode is formed by ion implantation using the oxide film as a mask.

Japanese Patent Laid-Open No. 5-293421 JP 2007-242754 A

In Patent Document 1, it is difficult to control the width of the ridge-like resist remaining after exposing and developing a positive chemically amplified resist. As a result, the shape of the gate electrode and the low concentration region are difficult to obtain stably, and there is a problem that the manufacturing yield of the MOSFET is lowered.

Further, Patent Document 2 requires a process of forming and removing an oxide film and a resist pattern on the gate electrode, and the manufacturing process becomes complicated. As a result, there is a problem that the cost of the MOSFET increases.

In view of the above problems, an object of the present invention is to provide a high breakdown voltage and low on-resistance semiconductor device and a semiconductor integrated circuit device including the semiconductor device with high yield and low cost.

In order to solve the above problems, a semiconductor device according to the present invention is formed on a surface side of a semiconductor substrate of a first conductivity type and a second conductivity type opposite to the first conductivity type. A semiconductor device comprising a source region, a low concentration drain region and a high concentration drain region, a gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film,
The gate electrode is formed so as to cover at least a part of the low-concentration drain region, and has an opening above the low-concentration drain region.

The semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit formed by forming a plurality of semiconductor elements on a semiconductor substrate of a first conductivity type,
At least one of the plurality of semiconductor elements is a second conductivity type opposite to the first conductivity type, and a source region, a low concentration drain region and a high concentration drain region formed on the surface side of the semiconductor substrate, A gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film,
The gate electrode is formed so as to cover at least a part of the low-concentration drain region, and has an opening above the low-concentration drain region.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a first conductive type semiconductor substrate; and a second conductive type opposite to the first conductive type, the source region being formed on the surface side of the semiconductor substrate; A method for manufacturing a semiconductor device comprising: a low concentration drain region and a high concentration drain region; a gate insulating film formed on the semiconductor substrate; and a gate electrode formed on the gate insulating film,
A first step of forming an opening in a part of the gate electrode; and a second step of forming the low-concentration drain region by ion implantation using the gate electrode as a mask after the first step; It is characterized by providing.

Since the present invention is configured as described above, a high breakdown voltage and low on-resistance semiconductor device and a semiconductor integrated circuit device including the semiconductor device can be provided with a high yield and at a low cost.

2A and 2B are a plan view and a cross-sectional view of main parts of the semiconductor device and the semiconductor integrated circuit device according to the embodiment of the present invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a top view of the principal part of the semiconductor device which concerns on the modification of embodiment of this invention. It is the top view and sectional view of the principal part of the semiconductor device concerning the modification of the embodiment of the present invention.

Hereinafter, a semiconductor device, a semiconductor integrated circuit device, and a method for manufacturing a semiconductor device according to embodiments of the present invention will be described. However, the drawings are schematic and different from actual ones.

FIG. 1A is a diagram showing a planar structure of the main part of the semiconductor integrated circuit device 100 according to the embodiment of the present invention, and FIG. 1B shows a cross-sectional structure of the main part of the semiconductor integrated circuit device 100. FIG.

A semiconductor integrated circuit device 100 according to an embodiment of the present invention includes a high breakdown voltage MOSFET cell 10 and a low breakdown voltage MOSFET cell 20 formed on the same semiconductor substrate 1. The MOSFET 10 and the MOSFET 20 are respectively lateral MOSFETs, and on the surface side of the semiconductor substrate 1 (upper side in FIG. 1B), a field oxide film 2 as an element isolation region is formed between each.

The MOSFET 10 is a semiconductor device according to the present invention, and includes a p-type semiconductor substrate 1, an n + -type source region 11 formed on the surface side of the semiconductor substrate 1, an n − -type low-concentration drain region 12, and an n + -type high A concentration drain region 13, a gate insulating film 14 formed on the semiconductor substrate 1, and a gate electrode 15 formed on the gate insulating film 14 are provided. The source region and the drain region are connected to the source electrode and the drain electrode in an opening portion (not shown). The low concentration drain region 12 is a diffusion layer having an impurity concentration lower than that of the high concentration drain region 13. Moreover, the broken line shown in FIG. 1A indicates the end of the low concentration drain region 12 on the source region 11 side.

The MOSFET 10 has a GOLD (Gate Overlapped Lightly Doped Drain) structure and has a higher breakdown voltage than the MOSFET 20. That is, the low-concentration drain region 12 is formed adjacent to the high-concentration drain region 13, and a part of the low-concentration drain region 12 and a part of the gate electrode 15 have a region overlapping each other. The gate electrode 15 is made of, for example, polysilicon, and a plurality of concave openings 16 are formed in a region overlapping the low-concentration drain region 12 when viewed in plan. The opening 16 is preferably formed so as to penetrate the gate electrode 15 when viewed in cross section. The width and length of the opening 16 and the distance between adjacent openings are determined by characteristics required for the MOSFET 10.

The MOSFET 20 is a semiconductor element according to the present invention, and includes a p-type semiconductor substrate 1, an n + -type source region 21 and an n + -type high-concentration drain region 23 formed on the surface side of the semiconductor substrate 1, and the semiconductor substrate 1. And a gate electrode 25 formed on the gate insulating film 24. The source region and the drain region are connected to the source electrode and the drain electrode in an opening portion (not shown).

FIG. 2 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. A method for manufacturing MOSFET 10 in semiconductor integrated circuit device 100 will be described with reference to FIG.

As shown in FIG. 2A, a gate insulating film 14 is formed on the p-type semiconductor substrate 1. Further, a polysilicon film 15 ′ is formed on the gate insulating film 14. The gate insulating film 14 is formed by a well-known thermal oxidation method or CVD (Chemical Vapor Deposition) method, and the polysilicon film 15 ′ is formed by a well-known CVD method.

Next, as shown in FIG. 2B, the polysilicon film 15 ′ is patterned by a well-known photolithography process to form the gate electrode 15 (first process). The photolithography process includes a process of forming a mask 17 made of a resist pattern having a concave opening in plan view, and a dry process such as RIE (Reactive Ion Etching) that etches the polysilicon film 15 ′ through the mask 17. It is preferable to include an etching step. In the dry etching process, since the gate insulating film 14 serves as an etching stopper layer, the opening 16 penetrating the gate electrode 15 is easily formed.

Next, as shown in FIG. 2C, an ion implantation process is performed using the gate electrode 15 as a mask to form a low concentration region 12 ′ (second process). In this embodiment, the low concentration region 12 ′ is formed by implanting P (phosphorus) ions into the semiconductor substrate 1 so that the impurity concentration is about 1 × 10 13 cm −3. The low concentration region 12 ′ is formed in a region where the gate electrode 15 is not formed on the surface of the semiconductor substrate 1. That is, the low concentration region 12 ′ is also formed in a region exposed by the opening of the gate electrode 15 in the semiconductor substrate 1. After the ion implantation step, the impurity in the low concentration region 12 ′ is diffused also in the region immediately below the gate electrode 15 by the thermal diffusion step, and the low concentration drain region 12 is formed. Therefore, the gate electrode 15 and the low-concentration drain region 12 have regions that overlap each other in plan view.

Next, as shown in FIG. 2D, a mask 18 is formed on the gate electrode 15 by a known photolithography process (third process). Thereafter, an ion implantation step is performed through the mask 18 to form the source region 11 and the high concentration drain region 13 (fourth step). The source region 11 and the high concentration drain region 13 in the present embodiment are formed by implanting P ions so that the impurity concentration is about 1 × 10 16 cm −3. After the ion implantation process, the MOSFET 10 is obtained through a mask 18 removal process and the like.

The effects of the MOSFET 10 and the semiconductor integrated circuit device 100 according to this embodiment will be described.

The gate electrode 15 of the MOSFET 10 has a plurality of concave openings 16. The lightly doped drain region 12 is formed by diffusing impurities implanted into the surface of the semiconductor substrate 1 from the opening 16, so that the MOSFET 10 having a GOLD structure in which the gate electrode 15 and the lightly doped drain region 12 overlap each other is formed. can get. Therefore, a high breakdown voltage and low on-resistance semiconductor device and a semiconductor integrated circuit device including the same can be provided.

The region where the gate electrode 15 and the lightly doped drain region 12 overlap each other depends on the size (width, length and interval) of the concave opening 16 in the gate electrode 15 and the impurity diffusion conditions (temperature, time). Well controlled. Therefore, the manufacturing yield of the high breakdown voltage and low on-resistance MOSFET and the semiconductor device including the MOSFET is improved as compared with the conventional semiconductor device.

The low concentration region 12 ′ (low concentration drain region 12) is formed by an ion implantation process (second process) using the gate electrode 15 having the concave opening 16 as a mask. Therefore, it is not necessary to perform a mask formation step for forming a low concentration region, and a MOSFET having a higher breakdown voltage than a conventional semiconductor device and a semiconductor device including the MOSFET can be provided at low cost. Further, since the low concentration region 12 ′ is formed in a self-aligned manner with respect to the gate electrode 15, the semiconductor device is downsized.

Even when the opening 16 is formed so as not to penetrate the gate electrode 15, the above-described effects can be obtained.

FIG. 3 is a diagram illustrating a planar structure of a main part of a semiconductor device according to a modification of the embodiment of the present invention.

The MOSFETs 10a to 10c according to the modified example of the present embodiment are different from the concave opening 16 of the gate electrode 15 shown in FIG. For example, as shown in FIG. 3A, the MOSFET 10a according to the first modified example of the present embodiment has a square opening 16a in the gate electrode 15a, and the MOSFET 10b according to the second modified example 3 (b), the gate electrode 15b has a circular opening 16b, and the MOSFET 10c according to the third modified example has an antenna-type opening as shown in FIG. 3 (c). It has a hole 16c. In each modification, the shape of the gate insulating film 14 may be different.

According to the MOSFET according to the modification of the present embodiment, the same operational effects as those of the MOSFET 10 and the semiconductor integrated circuit device 100 according to the present embodiment can be obtained.

FIG. 4A is a diagram showing a planar structure of the main part of the MOSFET 10d according to the fourth modification of the present embodiment, and FIG. 4B is a diagram showing a cross-sectional structure of the main part of the MOSFET 10d. .

The MOSFET 10d according to the fourth modification example of the present embodiment is formed of a single crystal substrate whose semiconductor substrate 1 ′ is SiC (silicon carbide). Other structures and manufacturing methods are substantially the same as those of the MOSFET 10 according to the present embodiment.

The MOSFET 10d according to the fourth modification example of the present embodiment is formed of a single crystal substrate whose semiconductor substrate 1 ′ is SiC (silicon carbide). Other structures and manufacturing methods are substantially the same as those of the MOSFET 10 according to the present embodiment.

It is known that SiC has a smaller impurity diffusion coefficient than Si (silicon). That is, impurity ions introduced into the semiconductor substrate 1 ′ by ion implantation are less likely to diffuse in the depth direction and the lateral direction by the thermal diffusion process. Therefore, although the shape of the opening 16d is substantially the same as that of the gate electrode 15 of the MOSFET 10 according to this embodiment, the gate electrode 15d is preferably formed to have a larger width and length.

According to the MOSFET 10d according to the modification of the present embodiment, the same operational effects as those of the MOSFET 10 and the semiconductor integrated circuit device 100 according to the present embodiment can be obtained.

As mentioned above, although an example of an embodiment of the present invention was explained, the present invention is not limited to the specific embodiment concerned, and various changes are within the scope of the gist of the present invention described in the claims. Is possible. For example, the present invention can be implemented even in a structure in which a low concentration region is formed in the source region in addition to the drain region. In addition, the p-type and n-type conductivity types in the above embodiment may be interchanged, and various shapes other than the above can be selected for the shape and arrangement of the openings in the gate electrode. Further, the semiconductor element formed on the same substrate together with the GOLD type MOSFET in the semiconductor integrated circuit device is not limited to the MOSFET.

1, 1 'semiconductor substrate 2 field oxide film 10, 20 MOSFET
DESCRIPTION OF SYMBOLS 11, 21 Source region 12 Low concentration drain region 13, 23 High concentration drain region 14, 24 Gate insulating film 15, 25 Gate electrode 16 Opening 100 Semiconductor integrated circuit device

Claims (7)

A first conductivity type semiconductor substrate;
A source region, a low-concentration drain region, and a high-concentration drain region that are the second conductivity type opposite to the first conductivity type and are formed on the surface side of the semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film, and a semiconductor device comprising:
The semiconductor device, wherein the gate electrode is formed so as to cover at least a part of the low-concentration drain region, and has an opening above the low-concentration drain region.
The semiconductor device according to claim 1, wherein the low-concentration drain region and the high-concentration drain region are adjacent to each other.
The semiconductor device according to claim 1, wherein the gate electrode is formed so as to cover at least a part of the low-concentration drain region when seen in a plan view.
The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide.
A semiconductor integrated circuit formed by forming a plurality of semiconductor elements on a semiconductor substrate of a first conductivity type,
A source region, a low concentration drain region and a high concentration drain region formed on the surface side of the semiconductor substrate, wherein at least one of the plurality of semiconductor elements is a second conductivity type opposite to the first conductivity type;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film,
The semiconductor integrated circuit device, wherein the gate electrode is formed so as to cover at least a part of the low-concentration drain region, and has an opening above the low-concentration drain region.
The semiconductor integrated circuit device, wherein the plurality of semiconductor elements includes a first MOSFET and a second MOSFET having a higher breakdown voltage than the first MOSFET,
The first MOSFET includes a first source region and a first drain region formed on the surface side of the semiconductor substrate,
The second MOSFET is of the second conductivity type and formed on the surface side of the semiconductor substrate, the second source region, the low concentration drain region and the high concentration drain region,
The gate insulating film formed on the semiconductor substrate;
The gate electrode formed on the gate insulating film,
6. The semiconductor integrated circuit device according to claim 5, wherein the gate electrode is formed so as to cover at least a part of the low-concentration drain region, and has an opening above the low-concentration drain region. .
A first conductivity type semiconductor substrate;
A source region, a low-concentration drain region, and a high-concentration drain region that are the second conductivity type opposite to the first conductivity type and are formed on the surface side of the semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film, and a manufacturing method of a semiconductor device comprising:
A first step of forming an opening in a part of the gate electrode;
And a second step of forming the lightly doped drain region by ion implantation using the gate electrode as a mask after the first step.

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