JP2011099733A - Impact detecting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an impact detecting device allowing the degree of a momentary impact to be acquired even if some circuits are intermittently operated to save on power. <P>SOLUTION: This impact detecting device 1 is equipped with: impact detectors 2 and 3; a capacitor 8; a delay controller 5; a switch 6; a comparator 9; and a recording circuit 10. The impact detector 2 changes its output owing to the detection of an impact. The impact detector 3 changes its output of a detection signal according to acceleration. Electric charge corresponding to an output signal of the impact detector 3 is stored in the capacitor 8. By the delay controller 5 and the switch 6, the impact detector 3 is disconnected from the capacitor 8 a prescribed time period later than the detection of the impact made by the impact detector 2. The comparator 9 outputs an output signal related to the electric charge stored in the capacitor 8. The recording circuit 10 is started from a resting state a prescribed time period or more later than the detection of the impact based on the output of the impact detector 2 to record a real time clock when the output signal of the comparator changes. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to an impact detection device that performs predetermined processing based on an impact detection value that detects the degree of impact, and more particularly to a technique for reducing power consumption of the impact detection device.

  An impact detection device is used to detect the degree of vibration and impact that an article receives during transportation. Since a general impact detection device is used when an article is transported, a portable battery is used for a power supply circuit. In the impact detection device, an impact detection value (specifically, acceleration or the like) is detected by a sensor, and an output signal of the sensor is sampled and recorded at a predetermined sampling rate. Since the impact is generated with a time width of several tens of millimeters SEC to several seconds, the impact detection device requires a time resolution of about 1/10 of the time width of the impact. For this reason, the amount of data to be recorded increases depending on the sampling rate, and the memory capacity may become a problem. In addition, since high-speed data processing is required and the frequency of data processing increases, power consumption required for data processing becomes excessive, and battery capacity may become a problem.

  Therefore, by using an impact detection device that records only the impact detection value that is larger than a certain level and the impact detection value, the amount of data and the frequency of data processing may be suppressed to save power ( For example, see Patent Document 1.)

FIG. 1 is a block diagram of a configuration example of a conventional impact detection device with reference to Patent Document 1. In FIG.
The impact detection apparatus 101 includes an arithmetic processing unit 102, an impact detector 103, a filter 104, an amplifier 105, a peak hold unit 106, an A / D converter 107, a comparator 108, and a power supply circuit 109. The power supply circuit 109 supplies power to the arithmetic processing unit 102 and the A / D converter 107 when the power switch is turned on. The impact detector 103 receives an impact and outputs an impact detection signal. The filter 104 removes noise components from the impact detection signal. The amplifier 105 amplifies the impact detection signal. The peak hold unit 106 stores the peak value of the impact detection signal. The A / D converter 107 converts the peak value of the impact detection signal from analog data to digital data. The comparator 108 outputs a trigger signal when an impact detection signal exceeding the threshold level is input. The arithmetic processing unit 102 records the generation time of the trigger signal and the digital data in the memory.

  In addition, a GPS device may be used during transportation of an article (see, for example, Patent Document 2). In a GPS device, a GPS unit with high power consumption is intermittently operated, and only an RTC (Real Time Clock) unit with low power consumption is always operated to save power.

JP-A-1-265165 Special table 2007-521383 gazette

  In order to further save power in the impact detection device, it is desired to adopt intermittent operation like a GPS device. However, in order to employ intermittent operation in the impact detection device, there is a problem in the time required for rising when shifting from the sleep state to the active state.

  In the impact detection device, the impact occurs in a time span of several tens of millimeters of SEC to a few seconds, so if the impact is used as a start trigger, high-speed response that rises in about 1/10 of the impact duration ( Fast startability) is required. Therefore, it is difficult to adopt an intermittent operation like a GPS device as it is for an impact recording device. In particular, A / D converters and arithmetic circuits have a high time resolution and high operation frequency, so that the power saving effect by the intermittent operation is great. However, since the high-speed response is not sufficient, it is difficult to operate them intermittently.

  Therefore, an object of the present invention is to provide an impact detection device that can grasp the degree of impact even when some circuits are intermittently operated to save power than before.

  The impact detection device of the present invention includes a first impact detection unit, a second impact detection unit, a power storage unit, a delay switch unit, a charge detection unit, and a signal processing unit. The output of the first impact detector changes depending on the impact detected. The second impact detection unit outputs an impact detection value that changes according to the degree of impact. The power storage unit stores a charge corresponding to the impact detection value. The delay switch unit disconnects the connection between the second shock detection unit and the power storage unit with a predetermined time delay from the time of detection of the shock by the first shock detection unit. The charge detection unit outputs an output signal related to the amount of charge stored in the power storage unit. The signal processing unit rises from the sleep state with a delay of the predetermined time or more from the time of detection of the impact by the first impact detection unit, and performs processing based on the output signal of the charge detection unit.

  In this configuration, after the impact is detected by the first impact detection unit, the delay switch unit disconnects the connection between the power storage unit and the second impact detection unit when the impact is moderated to some extent. Therefore, the charge amount obtained by integrating the shock detection value output from the second shock detection unit is stored in the power storage unit so far, and the charge amount is held by disconnection of the delay switch unit. As a result, even if the signal processing unit starts up from the sleep state with a delay from the occurrence of the shock, the degree of the shock can be grasped from the amount of charge stored in the power storage unit according to the level of the shock before entering the active state. Is possible.

  The charge detection unit of the present invention is preferably such that the charge stored in the power storage unit is discharged at a known time ratio, and the output signal changes during the discharge. In this configuration, the time for discharging in the charge detection unit (discharge time) corresponds to the amount of charge stored in the power storage unit. Therefore, it is possible to grasp the discharge time and the degree of impact from the time interval at which the output signal changes.

  It is preferable that the impact detection device of the present invention further includes an RTC unit. The RTC unit outputs a real time clock by counting time. The signal processing unit counts the change interval of the output signal of the charge detection unit and records it in the memory together with the real time clock. In this configuration, since the signal processing unit only counts the discharge time and records it in the memory together with the real-time clock, the data processing is simple, the frequency and amount of data processing can be suppressed, and the power consumption associated with the recording processing can be saved. .

  In the delay switch unit according to the present invention, it is preferable that the second impact detection unit and the power storage unit are connected when an impact is detected by the first impact detection unit. With this configuration, it is possible to prevent power storage in the power storage unit from progressing with respect to a shock that is so small that the first shock detection unit does not detect the shock. Therefore, the power storage of the power storage unit progresses only with respect to the impact of a magnitude that can be detected by the first impact detection unit, and the degree of the impact can be grasped more accurately.

  The first impact detection unit and the second impact detection unit of the present invention may use the output of the same sensor. In this case, the first impact detection unit forms a switch signal that quickly rises in a substantially rectangular wave shape with a high gain, and what is the output signal of the second linear measurement sensor (impact detection unit) that measures the original acceleration? It is good to use separately.

  According to the present invention, since the amount of charge corresponding to the impact detection value is stored in the power storage unit and held, even if the signal processing unit rises from the sleep state after the occurrence of the impact, the charge state of the power storage unit is determined from the active state. The degree of impact that occurred before Therefore, since at least the signal processing unit can be operated intermittently, it is possible to save power in the impact detection device.

It is a schematic circuit diagram of the impact detection apparatus which concerns on a prior art example. It is a figure explaining the schematic structural example of the impact detection apparatus which concerns on the 1st Embodiment of this invention. It is a figure explaining the schematic structural example of the comparator with which the impact detection apparatus of FIG. 2 is provided. It is a figure explaining the schematic structural example of the impact detection apparatus which concerns on the 2nd Embodiment of this invention.

The impact detection device according to the first embodiment of the present invention will be described below.
FIG. 2 is a diagram illustrating a schematic configuration example of the impact detection device 1. The impact detection device 1 includes impact detection units 2 and 3, a delay control unit 5, a switch 6, a resistor 7, a capacitor 8, a comparator 9, a recording circuit 10, an RTC (Real Time Clock) unit 11, and a battery 12.

  The battery 12 supplies an operating voltage Vcc to each part. The RTC unit 11 measures the value of the real time clock RTC.

  The impact detection unit 2 is a first impact detection unit of the present invention, and includes an acceleration sensor (not shown), and outputs a binary signal Vt that becomes HIGH level while the acceleration sensor detects acceleration of a predetermined level or higher. . Note that the accuracy of impact detection by the first impact detection unit (impact detection unit 2) may be low, and it is preferable to use an acceleration sensor with low power consumption.

  The impact detector 3 is a second impact detector of the present invention, and includes an acceleration sensor 3A, an amplifier 3B, and a full-wave rectifier circuit 3C. The acceleration sensor 3A preferably has high accuracy even with high power consumption, and outputs an analog output signal that changes according to the acceleration. The amplifier 3B amplifies the output signal of the acceleration sensor 3A. The full wave rectification circuit 3C performs full wave rectification on the output signal of the amplifier 3B.

  The switch 6 is connected between the impact detection unit 3 and the resistor 7, and the open / close state is controlled by the output of the delay control unit 5. Therefore, the switch 6 and the delay control unit 5 constitute a delay switch unit of the present invention. The resistor 7 is connected between the comparator 9 and the capacitor 8 and the switch 6. One end of the capacitor 8 is connected between the resistor 7 and the comparator 9, and the other end is grounded. The capacitor 8 and the resistor 7 constitute an integration circuit and correspond to the power storage unit of the present invention.

  The delay control unit 5 switches the switch 6 from the open state to the closed state when the binary signal Vt output from the impact detection unit 2 becomes HIGH level. Further, the switch 6 is changed from the closed state to the open state after a predetermined time delay after the binary signal Vt output from the impact detection unit 2 becomes HIGH level. Therefore, the output of the impact detector 3 flows through the closed switch 6 only for a certain period after the impact detector 2 detects an impact of a predetermined level or higher. As a result, a charge based on the output of the impact detector 3 is stored in the capacitor 8. Then, after the lapse of the predetermined period, the delay control unit 5 opens the switch 6 again, so that it is possible to prevent the electric charge based on the output of the impact detection unit 3 from being stored in the capacitor 8 any more, The resistor 7 prevents the capacitor 8 from being discharged. In this way, the charge amount of the capacitor 8 is held.

  The comparator 9 corresponds to a charge detection unit of the present invention, and determines whether the charge voltage is larger than a predetermined level while discharging the charge of the capacitor 8 by an input resistance at a known time ratio. Output a signal. When the comparator 9 discharges, the charge voltage of the capacitor 8 decreases exponentially and becomes lower than a predetermined level, and the output changes to the LOW level. FIG. 3 is a diagram for explaining a schematic configuration example of the comparator 9. The comparator 9 is an analog IC, and compares the magnitude of the input voltage Ein with the reference voltage using the charge voltage of the capacitor 8 as the input voltage Ein, the divided voltage of the set voltage Et and the output voltage Eout as the reference voltage. The output voltage Eout of the comparator 9 changes from the LOW level to the HIGH level when the input voltage Ein becomes larger than the reference voltage, and changes from the HIGH level to the LOW level when the input voltage Ein becomes smaller. This comparator 9 has the same basic operation principle as that of the operational amplifier, has a very large amplification degree, and can detect only a slight difference between the differential inputs. Further, the reference voltage, which is a divided voltage of the set voltage Et and the output voltage Eout, has hysteresis, and in order to invert the output voltage Eout, the input voltage Ein needs to be larger than the set voltage Et by the hysteresis. For this reason, it is possible to prevent the operation of the comparator 9 from becoming unstable due to a slight voltage difference such as noise. Such a comparator 9 is generally called a double integration type comparator (for example, http://www.mlab.ice.uec.ac.jp/mit/text/singou/Siryo/Supplement-1/node6. (See html, 2009/09/16.)

  The recording circuit 10 is a signal processing unit of the present invention, and is configured to operate intermittently by repeating a sleep state and an active state. The recording circuit 10 in the sleep state starts rising to the active state when the binary signal Vt output from the impact detection unit 2 becomes HIGH level. There is a startup lag between when the binary signal Vt becomes HIGH level and when the active state is actually started, and the recording circuit 10 becomes active after the capacitor 8 holds the electric charge. In order for the recording circuit 10 to shift from the active state to the sleep state, the binary signal Vt output from the impact detection unit 2 is at a LOW level for a certain time, or a certain time has elapsed after the active state has risen. It is preferable to make it a condition.

The recording circuit 10 in the active state counts clock pulses while the output signal of the comparator 9 is at a high level, and records it in the memory together with the real time clock.
The count number of the clock pulse depends on the charge discharge time by the comparator 9 and the charge amount of the capacitor 8. Therefore, from the count number of the clock pulses, it is possible to grasp the degree of impact, that is, the integrated value of the output of the impact detection unit 3 during a certain period after the impact detection unit 2 detects the impact. . Since the start lag is substantially constant, even if the time when the recording circuit 10 becomes active is after the start of discharge, the discharge is performed according to the number of clock pulses counted from the active state to the end of discharge. Time is uniquely determined.

  With the above configuration, the impact detection device 1 can be used to grasp the instantaneous impact level while intermittently operating the recording circuit 10, the comparator 9, the impact detection unit 3, and the like. Therefore, the power consumption of the entire apparatus can be suppressed, and the capacity and size of the battery 12 can be reduced. Further, since the data to be recorded in the memory by the recording circuit 10 is only the count number in the discharge time, the start time, the discharge end time, the discharge time, etc., memory saving and the frequency of the data recording process of the recording circuit 10 are suppressed. Is possible. Therefore, power saving can be promoted also from this point.

The present invention can be implemented with various other configurations of the above-described embodiments. For example, instead of the impact detection unit 2, a circuit for determining whether the output of the acceleration sensor 3A is equal to or higher than a threshold level and outputting a detection signal of a HIGH / LOW level is provided, and the first and second impact detection units Alternatively, the output of the same sensor may be used. In this case, it is preferable to use a sensor that outputs an analog output signal that changes in accordance with acceleration with high accuracy. If the same sensor is used for the first and second impact detection units, the number of parts of the impact detection unit is reduced, and the entire apparatus can be reduced in size. Since the signal processing unit can operate intermittently even if the number of parts of the impact detection unit is reduced, it is possible to save power compared to when the signal processing unit is always operated.
Further, the impact detection value may be directly calculated by the recording circuit and then recorded in the memory. Further, the data may be transmitted via the communication circuit without performing recording in the memory by the recording circuit. The present invention can be suitably implemented by using a circuit configuration that can grasp at least the amount of charge stored based on the detection signal of impact.

Next, an impact detection apparatus according to a second embodiment of the present invention will be described.
FIG. 4 is a diagram illustrating a schematic configuration example of the impact detection device 21. The impact detection device 21 includes an intermittent operation control unit 22 in addition to the same configuration as the impact detection device 1 described above. The power supply 12 directly supplies operating power to the intermittent operation control unit 22, the impact detection unit 2, the RTC unit 11, and the recording circuit 10, and the impact detection unit 3 and the comparator 9 are connected via the intermittent operation control unit 22. To indirectly supply operating power. The intermittent operation control unit 22 supplies the operating voltage Vcc to the impact detection unit 3 and the comparator 9 in synchronization with a period during which the switch 6 is closed by the control from the delay control unit 5.

  Even with such a configuration, the present invention can be suitably implemented. With this configuration, the impact detection unit 3 and the comparator 9 can also be intermittently operated to further advance power saving.

DESCRIPTION OF SYMBOLS 1, 21 ... Impact detection apparatus 2, 3 ... Impact detection part 3A ... Acceleration sensor 3B ... Amplifier 3C ... Full wave rectification circuit 5 ... Delay control part 6 ... Switch 7 ... Resistance 8 ... Capacitor 9 ... Comparator 10 ... Recording circuit 11 ... RTC unit 12 ... Battery

Claims (5)

A first impact detector whose output changes upon detection of impact;
A second impact detector that outputs an impact detection value that changes in accordance with the degree of impact;
A power storage unit that stores electric charge according to the impact detection value;
A delay switch unit that disconnects the connection between the second shock detection unit and the power storage unit with a predetermined time delay from the time of detection of the shock based on the output of the first shock detection unit;
A charge detection unit that outputs an output signal related to the amount of charge stored in the power storage unit; and
An impact detection comprising: a signal processing unit that starts from a resting state with a delay of a predetermined time or more from the time of detection of an impact based on the output of the first impact detection unit and performs processing based on an output signal of the charge detection unit apparatus.   The impact detection device according to claim 1, wherein the charge detection unit discharges the charge stored in the power storage unit at a known time ratio, and the output signal changes during discharge. It further includes an RTC unit that outputs a real-time clock according to timing,
The impact detection device according to claim 2, wherein the signal processing unit counts a change interval of an output signal of the charge detection unit and records it in a memory together with a real-time clock.   The delay switch unit connects between the second shock detection unit and the power storage unit when detecting a shock based on an output of the first shock detection unit. Shock detection device.   The impact detection device according to any one of claims 1 to 4, wherein the first impact detection unit and the second impact detection unit use an output of the same sensor.

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