JP2011097370A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase speed of processing from the decoding of compressed encoded image data and compressed encoded alpha data to alpha blending using the decoded results. <P>SOLUTION: A moving image decoder 25 and an alpha data decoder 26 supply decoded results of the compressed encoded image data and the compressed encoded alpha data to an external memory I/F 27 by one macroblock at a time, and writes the decoded results in a buffer 27A<SB>1</SB>(or 27A<SB>2</SB>) and a buffer 27B<SB>1</SB>(or 27B<SB>2</SB>) of the external memory. A bus I/F 21C merges the decoded results written in the buffer 27A<SB>1</SB>(or 27A<SB>2</SB>) and a buffer 27B<SB>1</SB>(or 27B<SB>2</SB>) into 64-bit data and transfers the data to an external memory module 102. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technology for decoding moving image compression-encoded image data and compression-encoded alpha data.

Some video playback devices include MPEG (Moving
From multiple types of circuits such as an image processing device that decodes compression-encoded image data that has been compression-encoded by a compression algorithm such as Picture Expert Group, and a drawing device that draws an image using the decoding result of the image processing device Some are configured. Alpha blending is a technique related to drawing of an image by a drawing device in the moving image reproducing device. In this alpha blending, color data (for example, luminance of each component of R, G, B) of each pixel of an image to be rendered (hereinafter referred to as a source image), alpha data indicating the transparency of each pixel, and a source This is a technique for calculating the color value of each pixel of the destination image after overlapping the source image based on the color value of each pixel of the image serving as the background of the image (hereinafter referred to as the destination image). More specifically, in this alpha blending, as shown in FIG. 7, the color value of one pixel constituting the source image (hereinafter referred to as source pixel) is SC, the alpha data of the source pixel is α, and the destination image When the color value of the pixel at the same position as the source pixel (hereinafter referred to as the destination pixel) is D, the color value D ′ shown in the following equation is calculated, and the source pixel is overlaid on the destination pixel Color value.
D ′ = α · SC + (1−α) · D (1)
Thereby, it is possible to produce a state in which the destination image on which the source images are superimposed can be seen through the source image. For example, Patent Document 1 discloses a document that discloses a technique related to this alpha blending.

JP 2006-191240 A

  In this type of conventional moving image reproducing apparatus, compression-encoded alpha data obtained by compression-encoding compression-encoded image data obtained by compression-encoding image data constituting each frame and alpha data forming a pair with these image data is provided. Data is prepared in the pattern ROM, and the compression-encoded image data and compression-encoded alpha data in the pattern ROM are sequentially decoded one by one, and alpha blending for one frame is performed using these two types of decoding results. It was. However, in this case, since the decoding result of the compression-encoded image data and the decoding result of the compression-encoded alpha data necessary for drawing one frame image are written in different areas of the memory, both of these two types of decoding results It took a long time to read the data, and this was one of the obstacles to speeding up the processing.

  The present invention has been devised under such a background, and speeds up processing from decoding of compression-encoded image data and compression-encoded alpha data to alpha blending using the decoding result. With the goal.

  The present invention includes a moving image decoder that decodes compression-encoded image data obtained by compression-encoding an image, an alpha data decoder that decodes compression-encoded alpha data obtained by compression-encoding alpha data used for image alpha blending, Image data and alpha corresponding to a predetermined number of pixels obtained by dividing an image data output as a decoding result from the moving picture decoder and alpha data output from the alpha data decoder as a decoding result used for the image data into one frame image There is provided an image processing apparatus comprising merging means for merging data and transferring them to an external memory module.

  This image processing apparatus constitutes a moving image reproducing apparatus together with a pattern ROM that stores compression-encoded image data and compression-encoded alpha data and a drawing apparatus that performs alpha blending using the decoding results thereof. In this image processing apparatus, image data that is a decoding result of compression-encoded image data and alpha data that is a decoding result of compression-encoded alpha data are merged into image data and alpha data for a predetermined number of pixels, and the external memory module Forward to. Thus, in the external memory module, two types of decoding results necessary for alpha blending of an image for a predetermined number of pixels are stored in a continuous address area. Therefore, compared to a case where image data for a predetermined number of pixels, which is a decoding result of compression-encoded image data, and alpha data for a predetermined number of pixels, which is a decoding result of compression-encoded alpha data, are stored separately in separate areas. The time required for reading the decoding result by the drawing apparatus is shortened, and the processing can be speeded up.

It is a block diagram which shows the structure of the moving image reproduction apparatus containing the image processing apparatus which is one Embodiment of this invention. It is a figure which shows the data structure of the decoding execution command given to the image processing apparatus. It is a figure which shows the decoding result of the compression encoding image data and compression encoding alpha data by the image processing apparatus. It is a figure which shows the operation | movement of the moving image decoder of the same image processing apparatus, an alpha data decoder, an external memory interface, and bus | bath I / F. It is a figure which shows the conversion table used for conversion of the resolution of the alpha data in the image processing apparatus. It is a figure which shows the procedure of the transfer of the decoding result from the image processing apparatus to an external memory module. It is a figure which shows the processing content of alpha blending.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a moving image playback apparatus 1 including an image processing apparatus 100 according to an embodiment of the present invention. The image processing apparatus 100 receives a command from the host CPU 103 via the bus 101A, and receives and decodes the compressed encoded image data and the compressed encoded alpha data of the moving image from the pattern ROM 104 connected to the bus 101B according to the command. The image data and alpha data of the moving image as the decoding result are delivered to the drawing device 105 via the external memory module 102 connected to the bus 101C.

  Here, in the pattern ROM 104 connected to the bus 101B, a plurality of types of compression-encoded image data of a plurality of types of moving images and a plurality of types of compression-encoded alpha data used in combination with those compression-encoded image data are stored. Stored with attribute information. Various compression-coded image data in the pattern ROM 104 is obtained by dividing each frame image of a moving image into 16 × 16 pixel macroblocks, and irreversible compression coding processing (more specifically, Data obtained by performing DCT (Discrete Cosine Transform), inter-frame predictive coding processing, Huffman coding, and the like.

  In addition, various compression-coded alpha data in the pattern ROM 104 is obtained by dividing a matrix of alpha data representing the transparency of each pixel in an image of each frame into macroblocks (16 × 16), and reversibly for each of the divided macroblocks. Data obtained by performing compression encoding processing (more specifically, processing such as DPCM (Differential Pulse Code Modulation) and Huffman encoding). The compression-encoded alpha data in the pattern ROM 104 includes compression-encoded alpha data representing the transparency of each pixel with 1-bit resolution (2 gradations) and transparency of each pixel with a 2-bit resolution (4 (Gradation) alpha data expressed by compression encoding, transparency data of each pixel expressed by 3-bit resolution (8 gradations) compression data encoding, and transparency of each pixel by 4 bits There are four types, which are compression-encoded alpha data expressed in 16 resolutions. In the attribute information of each of these four types of compression-encoded alpha data in the pattern ROM 104, the resolution of the original alpha data that was the object of compression encoding is either 1 bit, 2 bits, 3 bits, or 4 bits. It is described whether there is.

  In FIG. 1, bus I / Fs (interfaces) 21A, 21B, and 21C are interfaces that mediate transmission / reception of data via buses 101A, 101B, and 101C, respectively. The host I / F 22 receives various commands output from the host CPU 103 connected to the bus 101A via the bus I / F 21A, stores them in the built-in command buffer 22A, and stores the stored commands in the image processing apparatus 100. It is an interface supplied to each part. The register group 23 is a collection of registers for storing control information for controlling each unit in the image processing apparatus 100 or data exchanged between the units. The pattern ROM I / F 24 includes buffers 24A and 24B, each of which is a FIFO (First-In First-Out) buffer. The pattern ROM I / F 24 receives the compressed encoded image data in the pattern ROM 104 connected to the bus 101B via the bus I / F 21B, stores it in the buffer 24A, and stores the stored compressed encoded image data from the oldest one. It supplies to the moving image decoder 25 in order. The pattern ROM I / F 24 receives the compression encoded alpha data in the pattern ROM 104 connected to the bus 101B via the bus I / F 21B and stores it in the buffer 24B. The stored compression encoded alpha data is old. Are supplied to the alpha data decoder 26 in order.

  The moving picture decoder 25 is a device that decodes compression-encoded image data supplied from the pattern ROM I / F 24 by one macro block. The alpha data decoder 26 is a device that decodes the compression encoded alpha data supplied from the pattern ROM I / F 24 by one macro block.

  The cache control unit 12 acquires the decoded image data to be reused in the decoding by the moving picture decoder 25 from the external memory module 102 and stores it in the cache memory 11, and the decoding is performed in response to a request from the moving picture decoder 25. The completed image data is extracted from the cache memory 11 and supplied to the moving picture decoder 25.

The external memory I / F 27 includes two buffers 27A ₁ and 27A ₂ that are image data buffers for storing image data output as a decoding result from the moving picture decoder 25, and alpha data output as a decoding result from the alpha data decoder 26. It has a built-in two and buffers 27B ₁ and 27B ₂ are alpha data buffer for storing. The external memory I / F 27, while utilizing a buffer 27A ₁ and 27A ₂ alternately, and storing image data outputted from the video decoder 25 to the buffer 27A ₁ and 27A _2, the stored image data bus I / F21c To the external memory module 102. The external memory I / F 27 accumulates the alpha data output from the alpha data decoder 26 in the buffers 27B ₁ and 27B ₂ while alternately using the buffers 27B ₁ and 27B _2, and stores the accumulated alpha data in the bus I The data is transferred to the external memory module 102 via / F21C.

  The drawing device 105 connected to the bus 101C together with the image processing device 100 and the external memory module 102 reads the moving image data and alpha data stored in the external memory module 102 and reflects them on the display content of a display device (not shown). The drawing process to be executed is executed. At that time, the drawing apparatus 105 uses the alpha data read from the external memory module 102 to display an image that is a background image of the moving image in the display content and an image for one frame constituting the moving image (read from the external memory module 102). Alpha blending with image data.

The above is the outline of the configuration of the image processing apparatus 100 according to the present embodiment. The features of the image processing apparatus 100 are as follows.
<Characteristic 1> When compression-encoded alpha data to be decoded is compression-encoded alpha data having a resolution different from 4 bits, which is a preset resolution, obtained by decoding compression-encoded alpha data The decoding result is obtained by converting the alpha data into alpha data having a 4-bit resolution instead of the alpha data.
<Characteristic 2> Image data that is a decoding result of compression-encoded image data and alpha data that is a decoding result of compression-encoded alpha data are merged into image data and alpha data for a predetermined number of pixels and stored in the external memory module 102. The point to transfer.

  Hereinafter, a mechanism for enabling such a feature will be described. In the present embodiment, the host CPU 103 writes the compression encoded image data and compression encoded alpha data to be decoded, the storage start address of each attribute information, and the like as control information in a predetermined register in the register group 23. After that, a decoding execution command for instructing execution of decoding of both compression encoded image data and compression encoded alpha data, a decoding execution command for instructing only execution of decoding of the compression encoded image data, and compression encoding One of the three types of decoding execution commands for instructing only execution of decoding of alpha data is written to the command buffer 22A in the host I / F 22.

  More specifically, as shown in FIG. 2, the host CPU 103 sets 2 bits out of all the bits constituting the decoding execution command as decoding target control bits, and both of the compression encoded image data and the compression encoded alpha data. When instructing execution of decoding, a decoding execution command with the decoding target control bit set to “00” or “01” is written to the command buffer 22A. When instructing only execution of decoding of compression-encoded image data, a decoding execution command with the decoding target control bit set to “10” is written in the command buffer 22A, and only execution of decoding of compression-encoded alpha data is performed. Is written, the decoding execution command with the decoding target control bit set to “11” is written to the command buffer 22A. When the decoding execution command is written in the command buffer 22A, the moving picture decoder 25, the alpha data decoder 26, the external memory I / F 27, and the bus I / F 21C operate in cooperation as follows.

a1. When a decoding execution command instructing execution of decoding of both compressed encoded image data and compressed encoded alpha data is written in the command buffer 22A. In this case, as shown in FIG. Data and compression-encoded alpha data are decoded to generate one macroblock (16 × 16 pixels) YUV color space image data and alpha data matrix, and each of the image data and alpha data matrix is horizontally And divided into 8 × 8 blocks of 2 × 2 pixels. Then, as shown in FIG. 3B, for each of 8 × 8 blocks, the color value (more specifically, the Y value (luminance), U value (color difference), and V value ( 64-bit data obtained by merging the three color values (color difference) and alpha data is transferred to the external memory module 102 as a decoding result. The 64-bit data is composed of the following data.

Data V ₃₂₁₀
This is data indicating a representative value of V values of each of the four pixels in the block (for example, an average value of V values of each of the four pixels) as an 8-bit bit string.
Data Y ₃
This is data indicating the Y value of the lower right pixel in the block as an 8-bit bit string.
Data Y ₂
This is data indicating the Y value of the upper right pixel in the block as an 8-bit bit string.
Data α ₃
This is data indicating the transparency of the lower right pixel in the block as a 4-bit bit string.
Data α ₂
This is data indicating the transparency of the upper right pixel in the block as a 4-bit bit string.
Data U ₃₂₁₀
This is data representing a representative value of U values of each of four pixels in the block (for example, an average value of U values of each of four pixels) as an 8-bit bit string.
Data Y ₁
This is data indicating the Y value of the lower left pixel in the block as an 8-bit bit string.
Data Y ₀
This is data indicating the Y value of the upper left pixel in the block as an 8-bit bit string.
Data α ₁
This is data indicating the transparency of the lower left pixel in the block as a 4-bit bit string.
Data α ₀
This is data indicating the transparency of the upper left pixel in the block as a 4-bit bit string.

FIG. 4 is a diagram showing operations of the moving picture decoder 25, the alpha data decoder 26, the external memory I / F 27, and the bus I / F 21C in this case.
When the decoding execution command is written in the command buffer 22A, the moving picture decoder 25 refers to the storage start address written as control information in the register in the register group 23, and sends a data request including this storage start address to the pattern ROM. The data is sent to the pattern ROM 104 via the I / F 24. In response to the data request, the pattern ROM 104 reads the attribute information from the ROM 104 and outputs it, and then sequentially reads out and outputs the compressed encoded image data and the compressed encoded alpha data of the frames 1, 2 and so on. . The compression-encoded image data and compression-encoded alpha data output from the pattern ROM 104 are supplied to the moving picture decoder 25 and the alpha data decoder 26 via the buffers 24A and 24B of the pattern ROM I / F 24.

The moving picture decoder 25 performs a predetermined decoding process on the compression-encoded image data to generate image data for one macroblock, and divides the image data for one macroblock into 8 × 8 blocks. Then, the moving picture decoder 25 scans the 8 × 8 blocks one block at a time, sequentially extracts data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , and Y ₀ from each block, and external memory I / F 27. To supply.

  Further, the alpha data decoder 26 acquires the attribute information output from the ROM 104 prior to the start of the output of the compression encoded alpha data by the pattern ROM 104, and compresses the compression encoded alpha data supplied thereafter from the ROM 104. Find the resolution of the original alpha data that was to be encoded. When compression-encoded alpha data starts to be supplied from the pattern ROM 104 via the pattern ROM I / F 24, the following processing is performed.

  The alpha data decoder 26 performs a predetermined decoding process on the compression-encoded alpha data to generate an alpha data matrix (16 × 16 alpha data matrix) for one macroblock. Then, when the resolution obtained from the attribute information is 4 bits, the alpha data decoder 26 divides each alpha data for one macro block obtained by the decoding process into 8 × 8 blocks as it is, If the resolution determined by the attribute information is different from 4 bits, each piece of alpha data (1 bit, 2 bits, or 3 bits of alpha data) obtained by decoding processing is obtained. ) Is converted into alpha data having a resolution of 4 bits and then divided into 8 × 8 blocks.

  Conversion from alpha data of 1-bit, 2-bit, and 3-bit resolution to alpha data of 4-bit resolution is a bit string for two gradations of minimum value (0) and maximum value (1) in 1-bit resolution. And a bit string for four gradations between a minimum value (00) and a maximum value (11) at a resolution of 2 bits, and between a minimum value (000) and a maximum value (111) at a resolution of 3 bits. This is performed by referring to a conversion table in which a bit string for 8 gradations and a bit string for 16 gradations between the minimum value (0000) and the maximum value (1111) in a resolution of 4 bits are associated. FIG. 5 is a diagram illustrating an example of the conversion table.

The alpha data decoder 26 divides each piece of alpha data for one macro block into 8 × 8 blocks, and then scans the 8 × 8 block one block at a time, and outputs data α ₃ , α ₂ , α ₁ , α from each block. ₀ one by two (more specifically, the data alpha ₃ and alpha ₂ pairs (a total of 8 bits) and data alpha ₁ and alpha ₀ the pairs (a total of 8 bits)) supplied is taken out in the order to the external memory I / F 27 To do.

4, the external memory I / F 27 is, for writing the one of the buffers 27A ₁ and 27A _2, and the other as a read, data V supplied thereto as a result of decoding the compression encoded image data from the video decoder 25 ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ are sequentially written to the storage destination byte address in the write buffer 27A ₁ (or buffer 27A ₂ ). Then, each time the buffer 27A ₁ for writing (or buffer 27A ₂₎ to one macroblock decoding result is stored, the buffer 27A ₁ for writing (or buffer 27A ₂₎ a buffer _27A 2 for reading ( Alternatively, the buffer 27A ₁ ) is switched and the decoding result for the next one macroblock is written into the buffer 27A ₂ (or buffer 27A ₁ ) switched for writing and the buffer 27A ₁ (or buffer 27A switched for reading). ₂ ) The decoding result in ( ₂ ) is supplied to the bus I / F 21C.

The external memory I / F 27 includes a buffer 27B ₁ and 27B for writing one of the _two, and for reading the other data alpha ₃ from alpha data decoder 26 supplied thereto as a result of decoding the compression-encoded alpha data , Α ₂ , α ₁ , α ₀ are sequentially written into the storage byte address in the write buffer 27B ₁ (or buffer 27B ₂ ). Then, each time the buffer 27B ₁ for writing (or buffer 27B ₂₎ to one macroblock decoding result is stored, the buffer 27B ₁ for writing (or buffer 27B ₂₎ a buffer _27B 2 for reading ( Alternatively, the buffer 27B ₁ ) is switched, the decoding result for the next one macroblock is written into the buffer 27B ₂ (or buffer 27B ₁ ) switched for writing, and the buffer 27B ₁ (or buffer 27B switched for reading). ₂ ) The decoding result in ( ₂ ) is supplied to the bus I / F 21C.

The bus I / F 21C is supplied with data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ and data α ₃ , supplied from the moving picture decoder 25 and the alpha data decoder 26 via the external memory I / F 27. α ₂ , α ₁ , α ₀ are merged into 64-bit data (FIG. 3B) having the above-described data structure, and serve as merging means for transferring the merged data to the external memory module 102. More specifically, the bus I / F 21C uses its own memory as the ring buffer 89 and performs the first and second write processes in parallel. The first write process advances the write destination pointer of the buffer 90-k (k = 1, 2,...) In the ring buffer 89 by one each time the writing of data for one macroblock is completed, and the external memory I / F 27 Is a process of writing the data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , and Y ₀ supplied from the data into the buffer 90-k indicated by the write destination pointer at the time of supply. The second write process advances the write destination pointer of the buffer 90-k (k = 1, 2,...) In the ring buffer 89 by one each time the writing of data for one macroblock is completed, and the external memory I / F 27. Is a process of writing the data α ₃ , α ₂ , α ₁ , α ₀ supplied from the buffer 90-k indicated by the write destination pointer at the time of supply. The bus I / F 21C stores data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ and data α ₃ , α ₂ , α in the common buffer 90-k in the first and second write processes. ₁ , α ₀ , data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ and data α ₃ , α ₂ , α ₁ , α ₀ are merged to form the above-described data structure. To do. Then, the bus I / F21c are data _V 3210 of one macro block in the buffer _{90-k, Y 3, Y} 2, U 3210, Y 1, Y 0 and the data alpha _3, alpha _2, alpha _1, the alpha ₀ When both are accumulated, the accumulated data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ and the data α ₃ , α ₂ , α ₁ , α ₀ are externally converted as decoding results for one macroblock. DMA (Direct to memory module 102
Memory Access) Transfer. Here, both data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ and data α ₃ , α ₂ , α ₁ , α ₀ for one macroblock are stored in the buffer 90-k. each time the DMA transfer performed, as shown in FIG. 6, each of the decoding result of a plurality of macro-blocks obtained by dividing an image of one frame (one macroblock data _{V 3210, Y 3, Y 2} , U 3210, Y ₁ , Y ₀ , α ₃ , α ₂ , α ₁ , α ₀ ) are stored in the external memory module 102 in a raster block order layout of the macroblocks.

b1. When a decoding execution command for instructing only execution of decoding of compressed encoded image data is written in the command buffer 22A In this case, the moving picture decoder 25 decodes the compressed encoded image data and outputs image data for one macroblock. And V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ are taken out from the generated image data, and the bus I / F 21 C is passed through the buffers 27 A ₁ and 27 A ₂ in the external memory I / F 27. Send to. The alpha data decoder 26 does not decode the compression-encoded alpha data. Instead, the data α ₃ , α ₂ , α ₁ , α ₀ (the transparency of all pixels is set to the maximum value (1111) of 4-bit resolution. alpha data) to 100% sends to the bus I / F21c through a buffer 27B ₁ and 27B ₂ in the external memory I / F 27. The bus I / F 21C includes data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ , α ₃ , α ₂ , 1 macroblock supplied from each of the video decoder 25 and the alpha data decoder 26. α ₁ and α ₀ are merged and transferred to the external memory module 102.

c1. When a decoding execution command for instructing only execution of decoding of compression-encoded alpha data is written in the command buffer 22A In this case, the moving picture decoder 25 does not decode the compression-encoded image data, but instead uses 8-bit data. Data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ (image data indicating a transparent image) in the resolution of the image data are stored in buffers 27A ₁ and 27A ₂ in the external memory I / F 27. To the bus I / F 21C. The alpha data decoder 26 decodes the compression-encoded alpha data to generate alpha data for one macroblock, and this alpha data (data α ₃ , α ₂ , α ₁ , α ₀ ) is stored in the external memory I / F 27. send to the bus I / F21c through the buffer 27B ₁ and 27B _2. The bus I / F 21C includes data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ , α ₃ , α ₂ , 1 macroblock supplied from each of the video decoder 25 and the alpha data decoder 26. α ₁ and α ₀ are merged and transferred to the external memory module 102.

  As described above, in this embodiment, the image processing apparatus 100 has a 4-bit resolution when the compression-coded alpha data to be decoded is compression-coded alpha data having a resolution different from 4 bits. The alpha data is delivered to the rendering apparatus 105 as a decoding result of the compression-encoded alpha data. Therefore, the image processing apparatus 100 does not need to notify the apparatus 105 of how many bits the resolution of the decoding result is every time the decoding result of the compression-encoded alpha data is delivered to the drawing apparatus 105. Therefore, it is possible to increase the processing speed from the decoding of the compression encoded image data and the compression encoded alpha data to the alpha blending using the decoding result.

Further, in the present embodiment, the image processing apparatus 100 is the data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ that are the decoding results by the moving picture decoder 25, and the decoding results by the alpha data decoder 26. The data α ₃ , α ₂ , α ₁ , α ₀ are merged 64 bits at a time, and the merged data is transferred to the external memory module 102. Thereby, in the external memory module 102, ten types of data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ , α ₃ , α ₂ , α ₁ , α ₀ necessary for alpha blending of one block. Are stored in consecutive address areas. Therefore, data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ that are the decoding results of the compression-encoded image data and α ₃ , α ₂ , α ₁ , which are the decoding results of the compression-encoded alpha data. The data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ , α ₃ , α ₂ , α ₁ , α by the drawing device 105 are compared with the case where α ₀ is stored separately in another address area. _The time required for reading ₀ is shortened, and the processing can be speeded up.

In the present embodiment, the image processing apparatus 100 receives the data V _{3210 having the} minimum value (00000000) in the 8-bit resolution when a decoding execution command for instructing only the decoding of the compression-encoded alpha data is given. , Y ₃ , Y ₂ , U ₃₂₁₀ , Y ₁ , Y ₀ instead of the decoding result of the compression-encoded image data, the data V ₃₂₁₀ , Y ₃ , Y ₂ , U ₃₂₁₀ , Y _{1 of} this minimum value (00000000) , Y ₀ are transferred to the external memory module 102 together with the data α ₃ , α ₂ , α ₁ , α ₀ which are the decoding results of the compression encoded alpha data. Therefore, by instructing only the execution of the decoding of the compression-encoded alpha data, it is possible to change the intensity of the color of the image that becomes the background image of the moving image and realize a kind of effect.

<Other embodiments>
As mentioned above, although embodiment of this invention was described, various other embodiment can be considered to this invention. For example, it is as follows.
(1) In the above embodiment, image data that is a decoding result of compression-encoded image data and alpha data that is a decoding result of compression-encoded alpha data are converted into image data and alpha data for one block (2 × 2 pixels). Merged. However, the image data and alpha data for a predetermined number of pixels different from one block (2 × 2 pixels) may be merged.

(2) In the above embodiment, one macroblock is obtained by dividing a matrix of image data and alpha data by the number of 16 × 16 pixels. However, one macroblock may be obtained by dividing a matrix of image data and alpha data by a predetermined number of pixels different from 16 × 16 pixels.

DESCRIPTION OF SYMBOLS 1 ... Moving image reproducing device, 100 ... Image processing device, 101A, 101B, 101C ... Bus, 103 ... Host CPU, 104 ... Pattern ROM, 105 ... Drawing device, 11 ... Cache memory, 12 ... Cache control unit, 21A, 21B, 21C ...... Bus I / F, 22 ... Host I / F, 23 ... Register group, 24 ... Pattern ROM I / F, 25 ... Movie decoder, 26 ... Alpha data Decoder, 27 ... External memory I / F

Claims (2)

A video decoder that decodes compression-encoded image data obtained by compression-encoding an image;
An alpha data decoder for decoding compression-encoded alpha data obtained by compression-encoding alpha data used for alpha blending of an image;
Image data and alpha corresponding to a predetermined number of pixels obtained by dividing an image data output as a decoding result from the moving picture decoder and alpha data output from the alpha data decoder as a decoding result used for the image data into one frame image An image processing apparatus comprising: merge means for merging data and transferring the data to an external memory module. Built-in two image data buffers for storing image data output as decoding results from the moving picture decoder, and two alpha data buffers for storing image data output as decoding results from the alpha data decoder Each time image data for one macroblock obtained by dividing an image of one frame is accumulated in one of the two image data buffers, the image data for one macroblock accumulated in one of the image data buffers is Each time the image data for one macroblock is stored in one of the two alpha data buffers, the alpha data for one macroblock stored in one of the alpha data buffers is merged with the merge means. Comprising an external memory interface for supplying means The image processing apparatus according to claim 1.

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