JP2011097165A - DIGITAL/ANALOG CONVERTER, DeltaSigma TYPE ANALOG/DIGITAL CONVERTER USING THE SAME, AND ELECTRONIC EQUIPMENT USING THE SAME - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ΔΣ type analog/digital converter with improved accuracy. <P>SOLUTION: A D/A converter 40 converts a digital input signal D<SB>IN</SB>input in each cycle into an analog output signal V<SB>OUT</SB>. Each unit element UC receives control data that can take any of a plurality of candidate values, and generates an analog signal showing the value. An addition computing element 44 adds an analog signal V generated by the unit element UC, and generates an analog output signal V<SB>OUT</SB>. A control circuit 42 outputs control data to each unit element UC by cycle. The control circuit 42 generates control data to each unit element UC so as to satisfy Y=Σ<SB>i=1 to N</SB>X<SB>i</SB>when the value of a digital input signal is written as Y and the value of control data to the i(1≤i≤N)-th unit element UC is written as X<SB>i</SB>. The control circuit 42 manages L candidate values among a plurality of candidate values as a circulation target value (L is natural number), and cyclically allocates control data showing each circulation target value to N unit elements UC. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a digital-to-analog converter.

In audio signal processing and the like, analog-to-digital converters using ΔΣ modulation (ΔΣ-type analog-to-digital converters) are widely used. A general ΔΣ type analog-digital converter mainly performs the following processing.
1. A difference signal indicating a difference between the analog input signal and the analog feedback signal is generated.
2. Integrate (filter) the difference signal.
3. Quantize the filtered signal. The quantized digital value is output as a result of analog-digital conversion, and is fed back as a feedback signal.

Japanese Patent Laid-Open No. 2008-17212 JP 2006-13704 A JP 2006-13705 A

  The ΔΣ analog-to-digital converter is provided with a digital-to-analog converter for converting the digital output signal into an analog feedback signal. Since the performance of the digital-analog converter affects various characteristics including noise of the entire ΔΣ-type analog-digital converter, a highly accurate digital-analog converter is desired. The high-precision digital-analog converter is useful for applications other than the ΔΣ-type analog-digital converter.

  The present invention has been made in view of such a problem, and an exemplary object of an embodiment thereof is to provide a digital-to-analog converter with improved accuracy.

One embodiment of the present invention relates to a digital-analog converter that converts a digital input signal input every cycle into an analog output signal. Each of the digital-analog converters receives N pieces of control data that can take any one of a plurality of candidate values, and generates N analog elements (N is an integer of 2 or more), and N pieces of unit elements. An addition operation circuit for adding analog signals generated by the unit elements to generate an analog output signal, and a control circuit for outputting control data to each of the N unit elements for each cycle. When the control circuit writes the value of the digital input signal as Y and the value of the control data for the i (1 ≦ i ≦ N) th unit element as X _i , Y = Σ _{i = 1: N} X _i is satisfied. Control data for each unit element is generated. Further, the control circuit sets L among the plurality of candidate values (L is a natural number) as a circulation target value, and cyclically assigns control data indicating each circulation target value to the N unit elements.

  According to this aspect, when the digital-analog conversion process is performed over a plurality of cycles, an analog signal indicating each circulation target value is generated by the plurality of unit elements without deviation. In other words, the use frequency of the plurality of unit elements for each circulation target value is made uniform. Therefore, even if the analog signal indicating the circulation target value varies for each of the plurality of unit elements, the statistical accuracy of the long-term analog output signal can be improved.

The L circulation target values may include two values having different signs and the same absolute value.
In this case, the frequency of use of the plurality of unit elements for each circulation target value having a different sign can be made uniform. Therefore, when the variation amounts of the positive analog signal and the negative analog signal having the same absolute value for each unit element have symmetry, the variation can be preferably canceled.

  The plurality of candidate values may be 0, −1, and 1, and the L circulation target values may be −1 and 1. The control circuit may cyclically assign control data indicating the circulation target value −1 to N unit elements and cyclically assign control data indicating the circulation target value 1 to N unit elements.

  The plurality of candidate values may be 0, −1, and 1, and the L circulation target values may be −1 and 1. The value Y of the digital input signal may take any one of 0, at least one positive value, and at least one negative value. When the value Y is positive in a certain cycle and the value of the first pointer indicating the number of the first unit element to which control data indicating the circulation target value 1 is to be assigned in that cycle is j, the control circuit The control data indicating the circulation target value 1 is allocated to the Y unit elements starting from the unit element indicated by, the control data indicating 0 is allocated to the remaining unit elements, and the value of the first pointer is updated to j + Y. Also good. In addition, when the value Y is negative in a certain cycle and the value of the second pointer indicating the number of the first unit element to which control data indicating the circulation target value −1 is to be assigned in that cycle is k, The control data indicating the circulation target value −1 is assigned to the Y unit elements starting from the unit element indicated by the two pointers, the control data indicating 0 is assigned to the remaining (N−Y) unit elements, and The value of the 2 pointer may be updated to k + Y.

  The control circuit may include L memories provided for each of the L circulation target values, and a logic unit that generates control data for the N unit elements based on the values of the L memories. Each memory may hold a pointer value indicating the number of the first unit element to which control data indicating the corresponding circulation target value in the cycle is to be assigned. The logic unit may generate control data for the N unit elements based on pointer values held in the L memories.

The plurality of candidate values may be 0, −1, and 1, and the L circulation target values may be −1 and 1. The value Y of the digital input signal may take any one of 0, at least one positive value, and at least one negative value. The control circuit may generate a set of control data so that the number of control data indicating the candidate value 0 is minimized.
When the value of the analog signal corresponding to 0 varies, the accuracy of the digital-analog converter can be increased by reducing the frequency of occurrence of 0.

  In one aspect, the number of control data indicating the candidate value 0 may be reduced by replacing two zeros (zero pairs) with two value pairs having different signs and equal absolute values.

Another aspect of the present invention relates to a ΔΣ analog-to-digital converter that converts an analog input signal into a digital output signal. This ΔΣ analog-to-digital converter receives a digital output signal and converts it into an analog feedback signal. The digital-to-analog converter according to any one of the above aspects, a signal according to the analog input signal, and a signal according to the analog feedback signal A difference calculation circuit that generates a difference signal corresponding to the difference between the filter circuit, a filter circuit that filters at least one integrator, filters the difference signal, and a quantizer that quantizes the output signal of the filter circuit and generates a digital output signal And comprising.
The ΔΣ analog-digital converter performs a temporal accumulation process (integration process). According to the digital-analog converter described above, since long-term fluctuations in the variation of the analog feedback signal are suppressed, the accuracy of the ΔΣ-type analog-digital converter can be increased.

  In addition to the control circuit method described above, the digital-analog converter is configured to be able to generate control data using a different method, and the control data generation method can be switched in response to an external switching signal. It may be configured.

  Yet another embodiment of the present invention is an electronic device. This electronic apparatus includes the above-described ΔΣ analog-to-digital converter that converts an analog audio signal into a digital signal, and a signal processing unit that performs predetermined signal processing on the digitized audio signal.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  The digital-analog converter according to the present invention can reduce errors.

It is a circuit diagram which shows the structure of the D / A converter which concerns on embodiment. It is a time chart which shows operation | movement of the D / A converter of FIG. FIGS. 3A and 3B are state transition diagrams showing operations of the D / A converter according to the embodiment and the D / A converter according to the comparison technique. It is a block diagram which shows the structure of a delta-sigma type A / D converter provided with the D / A converter of FIG. FIG. 5 is a circuit diagram illustrating a specific configuration example of a D / A converter in the ΔΣ A / D converter of FIG. 4. It is a block diagram which shows the modification of the D / A converter of FIG. It is a block diagram which shows the structure of an electronic device provided with the delta-sigma type A / D converter of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

FIG. 1 is a circuit diagram showing a configuration of a digital analog (D / A) converter according to an embodiment. D / A converter 40 receives a digital input signal _{D IN} to be entered for each cycle, into an analog output signal _{V OUT} corresponding to the value Y.

The present invention is applicable to any resolution and number of quantization of the D / A converter, for ease of understanding in the following, the value of the digital input signal D _IN is 9 values at 1 increments until -4～4 Shall be taken. The correspondence between the voltage value of the values and the analog output signal V _OUT of the digital input signal D _IN below.
V _OUT = D _IN × ΔV + Vc (1)
ΔV is a potential difference corresponding to 1LSB of the digital input signal _{D IN,} Vc is a voltage level corresponding to the value 0 of the digital input signal _{D IN.}
When the power supply voltage Vdd and the ground voltage (0 V) are supplied to the D / A converter 40, Vc is set to the midpoint Vdd / 2 of the power supply voltage Vdd. When the positive power supply voltage Vdd and the negative power supply voltage −Vdd are supplied to the D / A converter 40, Vc may be the ground voltage 0V.

It includes a D / A converter 40, a control circuit 42, an addition calculator 44, and a plurality of unit elements UC _{0 to} UC _N−1 . The D / A converter 40 is a so-called segment-switched capacitor type D / A converter, and a configuration example thereof is disclosed in Patent Document 2 and is omitted here.

The plurality of N unit elements UC _{0 to} UC _N-1 all have the same configuration. Each unit element UC receives control data CNT that can take any one of a plurality of candidate values, and generates an analog signal indicating the value. FIG. 1 shows a case where N = 8.
Each unit element UC includes capacitors having the same capacitance value. Each capacitor is charged with a reference voltage corresponding to the value of the corresponding control data. The voltage generated in each capacitor is output as an analog signal to the addition calculator 44 at the subsequent stage.

Specifically, the i-th (0 ≦ i ≦ N−1) unit element UC _i receives the corresponding control signal CNT _i from the control circuit 42 and receives the analog signal V indicating the value X _i of the control signal CNT _{i. i} is generated.
V _i = ΔV × X _i (2)
The control signal CNT _i takes one of a plurality of candidate values (a1, a2,... AM).

The number M of candidate values is not particularly limited, but in the present embodiment, the number M of candidate values is 3, and a1 = −1, a2 = 1, and a3 = 0. That is, the analog signal V _i output from the unit element UC can take any of (−ΔV, ΔV, 0).

The addition calculator 44 adds the analog signals V _{0 to} V ₇ generated by the _N unit elements UC _{0 to} UC _N−1 to generate an analog output signal _VOUT .
V _OUT = Σ _{i = 0: N−1} V _i (3)

The control circuit 42 outputs the control data _CNT 0 to CNT _N-1 to N unit elements _UC of 0 _{to UC N-1,} respectively for each cycle. When writing the value of the digital input signal _{D IN} Y, i a value of (0 ≦ i ≦ N-1 ) th unit element control data CNT _i for UC _i and _{X i,} the control circuit 42,
Y = Σ _{i = 0: N−1} X _i (4)
The control data sets CNT _{0 to} CNT _N−1 for each unit element UC are generated so as to satisfy the above.

At least one (L) of the plurality of candidate values a1 to a3 is defined as the circulation target value. L is a natural number. The control circuit 42 cyclically assigns control data indicating each circulation target value to the N unit elements UC _{0 to} UC _N−1 .

  The generation of the control data CNT by the control circuit 42 will be described in detail.

It is desirable that the L circulation target values include two values having different signs. For example, for the candidate values −1, 1, 0, L = 2 and the circulation target value may be −1 and 1. The control circuit 42 cyclically assigns the control data indicating the circulation target value −1 to the N unit elements UC _{0 to} UC _N−1 . Similarly, the control circuit 42 cyclically assigns control data indicating the circulation target value 1 to the N unit elements UC _{0 to} UC _N−1 . The number of each unit element is virtual, and when a plurality of unit elements UC are arranged in a line, they may be numbered as 0, 1,... Numbering may be performed regardless of the arrangement.

As described above, the value Y of the digital input signal _{D IN} is 0, at least one positive value (1,2,3,4), and at least one negative value (-1, -2, -3, -4)

  The control circuit 42 manages pointers P1 and P2 associated with L circulation target values −1 and 1, respectively. When the value Y is negative in a certain cycle and the value of the first pointer P1 indicating the number of the first unit element to which control data indicating the circulation target value −1 is to be assigned in that cycle is j, the control circuit 42 Control data indicating the circulation target value −1 is assigned to consecutive Y unit elements starting from the unit element indicated by the first pointer P1, and control data indicating 0 is assigned to the remaining unit elements. Then, the control circuit 42 updates the value of the first pointer P1 to j + Y.

Similarly, when the value Y is positive in a certain cycle and the value of the second pointer P2 indicating the number of the first unit element to which control data indicating the circulation target value 1 is to be assigned in that cycle is the control circuit 42, The control data indicating the circulation target value 1 is allocated to the Y unit elements starting from the unit element UC indicated by the second pointer P2, and the control data indicating 0 is allocated to the remaining (N−Y) unit elements. At the same time, the value P2 of the second pointer is updated to k + Y. When N unit elements UC _{0 to} UC _N−1 are provided, the values of the first pointer P1 and the second pointer P2 can take any of 0 to N−1.

  Note that “the number of the first unit element to which control data indicating a circulation target value in a certain cycle is to be assigned” is “the last unit element to which control data indicating a circulation target value is assigned in the previous cycle”. One-to-one correspondence is possible. Thus, whatever is used as a pointer is equivalent.

Since the control data indicating the same circulation target value is cyclically assigned to the plurality of unit elements UC _{0 to} UC _N−1 , the Nth, N + 1th,... Unit elements,. Corresponds to 0th, 1st,... Unit elements.

When the value Y is 0 in a certain cycle, the control circuit 42 assigns control data indicating the value 0 to all the unit elements UC _{1 to} UC _{8 and} keeps the values of the first pointer P1 and the second pointer P2 as they are. Hold.

  The above is the control data generation rule. The control circuit 42 includes a first memory 50, a second memory 52, and a logic unit 54. The first memory 50 and the second memory 52 are provided for every L (L = 2) circulation target values (−1, +1). Each memory holds a pointer value indicating the number of the first unit element to which control data indicating the corresponding circulation target value should be assigned in each cycle.

The first memory 50 holds the value of the first pointer P1 related to the circulation target value-1. The second memory 52 holds the value of the second pointer P2 related to the circulation target value 1. The logic unit 54 generates control data CNT _{1 to} CNT ₈ for the N unit elements based on the L memory values P1 and P2.

Logic unit 54 determines the sign of the digital input signal _{D IN.} If negative, the first memory 50 is referred to, and the value j of the first pointer P1 in that cycle is acquired. When the value of the first pointer P1 is j, the unit elements _{UC j ~UC j + Y-1} , and outputs the control data _{CNT j ~CNT} j _{+ Y-1} indicating the value -1, the other unit element UC, the value 0 The control data shown is output. Then, the value of the first pointer P1 is rewritten to j + Y.

Logic unit 54, the sign of the digital input signal D _IN is the case of positive, referring to the second memory 52, obtains the value k of the second pointer P2. When the value of the second pointer P2 is k, the unit elements _{UC k ~UC k + Y-1} , and outputs the control data _{CNT k ~CNT} k _{+ Y-1} indicating the value 1, the other unit elements UC, indicating the value 0 Output control data. Then, the value of the second pointer P2 is rewritten to k + Y.

  The first memory 50 and the second memory 52 may be a 3-bit counter that counts up based on data from the logic unit 54. In this case, the logic unit 54 may count up the first memory 50 by one each time control data indicating the circulation target value −1 is assigned to one unit element UC. Similarly, the logic unit 54 may count up the second memory 52 by one each time control data indicating the circulation target value 1 is assigned to one unit element UC. A countdown may be used instead of the countup.

The above is the configuration of the D / A converter 40 according to the embodiment. Next, the operation will be described. FIG. 2 is a time chart showing the operation of the D / A converter 40 of FIG. The horizontal axis represents time (cycle). For example, in the initial state, the values of the pointers P1 and P2 are both 0. Since the value Y of the input digital signal _{D IN} to the first cycle is zero, all control data _CNT 0 to CNT ₇ is zero. The values of the pointers P1 and P2 maintain the initial value 0.

Since the value Y of the input digital signal _{D IN} in the next cycle t2 is 1, control data CNT ₀ for one of the unit elements UC ₀ to start the unit elements UC ₀ which is indicated by j = 0 of the second pointer P2 values _{X 0} is 1, and the value _X 1 to X ₇ of other control data _CNT 1 to CNT ₇ becomes zero. Then, the value of the second pointer P2 is incremented by 1 (= abs (Y)), and P1 = 1. The value of the first pointer P1 is maintained.

The value Y of the input digital signal _{D IN} in the next cycle t3 -2. Since the value of the first pointer P1 is 0, 2, top unit elements _{UC 0 (= abs (Y)} ) control data _CNT 0 for number of unit elements _UC 0, UC _1, CNT ₁ values _X 0, X ₁ is -1, and the value _X 2 to X ₇ of other control data _CNT 2 to CNT ₇ becomes zero. Then, the value of the first pointer P1 is incremented by 2 (= abs (Y)). The value of the second pointer P2 is maintained.

The value Y of the input digital signal _{D IN} In further subsequent cycle t4 is -1. Since the value of the first pointer P1 is 2, the unit element UC ₂ 1 and the top (= abs (Y)) values _{X 2} of the control data CNT ₂ for number of unit elements UC ₂ is next to 1, Other control data _{CNT 0,} the value _X 2 to X ₇ of CNT _1, CNT 3 ~CNT ₇ becomes zero. Then, the value of the first pointer P1 is incremented by 1 (= abs (Y)). The value of the second pointer P2 is maintained.

  Thereafter, the D / A converter 40 repeats the same processing for each cycle.

The D / A converter 40 according to the embodiment has the following advantages.
In this D / A converter 40, control data indicating the predetermined circulation target value among the plurality of candidate values is cyclically assigned to the plurality of unit elements. Is generated without deviation by the plurality of unit elements. In other words, the frequency of use of a plurality of unit elements for each circulation target value can be made uniform.

  Actually, it is difficult to manufacture all the unit elements UC without variation, and therefore, the voltage value (or current value) of the analog signal indicating the circulation target value −1 is different for each unit element. The voltage value (or current value) of the analog signal indicating the target value 1 is also different. Therefore, when non-zero control data is intensively assigned to a certain unit element UC, there arises a problem that an error of an analog signal is accumulated. On the other hand, in the D / A converter 40 according to the embodiment, the variation in the value of the analog signal can be canceled by equalizing the use frequency of the plurality of unit elements for each circulation target value.

  Further, in the unit element UC, variations in the analog signal corresponding to two values (−1, 1) having different signs and the same absolute value have symmetry, in other words, the value of the analog signal corresponding to the control data−1. And the absolute value of the analog signal corresponding to the control data-1 may be equal. In this case, by managing two values (−1, 1) having different signs and the same absolute value as the circulation target values, a positive analog signal and a negative analog signal having the same absolute value are managed for each unit element. The variation amount can be suitably canceled, and long-term accuracy can be improved.

  The advantages of the D / A converter 40 according to the embodiment are clarified by comparison with a comparative technique. FIGS. 3A and 3B are state transition diagrams showing operations of the D / A converter 40 according to the embodiment and the D / A converter according to the comparison technique.

  The comparison technique will be described with reference to FIG. The control data generation method in this comparative technique is referred to as an element circulation method, and the control data generation method in the embodiment is referred to as an improved element circulation method.

  In the element circulation method, a single common pointer is managed for a plurality of circulation target values −1 and 1. This common pointer indicates the number of the first unit element to which control data indicating non-zero should be assigned. When the value Y is negative in a certain cycle and the value of the common pointer is j, the control circuit performs control to indicate the circulation target value −1 in consecutive Y unit elements starting from the unit element indicated by the common pointer. Data is assigned, and control data indicating 0 is assigned to the remaining unit elements. Then, the control circuit 42 updates the value of the common pointer to j + Y.

  Similarly, when the value Y is positive in a certain cycle and the value of the common pointer is k in that cycle, the control circuit 42 applies a circulation target value to Y unit elements starting with the unit element UC indicated by the common pointer. Control data indicating 1 is allocated, and control data indicating 0 is allocated to the remaining (N−Y) unit elements. Then, the value of the common pointer is updated to k + Y.

According to the element circulation method of FIG. 3B, a non-zero analog signal can be generated without bias by the plurality of unit elements UC. However, focusing on the unit elements UC ₀ and UC ₁ , for example, −1 is assigned in 3 cycles out of 9 cycles, and 1 is never assigned. On the other hand, when attention is paid to the unit element UC ₃ , a situation occurs in which 1 is assigned in 2 cycles out of 9 cycles and −1 is never assigned.

  On the other hand, as shown in FIG. 3A, in the D / A converter 40 according to the embodiment, the frequency at which 1 is allocated and the frequency at which −1 is allocated are substantially equal in each unit element UC. Therefore, the positive / negative variation when viewed in the long term can be suitably canceled.

  The D / A converter 40 according to the embodiment has been described above. Next, a suitable application will be described. FIG. 4 is a block diagram illustrating a configuration of a ΔΣ A / D converter 100 including the D / A converter 40 of FIG. The ΔΣ A / D converter 100 includes a difference calculation circuit 10, a filter circuit 20, a quantizer 30, and the D / A converter 40 of FIG.

  The D / A converter 40 converts the digital output signal Sout of the ΔΣ A / D converter 100 into an analog feedback signal Sfb. The difference calculation circuit 10 generates a difference signal Sd corresponding to a difference (Sin−Sfb) between a signal Sin corresponding to the input signal Sin and a signal corresponding to the feedback signal Sfb.

  The filter circuit 20 filters the difference signal Sd. The filter circuit 20 includes a plurality of integrators INT1 to INT3 according to the order, a plurality of coefficient circuits g1 to g7, and a plurality of adders ADD1 and ADD2. Since the circuit topology of the filter circuit 20 is a known one, the description is omitted. In addition, the configuration is not limited to that of FIG. 1, and those skilled in the art will recognize that there are other variations.

  The quantizer 30 quantizes the output signal Sf of the filter circuit 20 and generates a digital output signal Sout.

  FIG. 5 is a circuit diagram showing a specific configuration example of the D / A converter in the ΔΣ A / D converter of FIG. 4. The D / A converter 40 is configured integrally with the difference calculation circuit 10. Specifically, the addition arithmetic unit 44 of the D / A converter 40 and the difference arithmetic circuit 10 are configured by sharing one operational amplifier 46, and the segment switched capacitor type D / A converter and the switch This is a hybrid circuit of a capacitor-type adder.

  In the D / A converter 40, the switch group denoted by reference numeral 1 and the switch group denoted by reference numeral 2 are alternately turned on and off alternately. As a result, a difference signal Sd indicating a difference between the input signal Sin and the feedback signal Sfb is generated.

Since each unit element UC is configured similarly, only the unit element UC ₀ is shown in detail.
The control data CNT _{0 to} CNT _N−1 generated by the control circuit 42 includes first data S1 and second data S2, respectively. When the value of the control data CNT is 1, S1 = 0, S2 = 1, when the value of the control data CNT is -1, when S1 = 1, S2 = 0, and when the value of the control data CNT is 0 , S1 = 0 and S2 = 0.

  The switch SW1 of the unit element UC is turned on when the first data S1 is 1, and turned off when the first data S1 is 0. The switch SW2 of the unit element UC is turned on when the second data S2 is 1, and turned off when it is 0. That is, the unit element UC is coupled to the addition calculator 44 in reverse phase when the value of the control data CNT is 1 and −1. Therefore, it can be said that the variation in absolute values of the analog signal corresponding to the value 1 and the analog signal corresponding to the value −1 is equal. When the value of the control data CNT is 0, the unit element UC is disconnected from the addition calculator 44.

  The D / A converter 40 is a differential type, but may be configured as a single end type. When the D / A converter 40 is used alone, the circuit block 45 to which the input signal Sin is input may be omitted. Further, the present invention can be applied not only to the switched capacitor type but also to other segment type D / A converters.

The above is the configuration of the ΔΣ A / D converter 100.
The ΔΣ A / D converter 100 performs temporal accumulation processing (integration processing). Therefore, by using the above-described D / A converter 40, the variation of the analog feedback signal Sfb is canceled in the long term, so that the accuracy of the ΔΣ analog-digital converter can be improved.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  FIG. 6 is a block diagram showing a modification of the D / A converter of FIG. The D / A converter 40a is configured to be capable of generating the control data CNT by another method different from the method of the control circuit 42 (the improved element circulation method) described above. The D / A converter 40a can switch the generation method of the control data CNT in accordance with the switching signal SEL from the outside.

For example, one of the other methods is an element circulation method shown in FIG. One alternative is a random method. In the random method, predetermined control data is fixedly generated for each value Y. For example, control data is generated according to the following rules.
Y = -4 CNT _{0 to} CNT ₃ = -1 CNT _{4 to} CNT ₇ = 0
Y = -3 CNT _{0 to} CNT ₂ = -1 CNT _{3 to} CNT ₇ = 0
Y = -2 CNT _{0 to} CNT ₁ = -1 CNT _{2 to} CNT ₇ = 0
Y = -1 CNT ₀ = -1 CNT _{1 to} CNT ₇ = 0
Y = −0 CNT _{0 to} CNT ₇ = 0
Y = 1 CNT ₀ = 1 CNT _{4 to} CNT ₇ = 0
Y = 2 CNT _{0 to} CNT ₁ = 1 CNT _{2 to} CNT ₇ = 0
Y = 3 CNT _{0 to} CNT ₂ = 1 CNT _{3 to} CNT ₇ = 0
Y = 4 CNT _{0 to} CNT ₃ = 1 CNT _{4 to} CNT ₇ = 0

  For example, one of the other methods may be a secondary-DWA method described in Patent Document 2 described above.

  Only one control circuit selected by the control signal SEL is active, and the other control circuits are inactive.

  Each of the plurality of control methods has different characteristics (S / N level, THD + N level, power consumption). Therefore, according to the D / A converter 40 of FIG. 6, the optimum control method can be switched and used for each application.

  The inactive control circuit is stopped from supplying any one of the clock signal, the reference current, the power supply voltage, or any combination thereof. As a result, an increase in power consumption is suppressed.

In the above-described improved element circulation method or element circulation method, the control circuit 42 of the D / A converter 40 may generate a set of control data so that the number of control data indicating the candidate value 0 is minimized. .
Control data is
Y = Σ _{i = 0: N−1} X _i (4)
Generated to satisfy. Thus, two zero-pairs of control data can be replaced with two value pairs of equal absolute value and different signs (positive and negative), for example, 1 and −1 pairs. For example, in the first cycle of FIG. 3A, the control data CNT _{4 to} CNT ₇ are (0, 0, 0, 0), which is (1, 1, -1, -1) or (1,- 1,1, -1) or the like.

That is, when the control data sets CNT _{0 to} CNT ₇ are generated by the above-described improved element circulation method (or element circulation method, random method), and then the number of control data to which 0 is assigned is two or more. Replaces two zero pairs (0,0) with (-1,1).

Actually, the analog signal indicating the candidate value 0 also varies, and it is difficult to cancel this error. That is, every time the unit element UC outputs an analog signal having a value of 0, the error of the analog output signal _VOUT increases.
By replacing the zero pair (0,0) with (1, -1), the error corresponding to the value 0 can be preferably canceled.

  Finally, an application of the ΔΣ A / D converter 100 in FIG. 4 will be described. FIG. 7 is a block diagram illustrating a configuration of the electronic device 2 including the ΔΣ A / D converter 100. The electronic device 2 includes a microphone 4, a ΔΣ A / D converter 100, and a signal processing unit 6. For example, the electronic device 2 is a device having a function of recording an audio signal, such as an IC recorder, a digital camera, a video camera, and a mobile phone.

  The microphone 4 converts an acoustic signal into an analog electric signal. The ΔΣ A / D converter 100 converts an analog electrical signal Sin into a digital electrical signal Sout. The signal processing unit 6 performs digital signal processing unique to the device on the digital signal Sout. For example, in the case of an IC recorder, a digital camera, or a video camera, the digital signal Sout is compressed in a predetermined format and stored together with video in a memory (not shown).

  According to the electronic device 2 in FIG. 7, since the audio signal can be converted into a digital signal with low noise, a high-quality audio signal is obtained when the digital signal is reconverted into an analog signal and reproduced later. be able to.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and changes in the arrangement are allowed within the range not to be performed.

DESCRIPTION OF SYMBOLS 10 ... Difference arithmetic circuit, 20 ... Filter circuit, 30 ... Quantizer, ADD ... Adder, INT ... Integrator, 40 ... D / A converter, 42 ... Control circuit, 44 ... Addition arithmetic unit, 50 ... 1st Memory, UC, unit element, 52, second memory, 54, logic unit, 100, ΔΣ A / D converter.

Claims (9)

A digital-analog converter that converts a digital input signal input every cycle into an analog output signal,
N unit elements (N is an integer of 2 or more) each receiving control data that can take any of a plurality of candidate values and generating an analog signal indicating the value,
An addition operation circuit for adding the analog signals generated by the N unit elements and generating the analog output signal;
A control circuit for outputting control data to each of the N unit elements for each cycle;
With
The control circuit writes Y as the value of the digital input signal and X _{i as} the value of control data for the i (1 ≦ i ≦ N) -th unit element,
Y = Σ _{i = 1: N} X _i
Control data for each unit element is generated so as to satisfy, and the control circuit sets L of the plurality of candidate values (L is a natural number) as a circulation target value, and the control data indicating each circulation target value Is cyclically assigned to the N unit elements.   The digital-to-analog converter according to claim 1, wherein the L circulation target values include two values having different signs and the same absolute value. The plurality of candidate values are 0, −1 and 1, and the L circulation target values are −1 and 1.
The control circuit cyclically assigns control data indicating the circulation target value −1 to the N unit elements, and cyclically assigns control data indicating the circulation target value 1 to the N unit elements. The digital-to-analog converter according to claim 1, wherein The plurality of candidate values are 0, -1 and 1, the L circulation target values are -1 and 1, the value Y of the digital input signal is 0, at least one positive value, and Take one of at least one negative value,
When the value Y is positive in a certain cycle and the value of the first pointer indicating the number of the first unit element to which control data indicating the circulation target value 1 is to be assigned in that cycle is j, Control data indicating circulation target value 1 is allocated to Y unit elements starting from the unit element indicated by the pointer, control data indicating 0 is allocated to the remaining unit elements, and the value of the first pointer is updated to j + Y. ,
The unit indicated by the second pointer when the value Y is negative in a certain cycle and the value of the second pointer indicating the number of the first unit element to which control data indicating the circulation target value −1 is to be assigned in that cycle is k The control data indicating the circulation target value −1 is allocated to the Y unit elements starting from the element, the control data indicating 0 is allocated to the remaining (N−Y) unit elements, and the value of the second pointer is set. The digital-to-analog converter according to claim 1, wherein the digital-to-analog converter is updated to k + Y. The control circuit includes:
L memories provided for each of the L circulation target values, each holding a pointer value indicating the number of the first unit element to which control data indicating the corresponding circulation target value should be assigned in each cycle;
A logic unit that generates the control data for the N unit elements based on values held by the L memories;
The digital-to-analog converter according to claim 1, comprising: The plurality of candidate values are 0, -1 and 1, the L circulation target values are -1 and 1, the value Y of the digital input signal is 0, at least one positive value, and Take one of at least one negative value,
2. The digital-analog converter according to claim 1, wherein the control circuit generates the set of control data so that the number of control data indicating the candidate value 0 is minimized. A ΔΣ analog-to-digital converter that converts an analog input signal into a digital output signal,
The digital-to-analog converter according to any one of claims 1 to 6, wherein the digital-output signal is received and converted into an analog feedback signal;
A difference calculation circuit that generates a difference signal according to a difference between the signal according to the analog input signal and the signal according to the analog feedback signal;
A filter circuit including at least one integrator and filtering the difference signal;
A quantizer that quantizes the output signal of the filter circuit and generates the digital output signal;
A ΔΣ analog-to-digital converter characterized by comprising:   The digital-to-analog converter is configured to be able to generate the control data by another method different from the method of the control circuit according to claim 1, and the control data according to a switching signal from the outside. The ΔΣ analog-to-digital converter according to claim 7, wherein the control data generation method of the circuit can be switched. The ΔΣ analog-to-digital converter according to claim 7 or 8, which converts an analog audio signal into a digital signal;
A signal processing unit that performs predetermined signal processing on the digitized audio signal;
An electronic device comprising:

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