JP2011096736A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a gate insulating film of an anti-fuse composed of a transistor excellent in characteristics after breakage. <P>SOLUTION: A semiconductor device 100 includes: the anti-fuse element composed of the transistor comprising a gate 119 comprising a gate insulating film 107 formed on one surface of a substrate (P well 102), a gate electrode 108, and side walls 111 formed on both sides of the gate electrode 108, and a first source-drain region 104a and a second source-drain region 104b formed on the one surface of the P well 102 on both sides of the gate 119 respectively; and side wall contacting contacts (134) formed in the side walls 111 and electrically connected to the first source-drain region 104a and second source-drain region 104b or the gate electrode 108. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an antifuse.

  As an element for programming information, a gate insulating film breakdown type antifuse element is known. In such an anti-fuse element, as a programming method, writing is performed by applying a voltage to the gate electrode to break the gate insulating film and make the gate electrode and the source / drain conductive.

  Patent Document 1 (US Pat. No. 7,277,347) describes a configuration using an NMOS structure formed in an N well as an antifuse.

U.S. Pat. No. 7,277,347

Bonnie E. Weir et al, “GATE DIELECTRIC BREAKDOWN: A FORCUS ON ESD PROTECTION”, Fig.3, 4, IRPS2004

  However, if the gate insulating film of an anti-fuse element having an NMOS transistor structure is destroyed and a filament is formed between the gate electrode and the substrate, a parasitic transistor in which the filament portion serves as a drain is formed. Become. FIG. 5 is a diagram showing a configuration of the semiconductor device 10 using an NMOS transistor as an antifuse element. FIG. 5A shows a configuration before the gate insulating film is broken, and FIGS. 5B and 5C show a configuration after the gate insulating film is broken.

  As shown in FIG. 5A, the semiconductor device 10 includes a P well 12, a gate 19 formed on the P well 12, and source / drain regions formed on both sides of the gate 19 on the surface of the P well 12. 14 and. The gate 19 includes a gate insulating film 20, a gate electrode 22, a silicide layer 24 formed on the surface of the gate electrode 22, and sidewalls 25 formed on both sides of the gate electrode 22. A silicide layer 15 is also formed on the surface of the source / drain region 14. Here, the source / drain region 14 may be an N-type impurity diffusion region.

  As shown in FIG. 5B, when a predetermined voltage Vg is applied to the gate electrode 22 with the source / drain region 14 grounded, the gate insulating film 20 is destroyed and a filament 50 is formed in the gate insulating film 20. The As a result, the gate electrode 22 is electrically connected to the P well 12 through the filament 50. However, when the filament 50 is formed as described above, the filament 50 functions as a drain, and a parasitic transistor is formed between the source / drain regions 14. Here, in this parasitic transistor, since the filament 50 functioning as the drain is short-circuited to the gate electrode 22, a high voltage Vg is applied. Further, this parasitic transistor has a short gate length. Therefore, hot carriers are generated in the parasitic transistor. When hot carriers are generated in the parasitic transistor, the characteristics are deteriorated, Vt of the parasitic transistor is increased, and the current flowing through the filament 50 is reduced. Therefore, it causes a defect as an antifuse device.

  The present inventors examined the cause of the increase in Vt of such a parasitic transistor. The inventors have found that the cause of the increase in Vt of the parasitic transistor is that hot carriers generated in the parasitic transistor are trapped in the sidewall 25. In particular, when the antifuse element is constituted by an NMOS transistor, hot electrons (electrons) are generated as hot carriers. As a result, electrons are held in the sidewall 25 for a long time. This state is shown in FIG. In the state shown in FIG. 5C, the electrons 60 are trapped in the sidewall 25. Since the electrons 60 are trapped in the sidewall 25 in this way, even when a voltage is applied to the gate electrode 22, a sufficient voltage is not applied below the gate electrode 22 due to the influence of the electrons 60, and a channel is difficult to be formed. Therefore, it is considered that Vt of the parasitic transistor is increased.

According to the present invention,
A gate composed of a gate insulating film formed on one surface of the substrate, a gate electrode, and sidewalls respectively formed on both sides of the gate electrode; and on both sides of the gate on the one surface of the substrate An anti-fuse element formed of a transistor including a first source / drain region and a second source / drain region respectively formed in
A sidewall contact contact formed in the sidewall and electrically connected to the first source / drain region and the second source / drain region, or the gate electrode;
A semiconductor device is provided.

  According to this configuration, after breakdown of the gate insulating film of the antifuse element, a parasitic transistor is formed between the filament formed in the gate insulating film and the first source / drain region or the second source / drain region. Even if hot carriers are generated, the carriers can be released from the source / drain regions or the gate electrode through the sidewall contact contacts and can be prevented from being trapped by the sidewalls. Thus, when a voltage is applied to the gate electrode, the voltage is applied to the first source / drain region and the second source / drain region, the parasitic transistor is turned on, and the gap between the gate electrode and the channel region is turned on. Good electrical connection is maintained. As a result, the current after the breakdown of the gate insulating film can flow stably, and the reliability can be improved. That is, it is possible to satisfactorily read the program state for the antifuse element.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between methods, apparatuses, and the like are also effective as an aspect of the present invention.

  According to the present invention, it is possible to improve the characteristics after the breakdown of the gate insulating film of the antifuse composed of the transistors.

It is sectional drawing which shows an example of a structure of the semiconductor device in embodiment of this invention. It is a top view which shows an example of a structure of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the other example of a structure of the semiconductor device in embodiment of this invention. It is a top view which shows the other example of a structure of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing which shows the problem at the time of using common NMOS as an antifuse. It is a schematic diagram which shows the effect of the semiconductor device in embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same constituent elements are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

FIG. 6 is a cross-sectional view showing a configuration of the semiconductor device 10 using a general NMOS transistor as an antifuse. 6A shows a configuration before the gate insulating film is broken, and FIG. 6B shows a configuration after the gate insulating film is broken.
The semiconductor device 10 has the same configuration as that of the semiconductor device 10 shown in FIG. 5, but in addition to the configuration shown in FIG. 5, a channel region 16 formed between the source / drain regions 14 on the surface of the P well 12. And an interlayer insulating film 30 formed to bury the gate 19 on the P well 12. Further, the sidewall 25 can be constituted by a laminated film of a silicon oxide film 26, a silicon nitride film 28, and a silicon oxide film 29 formed in this order on the side of the gate electrode 22.

  In the interlayer insulating film 30, a contact 32 for connecting the source / drain region 14 and the wiring layer 42 and a contact 34 for connecting the gate electrode 22 and the wiring layer 44 are formed. Although not shown, a silicide layer similar to the silicide layer 15 described with reference to FIG. 5 may be formed on the surface of the source / drain region 14. As shown in FIG. 6B, in the semiconductor device 10 having such a configuration, in particular, the electrons 60 are easily trapped in the silicon nitride film 28 of the sidewall 25. Even when the sidewall does not include a silicon nitride film, electrons 60 are trapped in the insulating film constituting the sidewall.

  Therefore, in the following embodiment, there is provided a configuration in which such electrons 60 are not trapped by the sidewall 25 and escape to the outside. In the following embodiments, a semiconductor device includes a contact formed in a sidewall of an antifuse element formed of a MOS transistor and electrically connected to a source region and a drain region, or a gate electrode. be able to. Thus, electrons can be released from the source / drain region or the gate electrode to the outside through the contact, and can be prevented from being trapped by the sidewall.

(First embodiment)
FIG. 1 is a cross-sectional view illustrating an example of the structure of the semiconductor device in this embodiment. FIG. 1A shows a configuration before the gate insulating film is broken, and FIG. 1B shows a configuration after the gate insulating film is broken. FIG. 2 is a plan view showing an example of the structure of the semiconductor device in this embodiment. FIG. 1 corresponds to a cross-sectional view taken along the line aa in FIG. Here, a configuration is shown in which electrons are released from the sidewall to the source / drain region through a contact.

  The semiconductor device 100 includes a P-well 102 (substrate) formed on a substrate, a gate 119 formed on the P-well 102, and first sources formed on both sides of the gate 119 on the surface of the P-well 102, respectively. A drain region 104a and a second source / drain region 104b; a channel region 106 formed below the gate 119 between the first source / drain region 104a and the second source / drain region 104b on the surface of the P well 102; including. The gate 119 includes a gate insulating film 107, a gate electrode 108 formed thereon, a silicide layer 110 formed on the surface of the gate electrode 108, and sidewalls 111 formed on both sides of the gate electrode 108. . The sidewall 111 can be constituted by a laminated film of a silicon oxide film 112, a silicon nitride film 114, and a silicon oxide film 115 formed in this order on the side of the gate electrode. Although not shown here, a silicide layer similar to the silicide layer 15 described with reference to FIG. 5 is also formed on the surfaces of the first source / drain region 104a and the second source / drain region 104b. It can be configured.

  The semiconductor device 100 includes an interlayer insulating film 120 that is formed on the P well 102 and embeds the gate 119, and a source / drain wiring layer 140 and a gate wiring layer 142 formed on the interlayer insulating film 120. . In the interlayer insulating film 120, contacts 130 (first contact and second contact) that connect the first source / drain region 104a and the second source / drain region 104b to the source / drain wiring layer 140, respectively. And a contact 132 for connecting the gate electrode 108 and the gate wiring layer 142 are formed.

  Further, in the present embodiment, the contact formed on the interlayer insulating film 120 in the sidewall 111 and connected to the first source / drain region 104a and the second source / drain region 104b, respectively. 134 (side wall contact contact) is provided. In the present embodiment, the contact 134 passes through the sidewall 111. The contact 134 is formed so as to be in contact with the silicon nitride film 114 on the sidewall 111. As shown in FIG. 2, the contact 134 can be laid out so as to overlap the sidewall 111.

  In the present embodiment, the contact 134 is a diffusion region (first source / drain region 104a, second source / drain region 104b, and channel region) in the major axis direction (gate width direction) of the gate electrode 108. 106) may be provided to extend throughout. In another example, a plurality of contacts 134 may be provided on each side of the contact 132 along the outer edge of the sidewall 111.

  In the semiconductor device 100 configured as described above, the first source / drain region 104a and the second source / drain region 104b are grounded via the source / drain wiring layer 140 and the contact 130, respectively. A predetermined voltage Vg is applied to the gate electrode 108 through the wiring layer 142 and the contact 132. As a result, the gate insulating film 107 is broken, and a filament 150 is formed in the gate insulating film 107. FIG. 1B shows this state.

  As a result, the gate electrode 108 is electrically connected to the channel region 106 through the filament 150. However, as described above, the filament 150 functions as a drain, and a parasitic transistor is formed between the first source / drain region 104a and the second source / drain region 104b. Become. Therefore, hot carriers (hot electrons) are generated in the parasitic transistor, and the electrons 160 may be trapped in the sidewall 111 as described with reference to FIG.

  However, in the present embodiment, as shown in FIG. 1B, the contact 134 is provided so as to be in contact with the sidewall 111, particularly the silicon nitride film 114, and the contact 134 further includes the first source / drain region 104a and the first source / drain region 104a. It is connected to the second source / drain region 104b. Therefore, electrons 160 that are likely to be trapped in the sidewall 111 can escape from the first source / drain region 104a and the second source / drain region 104b through the contact 134.

  Thus, when a voltage is applied to the gate electrode 108, the voltage is applied to the first source / drain region 104a and the second source / drain region 104b, the parasitic transistor is turned on, and the gate electrode 108 and the channel region are turned on. The electrical connection state with 106 is kept good. Thereby, the current after the breakdown of the gate insulating film 107 can be flowed stably, and the reliability can be improved. That is, it is possible to satisfactorily read the program state for the antifuse element. FIG. 7 is a schematic diagram showing an effect of the semiconductor device 100 according to the present embodiment. In this embodiment, by providing the contact 134, variation in the current value of the current flowing through the antifuse element after the gate insulating film 107 is broken can be greatly reduced, and the program state of the antifuse element can be improved. Can be read.

  In addition, the antifuse element in the present embodiment can be manufactured without an additional process simultaneously with the manufacture of the CMOS in the basic CMOS manufacturing process. The contact 134 can be formed by changing the mask pattern simultaneously with the formation of the contact 130 and the contact 132. Thereby, an antifuse element having high reliability can be formed without adding a process specific to the antifuse element manufacturing to the CMOS manufacturing process.

  Also, when considering breakdown at a lower voltage, the breakdown voltage required for breakdown is generally higher by about 0.5 to 1.5 V than that of NMOS because PMOS has a lower tunnel leakage current. (Non-Patent Document 1). Therefore, the gate insulating film can be destroyed at a low voltage if the anti-fuse element is constituted by an NMOS transistor. On the other hand, when the anti-fuse element is formed of an NMOS transistor, the above-described hot electrons are easily generated, and a problem of increasing the Vt of the parasitic transistor is likely to occur. According to the semiconductor device 100 of the present embodiment, even when an NMOS transistor is used as an antifuse element, it is possible to prevent the generated electrons from being trapped on the sidewall and to destroy the gate insulating film at a low voltage. In addition, the program state of the antifuse element can be read well.

(Second Embodiment)
FIG. 3 is a cross-sectional view illustrating an example of the structure of the semiconductor device in this embodiment. 3A shows a configuration before the gate insulating film is broken, and FIG. 3B shows a configuration after the gate insulating film is broken. FIG. 4 is a plan view showing an example of the structure of the semiconductor device in this embodiment. FIG. 3 corresponds to the bb cross-sectional view of FIG.
In the present embodiment, the semiconductor device 100 has the same configuration as that described with reference to FIGS. 1 and 2 in the first embodiment, except that the contact 136 is provided instead of the contact 134. . Here, a configuration is shown in which electrons are released from a sidewall to a wiring layer connected to a gate electrode through a contact. That is, here, the contact 136 functions as a sidewall contact contact.

  The contact 136 is formed in the sidewall 111 and is electrically connected to the gate electrode 108. Here, the contact 136 is formed so as to be in contact with the silicon nitride film 114 of the sidewall 111. As a result, after the gate insulating film 107 is broken, as shown in FIG. 3B, electrons 160 that are likely to be trapped in the sidewall 111, particularly the silicon nitride film 114, from the gate wiring layer 142 through the contact 136. I can escape. As a result, as described in the first embodiment, it is possible to satisfactorily read the program state for the antifuse element.

In addition, the antifuse element in the present embodiment can be manufactured without an additional process simultaneously with the manufacture of the CMOS in the basic CMOS manufacturing process. The contact 136 can be formed only by changing the mask pattern simultaneously with the formation of the contact 130. However, in this embodiment, the contact 136 is not connected to the first source / drain region 104a and the second source / drain region 104b via the contact 136. It is necessary to form the drain region 104a and the second source / drain region 104b so as not to contact each other. In the present embodiment, interlayer insulating film 120 can be formed of, for example, a silicon oxide film. In such a configuration, when the sidewall 111 includes the silicon nitride film 114, the silicon nitride film 114 functions as an etching stopper film when the contact hole for forming the contact 136 is formed, and the contact 136 is the first Contact with the source / drain region 104a and the second source / drain region 104b can be prevented. Thereby, an antifuse element having high reliability can be formed without adding a process specific to the antifuse element manufacturing to the CMOS manufacturing process.
Also in this embodiment, the contact 136 is formed in the diffusion region (first source / drain region 104a, second source / drain region 104b, and channel in the major axis direction (gate width direction) of the gate electrode 108. The region 106) may be provided so as to extend over the entire area 106).

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  In the above embodiment, the case where the antifuse element is constituted by an NMOS transistor has been described as an example. As described above, when the anti-fuse element is constituted by an NMOS transistor, there is a problem that electrons are trapped in the sidewall 111, and the effect of the present invention is great. However, even when the antifuse element is configured by a PMOS transistor, there is an effect that hot carriers are trapped in the sidewall. The present invention can also be applied to a case where the antifuse element is configured by a PMOS transistor.

  In the first embodiment, the contact 134 provided in contact with the sidewall 111 and the contact 130 are provided separately, and the contact 134 is not connected to the source / drain wiring layer 140. It was. However, the contact 134 may be configured to be connected to the source / drain wiring layer 140. Further, in the first source / drain region 104a and the second source / drain region 104b, the region immediately below the sidewall 111 is a so-called extension region, and the impurity ion concentration is lower than other regions. Yes. In addition, no silicide layer is formed in a region immediately below the sidewall 111. Therefore, if the contact for electrically connecting the first source / drain region 104a (or the second source / drain region 104b) and the source / drain wiring layer 140 is provided only in the extension region, the contact can be obtained. Resistance becomes high. However, if the contact is also provided in the impurity ion high concentration region (other than the extension region) of the first source / drain region 104a (or the second source / drain region 104b), the contact 130, the contact 134, Can also be formed integrally. In the case where the contact 130 and the contact 134 are formed integrally, the contact diameter can be made wider than usual.

100 semiconductor device 102 P well 104a first source / drain region 104b second source / drain region 106 channel region 107 gate insulating film 108 gate electrode 110 silicide layer 111 sidewall 112 silicon oxide film 114 silicon nitride film 115 silicon oxide film 119 Gate 120 Interlayer insulating film 130 Contact 132 Contact 134 Contact 136 Contact 140 Source / drain wiring layer 142 Gate wiring layer 160 Electron

Claims (5)

A gate composed of a gate insulating film formed on one surface of the substrate, a gate electrode, and sidewalls respectively formed on both sides of the gate electrode; and on both sides of the gate on the one surface of the substrate An anti-fuse element formed of a transistor including a first source / drain region and a second source / drain region respectively formed in
A sidewall contact contact formed in the sidewall and electrically connected to the first source / drain region and the second source / drain region, or the gate electrode;
A semiconductor device including: The semiconductor device according to claim 1,
The antifuse element is a semiconductor device composed of an NMOS transistor. The semiconductor device according to claim 1 or 2,
The side wall is constituted by a laminated structure of a silicon oxide film and a silicon nitride film, and the side wall contact contact is formed in contact with the silicon nitride film in the side wall. The semiconductor device according to claim 1,
An interlayer insulating film formed on the substrate so as to cover the gate;
A source / drain wiring layer formed on the interlayer insulating film;
A first contact and a first contact formed in the interlayer insulating film and connected to the first source / drain region and the second source / drain region, respectively, and to the source / drain wiring layer. Two contacts,
Further including
The sidewall contact is a semiconductor device formed simultaneously with the first contact and the second contact. The semiconductor device according to claim 1,
An interlayer insulating film formed on the substrate so as to cover the gate;
A gate wiring layer formed on the interlayer insulating film;
Further including
The sidewall contact contact is a semiconductor device formed so as to electrically connect the gate wiring layer and the gate electrode of the gate.

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