JP2011096153A - Compile processing device, data processing device, compile processing method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the efficiency of reuse of values by shortening the bit length of data to be kept in a memory storing an execution result when reusing the values (Memoization). <P>SOLUTION: A reuse-instruction determination unit 120 analyzes the use modes of a plurality of instruction sections in a program, and determines reuse sections in which the execution result is used again from among the instruction sections. A hash function determination unit 200 determines a section identification value generating function from candidate functions that are candidates of section identification value generating function, the generating function generating a section-identification value identifying a reuse section by a value of a bit width narrower than the bit width of the starting address of the reuse section. A machine-word program generation unit 140 generates a machine-word program embedding the section identification value generating function determined by the hash function determination unit 200. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a compile processing apparatus, and in particular, a compile processing apparatus, a data processing apparatus, and a compile processing method for identifying an instruction section in which an execution result is reused using a hash value generated by a hash function, and Regarding the program.

  Various techniques have been developed to increase the processing speed of programs. In recent years, as one of devices using the technology, an interval reuse device using a technique for reusing the execution result of an instruction interval called value reuse (memoization) has been proposed (for example, a patent) Reference 1). This section reuse device saves input values and execution results in a predetermined instruction section of a program in a cache so that the input values match when the same instruction section is executed again when it is executed again. This is a device that outputs an output value that is the execution result.

  As one of devices for speeding up retrieval of execution results in this section reuse device, a device for generating a cache index used as an index at the time of retrieval using a hash function has been proposed (for example, non-reuse) (See Patent Document 1). The interval reuse device that generates a cache index using this hash function calculates a hash value that is a cache index by using two input values of the Ackerman function as inputs of the hash function. Then, the section reuse device stores the execution result of the Ackermann function based on the generated cache index, and searches the execution result using the generated cache index as an index when searching the execution result.

JP 2004-258905 A (FIG. 1)

Stephen E. Richardson, "Caching Function Results: Faster Arithmetic by Avoiding Unnecessary Computation", Sun Microsystems Laboratories, Inc., 1992

  In the above prior art, it is possible to reduce the time required to search for an execution result by searching for an execution result using a cache index generated from two input values of the Ackermann function. However, since such a section reuse device uses a single hash function that matches the size of the memory that stores the execution results, the hash function should be selected according to the number of cache indexes required. The problem of not being able to occur.

  In such a section reuse device, for example, the search may take a long time because the bit length of the hash value (cache index) is unnecessarily long with respect to the number of execution results to be held. If this search takes time, in such a section reuse device, the efficiency of value reuse is reduced.

  Therefore, the present invention has been made in view of such a situation, and when performing value reuse (memoization), by shortening the bit length of data to be held in a memory for storing execution results, The purpose is to improve the efficiency of value reuse.

  The present invention has been made in order to solve the above-mentioned problems, and a first aspect of the present invention is to re-use the execution result again among the instruction sections by analyzing the usage of a plurality of instruction sections in the program. A candidate for a section identification value generation function for generating a section identification value for identifying the reuse section by a value of a bit width narrower than the bit width of the start address of the reuse section By using a candidate function, a candidate value generation unit that associates a candidate value that is a candidate for the section identification value with the candidate function and generates the candidate value from the start address, and the candidate value generated by the candidate value generation unit A candidate value table held as a candidate value list for each associated candidate function, and the candidate value list in which the candidate values are all different from each other are extracted, and the extracted candidate values A section identification value generation function output unit that outputs the associated candidate function of the candidate value list selected based on the bit width of the candidate value in the list as the section identification value generation function, and the section identification value generation function Compile processing apparatus, machine method thereof, and program for causing a computer to execute the method, and a machine language program generation unit that generates a machine language program embedded with a machine language program based on the analyzed program and the section identification value generation function It is. As a result, the section identification value generation function selected from the candidate functions is embedded in the program.

  In the first aspect, the candidate function is a hash function, and the section identification value generation function output unit is selected based on the bit width of the candidate value in the extracted candidate value list. The hash function associated with the candidate value list may be output as the section identification value generation function. This brings about the effect that the hash function is embedded in the program. In this case, the hash function is a hash function in which a value in a predetermined number of bits from the least significant bit of the start address is used as the candidate value, and the section identification value generation function output unit outputs the extracted candidate The hash function associated with the candidate value list selected based on the bit width of the candidate value in the value list may be output as the section identification value generation function. As a result, the program is embedded with a hash function for calculating a value in a predetermined number of bits from the least significant bit as a hash value.

  Further, in the first aspect, the section identification value generation function output unit outputs the associated candidate function of the candidate value list having the narrowest bit width in the extracted candidate value list as the section. You may make it output as an identification value generation function. As a result, the candidate function that generates the candidate value having the narrowest bit width among the candidate functions that generate candidate values that are all different from each other is output as the section identification value generation function.

  In the first aspect, the section identification value generation function output unit outputs an identifier for identifying the section identification value generation function as the section identification value generation function, and the machine language program generation unit includes: A machine language program in which the identifier is embedded may be generated. As a result, the program in which the identifier for identifying the section identification value generation function is embedded is generated.

  The second aspect of the present invention includes an execution unit that executes a plurality of instruction sections and outputs execution results, and a bit width of a start address of a reuse section in which execution results are reused among the instruction sections. A history memory for holding a section identification value for identifying the reuse section with a narrow bit width value, an input value of the reuse section, and an execution result of the reuse section as an execution history, the section identification value, and The data processing apparatus includes a history search unit that searches the history memory for the execution history based on the input value, and outputs the execution result when the execution history is searched. As a result, the section identification value, the input value, and the execution result are stored in the history memory as an execution history.

  Further, in the second aspect, when the execution unit outputs the start address when the reuse section is executed, the section identification value generation function for generating the section identification value is used to generate the section identification value. A section identification value generation unit configured to generate the section identification value from a start address; the execution unit supplies the section identification value generation function to the section identification value generation unit; and the history memory includes the section identification value The section identification value, the input value, and the execution result generated by the value generation section are stored as the execution history, and the history search section is configured to store the section identification value and the input value from the history memory based on the section identification value and the input value. The execution history may be searched, and when the execution history is searched, the execution result may be output. As a result, the section identification value generated from the start address by the section identification value generation unit, the input value supplied from the execution unit, and the execution result are retained in the history memory as an execution history. In this case, the execution unit supplies the section identification value generation function to the section identification value generation unit, and the section identification value generation unit performs the start address when the execution unit executes the reuse section. Is output, the section identification value may be generated from the start address using the section identification value generation function supplied from the execution unit. Thus, the section identification value is generated from the start address using the section identification value generation function supplied from the execution unit. In this case, the execution unit supplies an identifier for identifying the section identification value generation function to the section identification value generation unit, and the section identification value generation unit is a candidate function that is a candidate for the section identification value generation function. The section identification value generation function is selected based on the identifier, and when the execution unit outputs the start address when the reuse section is executed, the section identification value generation function is used to select the section identification value generation function. The section identification value may be generated from the start address. Thus, the section identification value generation function is selected from the candidate functions based on the identification value supplied from the execution unit, and the section identification value is generated from the start address using the selected section identification value.

  In the second aspect, the execution unit supplies the section identification value to the history memory when the reuse section is executed by an instruction including the section identification value. The section identification value, the input value, and the execution result are held as the execution history, and the history search unit searches the execution history from the history memory based on the section identification value and the input value, When the execution history is searched, the execution result may be output. As a result, the section identification value, the input value, and the execution result supplied from the execution unit are stored in the history memory as an execution history.

  According to a third aspect of the present invention, there is provided an analysis unit for analyzing a usage state of a plurality of instruction sections in a program and determining a reuse section in which an execution result is reused among the instruction sections, and the reuse section. By using a candidate function that is a candidate of a section identification value generation function for generating a section identification value for identifying the reuse section by a value having a bit width narrower than the bit width of the start address of A candidate value generation unit that generates a candidate value associated with the candidate function, a candidate value table that holds the candidate value generated by the candidate value generation unit as a candidate value list for each of the associated candidate functions, and The candidate value list in which the candidate values are all different from each other is extracted, and the candidate value list selected based on the bit width of the candidate value from the extracted candidate value list A section identification value output section for outputting the candidate value as the section identification value, a command conversion section for converting a command for calling the reuse section into a section identification value-added instruction including the section identification value, and the reuse section Is a compile processing device including a machine language program generation unit that generates a machine language program called by the section identification value-added instruction based on a source program including the section identification value-added instruction. This brings about the effect | action of producing | generating the program in which the instruction with a section identification value is included.

  In the third aspect, the candidate value generation unit generates the candidate value by using the candidate function having an input value that is a number assigned according to a predetermined order of the start address. Also good. This brings about the effect that the candidate value is generated from the number assigned according to the predetermined order of the start address.

  In the third aspect, the candidate value generation unit may generate the candidate value by using the candidate function having the start address as an input value. This brings about the effect | action that a candidate value is produced | generated from a start address.

  According to a fourth aspect of the present invention, there is provided an execution unit that executes a plurality of instruction sections and outputs an execution result, and the reuse section is defined by a bit width value smaller than a bit width of a start address of the reuse section. A candidate that is generated from the start address by associating a candidate value that is a candidate for the section identification value with the candidate function by using a candidate function that is a candidate for the section identification value generation function for generating the section identification value to be identified A candidate value table that holds the candidate value generated by the value generation unit, the candidate value generation unit as a candidate value list for each of the associated candidate functions, and the candidate value list in which the candidate values are all different from each other In the extracted candidate value list, the associated candidate function of the candidate value list selected based on the bit width of the candidate value is defined as the section identification value generation function. When the start address is output when the section identification value generation function output unit and the execution unit execute the reuse section, the section identification value generation function is used to identify the section from the start address. A section identification value generation unit that generates a value, a history memory that holds the section identification value, the input value, and the execution result of the reuse section as an execution history, and the history based on the section identification value and the input value The data processing apparatus includes a history search unit that searches the execution history from a memory and outputs the execution result when the execution history is searched. Accordingly, the section identification value is generated from the start address using the section identification value generation function output from the section identification value generation function output unit, and the generated section identification value, the input value supplied from the execution unit, and the execution The result is stored in the history memory as an execution history.

  Therefore, the present invention has been made in view of such a situation, and when performing value reuse (memoization), by shortening the bit length of data to be held in a memory for storing execution results, The purpose is to improve the efficiency of value reuse.

It is a block diagram which shows the structural example of the compile processing apparatus 100 in the 1st Embodiment of this invention. It is a conceptual diagram which shows an example of the program which the reuse command discrimination | determination part 120 in the 1st Embodiment of this invention analyzes. It is a block diagram which shows the structural example of the hash function determination part 200 in the 1st Embodiment of this invention. It is a conceptual diagram which shows an example of the hash value which the candidate hash value generation part 230 in the 1st Embodiment of this invention produces | generates. It is a conceptual diagram which shows an example of the hash value hold | maintained at the hash value table 240 in the 1st Embodiment of this invention. It is a conceptual diagram which shows an example of the hash function designation | designated instruction in the 1st Embodiment of this invention. It is a flowchart which shows the process sequence of the compile process by the compile processing apparatus 100 in the 1st Embodiment of this invention. It is a flowchart which shows the first half of the example of a process sequence of the hash function determination process (step S920) by the hash function determination part 200 in the 1st Embodiment of this invention. It is a flowchart which shows the second half of the process sequence example of the hash function determination process (step S920) by the hash function determination part 200 in the 1st Embodiment of this invention. It is a block diagram which shows the structural example of the data processor 300 in the 2nd Embodiment of this invention. It is a block diagram which shows the structural example of the processor core 400, the hash conversion part 500, and the log | history management part 600 in the 2nd Embodiment of this invention. It is a conceptual diagram which shows an example of the data structure of the history memory 630 in the 2nd Embodiment of this invention. It is a flowchart which shows the example of a process sequence of the command processing method by the data processor 300 in the 2nd Embodiment of this invention. It is a block diagram which shows the structural example of the compile processing apparatus 100 in the 3rd Embodiment of this invention. It is a block diagram which shows the structural example of the hash value determination part 700 in the 3rd Embodiment of this invention. It is a conceptual diagram which shows an example of the hash value hold | maintained at the hash value table 740 in the 3rd Embodiment of this invention. FIG. 20 is a conceptual diagram illustrating an example of a function call instruction and a function reuse instruction according to the third embodiment of the present invention. It is a flowchart which shows the process sequence of the compilation process by the compilation processing apparatus 100 in the 3rd Embodiment of this invention. It is a flowchart which shows the first half of the process sequence example of the hash value determination process (step S960) by the hash value determination part 700 in the 3rd Embodiment of this invention. It is a flowchart which shows the second half of the process sequence example of the hash value determination process (step S960) by the hash value determination part 700 in the 3rd Embodiment of this invention. It is a block diagram which shows the structural example of the data processor 300 in the 4th Embodiment of this invention. It is a block diagram which shows the structural example of the processor core 400 and the log | history management part 600 in the 4th Embodiment of this invention. It is a flowchart which shows the example of a process sequence of the command processing method by the data processor 300 in the 4th Embodiment of this invention. It is a block diagram which shows the structural example of the data processor 300 in the 5th Embodiment of this invention. It is a block diagram which shows the structural example of the processor core 400, the hash transformation part 500, and the log | history management part 600 in the 5th Embodiment of this invention. It is a flowchart which shows the example of a process sequence of the command processing method by the data processor 300 in the 5th Embodiment of this invention. It is a flowchart which shows the example of a process sequence of the program execution process (step S990) in the 5th Embodiment of this invention.

Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First embodiment (compilation control: example of selecting a hash function and embedding it in a program)
2. Second embodiment (data processing control: an example of processing a program in which a hash function is embedded)
3. Third embodiment (compilation control: example of selecting a hash value and generating a reuse instruction with a hash value)
4). Fourth embodiment (data processing control: example of processing a reuse instruction with hash value)
5. Fifth embodiment (data processing control: an example in which a hash value is generated from the start address of a reuse section of an already generated object program)

<1. First Embodiment>
[Configuration example of the compile processing apparatus 100 according to the first embodiment of the present invention]
FIG. 1 is a block diagram showing a configuration example of a compile processing apparatus 100 according to the first embodiment of the present invention. The compile processing apparatus 100 includes a source program storage unit 110, a reuse instruction determination unit 120, a hash function determination unit 200, a machine language program generation unit 140, and an object program storage unit 150.

  The source program storage unit 110 stores a source program to be compiled. This source program is, for example, a source program including a reuse section in which the execution result is reused. The source program storage unit 110 supplies the stored source program to the reuse instruction determination unit 120.

  The reuse instruction determination unit 120 analyzes the source program read from the source program storage unit 110 and generates a program including the reuse instruction. Here, the reuse instruction is for reusing the execution result when the reuse section is called by distinguishing the reuse section and the non-reuse section based on the degree of reuse. This is an instruction for causing the data processing apparatus to perform processing.

  The reuse command determination unit 120 includes a reuse candidate section extraction unit 121, a reuse candidate section analysis unit 122, a reuse degree generation unit 123, and a reuse command conversion unit 124. The reuse instruction determination unit 120 supplies a program including the generated reuse instruction to the hash function determination unit 200. The reuse command determination unit 120 is an example of an analysis unit described in the claims.

  The reuse candidate section extraction unit 121 extracts, from the program, a reuse candidate section that is a candidate for a reuse section that reuses an execution result among a plurality of command sections. Here, it is assumed that the instruction section processed by the compile processing apparatus 100 is a function or a loop. The reuse candidate section extraction unit 121 extracts command sections that may be called a plurality of times, such as functions and loops, as reuse candidate sections.

  In addition, the reuse candidate section extraction unit 121 excludes from the reuse candidate section functions that have no possibility of reusing execution results, such as functions that have different input results even if the input values are the same. Here, the input value is a value required for execution of the function or loop, and is a value composed of arguments. For example, in the case of a function having three variables as arguments, The value of the variable. For example, the reuse candidate section extraction unit 121 excludes a function including a system call or a random number generation function from the reuse candidate section. This reuse candidate section extraction unit 121 supplies the extracted reuse candidate section identification information to the reuse candidate section analysis unit 122 together with the program.

  The reuse candidate section analysis unit 122 analyzes the usage mode related to the reuse candidate section extracted by the reuse candidate section extraction unit 121. The reuse candidate section analysis unit 122 analyzes, for example, the contents relating to the arguments that are the input values of the function and the loop and the contents relating to the number of calls of the function and the loop as usage modes. The reuse candidate section is an example of an instruction section described in the claims.

  Based on the analysis result supplied from the reuse candidate section analysis unit 122, the reuse degree generation unit 123 generates a reuse degree indicating the degree to which the execution result of the reuse candidate section is reused. For example, the reuse degree generation unit 123 generates a reuse degree according to a combination of input values of reuse candidate sections. In this case, since the degree of reuse increases as the number of combinations of input values in the reuse candidate section decreases, the degree of reuse with the number of combinations of input values as the denominator is generated. The reuse level generation unit 123 supplies the generated reuse level together with the identification information of the reuse candidate section and the program to the reuse command conversion unit 124.

  The reuse instruction conversion unit 124 converts a call instruction of a reuse candidate section for reusing an execution result into a reuse instruction based on the degree of reuse supplied from the reuse degree generation unit 123. For example, when a reuse candidate section for reusing an execution result is a function, an assembly language “call” instruction that is an instruction for calling a function is converted into a “memocall” instruction newly defined as a reuse instruction. . The reuse instruction conversion unit 124 supplies a program including the converted instruction to the hash function determination unit 200.

  The hash function determination unit 200 determines a hash function that generates a hash value from a start address for identifying a reuse section. For example, the hash function determination unit 200 generates a hash value based on the start address of the reuse section for each hash function using a plurality of hash functions using the start address of the reuse section as a function input value. Here, the function input value is a value that becomes an input of the hash function. Then, the hash function determination unit 200 determines and outputs a hash function that generates a hash value having the narrowest bit width among the plurality of hash functions. That is, the hash function determination unit 200 determines and outputs a hash function that generates a hash value for identifying a reuse section based on a bit width value narrower than the bit width of the start address of the reuse section. The hash function determination unit 200 supplies the determined hash function together with the program to the machine language program generation unit 140.

  The machine language program generation unit 140 generates an object program that is a machine language program based on the program supplied from the hash function determination unit 200. For example, the machine language program generation unit 140 generates an object program in which the hash function determined by the hash function determination unit 200 is embedded. In addition, the machine language program generation unit 140 adds a hash function designation command for causing the data processing apparatus that executes the object program to recognize the hash function embedded in the object program. The machine language program generation unit 140 supplies the generated object program to the object program storage unit 150.

  The object program storage unit 150 stores the object program supplied from the machine language program generation unit 140.

  In this way, the compile processing apparatus 100 first distinguishes a reuse section from a non-reuse section by converting a function call instruction into a reuse instruction according to the degree to which the function execution result is reused. It can be so. Then, the compile processing apparatus 100 can generate a program in which the determined hash function is embedded by determining a hash function for generating a hash value for identifying a reuse section.

  Here, the compile processing apparatus 100 has been described with respect to an example in which a function is a reuse target. However, a loop can also be a reuse target.

  Here, for the sake of convenience, the example in which the reuse candidate section analysis unit 122 analyzes the usage mode of the reuse candidate section for each function has been described, but for each function call instruction to analyze the usage mode in more detail. It may be analyzed. Also, the example of generating the reuse level for each function has been described for the reuse level generation unit 123, but it may be generated for each function call instruction in order to analyze in more detail. In this case, the reuse instruction conversion unit 124 converts the call instruction into a reuse instruction for each function call instruction based on a different reuse degree for each function call instruction even if the function is the same.

  In addition, here, an example in which the degree of reuse is converted into a reuse instruction has been described, but the present invention is not limited to this. For example, all instructions that call functions may be reused.

[Program Example Analyzed by Reuse Instruction Discriminating Unit 120 in the First Embodiment of the Present Invention]
FIG. 2 is a conceptual diagram showing an example of a program analyzed by the reuse instruction determination unit 120 according to the first embodiment of the present invention.

  Here, an example of a combination of input values in a reuse candidate section and a reuse degree generated by the reuse degree generation unit 123 based on the combination of input values will be described. Here, it is assumed that the following C language program is analyzed in the reuse candidate section analysis unit 122.

First, the reuse candidate section analysis unit 122 analyzes combinations of input values of four functions (funcA to D) in the program of FIG. The function (funcA) to char type arguments one variable, for char type is 16-bit binary character data, a combination of input values are up to ^{2 to 16} and analysis. For a function (funcB) having one variable of char type and one variable of bool (Boolean) type as an argument, the bool type is binary numeric data of 1 bit, and therefore “2 ¹⁶ × 2 = 2 ¹⁷ the combination of input values by "the maximum 2 ¹⁷ and analysis.

Further, with respect to a function (funcC) having one variable of a Boolean type as an argument, the maximum number of combinations of input values is analyzed. For int (integer The) type one variable function with arguments (funcD), int type for a 32-bit binary numerical data, a combination of input values are up to ^{2 to 32} and analysis.

Then, the reuse level generation unit 123 generates the reuse level with the number of combinations of input values as the denominator based on the analysis result of the four functions (funcA to D), thereby reusing the following relationships: Generate degrees.

  As described above, the function (funcC) having a single variable of the bool type has the highest degree of reuse, and the function having the single variable of the char type (funcA) has the second highest degree of reuse. To be high. A function (funcB) that has one variable of char type and one variable of bool type as an argument (funcB) has the third highest degree of reuse, and a function (funcD) that uses one variable of int type as an argument Usage is the lowest.

In other words, the reuse candidate section analysis unit 122 analyzes the reuse candidate section, and the reuse degree generation unit 123 re-ranks the ranking when the reuse section is generated based on the reuse degree generated based on the analysis result. This is done for the use candidate section. Then, the reuse instruction conversion unit 124 determines the reuse sections in order from the reuse candidate section having the highest degree of reuse.
Thereby, the compile processing apparatus 100 can generate an object program in which a reuse candidate section having a high degree of reuse is used as a reuse section.

[Configuration Example of Hash Function Determination Unit 200 in the First Embodiment of the Present Invention]
FIG. 3 is a block diagram illustrating a configuration example of the hash function determination unit 200 according to the first embodiment of the present invention. The hash function determination unit 200 includes a start address acquisition unit 210, a candidate hash function holding unit 220, a candidate hash value generation unit 230, a hash value table 240, and a hash function output unit 250.

  The start address acquisition unit 210 acquires the start address of the reuse section from the program including the reuse command from the reuse command conversion unit 124. The start address acquisition unit 210 holds the acquired start address as a start address list. The start address acquisition unit 210 supplies the acquired start address to the candidate hash value generation unit 230.

  The candidate hash function holding unit 220 holds a plurality of hash functions for converting the start address into a hash value. That is, the candidate hash function holding unit 220 holds a hash function that is a hash function candidate determined by the hash function determining unit 200. The candidate hash function holding unit 220 holds a hash function predetermined as a hash function candidate determined by the hash function determining unit 200.

  For example, when the ten hash functions are held, the candidate hash function holding unit 220 supplies the ten hash functions to the candidate hash value generation unit 230. For example, when one hash function is determined in the hash function output unit 250, the candidate hash function holding unit 220 supplies the hash function to the hash function output unit 250. Note that the hash function supplied from the candidate hash function holding unit 220 is an example of a candidate function described in the claims.

  The candidate hash value generation unit 230 uses the start address supplied from the start address acquisition unit 210 as a function input value, and generates the hash value using the function input value as an input of the hash function supplied from the candidate hash function holding unit 220. Is. That is, the candidate hash value generation unit 230 uses a hash function that is a hash function candidate determined by the hash function determination unit 200 to generate a hash value that is a hash value candidate for identifying a reuse section as a start address. Generate from. In addition, when generating the hash value, the candidate hash value generation unit 230 associates the hash function that generated the hash value with the hash value so that it can be identified from which hash function.

  For example, when 10 start addresses are held in the start address acquisition unit 210 and 10 hash functions are held in the candidate hash function holding unit 220, the candidate hash value generation unit 230 The combination “10 × 10 = 100” hash values are generated.

  The candidate hash value generation unit 230 supplies the generated hash value to the hash value table 240. The candidate hash value generation unit 230 is an example of a candidate value generation unit described in the claims. Further, the hash value generated by the candidate hash value generation unit 230 is an example of the candidate value described in the claims.

  The hash value table 240 holds the hash value supplied from the candidate hash value generation unit 230. The hash value table 240 holds a hash value as a hash value list for each hash function that generates the hash value. Further, the hash value table 240 supplies the held hash value list to the hash function output unit 250. The hash value table 240 is an example of a candidate value table described in the claims. The hash value list is an example of a candidate value list described in the claims.

  The hash function output unit 250 extracts hash value lists whose hash values are all different from each other, and outputs a hash function associated with the hash value list in which the bit width of the hash value is the narrowest among the extracted hash value lists. Is. The hash function output unit 250 includes a unique hash value list determination unit 251 and a definite hash function selection unit 252. The hash function output unit 250 is an example of the section identification value generation function output unit described in the claims. The hash function output by the hash function output unit 250 is an example of a section identification value generation function described in the claims.

  The unique hash value list discriminating unit 251 discriminates hash value lists whose hash values are all different from each other among the hash value lists held in the hash value table 240. The unique hash value list discriminating unit 251 selects, for example, three hash value lists when there are three hash values that are all different from each other among the ten hash value lists held in the hash value table 240. Determine. The unique hash value list determination unit 251 supplies the determined hash value list to the determined hash function selection unit 252.

  The confirmed hash function selection unit 252 outputs a hash function associated with a hash value list in which the bit width of the hash value is the narrowest among the hash value lists supplied from the unique hash value list determination unit 251. That is, the determined hash function selection unit 252 determines one hash function from among the plurality of hash functions held by the candidate hash function holding unit 220, and outputs the decided hash function. The deterministic hash function selection unit 252 detects one hash value list having the narrowest bit width of hash values among hash value lists whose hash values supplied from the unique hash value list determination unit 251 are all different from each other. Then, the determined hash function selection unit 252 acquires a hash function associated with the detected hash value list from the candidate hash function holding unit 220 and supplies the acquired hash function to the machine language program generation unit 140.

  As described above, in the first embodiment of the present invention, by providing the hash function determination unit 200, a hash that generates hash values having the narrowest bit width, which are all different hash values among a plurality of hash functions, is provided. Functions can be embedded in programs.

  Here, although the example in which the candidate hash function holding unit 220 supplies all the stored hash functions to the candidate hash value generating unit 230 has been described, the present invention is not limited to this. For example, by allowing the candidate hash function holding unit 220 to be controlled from the outside, the hash function supplied to the candidate hash value generating unit 230 may be designated from the outside according to the program.

  Although the example in which the deterministic hash function selection unit 252 supplies the hash function to the machine language program generation unit 140 has been described here, the present invention is not limited to this. For example, the deterministic hash function selection unit 252 may supply an identifier indicating the hash function instead of the hash function. In this example, the machine language program generation unit 140 generates an object program in which the identifier supplied from the fixed hash function selection unit 252 is embedded. As a result, the object program can be shortened as compared with the method of embedding the hash function in the object program. Therefore, when executing a program that frequently exchanges the hash function, the execution process of the program can be accelerated. The identifier embedded in the object program instead of the hash function is an example of the identifier described in the claims.

[One Example of Hash Value Generated by Candidate Hash Value Generation Unit 230 in the First Embodiment of the Present Invention]
FIG. 4 is a conceptual diagram illustrating an example of a hash value generated by the candidate hash value generation unit 230 according to the first embodiment of this invention. Here, the bit width of the start address is 64 bits. Further, here, the left end indicates the most significant bit (MSB) and the right end indicates the least significant bit (LSB: Least Significant Bit).

Here, as an example, a plurality of hash functions held by the candidate hash function holding unit 220 is assumed to be a function that calculates a value in a predetermined number of bits from the least significant bit of the start address of the reuse interval. . An example of this hash function is shown in Equation 1 below.

Here, h is a hash value generated by the candidate hash value generation unit 230. Further, a is a function input value of the hash function, and here is a start address supplied from the hash value table 240 to the candidate hash value generation unit 230. & Is an AND operation in bit units. m _b is a mask bit in which the numerical value (m) is expressed by a binary number (b). Further, Expression 2 shown below Expression 1 is an example of an expression for calculating m of Expression 1. I in Expression 2 is a value for designating the bit width of h (hash value) calculated in Expression 1.

  FIG. 4A shows a start address 261 that is an example of the start address supplied from the hash value table 240. The start address 261 is a bit string composed of 64 bits from the 0th to the 63rd bits from the LSB side. This start address 261 is used as a function input value of the hash function in the candidate hash value generation unit 230.

  FIG. 4B shows hash values 262 to 266 which are examples of hash values generated using the start address shown in FIG. 4A as a function input value.

The hash value 262 is h (hash value) calculated from the start address 261 using Expression 1 in which i (bit width) of Expression 2 is specified as “1”. When i (bit width) in Expression 2 is “1”, m is “1”. That is, Equation 1 is a hash function shown in Equation 3 below.

  With the hash function shown in Equation 3, a 1-bit hash value 262 whose 0th value is “0” is calculated based on the 0th value (0) of the start address 261.

The hash value 263 is h (hash value) calculated from the start address 261 using Expression 1 in which i (bit width) of Expression 2 is designated as “2”. If i (bit width) in Expression 2 is “2”, m is “3”. That is, Equation 1 is a hash function shown in Equation 4 below.

  By the hash function shown in Expression 4, the hash value 263 of the 2-bit bit string in which the values of the 0th and 1st are “0 and 1” are changed to the 0th and 1st values (0 and 1) of the start address 261. Calculated based on

The hash value 264 is h (hash value) calculated from the start address 261 using Expression 1 in which i (bit width) of Expression 2 is specified as “3”. If i (bit width) in Expression 2 is “3”, m is “7”. That is, Equation 1 is a hash function shown in Equation 5 below.

  By using the hash function shown in Equation 5, the hash value 264 of the 3-bit bit string in which the values from 0 to 2 are “0, 1 and 0” is the values from 0 to 2 of the start address 261 (0, 1 And 0).

The hash value 265 is h (hash value) calculated from the start address 261 using Expression 1 in which i (bit width) of Expression 2 is specified as “4”. When i (bit width) in Expression 2 is “4”, m is “15”. That is, Equation 1 is a hash function shown in Equation 6 below.

  According to the hash function shown in Expression 6, the hash value 265 of the 4-bit bit string whose values from 0 to 3 are “0, 1, 0, and 1” is the values from 0 to 3 of the start address 261 (0 1, 0 and 1).

The hash value 266 is h (hash value) calculated from the start address 261 using Expression 1 in which i (bit width) of Expression 2 is designated as “5”. If i (bit width) in Equation 2 is “5”, m is “31”. That is, Equation 1 is a hash function shown in Equation 7 below.

  According to the hash function shown in Expression 7, the hash value 266 of the 5-bit bit string in which the values of 0 to 4 are “0, 1, 0, 1 and 1” is the values of 0 to 4 of the start address 261 Calculated based on (0, 1, 0, 1 and 1).

  Thus, in the first embodiment of the present invention, by providing the candidate hash value generation unit 230, a plurality of hash values can be generated using a plurality of hash functions.

  Here, the hash functions shown in Equations 1 to 7 have been described as an example, but the present invention is not limited to this. For example, a hash function for calculating an exclusive OR (EOR) of a predetermined number of bits from the most significant start address and a predetermined number of bits from the least significant address may be considered.

[An example of the hash value held in the hash value table 240 in the first embodiment of the present invention]
FIG. 5 is a conceptual diagram illustrating an example of hash values held in the hash value table 240 according to the first embodiment of this invention. Here, it is assumed that a hash value is generated using the hash functions of Expressions 3 to 7 described in FIG. Here, the reuse interval in the program is assumed to be eight functions (funcA to funcH).

  The start address list 271 shows the list name of the start address that is the basis of the hash value registered in the hash value table 240. In the start address list 271, a value related to funcA is shown in a row 282, a value related to funcB is shown in a row 283, and a value related to funcC is shown in a row 284. In addition, row 285 shows a value for funcD, row 286 shows a value for funcE, row 287 shows a value for funcF, row 288 shows funcG, and row 289 shows funcH. Indicates that the value is shown.

  The hash value list 272 shows a list of hash values calculated using Expression 7, which is a hash function in which i (bit width) of Expression 1 is “5”. In the row 281 of the hash value list 272, “i = 5” is used, which indicates that Expression 7 which is a hash function in which i (bit width) of Expression 1 is “5” is used. In the rows 282 to 289 of the hash value list 272, hash values calculated using the start addresses of eight functions (funcA to funcH) as the function input values of Expression 7 are shown. That is, in the rows 282 to 289 of the hash value list 272, values of 5 bits from the least significant bit of the start addresses of the eight functions (funcA to funcH) are shown, respectively. The hash values shown in the rows 282 to 289 of the hash value list 272 are associated with Expression 7 and stored as a list in the hash value table 240.

  The hash value list 273 shows a list of hash values calculated using Expression 6, which is a hash function with i (bit width) of Expression 1 set to “4”. In the row 281 of the hash value list 273, “i = 4” is used, which indicates that the hash function “Expression 6” in which “i” (bit width) of Expression 1 is “4” is used. Rows 282 to 289 of the hash value list 273 show hash values calculated using the start addresses of eight functions (funcA to funcH) as the function input values of Equation 6. That is, the values of 4 bits from the least significant bit of the start address of the eight functions (funcA to funcH) are shown in rows 282 to 289 of the hash value list 273, respectively. The hash values shown in the rows 282 to 289 of the hash value list 273 are associated with Equation 6 and stored as a list in the hash value table 240.

  The hash value list 274 shows a list of hash values calculated using Expression 5, which is a hash function where i (bit width) of Expression 1 is “3”. In the row 281 of the hash value list 274, “i = 3” is shown, which indicates that Expression 5 which is a hash function where i (bit width) of Expression 1 is “3” is used. Rows 282 to 289 of the hash value list 274 show hash values calculated using the start addresses of the eight functions (funcA to funcH) as the function input values of Equation 5. That is, in the rows 282 to 289 of the hash value list 274, values of 3 bits from the least significant bit of the start address of the eight functions (funcA to funcH) are shown, respectively. The hash values shown in rows 282 to 289 of the hash value list 274 are stored in the hash value table 240 as a list in association with Expression 5.

  The hash value list 275 shows a list of hash values calculated using Expression 4, which is a hash function with i (bit width) of Expression 1 set to “2”. In the row 281 of the hash value list 275, “i = 2” indicating that Expression 4 which is a hash function in which i (bit width) of Expression 1 is “2” is used is shown. Rows 282 to 289 of the hash value list 275 show hash values calculated using the start addresses of the eight functions (funcA to funcH) as the function input values of Expression 4. That is, in the rows 282 to 289 of the hash value list 275, 2-bit values from the least significant bit of the start address of the eight functions (funcA to funcH) are shown, respectively. The hash values shown in rows 282 to 289 of the hash value list 275 are associated with Equation 4 and stored as a list in the hash value table 240.

  The hash value list 276 shows a list of hash values calculated using Expression 3, which is a hash function with i (bit width) of Expression 1 set to “1”. In the row 281 of the hash value list 276, “i = 1” is shown, which indicates that Expression 3 which is a hash function in which i (bit width) of Expression 1 is “1” is used. Rows 282 to 289 of the hash value list 276 show hash values calculated using the start addresses of the eight functions (funcA to funcH) as the function input values of Equation 3. That is, the values of the least significant bits of the start addresses of the eight functions (funcA to funcH) are shown in rows 282 to 289 of the hash value list 276, respectively. The hash values shown in rows 282 to 289 of this hash value list 276 are associated with Equation 3 and held as a list in the hash value table 240.

  Thus, in the first embodiment of the present invention, by using the hash value table 240, hash values can be stored as a list in association with the generated hash function.

  Next, the hash value list determined by the unique hash value list determination unit 251 and the hash function selected by the deterministic hash function selection unit 252 will be described with reference to FIG.

  First, the unique hash value list discriminating unit 251 discriminates hash value lists whose hash values are all different from each other, and a hash value list whose discriminated hash values are all different from each other is supplied to the deterministic hash function selecting unit 252. At this time, since the hash values of funcA, funcC, funcE, and funcG overlap with “0” and the hash values of the other four functions overlap with “1”, the hash value list 276 has a fixed hash. It is not supplied to the function selection unit 252.

  In addition, since the hash values of funcA, funcC, and funcE are duplicated by “10” and the hash values of funcB, funcF, and funcH are duplicated by “11”, the hash value list 275 has a definite hash function selection unit. 252 is not supplied. Furthermore, since the hash values of funcA and funcE overlap with “110” and the hash values of funcF and funcH overlap with “011”, the hash value list 274 is not supplied to the confirmed hash function selection unit 252. .

  As a result, hash value lists 272 and 273 whose hash values are all determined to be different from each other are supplied to the determined hash function selection unit 252 by the unique hash value list determination unit 251.

  When the hash value list is supplied from the unique hash value list determination unit 251, the deterministic hash function selection unit 252 hashes the hash values having the narrowest bit width among the hash value lists supplied from the unique hash value list determination unit 251. Detect a list of values.

  As a result, the hash value list 273 is detected as the hash value list having the narrowest bit width among the hash value list 273 of the 4-bit hash value and the hash value list 272 of the 5-bit hash value. Then, the deterministic hash function selection unit 252 acquires the hash function expression 6 associated with the hash value list 273 from the candidate hash function holding unit 220, and the acquired expression 6 as the hash function determined by the hash function determination unit 200 Is output.

As described above, in the first embodiment of the present invention, by providing the unique hash value list determination unit 251, the hash value list having all different hash values is determined from the hash value list held in the hash value table 240. can do. In addition, by providing the deterministic hash function selection unit 252, the hash function associated with the hash value list having the narrowest bit value among the hash value lists determined by the unique hash value list determination unit 251 is determined. Can do.
Here, the case where the hash value is generated using only the hash function using the value of the predetermined number of bits from the least significant bit of the start address as the hash value has been described. A narrower hash value can be generated.

  Further, here, a case has been described in which there is a hash value list in which all hash values are different from each other. However, there may be a case where there are no hash value lists in the hash value table 240 that have different hash values. In such a case, the deterministic hash function selection unit 252 outputs a function that outputs the value of the start address as it is. Alternatively, the fixed hash function selection unit 252 outputs information indicating that there is no hash function.

[Example of Hash Function Specification Instruction in First Embodiment of the Present Invention]
Next, a hash function specifying instruction generated by the compile processing apparatus 100 according to the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 6 is a conceptual diagram showing an example of a hash function designation instruction in the first embodiment of the present invention. Here, it is assumed that the processor core of the data processing apparatus is configured by MIPS. Here, the left end indicates the most significant bit (MSB), and the right end indicates the least significant bit (LSB).

  FIG. 6A shows an example of a hash function specifying instruction for causing a data processing apparatus that executes an object program to recognize a hash function embedded in the object program. This hash function designation command is expressed by a bit string of 32 bits (0 to 31). This hash function designation instruction is composed of an operation code field 291, a hash function address field 292, an unused field 293, and a user-defined instruction field (UDI: User Definable Instruction) 295.

  The opcode field 291 is a field for designating the type of instruction. The opcode field 291 is a bit string composed of the 26th to 31st bits. In the operation code field 291 of the hash function designation instruction, a bit string “011100” is stored as the SPECIAL2 instruction. Here, the SPECIAL2 instruction is an instruction indicating that the instruction is uniquely defined by the user.

  The hash function address field 292 is a field for designating a register for storing the address of the hash function. The hash function address field 292 is a bit string composed of the 21st to 25th bits.

  The unused field 293 is a field that is not used in the hash function designation instruction. The unused field 293 is a 15-bit bit string composed of the sixth to twentieth bits. In this unused field 293, for example, a bit string (000000000000000000) is stored.

  The user-defined instruction field (UDI) 295 is a field for designating one instruction among a plurality of instructions defined by the user in the SPECIAL2 instruction. The user-defined instruction field (UDI) 295 is a bit string composed of 0th to 5th bits. This user-defined instruction field (UDI) 295 specifies a hash function specifying instruction by a bit string (010001), for example.

  As described above, in the first embodiment of the present invention, the hash function embedded in the object program can be used by the data processing apparatus by using the hash function designation instruction.

  Next, an identifier supply instruction used when the confirmed hash function selection unit 252 outputs an identifier, which has been described as another function related to the confirmed hash function selection unit 252 in FIG. 3, will be described. Here, the identifier supply instruction is an instruction for supplying an identifier to a data processing apparatus that executes an object program and causing the data processing apparatus to use the identifier.

  FIG. 6B shows an example of an identifier supply instruction for supplying an identifier indicating a hash function. This identifier supply command is expressed by a bit string of 32 bits (0 to 31).

  This identifier supply command is composed of an operation code field 291, an identifier field 294, and a user-defined command field (UDI) 295. Here, since the functions of the fields other than the identifier field 294 are the same as the functions of the fields of the hash function designation instruction shown in FIG. 6A, the same reference numerals as those in FIG. A detailed description thereof is omitted here.

  The identifier field 294 is a field for storing an identifier for identifying the hash function determined by the hash function determination unit 200. This identifier field 294 is, for example, a bit string composed of the 6th to 25th 20 bits.

As described above, according to the first embodiment of the present invention, the hash function determined by the hash function determination unit 200 or an identifier designating the hash function can be embedded in the object program.
When the opcode field 291 is a SPECIAL2 instruction, the sixth to 25th 20 bits are an encoding space definable by the user. Therefore, the present invention is not limited to the hash function designation instruction and the identifier supply instruction shown in FIGS. 6A and 6B, and various patterns are conceivable.

[Operation example of the compile processing apparatus 100 according to the first embodiment of the present invention]
Next, processing of the compile processing apparatus 100 according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a flowchart showing a processing procedure of compile processing by the compile processing apparatus 100 according to the first embodiment of the present invention.

  First, a source program is read from the source program storage unit 110 (step S911). Next, a reuse candidate section is extracted by the reuse candidate section extraction unit 121 (step S912).

  Then, the reuse candidate section analysis unit 122 analyzes the usage mode of the reuse candidate section (step S913). Subsequently, the reuse degree generation unit 123 generates a reuse degree based on the analysis result of the reuse candidate section (step S914).

  Next, the reuse command conversion unit 124 converts the call command for the reuse candidate section into a reuse command based on the degree of reuse (step S915). This means, for example, that a function call instruction (call) is converted into a reuse instruction (memoCall) when the function is a reuse candidate section. The reuse section is determined by a series of processes in steps S911 to S915. Note that steps S911 to S915 are an example of an analysis procedure described in the claims.

  Then, the hash function determination unit 200 performs a hash function determination process for determining a hash function for generating a hash value for identifying a reuse section with a bit width narrower than the bit width of the start address (step S920).

  Finally, the machine language program generation unit 140 generates a machine language program in which the hash function is embedded based on the analyzed program and the hash function (step S918). Then, the compilation process ends. Note that step S918 is an example of a machine language program generation procedure described in the claims.

FIG. 8 is a flowchart illustrating the first half of a processing procedure example of the hash function determination processing (step S920) by the hash function determination unit 200 according to the first embodiment of the present invention. Here, it is assumed that the total number of hash functions is “6”, which is the total number of hash functions that output the start address as it is and the hash functions of Expressions 3 to 7 shown in FIG. .
First, the start address acquisition unit 210 acquires the start address of the reuse section from the program and holds it as a start address list in the start address acquisition unit 210 (step S921).

  Next, the hash function counter (hn) is initialized to “1” (step S922). The hash function counter (hn) shown here is a value for identifying the hash function for which the hash value is generated by the candidate hash value generation unit 230. For example, the hash function counter (hn) is a value of “1 to 5” added to identify the expressions 7 to 3 associated with the hash value lists 272 to 276 shown in FIG.

  It is assumed that the hash function that outputs the start address as it is is assigned to the value “0” of the hash function counter (hn). For example, “h (hash value) = a (start address)” can be considered as a hash function that outputs the start address as it is.

  Subsequently, the start address counter (an) is initialized to “0” (step S923). Note that the start address counter (an) shown here is a value for identifying a hash value held in the hash value table 240 when used together with the hash function counter (hn).

  For example, when the hash function counter (hn) is “1”, the start address counter (an) is “0 to 7 for identifying eight hash values in the hash value list 272 associated with the expression 7. ". For example, when the hash function counter (hn) is “5”, the start address counter (an) is “0” for identifying the eight hash values in the hash value list 276 associated with Expression 3. To 7 ".

  Then, the hash value is calculated by the candidate hash value generation unit 230 using the hash function indicated by the hash function counter (hn), using the start address indicated by the start address counter (an) as a function input value (step S924). Next, “1” is added to the start address counter (an) (step S925).

  Subsequently, it is determined whether or not the start address counter (an) is the total number of start addresses in the start address list (step S926). When it is determined that the start address counter (an) is not the total number of start addresses in the start address list, the process returns to step S924. Thereby, a hash value that has not been calculated yet is calculated using the hash function indicated by the hash function counter (hn).

  On the other hand, when it is determined that the start address counter (an) is the total number of start addresses in the start address list, “1” is added to the hash function counter (hn) (step S927).

  Subsequently, it is determined whether or not the hash function counter (hn) is the total number of hash functions (step S928). When it is determined that the hash function counter (hn) is not the total number of hash functions, the process returns to step S923. Thereby, a hash function is calculated using a hash function for which a hash value has not yet been calculated. Note that steps S922 to S928 are an example of a candidate value generation procedure described in the claims.

  On the other hand, if it is determined that the hash function counter (hn) is the total number of hash functions, the process proceeds to step S929.

  FIG. 9 is a flowchart illustrating the second half of the processing procedure example of the hash function determination processing (step S920) by the hash function determination unit 200 according to the first embodiment of the present invention.

  First, when it is determined in step S928 in FIG. 8 that the hash function counter (hn) is the total number of hash functions, the selected hash function counter (h) is initialized to “0” (step S929).

  Subsequently, the hash value bit width size (ws) is changed to the bit width of the hash value generated by the hash function of the hash function counter (0) (step S931). That is, 64 bits of the bit width of the start address are set as the hash value bit width size (ws).

  Then, the hash function counter (hn) is changed to “1” (step S932). Subsequently, the unique hash value list determination unit 251 determines whether or not all hash values in the hash value list corresponding to the hash function indicated by the hash function counter (hn) are different from each other (step S933). If it is determined that all hash values in the hash value list associated with the hash function indicated by the hash function (hn) are not different from each other, the process proceeds to step S937.

  On the other hand, if it is determined that all hash values in the hash value list associated with the hash function indicated by the hash function counter (hn) are different from each other, the process proceeds to step S934. In step S <b> 934, the bit width of the hash value in the hash value list associated with the hash function indicated by the hash function counter (hn) is smaller than the hash value bit width size (ws) by the confirmed hash function selection unit 252. It is determined whether or not. When it is determined that the bit width of the hash value in the hash value list associated with the hash function indicated by the hash function (hn) is not a value smaller than ws, the process proceeds to step S937.

  On the other hand, if it is determined that the bit width of the hash value in the hash value list associated with the hash function indicated by the hash function counter (hn) is smaller than the hash value bit width size (ws), the process proceeds to step S935. move on. In step S935, the selected hash function number (h) is changed to the value of the hash function counter (hn).

  Subsequently, the hash value bit width size (ws) is changed to the bit width of the hash value in the hash value list associated with the hash function indicated by the hash function counter (hn) (step S936).

  Then, “1” is added to the hash function counter (hn) (step S937). Next, it is determined whether or not the hash function counter (hn) is the total number of hash functions (step S938). When it is determined that the hash function counter (hn) is not the total number of hash functions, the process returns to step S933.

  On the other hand, when it is determined that the hash function counter (hn) is the total number of hash functions, the hash function indicated by the selected hash function (h) is output as the hash function determined by the hash function determination unit 200 (step S939). Note that steps S929 to S939 are an example of the section identification value generation function output procedure described in the claims.

  As described above, in the first embodiment of the present invention, a hash function that generates hash values that are all different hash values and have the smallest bit width is selected from a plurality of hash functions and embedded in a program. Can do.

  Here, the hash function is selected based on the bit width of the hash value in the hash value list associated with the hash function indicated by the hash function counter (hn), but the present invention is not limited to this. For example, a case where a hash function is selected based on a value obtained by summing up the bit widths of the hash values in the hash value list may be considered.

<2. Second Embodiment>
[Configuration Example of Data Processing Device 300 in Second Embodiment of the Present Invention]
FIG. 10 is a block diagram illustrating a configuration example of the data processing device 300 according to the second embodiment of the present invention. The data processing device 300 is connected to the main storage unit 360 via the bus 350. Here, it is assumed that the instruction section in which the data processing device 300 executes processing is a function or a loop. Furthermore, here, it is assumed that the data processing device 300 executes the object program generated by the compile processing device 100 according to the first embodiment of the present invention.

  The data processing device 300 executes each process in the program. The data processing device 300 is realized by a CPU (Central Processing Unit) in a general computer, for example. The data processing device 300 includes a primary cache 310, a processor core 400, a hash conversion unit 500, and a history management unit 600.

  The primary cache 310 temporarily holds information handled by the processor core 400 via the bus 350. The primary cache 310 includes an instruction cache 311 and a data cache 312.

  The instruction cache 311 temporarily holds instructions executed in the processor core 400. This instruction cache 311 temporarily holds instructions frequently executed by the processor core 400, thereby reducing access from the processor core 400 to the main storage unit 360 and shortening data input waiting time in the processor core 400. Can be made. The instruction cache 311 supplies the processor core 400 with, for example, a reuse instruction supplied from the main storage unit 360 and an instruction specifying a hash function.

  The data cache 312 temporarily holds input data and output data of the processor core 400. The data cache 312 temporarily reduces the access from the processor core 400 to the main storage unit 360 by temporarily holding input data of the processor core 400 that is frequently used, thereby reducing the data input waiting time in the processor core 400. Reduce. For example, the data cache 312 outputs the input value and start address of the function or loop supplied from the main storage unit 360 to the processor core 400. In addition, the data cache 312 outputs, for example, information related to the hash function supplied from the main storage unit 360 to the processor core 400.

  The processor core 400 executes operations according to program instructions. The processor core 400 is realized by, for example, a MIPS (Microprocessor without Interlocked Pipeline Stages) processor. For example, the processor core 400 executes an instruction in the function or loop section input from the instruction cache 311 based on the input value and start address of the function or loop supplied from the data cache 312, and the result of the execution is executed. Output as the execution result.

  When the input instruction is a reuse instruction that designates a reuse section and the execution result is not supplied from the history management unit 600, the processor core 400 displays the execution result that is the result of executing this instruction in the data cache 312. And output to the history management unit 600. Further, when executing the reuse instruction, the processor core 400 supplies the hash conversion unit 500 with the start address of the reuse section specified by the reuse instruction.

  Further, when the execution result is supplied from the history management unit 600 when the input instruction is a reuse instruction designating a reuse section, the processor core 400 stops the process in the reuse section and performs this re-use. Return to the routine that called the usage interval and continue execution.

  The hash conversion unit 500 converts the start address into a hash value that identifies the reuse section with a bit width narrower than the bit width of the start address of the reuse section. The hash conversion unit 500 holds a hash function based on an instruction that designates a hash function among the instructions of the program. The hash conversion unit 500 generates a hash value from the function or loop start address supplied from the processor core 400 using the stored hash function. The hash conversion unit 500 supplies the generated hash value to the history management unit 600.

  The history management unit 600 holds and manages the execution result of the reuse section. The history management unit 600 holds the input value and execution result of the reuse section supplied from the processor core 400 and the hash value supplied from the hash conversion unit 500 as an execution history. Further, when the hash value and the input value of the function or loop are supplied, the history management unit 600 searches for an execution history including the hash value and the input value.

  The bus 350 is a bus that interconnects each unit of the data processing device 300 and the main storage unit 360.

  The main storage unit 360 holds data necessary for the data processing apparatus 300 to operate. The main storage unit 360 stores a program for causing the data processing device 300 to execute processing. For example, a RAM (Random Access Memory) may be used as the main storage unit 360. The main storage unit 360 outputs the stored data to the data processing device 300 via the bus 350.

[Configuration example of the processor core 400, the hash conversion unit 500, and the history management unit 600 in the second embodiment of the present invention]
FIG. 11 is a block diagram illustrating a configuration example of the processor core 400, the hash conversion unit 500, and the history management unit 600 according to the second embodiment of the present invention. Here, a processor core 400, a hash conversion unit 500, and a history management unit 600 are shown. Here, since the functions of the processor core 400, the hash conversion unit 500, and the history management unit 600 are the same as those in FIG. 10, the same reference numerals are given and detailed description thereof is omitted here.

  The processor core 400 includes a fetch unit 410, an instruction decoder 420, an execution unit 430, and a register file 440.

  The fetch unit 410 reads an instruction from the instruction cache 311 or the main storage unit 360. The fetch unit 410 temporarily holds the read instruction, and supplies an instruction to the instruction decoder 420 to be executed by the execution unit 430 among the held instructions. For example, the fetch unit 410 supplies a reuse instruction to be executed by the execution unit 430 among the temporarily held instructions to the instruction decoder 420. For example, the fetch unit 410 supplies a reuse instruction stored in the main storage unit 360 to the instruction decoder 420.

  The instruction decoder 420 generates a control signal for controlling the components in the processor core 400 by decoding (decoding) the instruction supplied from the fetch unit 410. For example, the instruction decoder 420 generates a control signal for controlling the execution unit 430 and the register file 440 by decoding the instruction, and supplies the generated control signal to the execution unit 430 and the register file 440.

  When a reuse instruction is supplied from the fetch unit 410, the instruction decoder 420 decodes the reuse instruction to generate control signals for controlling the execution unit 430 and the register file 440. This is supplied to the register file 440.

  The execution unit 430 executes the instruction decoded by the instruction decoder 420 based on the control signal supplied from the instruction decoder 420. When the instruction decoder 420 decodes an instruction specifying a hash function, the execution unit 430 outputs the hash function acquired from the register file 440 to the hash conversion unit 500 via the signal line 407.

  Further, when the instruction decoder 420 decodes the reuse instruction, the execution unit 430 starts processing of the reuse section specified by the reuse instruction. Then, along with the start of processing of the reuse section, the execution unit 430 outputs the reuse section start address acquired from the register file 440 to the hash conversion unit 500 via the signal line 408. The execution unit 430 executes processing in the reuse section based on the input value of the reuse section supplied from the register file 440, and the history management section receives the input value of the reuse section via the signal line 409. Output to 600.

  In addition, when the execution result of the reuse section is supplied from the history management unit 600, the execution unit 430 cancels the processing of the reuse section and indicates that the execution result is supplied from the history management unit 600. A signal to be notified is supplied to the fetch unit 410. At this time, the execution unit 430 outputs the execution result to the register file 440.

  On the other hand, when the execution result of the reuse section is not supplied from the history management unit 600, the execution unit 430 executes the process of the reuse section to the end, and outputs the execution result to the register file 440 and the signal line. The information is output to the history management unit 600 via 409.

  The register file 440 temporarily holds the data supplied from the data cache 312 and the execution result supplied from the execution unit 430. For example, when a control signal based on a reuse instruction is supplied from the instruction decoder 420, the register file 440 supplies the input value of the reuse section to the execution unit 430.

  The hash conversion unit 500 converts the start address into a hash value that identifies the reuse section with a bit width narrower than the bit width of the start address of the reuse section. The hash conversion unit 500 includes a fixed hash function holding unit 510 and a fixed hash value generation unit 520.

  The fixed hash function holding unit 510 holds the hash function supplied from the execution unit 430. That is, the fixed hash function holding unit 510 holds the hash function fixed by the fixed hash function selecting unit 252 shown in FIG. The fixed hash function holding unit 510 holds the hash function supplied from the execution unit 430 via the signal line 407, and supplies the held hash function to the fixed hash value generation unit 520.

  The fixed hash value generation unit 520 generates a hash value from the start address supplied from the execution unit 430 using the hash function supplied from the fixed hash function holding unit 510. That is, the confirmed hash value generation unit 520 generates a hash value from the start address supplied from the execution unit 430, using the hash function confirmed by the confirmed hash function selection unit 252 shown in FIG. When the function or loop start address is supplied via the signal line 408, the fixed hash value generation unit 520 generates a hash value using the hash function held by the fixed hash function holding unit 510. . The confirmed hash value generation unit 520 supplies the generated hash value to the history target data holding unit 610 via the signal line 509. The confirmed hash value generation unit 520 is an example of a section identification value generation unit described in the claims. The hash value generated by the confirmed hash value generation unit 520 is an example of the section identification value described in the claims. Further, the hash function used by the fixed hash value generation unit 520 is an example of the section identification value generation function described in the claims.

  The history management unit 600 holds and manages the execution result of the reuse section, and includes a history target data holding unit 610, a history search unit 620, a history memory 630, and a history registration unit 640.

  The history target data holding unit 610 temporarily holds data supplied from the execution unit 430 and the confirmed hash value generation unit 520. When the input value is supplied from the execution unit 430 and the hash value is supplied from the confirmed hash value generation unit 520, the history target data holding unit 610 supplies these to the history search unit 620 as a search request. . The history target data holding unit 610 is supplied from the input value of the function supplied from the execution unit 430 and the fixed hash value generation unit 520, for example, when a function reuse section is executed in the execution unit 430. The hash value is supplied to the history search unit 620 as a search request. In addition, when the execution unit 430 executes a loop reuse section, the history target data holding unit 610 and the hash value from the confirmed hash value generation unit 520 and the input value and loop counter value from the execution unit 430 Are supplied to the history search unit 620 as a search request. Here, the loop counter value is a value indicating the number of times of execution in the loop section.

  Further, the history target data holding unit 610 is provided with a condition for registering an execution history when an input value and an execution result are supplied from the execution unit 430 and a hash value is supplied from the confirmed hash value generation unit 520. In order to satisfy them, these are supplied to the history registration unit 640 as an execution history. For example, when the execution unit 430 executes a function reuse section, the history target data holding unit 610 receives the input value and execution result from the execution unit 430, the hash value from the confirmed hash value generation unit 520, and the like. Is supplied to the history registration unit 640 as an execution history. Further, the history target data holding unit 610 receives the input value from the execution unit 430, the execution result, the loop counter value, and the confirmed hash value generation unit 520 when the execution unit 430 executes the loop reuse section. Are supplied to the history registration unit 640 as an execution history.

  The history search unit 620 searches the execution history based on the search request supplied from the history target data holding unit 610. The history search unit 620 includes a search request input unit 621 and an execution result output unit 622.

  The search request input unit 621 searches for an execution history from the history memory 630 based on the search request supplied from the history target data holding unit 610. For example, when an instruction designating a reuse section of a function is decoded by the instruction decoder 420, the search request input unit 621 includes a hash value generated from the start address of the function designated by the instruction, The function input value is supplied to the history memory 630. Further, when an instruction designating a loop reuse section is decoded by the instruction decoder 420, the search request input unit 621 reads the hash value generated from the designated loop start address, the input value, The loop counter value is supplied to the history memory 630.

  The execution result output unit 622 extracts an execution result from the history memory 630 when the execution history is searched in the history memory 630 and outputs the extracted execution result to the execution unit 430. The execution result output unit 622 supplies the extracted execution result to the execution unit 430 via the signal line 609.

  The history memory 630 holds the execution history supplied from the history registration unit 640. For example, when a search request is supplied from the history search unit 620, the history memory 630 holds an execution history that matches the search request, and displays the execution result of the execution history as an execution result output unit 622. To supply. Further, when an execution history is supplied from the history registration unit 640, the history memory 630 holds the execution history. The history memory 630 is realized by, for example, a content addressable memory (CAM).

  The history registration unit 640 converts the execution history supplied from the history target data holding unit 610 into a data structure for holding the history memory 630, and registers the converted execution history in the history memory 630. . For example, when the history search unit 620 does not search for the execution history of the function, the history registration unit 640 uses the hash value generated from the start address of the function, the input value, and the execution result as a history of execution. Register in the memory 630. In addition, for example, when the loop search history is not searched by the history search unit 620, the history registration unit 640 generates a hash value, an input value, an execution result, and a loop counter value generated from the loop start address. Are registered in the history memory 630 as an execution history.

  As described above, in the second embodiment of the present invention, the hash conversion unit 500 is provided in the data processing device 300 so that the program in which the hash function is embedded is executed by the device of the first embodiment of the present invention. Thus, the start address can be converted into a hash value. As a result, a hash value for identifying a reuse section with a bit width narrower than the bit width of the start address can be held in the history memory 630 instead of the start address.

  That is, in the conventional technique, the start address, the input value, and the execution result are held in the history memory as the function execution history, but in the second embodiment of the present invention, a hash value having a bit width narrower than the bit width of the start address, The input value and the execution result are stored in the history memory 630. As described above, by holding the hash value having a bit width narrower than the bit width of the start address in the history memory 630 instead of the start address, the amount of execution history held in the history memory 630 can be increased.

  Here, an example in which the hash function supplied from the execution unit 430 is held in the deterministic hash function holding unit 510 has been described, but the present invention is not limited to this. For example, a plurality of hash functions that are the same as the candidate hash function holding unit 220 in the first embodiment of the present invention shown in FIG. 3 may be held in the deterministic hash function holding unit 510 in advance. In this example, the compile processing apparatus 100 according to the first embodiment of the present invention embeds an identifier indicating the hash function described in FIG. 3 in the program instead of the hash function. Then, the data processing device 300 according to the second embodiment of the present invention specifies a hash function based on the identifier.

  In this case, the execution unit 430 outputs the identifier to the hash conversion unit 500 when the instruction decoder 420 decodes the instruction specifying the identifier. Then, the deterministic hash function holding unit 510 selects from a plurality of hash functions holding the hash function corresponding to the identifier supplied from the execution unit 430, and sends the selected hash function to the deterministic hash value generation unit 520. Supply.

  Thereby, the start address can be converted into a hash value based on a program in which an identifier for identifying a hash function is embedded.

[Data structure example of history memory 630]
FIG. 12 is a conceptual diagram showing an example of the data structure of the history memory 630 according to the second embodiment of the present invention. Here, a configuration is shown in which the history memory 630 holds the execution history for one hash value in a tree structure among the execution histories held for each hash value. In this example, a function is assumed that has n arguments and returns an output as an execution result to m storage destinations.

  In this example, the function root 650 in the tree structure, the first argument nodes 661 and 662, the nth argument nodes 671 to 674, the first output nodes 681 to 684, and the mth output nodes 691 to 694 are shown. Is shown.

  In the function route 650, a hash value and a pointer pointing to the first argument node 661 are shown.

  The first and nth argument nodes 661, 662, and 671 to 674 include an input value indicating an argument value as an argument input value in the execution history held in the history memory 630, the type of the argument, The type indicating the storage location of the argument is shown. The storage location here refers to a register number or a memory address of the main storage unit 360.

  Further, the first and nth argument nodes 661, 662, and 671 to 674 include a right pointer that points to the argument node of the next argument when the input values to be compared match each other, and the same argument when they do not match And a lower pointer pointing to another argument node. Each of the nth argument nodes 671 to 674 is connected to the first and mth output nodes 681 to 684 and 691 to 694, respectively.

  The first and m-th output nodes 681 to 684 and 691 to 694 have an output value indicating an execution result value as an execution result in the execution history held in the history memory 630 and a storage location of the execution result. The type to be shown and the type of the execution result are shown. Further, the first output nodes 681 to 684 show a right pointer that points to the next output node. That is, the first and mth output nodes 681 to 684 and 691 to 694 constitute a linked list. Further, the mth output nodes 691 to 694 show a null indicating the end of the output node.

  In such a tree structure, when a hash value that matches the hash value indicated in the function route 650 is input from the history search unit 620, the input is made in the first argument node 661 indicated by the pointer of the function route 650. A value comparison process is executed. The input value comparison processing here is to compare the input value, type, and type indicated in the first argument node 661 with the input value from the history search unit 620.

  At this time, for example, if the input value indicated by the first argument node 661 matches the input value + from the history search unit 620, the next value indicated by the right pointer of the first argument node 661 is displayed. The input value comparison process is executed at the argument node. On the other hand, if the input value indicated by the first argument node 661 does not match the input value from the history search unit 620, the first argument indicated by the lower pointer of the first argument node 661 is displayed. The node 662 executes input value comparison processing.

  In this way, the argument node pointed to by the right or lower pointer is selected based on the result of the comparison process at each argument node, and the input value comparison process is sequentially executed at the selected argument node. For example, when the input value indicated in the nth argument node 671 and the input value from the history search unit 620 match each other, the first output node pointed to by the right pointer of the nth argument node 671 The execution result of 681 is output to the history search unit 620. Finally, the execution result of the m-th output node 691 is output to the history search unit 620.

  In this way, by configuring the history memory 630 with a tree structure for each hash value, it is not necessary to hold the input values of the same argument redundantly, so that a storage area can be saved. Further, by dividing the data structure for each hash value, it is possible to suppress a decrease in search speed.

[Operation Example of Data Processing Device 300 in Second Embodiment of the Present Invention]
Next, processing of the data processing device 300 according to the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 13 is a flowchart illustrating an example of a processing procedure of an instruction processing method performed by the data processing device 300 according to the second embodiment of the present invention. This flowchart describes an example of processing for each instruction decoded by the instruction decoder 420. The end of execution of the instruction decoded by the instruction decoder 420 is defined as the end of the flowchart.

  First, the instruction decoded by the instruction decoder 420 and the value executed by the execution unit 430 according to the instruction are read into the fetch unit 410 and the register file 440 (step S941). Next, the instruction decoder 420 decodes the instruction supplied from the fetch unit 410 (step S942).

  Subsequently, the execution unit 430 determines whether or not the decoded instruction is a hash function designation instruction (step S943). If it is determined that the decoded instruction is a hash function designation instruction, the hash function supplied from the register file 440 is registered in the confirmed hash function holding unit 510 via the signal line 407 (step S944). . As a result, the execution of the hash function designation instruction is completed.

  On the other hand, when it is determined that the decoded instruction is not a hash function designation instruction, it is determined whether or not the decoded instruction is a reuse instruction (step S945). If it is determined that the decoded instruction is not a reuse instruction, the execution section 430 executes the reuse section based on the input value supplied from the register file 440, thereby outputting an execution result. Then (step S946), the process proceeds to step S954.

  On the other hand, if it is determined in step S945 that the instruction is a reuse instruction, the determined hash value generation unit 520 calculates a hash value from the start address of the reuse section (step S947). Subsequently, the search request input unit 621 determines whether or not there is an execution history in the history memory 630 using the hash value and the input value (step S948). At this time, if the loop is a reuse section, whether or not there is an execution history in the history memory 630 is searched using the loop counter value in addition to the hash value and the input value.

  If it is determined that the execution history is not in the history memory 630, the execution section 430 executes the reuse section based on the input value supplied from the register file 440, thereby outputting the execution result. (Step S949). Then, the history registration unit 640 registers the execution history in the history memory 630 (step S951). As a result, the execution history is registered in the history memory 630. Then, the process proceeds to step S954.

  On the other hand, when it is determined that the execution history is in the history memory 630, the execution result output unit 622 outputs the execution result (step S952). As a result, the execution result of the reuse section being executed is output from the history memory 630. Subsequently, the execution unit 430 stops execution of the reuse section in which the execution result is output (step S953). Then, the process proceeds to step S954.

  Then, after the processing of steps S946, S951, and S953, the execution result is written back to the register file 440 (step S954). As a result, execution of the decoded instruction is completed.

  As described above, in the second embodiment of the present invention, by providing the hash conversion unit 500, the hash value, the input value, and the execution result can be held in the history memory 630 as an execution history.

<3. Third Embodiment>
[Configuration example of the compile processing apparatus 100 according to the third embodiment of the present invention]
FIG. 14 is a block diagram illustrating a configuration example of the compile processing apparatus 100 according to the third embodiment of the present invention. The compile processing apparatus 100 includes a hash value-added reuse instruction generation unit 170 instead of the hash function determination unit 200 of the compile processing apparatus 100 shown in FIG. Here, since the configuration other than the hash value-added reuse instruction generation unit 170 is the same as that in FIG. 1, the same reference numerals as those in FIG. 1 are given, and detailed description of the configuration of each unit is omitted here.

  The hash value reuse instruction generation unit 170 generates a hash value reuse instruction that is a reuse instruction including a hash value for identifying a reuse section with a bit width narrower than the bit width of the start address of the reuse section. It is. The hash value-added reuse instruction generation unit 170 includes a hash value determination unit 700 and a hash value addition unit 172. The hash value-added reuse instruction is an example of the section identification value-added instruction described in the claims.

  The hash value determination unit 700 determines a hash value for identifying a reuse section with a bit width narrower than the bit width of the start address of the reuse section. For example, the hash value determination unit 700 generates a hash value for each hash function using a plurality of hash functions, using a number assigned according to a predetermined order of the start address of the reuse interval as a function input value. Then, the hash value determination unit 700 determines and outputs a hash value having the smallest bit width among the plurality of hash functions, all having different values. The hash value determination unit 700 supplies the determined hash value to the hash value addition unit 172 together with the program.

  The hash value adding unit 172 generates a reuse instruction with a hash value by adding the hash value determined by the hash value determination unit 700 to a reuse instruction for calling a reuse section indicated by the hash value. The hash value adding unit 172 supplies a program including the generated reuse instruction with hash value to the machine language program generating unit 140. The hash value adding unit 172 is an example of an instruction conversion unit described in the claims.

  The machine language program generation unit 140 generates an object program that is a machine language program based on the program including the reuse instruction with hash value supplied from the hash value addition unit 172. In addition, when generating the object program, the machine language program generation unit 140 embeds an instruction for specifying a value for specifying the bit width of the hash value in the object program.

  As described above, in the compile processing device 100 according to the third embodiment of the present invention, first, a function call instruction is converted into a reuse instruction according to the degree to which the execution result of the function is reused. Make it possible to distinguish between functions that are used and functions that are not reused. Then, in the compilation processing device 100 according to the third embodiment of the present invention, the hash value for identifying the reuse section is determined and the hash value reuse instruction is generated, thereby reusing the hash value reuse. A program including instructions can be generated.

[Configuration Example of Hash Value Determining Unit 700 in the Third Embodiment of the Present Invention]
FIG. 15 is a block diagram illustrating a configuration example of the hash value determination unit 700 according to the third embodiment of this invention. The hash value determination unit 700 includes a start address acquisition unit 710, a candidate hash function storage unit 720, a candidate hash value generation unit 730, a hash value table 740, and a hash value output unit 750.

  Similar to the start address acquisition unit 210 shown in FIG. 3, the start address acquisition unit 710 acquires the start address of the reuse section from the program including the reuse command from the reuse command conversion unit 124. The start address acquisition unit 710 holds the acquired start address as a start address list. In addition, the start address acquisition unit 710 holds numbers assigned according to the acquisition order of the acquired start addresses as a number list. The start address acquisition unit 710 supplies the acquired start address or the assigned number to the candidate hash value generation unit 730.

  The candidate hash function holding unit 720 holds a plurality of hash functions for converting a start address or number into a hash value. That is, the candidate hash function holding unit 720 holds a hash function that is a hash function candidate for generating a hash value that is a hash value candidate determined by the hash value determining unit 700. The candidate hash function holding unit 720 holds a predetermined hash function.

  The candidate hash function storage unit 720 supplies the plurality of stored hash functions to the candidate hash value generation unit 730. Note that the hash function supplied from the candidate hash function holding unit 720 is an example of the candidate function described in the claims.

  The candidate hash value generation unit 730 uses the start address or number supplied from the start address acquisition unit 710 as a function input value, and uses the function input value as an input of the hash function supplied from the candidate hash function holding unit 720, to obtain a hash value. Is to be generated. That is, the candidate hash value generation unit 730 generates a hash value that is a hash value candidate determined by the hash value determination unit 700.

  For example, when a number is supplied from the start address acquisition unit 710, the candidate hash value generation unit 730 generates a hash value from the number using the hash function supplied from the candidate hash function holding unit 720. For example, when the start address is supplied from the start address acquisition unit 710, the candidate hash value generation unit 730 uses the hash function supplied from the candidate hash function holding unit 720 to calculate the hash value from the start address. Is generated.

  The candidate hash value generation unit 730 supplies the generated hash value to the hash value table 740. The candidate hash value generation unit 730 is an example of a candidate value generation unit described in the claims. The hash value supplied from the candidate hash value generation unit 730 is an example of the candidate value described in the claims.

  The hash value table 740 holds the hash value supplied from the candidate hash value generation unit 730. The hash value table 740 holds a hash value as a hash value list for each hash function that generates the hash value. Also, the hash value table 740 supplies the stored hash value list to the hash value output unit 750. The hash value table 740 is an example of a candidate value table described in the claims. The hash value list is an example of a candidate value list described in the claims.

  The hash value output unit 750 extracts hash value lists whose hash values are all different from each other, and outputs the hash value of the hash value list in which the bit width of the hash value is the narrowest among the extracted hash value lists. . The hash value output unit 750 includes a unique hash value list determination unit 751 and a confirmed hash value selection unit 752. The hash value output unit 750 is an example of the section identification value output unit described in the claims. The hash value output by the hash value output unit 750 is an example of a section identification value described in the claims.

  Similar to the unique hash value list determination unit 251 illustrated in FIG. 3, the unique hash value list determination unit 751 determines hash value lists whose hash values are all different from each other among the hash value lists held in the hash value table 740. To do. The unique hash value list determination unit 751 supplies the determined hash value list to the confirmed hash value selection unit 752.

  The confirmed hash value selection unit 752 selects a hash value list in which the bit width of the hash value is the narrowest from the hash value list supplied from the unique hash value list determination unit 751, and the hash value of the selected hash value list Is output. That is, the determined hash value selection unit 752 determines the hash value from the hash values of the hash value candidates determined by the hash value determination unit 700, and uses the determined hash value as the hash value determined by the hash value determination unit 700. Output.

  The confirmed hash value selection unit 752 detects one hash value list having the narrowest bit width of hash values among hash value lists whose hash values supplied from the unique hash value list determination unit 751 are all different from each other. Then, the determined hash value selection unit 752 supplies the hash value of the detected hash value list to the hash value addition unit 172.

  As described above, in the third embodiment of the present invention, by providing the hash value determination unit 700, all of the hash values with different hash values and the hash value with the narrowest bit width are included. A program can be generated.

  Here, an example has been described in which the candidate hash function holding unit 720 supplies all the stored hash functions to the candidate hash value generation unit 730, but the present invention is not limited to this. For example, the hash function supplied to the candidate hash value generation unit 730 may be controlled by enabling the candidate hash function holding unit 720 to be controlled from the outside. For example, the hash function used by the candidate hash value generation unit 730 may be determined based on the largest number among the numbers supplied from the hash value table 740.

[An example of hash values held in the hash value table 740 according to the third embodiment of the present invention]
FIG. 16 is a conceptual diagram illustrating an example of hash values held in the hash value table 740 according to the third embodiment of this invention. Here, for the sake of convenience, it is assumed that the start address acquisition unit 710 holds numbers assigned according to the order in which start addresses are acquired as a number list. Further, this number is assumed to be a value assigned in order from “1” to the start address registered in the hash value table 740. Further, here, it is assumed that the candidate hash function holding unit 720 holds the hash functions of Expressions 3 to 6 described in FIG.

  Here, the reuse interval in the program is assumed to be seven functions (funcA to funcG). Here, it is assumed that the start address acquisition unit 710 sequentially acquires seven functions (funcA to funcG) from funcA and supplies them to the hash value table.

In addition, when the hash value is calculated using only the hash function that shortens the bit width, the candidate hash value generation unit 730 uses the function input value as it is to reduce the data amount in the hash value table 740 as it is. It can be supplied to. That is, the candidate hash value generation unit 730 causes the hash value table 740 to hold a number list similar to the number list in the start address acquisition unit 710 when a number is supplied as a function input value from the start address acquisition unit 710. Be able to.
Further, when the candidate hash value generation unit 730 supplies the function input value to the hash value table 740 as it is, the data related to the bit width of the hash value generated by the hash function is stored in the hash value table 740 instead of the hash value list. Assume that they are retained.

  FIG. 16A shows an example of the number list 772 held in the hash value table 740.

  The start address list 771 indicates the list name of the start address that is the basis of the hash value registered in the hash value table 740. In this start address list 771, a value related to funcA is shown in line 782, a value related to funcB is shown in line 783, and a value related to funcC is shown in line 784. Furthermore, row 785 shows a value for funcD, row 786 shows a value for funcE, row 787 shows a value for funcF, and row 788 shows funcG. .

  The number list 772 is a list of numbers registered in the hash value table 740 when the candidate hash value generation unit 730 supplies the function input value as it is to the hash value table 740. This number list 772 represents the value (1 to 7) assigned to the start address (funcA to funcG) in decimal notation, and the number is a 64-bit binary number. The value represented by is shown in parentheses.

  In a case where such a number list 772 is held in the hash value table 740, the candidate hash value generation unit 730 holds data relating to the bit width of the hash value generated by the hash function in the hash value table 740 instead of the hash value list. Let

  FIG. 16B shows hash value lists 773 to 776 assumed from the number list 772 shown in FIG. 16A and data specifying the bit width of the number list.

  The hash value list 773 shows a list of hash values calculated when using Expression 6 which is a hash function with i (bit width) of Expression 1 being “4”. In the rows 782 to 788 of the hash value list 773, numbers (rows 782 to 788 of the number list 772) assigned according to the acquisition order of the start addresses of the seven functions (funcA to funcG) A hash value calculated as an input value is shown. That is, in the rows 782 to 788 of the hash value list 773, the lowest number of the bit string expressing the numbers (rows 782 to 788 of the number list 772) given in the binary number in accordance with the acquisition order of the start addresses of the seven functions. Bit to 4-bit values are shown respectively.

  The hash value list 774 shows a list of hash values calculated when Expression 5 which is a hash function in which i (bit width) of Expression 1 is “3” is used. In rows 782 to 788 of the hash value list 774, numbers (rows 782 to 788 of the number list 772) assigned according to the acquisition order of the start addresses of the seven functions (funcA to funcG) are the functions of the formula 5. A hash value calculated as an input value is shown. That is, in the rows 782 to 788 of the hash value list 774, the lowest number of the bit string expressing the numbers (rows 782 to 788 of the number list 772) given in the binary number in accordance with the acquisition order of the start addresses of the seven functions. Bit to 3-bit values are shown respectively.

  The hash value list 775 shows a list of hash values calculated when using Expression 4 which is a hash function with i (bit width) of Expression 1 being “2”. In rows 782 to 788 of the hash value list 775, numbers (rows 782 to 788 of the number list 772) assigned in accordance with the acquisition order of the start addresses of the seven functions (funcA to funcG) A hash value calculated as an input value is shown. That is, in the rows 782 to 788 of the hash value list 775, the lowest number of the bit string expressing the numbers (rows 782 to 788 of the number list 772) given in the binary number in accordance with the acquisition order of the start addresses of the seven functions. Bit to 2-bit values are shown respectively.

  The hash value list 776 shows a list of hash values calculated when Expression 3 which is a hash function in which i (bit width) of Expression 1 is “1” is used. In rows 782 to 788 of the hash value list 776, numbers (rows 782 to 788 of the number list 772) assigned according to the acquisition order of the start addresses of the seven functions (funcA to funcG) A hash value calculated as an input value is shown. That is, in the rows 782 to 788 of the hash value list 776, the lowest number of the bit string expressing the numbers (rows 782 to 788 of the number list 772) given in the binary number according to the acquisition order of the start addresses of the seven functions. Each bit value is shown.

  Next, the hash value list determined by the unique hash value list determination unit 751 and the hash value selected by the confirmed hash value selection unit 752 will be described with reference to FIG.

First, the unique hash value list discriminating unit 751 relates the hash value lists 773 to 776 shown in FIG. 16B to the number list 772 in FIG. 16A and the bit width of the hash value generated by the hash function. Assuming from data. Then, a hash value list having all different hash values is detected from the hash value lists 773 to 776, and the detected hash value list is supplied to the determined hash value selection unit 752.
At this time, since the hash values of funcA, funcC, funcE, and funcG overlap with “1” and the hash values of the other three functions overlap with “0”, the hash value list 776 has a fixed hash. It is not supplied to the value selector 752. Further, in the hash value list 775, the hash values of funcA and funcE are “01” and duplicated, the hash values of funcB and funcF are duplicated as “10”, and the hash values of funcC and funcG are duplicated as “11”. Not supplied. As a result, hash value lists 773 and 774 in which all hash values are determined to be different from each other are supplied to the determined hash value selection unit 752.

  Subsequently, the confirmed hash value selection unit 752 detects a hash value list having the narrowest bit width of the hash value from the supplied hash value list, and sends the hash value of the detected hash value list to the hash value addition unit 172. Supply. As a result, the hash value list 774 is detected as the hash value list with the narrowest bit width among the hash value list 773 of the 4-bit hash value and the hash value list 774 of the 3-bit hash value. Then, the determined hash value selection unit 752 outputs the hash value of the detected hash value list 774.

  As described above, in the third embodiment of the present invention, when only the hash values having different bit widths are generated by the candidate hash value generation unit 730, the function input values are held in the hash value table 740. The hash value can be determined. Thereby, since the data amount of the hash value list in the hash value table 740 can be reduced, it is possible to reduce processing such as searching for hash value lists having different hash values. Further, although the case where the number is a function input value has been described, the same processing can be performed in the case of a start address. That is, the method shown in FIG. 16 can be similarly performed by the hash function determination unit 200 in the first embodiment.

  Here, the hash value is calculated using the number assigned according to the order in which the start address is acquired as the function input value of the hash function, but the present invention is not limited to this. For example, as in the first embodiment shown in FIG. 5, the start address may be a function input value. In addition, the order in which the start address is acquired is not set as the function input value, but the order for the reuse level generated by the reuse level generation unit 123 may be set as the function input value.

  Also, here, the unique hash value list determination unit 751 has been described with respect to the case where the hash value lists 773 to 776 are assumed from the number list 772 and the data related to the bit width of the hash value generated by the hash function. The invention is not limited to this. For example, the hash value output unit 750 may be able to directly select a value having the smallest bit width from all different values from the number list held by the start address acquisition unit 710. Accordingly, the hash value determination unit 700 that does not include the candidate hash function holding unit 720, the candidate hash value generation unit 730, and the hash value table 740 can determine the hash value having the narrowest bit width and different values. .

[An example of a reuse instruction in the third embodiment of the present invention]
Next, a reuse instruction generated by the compile processing apparatus 100 according to the third embodiment of the present invention will be described with reference to the drawings.

  FIG. 17 is a conceptual diagram showing an example of a function call instruction and a function reuse instruction according to the third embodiment of the present invention. Here, it is assumed that the processor core of the data processing apparatus is configured by MIPS. Here, the left end indicates the most significant bit (MSB), and the right end indicates the least significant bit (LSB).

  FIG. 17A shows a JALR (Jump And Link Register) instruction which is a function call instruction (call) in the MIPS instruction set. The MIPS instruction set is a 32-bit fixed-length instruction set, and the JALR instruction is represented by a bit string of 32 bits (0 to 31).

  The JALR instruction includes an operation code field 810, a function address field (rs) 820, a first unused field 830, a return address field (rd) 840, a second unused field 850, and a function designation field 860. Composed.

  The opcode field 810 is a field for designating the type of instruction. The opcode field 810 is a bit string composed of the 26th to 31st bits. In this opcode field 810, a bit string (000000) is stored as a SPECIAL instruction.

  A function address field (rs) 820 is a field for designating a register for storing a function address. The function address field (rs) 820 is a bit string composed of the 21st to 25th bits.

  The first unused field 830 is a field that is not used in the JALR instruction. The first unused field 830 is the 16th to 20th bit strings. This first unused field 830 stores a bit string (00000) in the JALR instruction.

  A return address field (rd) 840 is a field for designating a return address from the function. The return address field (rd) 840 is a bit string composed of the 11th to 15th bits. This return address field (rd) 840 stores a bit string (11111) indicating the 31st register in the JALR instruction.

  The second unused field 850 is a field that is not used in the JALR instruction. The second unused field 850 is a bit string composed of sixth to tenth bits. This second unused field 850 stores a bit string (00000) in the JALR instruction.

  The function designation field 860 is a field for designating one function among the plurality of functions when the instruction designated by the operation code field 810 includes a plurality of functions. This function designation field 860 is a bit string composed of the 0th to 5th bits. This function designation field 860 stores a bit string (001001) in the JALR instruction.

  FIG. 17B shows an example of a reuse instruction with a hash value of a function according to the third embodiment of the present invention. This reusable instruction with hash value is represented by a bit string of 32 bits (0 to 31). This reusable instruction with hash value includes an operation code field 810, a function address field (rs) 820, first hash value fields 832 and 833, a return address field (rd) 840, and second hash value fields 852 and 853. And a function designation field 860. Here, since the configuration other than the first hash value fields 832 and 833 and the second hash value fields 852 and 853 is the same as that in FIG. 17A, the same reference numerals as in FIG. The description here is omitted.

  The first hash value fields 832 and 833 are fields indicating a reuse instruction to which a hash value is added together with the second hash value fields 852 and 853. The first hash value fields 832 and 833 become a field indicating a 10-bit numerical value indicating the hash value by being concatenated with the bit string of the second hash value fields 852 and 853. In the first hash value fields 832 and 833 and the second hash value fields 852 and 853, the bit strings of the first unused field 830 and the second unused field 850 in the JALR instruction are changed to bit strings other than “00000”. Is. However, the first hash value fields 832 and 833 and the second hash value fields 852 and 853 indicate a reuse instruction with a hash value if one bit string is other than “00000”, and the other bit string is “00000”. It may be.

  For example, the first hash value field 832 stores the value of the bit string in the reuse instruction with hash value having the lowest hash value value together with the second hash value field 852. The first hash value field 832 is concatenated with the second hash value field 852 to become a 10-bit bit string (0000000001). That is, in the data processing apparatus that processes this instruction, it is determined that this bit string (0000000001) indicates a hash value of “1”.

  Further, the first hash value field 833 stores the value of the bit string in the reuse instruction with hash value having the highest hash value value, together with the second hash value field 853. The first hash value field 833 is concatenated with the second hash value field 853 to become a 10-bit bit string (1111111111). That is, in the data processing apparatus that processes this command, it is determined that this bit string (11111111111) indicates the hash value of “1024”.

  In FIG. 17B, the hash value-added reuse instruction generated by the hash value adding unit 172 has been described. For the reuse instruction before the hash value generated by the reuse instruction conversion unit 124 is added, one of the first unused field 830 and the second unused field 850 is changed to a bit string other than “00000”. Anything changed may be used.

  As described above, in the third embodiment, by providing the hash value adding unit 172, it is possible to generate a reuse instruction to which a hash value is added.

  Here, although the hash value reuse instruction in which the hash value is embedded in the first unused field 830 and the second unused field 850 of JALR has been described, the present invention is not limited to this. For example, similarly to the hash function designation instruction and the identifier supply instruction shown in FIG. 6, the user may newly define a new reuse instruction with a hash value.

  For example, the SPECIAL2 instruction is stored in the operation code field 810, and one instruction among a plurality of instructions defined by the user is designated in the function designation field 860, like the user-defined instruction field (UDI) 295 in FIG. Stores a value. Then, in the 6th to 25th user definable encoding spaces, a value for specifying a register for storing the address of the function, a value for specifying a return address from the function, and an address for storing the hash value are stored. Store the value to be stored. Since a hash value having a bit width of 10 bits or more can be stored at the address where the hash value is stored, a reuse instruction with a hash value to which a hash value having a bit width larger than 10 bits is added is generated. be able to.

  By storing a field for designating a register for storing the address where the hash value is stored, it is possible to generate a reuse instruction with a hash value to which a hash value having a bit width larger than 10 bits is added.

[Operation Example of Compilation Processing Apparatus 100 in Third Embodiment of the Present Invention]
Next, processing of the compile processing apparatus 100 according to the third embodiment of the present invention will be described with reference to the drawings.

  FIG. 18 is a flowchart showing a processing procedure of compile processing by the compile processing device 100 according to the third embodiment of the present invention.

  First, a source program is read from the source program storage unit 110 (step S911). Next, a reuse candidate section is extracted by the reuse candidate section extraction unit 121 (step S912).

  Then, the reuse candidate section analysis unit 122 analyzes the usage mode of the reuse candidate section (step S913). Subsequently, the reuse degree generation unit 123 generates a reuse degree based on the analysis result of the reuse candidate section (step S914).

  Next, the reuse command conversion unit 124 converts the call command for the reuse candidate section into a reuse command based on the degree of reuse (step S915). This means, for example, that a function call instruction (call) is converted into a reuse instruction (memoCall) when the function is a reuse candidate section. The reuse section is determined by a series of processes in steps S911 to S915.

  Then, the hash value determination unit 700 performs a hash value determination process for determining a hash value for identifying a reuse section with a bit width narrower than the bit width of the start address (step S960).

  Subsequently, the hash value adding unit 172 generates a hash value-added reuse command (step S917).

  Finally, the machine language program generation unit 140 generates a machine language program including an instruction for specifying the bit width of the hash value and a reuse instruction with a hash value (step S918). Then, the compilation process ends.

  FIG. 19 is a flowchart illustrating the first half of a processing procedure example of the hash value determination process (step S960) by the hash value determination unit 700 according to the third embodiment of the present invention. Here, for convenience, it is assumed that the hash value table 740 holds the hash value list shown in FIG. Here, it is assumed that the total number of hash functions is “6”, which is the total number of hash functions that output the start address as it is and the hash functions of Expressions 3 to 7 shown in FIG. .

  First, the start address acquisition unit 710 acquires the start address of the reuse section from the program, and holds it as a start address list in the start address acquisition unit 710 (step S961). Subsequently, numbers are assigned according to the order in which the start addresses held in the start address acquisition unit 710 are held, and the numbers are held as a number list (step S962).

  Next, the hash function counter (hn) is initialized to “1” (step S963). Note that the hash function counter (hn) shown here is the same as the hash function counter (hn) shown in FIG. 8, and therefore detailed description thereof is omitted here. It is assumed that a hash function that outputs the start address as it is is assigned to the value “0” of the hash function counter (hn) as in the hash function counter (hn) shown in FIG.

  Subsequently, the start address counter (an) is initialized to “0” (step S964). Note that the start address counter (an) shown here is the same as the start address counter (an) shown in FIG. 8, and thus detailed description thereof will be omitted.

  Then, the hash value is calculated by the candidate hash value generation unit 730 using the hash function indicated by the hash function counter (hn) as the function input value using the number assigned to the start address indicated by the start address counter (an). (Step S965). Next, “1” is added to the start address counter (an) (step S966).

  Subsequently, it is determined whether or not the start address counter (an) is the total number of start addresses in the start address list (step S967). When it is determined that the start address counter (an) is not the total number of start addresses in the start address list, the process returns to step S965. As a result, a hash value that has not been calculated yet is calculated using the number assigned to the hash function indicated by the hash function counter (hn) as the function input value.

  On the other hand, when it is determined that the start address counter (an) is the total number of start addresses in the start address list, “1” is added to the hash function counter (hn) (step S968).

  Subsequently, it is determined whether or not the hash function counter (hn) is the total number of hash functions (step S969). When it is determined that the hash function counter (hn) is not the total number of hash functions, the process returns to step S964. Thereby, a hash function is calculated using a hash function for which a hash value has not yet been calculated.

  On the other hand, if it is determined that the hash function counter (hn) is the total number of hash functions, the process proceeds to step S970.

  FIG. 20 is a flowchart illustrating the second half of the processing procedure example of the hash value determination process (step S960) by the hash value determination unit 700 according to the third embodiment of the present invention.

  First, when it is determined in step S969 in FIG. 19 that the hash function counter (hn) is the total number of hash functions, the selected hash function counter (h) is initialized to “0” (step S970).

  Subsequently, the hash value bit width size (ws) is changed to the bit width of the hash value generated by the hash function of the hash function counter (0) (step S971). Thereby, the hash value bit width size (ws) is set to 64 bits of the bit width of the start address.

  Then, the hash function counter (hn) is changed to “1” (step S972). Subsequently, the unique hash value list discriminating unit 751 discriminates whether or not all hash values in the hash value list corresponding to the hash function indicated by the hash function counter (hn) are different from each other (step S973). If it is determined that all hash values in the hash value list associated with the hash function indicated by the hash function (hn) are not different from each other, the process proceeds to step S977.

  On the other hand, if it is determined that the hash values in the hash value list associated with the hash function indicated by the hash function counter (hn) are all different from each other, the process proceeds to step S974. In step S974, the confirmed hash value selection unit 752 has a bit width of the hash value of the hash value list associated with the hash function indicated by the hash function counter (hn) smaller than the hash value bit width size (ws). It is determined whether or not. If it is determined that the bit width of the hash value in the hash value list associated with the hash function indicated by the hash function (hn) is not a value smaller than ws, the process proceeds to step S977.

  On the other hand, if it is determined that the bit width of the hash value in the hash value list associated with the hash function indicated by the hash function counter (hn) is smaller than the hash value bit width size (ws), the process proceeds to step S975. move on. In step S975, the selected hash function number (h) is changed to the value of the hash function counter (hn).

  Subsequently, the hash value bit width size (ws) is changed to the bit width of the hash value in the hash value list associated with the hash function indicated by the hash function counter (hn) (step S976).

  Then, “1” is added to the hash function counter (hn) (step S977). Next, it is determined whether or not the hash function counter (hn) is the total number of hash functions (step S978). When it is determined that the hash function counter (hn) is not the total number of hash functions, the process returns to step S973.

  On the other hand, if it is determined that the hash function counter (hn) is the total number of hash functions, the process proceeds to step S979. In step S979, the hash value of the hash value list associated with the hash function indicated by the selected hash function (h) is output as the hash value determined by the hash value determination unit 700 (step S979).

  As described above, in the third embodiment of the present invention, by providing the hash value determination unit 700, hash values that are all different from each other among a plurality of hash functions and have the smallest bit width are generated. A hash value of a hash function can be output.

  As described above, according to the third embodiment of the present invention, it is possible to generate a program including a hash value reuse instruction.

<4. Fourth Embodiment>
[Configuration Example of Data Processing Device 300 in the Fourth Embodiment of the Present Invention]
FIG. 21 is a block diagram illustrating a configuration example of the data processing device 300 according to the fourth embodiment of the present invention. This data processing device 300 is obtained by removing the hash conversion unit 500 of the data processing device 300 shown in FIG. Since the instruction cache 311 and the data cache 312 in this data processing device 300 have the same functions as the components shown in FIG. 10, the same reference numerals as those in FIG. The main storage unit 360 to which the data processing device 300 is connected and the bus 350 via the connection have the same functions as those shown in FIG. The description here is omitted.

  Similar to the processor core 400 in FIG. 10, the processor core 400 executes operations in accordance with program instructions. When the reuse instruction with hash value shown in FIG. 17 is input, the processor core 400 stores the hash value included in the reuse instruction with hash value and the input value of the reuse section in the history management unit 600. To supply. Further, when the execution result is not supplied from the history management unit 600 when the hash value reuse instruction is executed, the processor core 400 displays the execution result as the result of executing this instruction in the data cache 312 and the history management unit 600. Output to.

  Further, when the execution result is supplied from the history management unit 600 when the input instruction is a reuse instruction with a hash value, the processor core 400 stops the process in the reuse section, and uses the reuse section. Return to the calling routine and continue execution.

  The history management unit 600 holds and manages the execution result of the reuse section. The history management unit 600 holds a hash value, an input value, and an execution result supplied from the processor core 400 as an execution history. In addition, when the hash value and the input value are supplied from the processor core 400, the history management unit 600 searches for an execution history including the hash value and the input value.

[Configuration Example of Processor Core 400 and History Management Unit 600 in the Fourth Embodiment of the Present Invention]
FIG. 22 is a block diagram illustrating a configuration example of the processor core 400 and the history management unit 600 according to the fourth embodiment of the present invention. Here, the processor core 400 and the history management unit 600 are shown. Here, since the functions of the processor core 400 and the history management unit 600 are the same as those in FIGS. 10 and 21, the same reference numerals are given and detailed description thereof is omitted here.

  The processor core 400 includes a fetch unit 410, an instruction decoder 420, an execution unit 430, and a register file 440. Note that the functions of the fetch unit 410, the instruction decoder 420, and the register file 440 in the fourth embodiment of the present invention are the same as those shown in FIG. Reference numerals are assigned and detailed description is omitted here.

  The execution unit 430 executes the instruction analyzed in the instruction decoder 420 based on the control signal supplied from the instruction decoder 420. When the instruction decoder 420 decodes an instruction specifying the bit width of the hash value, the execution unit 430 sets the bit width specified by the instruction as the bit width of the hash value.

  Further, when the instruction decoder 420 decodes the reuse instruction with hash value, the execution unit 430 starts processing of the reuse section designated by the reuse instruction with hash value. Then, along with the start of the processing of the reuse section, the execution unit 430 outputs the hash value acquired from the hash value-added reuse command to the history management unit 600 via the signal line 409. For example, when the bit width of the hash value is set to “5”, the execution unit 430 converts the 5-bit value from the least significant bits of the second hash value fields 852 and 853 shown in FIG. To the history management unit 600 via the signal line 409.

  The execution unit 430 executes processing in the reuse section based on the input value of the reuse section supplied from the register file 440, and the history management section receives the input value of the reuse section via the signal line 409. Output to 600.

  In addition, when the execution result of the reuse section is supplied from the history management unit 600, the execution unit 430 cancels the processing of the reuse section and indicates that the execution result is supplied from the history management unit 600. A signal to be notified is supplied to the fetch unit 410. At this time, the execution unit 430 outputs the execution result to the register file 440.

  On the other hand, when the execution result of the reuse section is not supplied from the history management unit 600, the execution unit 430 executes the process of the reuse section to the end, and outputs the execution result to the register file 440 and the signal line. The information is output to the history management unit 600 via 409.

  The history management unit 600 holds and manages the execution result of the reuse section, and includes a history target data holding unit 610, a history search unit 620, a history memory 630, and a history registration unit 640. Note that each configuration of the history management unit 600 according to the fourth exemplary embodiment of the present invention has the same function as each configuration illustrated in FIG. 11 except that the hash value is supplied from the execution unit 430. 11 will be assigned the same reference numerals and detailed description thereof will be omitted. That is, the history management unit 600 shown in FIG. 11 uses the hash value supplied from the hash conversion unit 500. However, the history management unit 600 in the fourth embodiment of the present invention is supplied from the execution unit 430. The difference is that a hash value is used.

  As described above, in the fourth embodiment of the present invention, the hash value and the input value are calculated based on the program including the reuse instruction with the hash value generated by the apparatus of the third embodiment of the present invention. The execution result can be held in the history memory 630 as an execution history.

[Operation Example of Data Processing Device 300 in the Fourth Embodiment of the Present Invention]
Next, processing of the data processing device 300 according to the fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 23 is a flowchart illustrating an example of a processing procedure of an instruction processing method performed by the data processing device 300 according to the fourth embodiment of the present invention. This flowchart describes an example of processing for each instruction decoded by the instruction decoder 420 after the instruction indicating the bit width of the hash value is executed. The end of execution of the instruction decoded by the instruction decoder 420 is described. The flowchart ends.

  First, the instruction decoded by the instruction decoder 420 and the value executed by the execution unit 430 according to the instruction are read into the fetch unit 410 and the register file 440 (step S941). Next, the instruction decoder 420 decodes the instruction supplied from the fetch unit 410 (step S942).

  Subsequently, the execution unit 430 determines whether or not the decoded instruction is a reuse instruction with a hash value designating a reuse section (step S945). If it is determined that the decoded instruction is not a reuse instruction with a hash value, the execution result is output by executing the reuse section based on the input value supplied from the register file 440. (Step S946). Then, the process proceeds to step S954.

  On the other hand, if it is determined in step S945 that the instruction is a reuse instruction with hash value, the search request input unit 621 uses the hash value and the input value to determine whether there is an execution history in the history memory 630. It is determined whether or not (step S948). When it is determined that the execution history is not in the history memory 630, the execution section 430 executes the reuse section based on the input value supplied from the register file 440 and outputs the execution result ( Step S949). Subsequently, the execution history is registered in the history memory 630 by the history registration unit 640 (step S951). As a result, the execution history is registered in the history memory 630. Then, the process proceeds to step S954.

  On the other hand, when it is determined that the execution history is in the history memory 630, the execution result output unit 622 outputs the execution result (step S952). As a result, the execution result of the reuse section being executed is output from the history memory 630. Subsequently, the execution unit 430 stops execution of the reuse section in which the execution result is output (step S953). Then, the process proceeds to step S954.

  Then, after the processing of steps S946, S951, and S953, the execution result is written back to the register file 440 (step S954). As a result, execution of the decoded instruction is completed.

  Thus, in the fourth embodiment of the present invention, the hash value, the input value, and the execution result can be held in the history memory 630 as an execution history.

<5. Fifth embodiment>
[Configuration Example of Data Processing Device 300 in the Fifth Embodiment of the Present Invention]
FIG. 24 is a block diagram illustrating a configuration example of the data processing device 300 according to the fifth embodiment of the present invention. The data processing device 300 includes a hash function determination unit 370 in addition to the components of the data processing device 300 shown in FIG. Here, the functions of the components other than the hash function determination unit 370 and the hash conversion unit 500 are the same as those in FIG. 10, and thus description thereof is omitted here.

  The hash function determination unit 370 determines the hash function before the processor core 400 executes the program. The hash function determination unit 370 acquires the start address of the reuse interval from the object program supplied from the main storage unit 360, and generates a hash value that identifies the reuse interval with a bit width narrower than the bit width of the start address. Determine the hash function to do.

  The hash function determining unit 370 includes the hash function determining unit 200 according to the first embodiment of the present invention shown in FIG. That is, in the hash function determination unit 370 according to the fifth embodiment of the present invention, the start address acquisition unit 210 analyzes the object program and acquires the start address of the reuse section. In the fifth embodiment of the present invention, the deterministic hash function selection unit 252 supplies the selected hash function to the hash conversion unit 500. The functions of the components other than the start address acquisition unit 210 and the deterministic hash function selection unit 252 in the hash function determination unit 370 are the same as those in FIG. 3, so the details in the fifth embodiment of the present invention The detailed explanation is omitted.

  The hash function determination unit 370 supplies the determined hash function to the hash conversion unit 500.

  The hash conversion unit 500 converts the start address into a hash value for identifying the reuse section with a bit width narrower than the bit width of the start address of the reuse section. The hash conversion unit 500 holds the hash function supplied from the hash function determination unit 370. The hash conversion unit 500 generates a hash value from the function or loop start address supplied from the processor core 400 using the stored hash function. The hash conversion unit 500 supplies the generated hash value to the history management unit 600.

  As described above, in the fifth embodiment of the present invention, the hash function determination unit 370 is provided in the data processing device 300, so that the hash function can be determined using the already generated object program.

[Configuration example of the processor core 400, the hash conversion unit 500, and the history management unit 600 in the fifth embodiment of the present invention]
FIG. 25 is a block diagram illustrating a configuration example of the processor core 400, the hash conversion unit 500, and the history management unit 600 according to the fifth embodiment of the present invention. Here, a processor core 400, a hash conversion unit 500, and a history management unit 600 are shown. In addition to the processor core 400, the hash conversion unit 500, and the history management unit 600, a hash function determination unit 370 that supplies a hash function to the hash conversion unit 500 is shown here.

  The processor core 400 includes a fetch unit 410, an instruction decoder 420, an execution unit 430, and a register file 440. Note that the functions of the fetch unit 410, the instruction decoder 420, and the register file 440 in the fifth embodiment of the present invention are the same functions as the respective components shown in FIG. Omitted.

  The execution unit 430 executes the instruction analyzed in the instruction decoder 420 based on the control signal supplied from the instruction decoder 420. The execution unit 430 in the fifth embodiment of the present invention omits the function of executing the instruction specifying the hash function in the execution unit 430 shown in FIG. The functions of the execution unit 430 other than the function of executing the hash function designation instruction are the same as the functions of the execution unit 430 in the first embodiment of the present invention shown in FIG. .

  The hash conversion unit 500 converts the start address into a hash value for identifying the reuse section with a bit width narrower than the bit width of the start address of the reuse section. The hash conversion unit 500 and the confirmed hash value A generation unit 520 is provided. Note that the function of the deterministic hash value generation unit 520 in the fifth embodiment of the present invention is the same as that shown in FIG. 11, and thus detailed description thereof is omitted here.

  The deterministic hash function holding unit 510 holds the hash function supplied from the hash function determining unit 370. When the hash function is supplied from the hash function determination unit 370 via the signal line 501, the fixed hash function storage unit 510 stores the hash function, and stores the stored hash function in the fixed hash value generation unit 520. Supply.

  The history management unit 600 holds and manages the execution result of the reuse section, and includes a history target data holding unit 610, a history search unit 620, a history memory 630, and a history registration unit 640. The functions of the components of the history management unit 600 according to the fifth embodiment of the present invention are the same as the functions of the components shown in FIG. 11, and thus detailed description thereof is omitted here. .

[Operation Example of Data Processing Device 300 in the Fifth Embodiment of the Present Invention]
Next, processing of the data processing device 300 according to the fifth embodiment of the present invention will be described with reference to the drawings.

  FIG. 26 is a flowchart illustrating an example of a processing procedure of an instruction processing method performed by the data processing device 300 according to the fifth embodiment of the present invention.

  First, the hash function is determined by the hash function determination unit 370 (step S981). Note that the processing procedure example for determining the hash function of the hash function determination unit 370 is the same as the processing procedure example of the hash function determination unit 200 shown in FIGS. 8 and 9, and a description thereof will be omitted here.

  Subsequently, the hash function determined by the hash function determination unit 200 is stored in the fixed hash function storage unit 510 in the hash conversion unit 500 (step S982). Then, program execution processing for executing program instructions is performed (step S990).

  FIG. 27 is a flowchart illustrating a processing procedure example of the program execution processing (step S990) according to the fifth embodiment of the present invention. In this flowchart, the start of program execution is the start of the flowchart, and the end of program execution is the end of the flowchart.

  First, the instruction decoded by the instruction decoder 420 and the value executed by the execution unit 430 according to the instruction are read into the fetch unit 410 and the register file 440 (step S941). Next, the instruction decoder 420 decodes the instruction supplied from the fetch unit 410 (step S942).

  Subsequently, the execution unit 430 determines whether or not the decoded (decoded) instruction is a reuse instruction (step S945). If it is determined that the decoded instruction is not a reuse instruction, the reuse section is executed based on the input value supplied from the register file 440, and the execution result is output (step S946). ). Then, the process proceeds to step S954.

  On the other hand, if it is determined in step S945 that the instruction is a reuse instruction, the determined hash value generation unit 520 calculates a hash value from the start address of the reuse section (step S947). Subsequently, the search request input unit 621 determines whether there is execution information in the history memory 630 using the hash value and the input value (step S948).

  When it is determined that the execution history is not in the history memory 630, the execution section 430 executes the reuse section based on the input value supplied from the register file 440 and outputs the execution result ( Step S949). Then, the history registration unit 640 registers the execution history in the history memory 630 (step S951). As a result, the execution history is registered in the history memory 630. Then, the process proceeds to step S954.

  On the other hand, when it is determined that the execution history is in the history memory 630, the execution result output unit 622 outputs the execution result (step S952). As a result, the execution result of the reuse section being executed is output from the history memory 630. Subsequently, the execution unit 430 stops execution of the reuse section in which the execution result is output (step S953). Then, the process proceeds to step S954.

  Then, after the processing of steps S946, S951, and S953, the execution result is written back to the register file 440 (step S954). As a result, execution of the decoded instruction is completed.

  Subsequently, it is determined whether or not the execution of the program has ended (step S995). If it is determined that the execution of the program has not ended, the process returns to step S941 and the process is repeated.

  As described above, in the fifth embodiment of the present invention, the hash function is supplied from the hash function determination unit 370 to the deterministic hash function holding unit 510, so that the start address of the reuse interval of the already generated object program is obtained. A hash value can be generated.

  Thus, according to the embodiment of the present invention, the efficiency of value reuse can be improved. That is, by generating a hash value from a start address using a hash function selected from a plurality of hash functions, the hash value, input value, and execution result can be held in the history memory 630 as an execution history. This hash value is a value for identifying a reuse section with a bit width shorter than the start address.

  That is, according to the embodiment of the present invention, the amount of data held in the history memory 630 is smaller than that of the prior art device that stores the function address, input value, and execution result in the history memory 630 as the execution history. Can be reduced. Thereby, the number of execution histories held in the history memory 630 can be increased, so that the hit rate in the search can be increased.

  In addition, since the start address becomes a hash value, the number of bits compared at the time of execution history search decreases. As a result, the number of search circuits can be reduced, so that the time required for the search can be reduced.

  The embodiment of the present invention shows an example for embodying the present invention. As clearly shown in the embodiment of the present invention, the matters in the embodiment of the present invention and the claims Each invention-specific matter in the scope has a corresponding relationship. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present invention having the same names as the claims have a corresponding relationship. However, the present invention is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the gist of the present invention.

  The processing procedure described in the embodiment of the present invention may be regarded as a method having a series of these procedures, and a program for causing a computer to execute the series of procedures or a recording medium storing the program May be taken as As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disk), a memory card, a Blu-ray Disc (registered trademark), or the like can be used.

DESCRIPTION OF SYMBOLS 100 Compile processing apparatus 110 Source program memory | storage part 120 Reuse instruction discrimination | determination part 121 Reuse candidate area extraction part 122 Reuse candidate area analysis part 123 Reuse degree generation part 124 Reuse instruction conversion part 140 Machine language program generation part 150 Object program Storage unit 170 Reuse instruction generation unit with hash value 172 Hash value addition unit 200 Hash function determination unit 210, 710 Start address acquisition unit 220, 720 Candidate hash function holding unit 230, 730 Candidate hash value generation unit 240, 740 Hash value table 250 Hash function output unit 251, 751 Unique hash value list determination unit 252 Deterministic hash function selection unit 300 Data processing device 310 Primary cache 311 Instruction cache 312 Data cache 350 Bus 3 DESCRIPTION OF SYMBOLS 0 Main memory | storage part 370 Hash function determination part 400 Processor core 410 Fetch part 420 Instruction decoder 430 Execution part 440 Register file 500 Hash conversion part 510 Deterministic hash function holding | maintenance part 520 Definite hash value generation part 600 History management part 610 History object data holding part 620 History search unit 621 Search request input unit 622 Execution result output unit 630 History memory 640 History registration unit 700 Hash value determination unit 750 Hash value output unit 752 Determined hash value selection unit

Claims (16)

An analysis unit for analyzing a usage state of a plurality of instruction sections in a program and determining a reuse section in which an execution result is reused among the instruction sections;
By using a candidate function that is a candidate of a section identification value generation function for generating a section identification value for identifying the reuse section by a value having a bit width narrower than the bit width of the start address of the reuse section, the section A candidate value generating unit that generates a candidate value that is a candidate for an identification value from the start address in association with the candidate function;
A candidate value table that holds the candidate values generated by the candidate value generation unit as a candidate value list for each of the associated candidate functions;
The candidate value lists having all the candidate values different from each other are extracted, and the associated candidate function of the candidate value list selected based on the bit width of the candidate value is extracted from the extracted candidate value lists. An interval identification value generation function output unit that outputs as a value generation function;
A compile processing apparatus comprising: a machine language program generating unit that generates a machine language program in which the section identification value generation function is embedded based on the analyzed program and the section identification value generation function. The candidate function is a hash function;
The section identification value generation function output unit outputs, as the section identification value generation function, the associated hash function of the candidate value list selected based on the bit width of the candidate value in the extracted candidate value list. The compile processing apparatus according to claim 1. The hash function is a hash function having a value in a predetermined number of bits from the least significant bit of the start address as the candidate value,
The section identification value generation function output unit outputs, as the section identification value generation function, the associated hash function of the candidate value list selected based on the bit width of the candidate value in the extracted candidate value list. The compile processing apparatus according to claim 2.   The section identification value generation function output unit outputs, as the section identification value generation function, the associated candidate function of the candidate value list of the candidate value having the narrowest bit width in the extracted candidate value list. The compilation processing apparatus according to 1. The section identification value generation function output unit outputs an identifier for identifying the section identification value generation function as the section identification value generation function,
The compile processing apparatus according to claim 1, wherein the machine language program generation unit generates a machine language program in which the identifier is embedded. An execution unit that executes a plurality of instruction sections and outputs an execution result; and
Among the instruction sections, a section identification value for identifying the reuse section by a value of a bit width narrower than a bit width of a start address of a reuse section in which an execution result is reused, an input value of the reuse section, and the A history memory that holds the execution result of the reuse section as an execution history;
A data processing apparatus comprising: a history search unit that searches the execution history from the history memory based on the section identification value and the input value, and outputs the execution result when the execution history is searched. When the execution unit outputs the start address when executing the reuse section, the section identification value is generated from the start address using a section identification value generation function for generating the section identification value. Further comprising a section identification value generation unit,
The execution unit supplies the section identification value generation function to the section identification value generation unit,
The history memory holds the section identification value, the input value, and the execution result generated by the section identification value generation unit as the execution history,
The said history search part searches the said execution log from the said log | history memory based on the said area identification value and the said input value, and when the said execution log is searched, the said execution result is output. Data processing device. The execution unit supplies the section identification value generation function to the section identification value generation unit,
When the execution unit outputs the start address when the execution unit executes the reuse section, the section identification value generation unit uses the section identification value generation function supplied from the execution unit to generate the start address. The data processing apparatus according to claim 7, wherein the section identification value is generated from the data. The execution unit supplies an identifier for identifying the section identification value generation function to the section identification value generation unit,
The section identification value generation unit selects the section identification value generation function from candidate functions that are candidates for the section identification value generation function based on the identifier, and when the execution unit executes the reuse section, 8. The data processing apparatus according to claim 7, wherein when a start address is output, the section identification value is generated from the start address using the selected section identification value generation function. The execution unit supplies the section identification value to the history memory when the reuse section is executed by an instruction including the section identification value.
The history memory holds the section identification value, the input value, and the execution result as the execution history,
The said history search part searches the said execution log from the said log | history memory based on the said area identification value and the said input value, and when the said execution log is searched, the said execution result is output. Data processing device. An analysis unit for analyzing a usage state of a plurality of instruction sections in a program and determining a reuse section in which an execution result is reused among the instruction sections;
By using a candidate function that is a candidate of a section identification value generation function for generating a section identification value for identifying the reuse section by a value having a bit width narrower than the bit width of the start address of the reuse section, the section A candidate value generation unit that generates a candidate value that is a candidate for an identification value in association with the candidate function;
A candidate value table that holds the candidate values generated by the candidate value generation unit as a candidate value list for each of the associated candidate functions;
Extracting the candidate value lists whose candidate values are all different from each other, and outputting the candidate values of the candidate value list selected based on the bit width of the candidate values as the section identification value An interval identification value output unit
An instruction conversion unit for converting an instruction for calling the reuse section into an instruction with a section identification value including the section identification value;
A compile processing apparatus comprising: a machine language program generation unit that generates a machine language program in which the reuse interval is called by the instruction with interval identification value based on a source program including the instruction with interval identification value.   12. The compile processing apparatus according to claim 11, wherein the candidate value generation unit generates the candidate value by using the candidate function having a number given according to a predetermined order of the start address as an input value.   12. The compile processing apparatus according to claim 11, wherein the candidate value generation unit generates the candidate value by using the candidate function having the start address as an input value. An execution unit that executes a plurality of instruction sections and outputs an execution result; and
By using a candidate function that is a candidate of a section identification value generation function for generating a section identification value for identifying the reuse section by a value having a bit width narrower than the bit width of the start address of the reuse section, the section A candidate value generating unit that generates a candidate value that is a candidate for an identification value from the start address in association with the candidate function;
A candidate value table that holds the candidate values generated by the candidate value generation unit as a candidate value list for each of the associated candidate functions;
The candidate value lists that are all different from each other in the candidate value are extracted, and the associated candidate function of the candidate value list selected based on the bit width of the candidate value in the extracted candidate value list is the section identification value An interval identification value generation function output section to output as a generation function;
A section identification value generation unit that generates the section identification value from the start address using the section identification value generation function when the start address is output when the execution unit executes the reuse section;
A history memory that holds the section identification value, input value, and execution result of the reuse section as an execution history;
A data processing apparatus comprising: a history search unit that searches the execution history from the history memory based on the section identification value and the input value, and outputs the execution result when the execution history is searched. A data processing method in a computer comprising a candidate value table that holds candidate values that are candidates for section identification values as a candidate value list for each candidate function that generated the candidate value,
An analysis procedure for analyzing a usage mode of a plurality of instruction sections in a program and determining a reuse section in which an execution result is reused among the instruction sections;
By using the candidate function that is a candidate for the section identification value generation function for generating the section identification value for identifying the reuse section by a value of a bit width narrower than the bit width of the start address of the reuse section, A candidate value generation procedure for generating the candidate value, which is a candidate for the section identification value, from the start address in association with the candidate function;
The candidate value lists having all the candidate values different from each other are extracted, and the associated candidate function of the candidate value list selected based on the bit width of the candidate value is extracted from the extracted candidate value lists. Section identification value generation function output procedure to output as a value generation function,
A compiling method comprising: a machine language program generation procedure for generating a machine language program in which the section identification value generation function is embedded based on the analyzed program and the section identification value generation function. A program in a computer comprising a candidate value table that holds candidate values that are candidates for section identification values as a candidate value list for each candidate function that generated the candidate value,
An analysis procedure for analyzing a usage mode of a plurality of instruction sections in a program and determining a reuse section in which an execution result is reused among the instruction sections;
By using the candidate function that is a candidate for the section identification value generation function for generating the section identification value for identifying the reuse section by a value of a bit width narrower than the bit width of the start address of the reuse section, A candidate value generation procedure for generating the candidate value, which is a candidate for the section identification value, from the start address in association with the candidate function;
The candidate value lists having all the candidate values different from each other are extracted, and the associated candidate function of the candidate value list selected based on the bit width of the candidate value is extracted from the extracted candidate value lists. Section identification value generation function output procedure to output as a value generation function,
A program for causing a computer to execute a machine language program in which the section identification value generation function is embedded based on the analyzed program and the section identification value generation function.

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