JP6214455B2 - Instruction table generation apparatus, instruction decode program generation apparatus, instruction table generation method, instruction decode program generation method, and program - Google Patents

Description

  The present invention relates to an instruction table generation device, an instruction decode program generation device, an instruction table generation method, an instruction decode program generation method, and a program.

  Software such as an instruction set simulator and a disassembler includes an instruction decoding process for identifying an instruction of an instruction word given in a binary format. The instruction decoding process depends on the instruction set of a target CPU (Central Processing Unit). Therefore, in order to obtain an instruction set simulator or disassembler corresponding to a plurality of CPUs, it is necessary to develop an instruction decoding process for each CPU.

  As a method for facilitating the development of instruction decoding processing for each CPU, there is a method of performing decoding processing by inputting an instruction table holding information dependent on instruction set architecture. The instruction table is data holding format information for each instruction necessary for instruction identification. The format information necessary for instruction identification includes information on which bits in the instruction word have constants and information on values for each bit having constants. As a data structure expressing the format information, a pair of a mask pattern and an opcode pattern in which a bit string having the same length as the instruction word is associated one-to-one in the same order as the bit string of the instruction word is used.

  The mask pattern is a bit pattern that holds "1" for bits corresponding to bits having constants and "0" for other bits. The opcode pattern is a bit pattern that holds the value of the constant in the bit corresponding to the bit having the constant in the instruction word, and holds “0” in the other bits.

  In the instruction decoding process using the instruction table and the instruction word as inputs, the instruction table is circulated and an instruction is identified by finding an instruction table entry that matches the instruction word. Whether or not the instruction word matches the instruction table entry is determined by whether or not the bitwise AND of the instruction word and the mask pattern matches the opcode pattern.

  An instruction table using pairs of mask patterns and opcode patterns can be created based on an instruction encoding diagram. The instruction encoding diagram is a diagram that visually represents an instruction format, and is generally used for manual description of a CPU. In the instruction encoding diagram, the instruction format is divided for each instruction field. In each instruction field, when the instruction field is a constant, that is, an operation code field, a value of the operation code is described. In addition, when the instruction field is an arbitrary value, that is, an operand field or an unused field, a symbol indicating an operand name or a symbol indicating that it is unused is described. Further, for each instruction field, the position and size of the instruction field are described near the corresponding instruction field as necessary.

  Although it is possible to create the instruction table directly from the instruction encoding diagram, in order to make the work easier, an instruction definition body that expresses the definition of the instruction set is created, and the instruction table is created from this instruction definition body. It has been proposed to generate

  According to Japanese Patent Laying-Open No. 8-2335019 (Patent Document 1), each of a plurality of entries included in an instruction definition body has a character string representing one instruction. In the mask data table generation process, the bit position of the corresponding entry in the mask data table corresponding to the character position at which the character representing 1 or 0 appears from the character pattern of each entry in the instruction definition body representing the definition of the instruction set 0 is placed in, otherwise 0 is placed. In the operation code table generation process, 1 is placed in the bit position corresponding to the character position where the character expressing 1 appears from the character pattern of each entry in the instruction definition body, and 0 in other cases. In the operand data generation process, an operand definition field composed of one or more consecutive characters is extracted from the character pattern of each item in the instruction definition body, and operand data is generated.

  In the above publication, “1101ssdd” is given as an example of a character string. Each of the characters corresponds to the 0th to 7th bits in order from right to left. “1101” represents the opcode of the MOV instruction, “ss” represents the source register number, and “dd” represents the destination register number. In this case, “11110000” is generated in the mask data table and “11010000” is generated in the operation code table. In addition, field names ss and dd are defined. The field dd is indicated by the 0th and 1st bits, and the field ss is indicated by the 2nd and 3rd bits.

JP-A-8-2335019

  According to the method disclosed in the above publication, the operation code included in the instruction definition body must be expressed in binary. However, instruction encoding diagrams do not always use binary numbers, and for example, hexadecimal numbers are often used. In this case, the hexadecimal number must be converted to a binary number, and care must be taken not to misplace the bit position when the result is input as a character of “0” or “1”. In addition, when confirming the correctness of the input data, it may be necessary to grasp binary data while counting the number of bits, or to convert it to an expression in a radix other than 2. Also, when inputting a specific character such as “s” or “d” in the bit position corresponding to each operand, care must be taken not to make a mistake in the bit position. Furthermore, when the name of the operand field consists of a plurality of characters in the instruction encoding diagram, it is necessary to assign some kind of character such as “s” or “d”.

  As described above, in the conventional method, the labor for creating the instruction definition body is large, and errors are easily generated in the work. This becomes particularly serious when an instruction table or an instruction decoding program is developed for each of a plurality of CPUs.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to generate an instruction table or an instruction decoding program that can be automatically generated from an instruction definition body excellent in descriptiveness and readability. An apparatus, a generation method, and a program are provided.

  The instruction table generating apparatus or instruction decoding program generating apparatus of the present invention includes a syntax analysis unit and a calculation unit. The syntax analysis unit performs syntax analysis on an instruction definition body that defines an instruction set. The instruction set includes instructions defined in an instruction format having a plurality of instruction fields. The instruction definition body includes a description string representing the instruction format. The description string includes, for each of the instruction fields, a position / size related character string representing any one item of LSB position, MSB position and size, and a content character string representing contents designated in each of the instruction fields, Are described in the order of the instruction fields. The syntax analysis unit acquires a value related to the one item for each of the instruction fields based on the description string. The calculation unit calculates a value related to another item different from the one item among the LSB position, the MSB position, and the size for each of the instruction fields, using the value related to the one item acquired by the parsing unit. .

  According to the present invention, the position / size related character string described in each instruction field by the description string of the instruction definition body represents any one item of the LSB position, the MSB position, and the size. Information is calculated. Thereby, even from an instruction definition body giving priority to descriptiveness and readability, sufficient information related to the position and size of the instruction field necessary for generating the instruction table or the instruction decoding program can be obtained. Therefore, an instruction table or an instruction decoding program can be automatically generated from an instruction definition body excellent in descriptiveness and readability.

It is a block diagram which shows schematically the structure of the instruction set simulation system containing the instruction table production | generation apparatus in Embodiment 1 of this invention. An example of an instruction table using a mask pattern and an opcode pattern as instruction format information is shown. It is a flowchart which shows roughly the instruction decoding process by the instruction set simulator of FIG. FIG. 3 is an instruction encoding diagram corresponding to the instruction table of FIG. 2. It is a figure which shows the extended Bacchus-Naur notation (EBNF) showing the grammar of the instruction definition body in Embodiment 1 of this invention. FIG. 6 is a diagram illustrating an instruction format of an ADD instruction and a description of a corresponding instruction definition entry in the first embodiment of the present invention. It is a flowchart which shows schematically the production | generation method of the instruction table in Embodiment 1 of this invention. FIG. 8 is a flowchart showing more details of the instruction field position / size resolution process of FIG. 7. It is a flowchart which shows the detail of the syntax analysis process of FIG. FIG. 10 is a flowchart showing more details of the “CONTENT” part reading process of FIG. 9. FIG. 11 is a flowchart showing more details of the “CONSTANT” part reading process of FIG. 10. FIG. 9 is a diagram showing information obtained as a result of applying the syntax analysis processing of FIG. 8 to the instruction definition entry of the ADD instruction of FIG. 6. It is a flowchart which shows the detail of the position and size calculation process of FIG. It is a figure which shows the information obtained as a result of applying the field position and size calculation process of FIG. 13 to the syntax analysis result of FIG. It is a flowchart which shows the detail of the instruction table production | generation process of FIG. FIG. 16 is a flowchart showing more details of the operation code pattern generation processing of FIG. 15. FIG. 16 is a flowchart showing more details of the mask pattern generation process of FIG. 15. It is a block diagram which shows roughly the structure of the instruction set simulation system containing the instruction decoding program production | generation apparatus in Embodiment 2 of this invention. It is a figure which shows the C language code of the instruction decoding program of FIG. 18 equivalent to the instruction decoding process which inputs the instruction table of FIG. It is a flowchart which shows schematically the production | generation method of the instruction decoding program in Embodiment 2 of this invention. It is a flowchart which shows the detail of the instruction decoding program production | generation process of FIG. It is a figure which shows EBNF showing the grammar of the instruction definition body in Embodiment 3 of this invention. It is a flowchart which shows schematically the structure of the "CONSTANT" part reading process in Embodiment 3 of this invention. It is a block diagram which shows roughly the syntax analysis part in Embodiment 4 of this invention, and the input to it. It is a figure which illustrates the instruction format of the ADD instruction | indication and description of a corresponding instruction definition body entry in Embodiment 5 of this invention. FIG. 26 is a diagram illustrating information obtained as a result of applying the syntax analysis processing of FIG. 8 to the instruction definition entry of the ADD instruction of FIG. It is a flowchart which shows schematically the structure of the position and size calculation process in Embodiment 5 of this invention. FIG. 28 is a diagram illustrating information obtained as a result of applying the field position / size calculation processing of FIG. 27 to the syntax analysis result of FIG. 26; It is a block diagram which shows roughly the structure of the instruction table production | generation part of Embodiment 6 of this invention. It is a flowchart which shows schematically the structure of the opcode pattern generation process in Embodiment 6 of this invention. It is a block diagram which shows roughly the system containing the computer which performs the production | generation of an instruction table or an instruction decoding program in Embodiment 7 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a block diagram schematically showing a configuration of an instruction set simulation system 901 including an instruction table generation apparatus 101 in the present embodiment. The instruction set simulation system 901 includes an instruction definition storage unit 50, an instruction table storage unit 51, an execution target program storage unit 60, an instruction set simulator 91, and an instruction table generation device 101. The instruction definition body is data defining an instruction set, which will be described later in detail. The instruction table generation apparatus 101 includes an instruction field position / size resolution unit 110 and an instruction table generation unit 121. The instruction field position / size resolution unit 110 includes a syntax analysis unit 111 and a calculation unit 112.

  FIG. 2 shows an example of an instruction table using a mask pattern and an opcode pattern as instruction format information. This instruction table is an instruction table corresponding to four instructions of an ADD instruction, an EQ instruction, a SUB instruction, and an ABS instruction included in the instruction set of the TriCore (registered trademark) architecture of Infineon Technologies. In the bit pattern in the figure, a hyphen is inserted every 4 bits for improving readability.

ADD instruction mask pattern
0000-1111-1110-0000-0000-0000-1111-1111
When the instruction word of the ADD instruction is counted from the LSB toward the MSB (Most Significant Bit) with the LSB (least significant bit) as the 0th bit, the 27th to 21st bit And 7th to 0th bits have constants, and the other bits have arbitrary values.

The ADD instruction opcode pattern
0000-0000-0000-0000-0000-0000-1000-1011
Indicates that the bit string of the 27th to 21st bits having a constant is “0000000” and the bit string of the 7th to 0th bits having a constant is “10001011”. That is, the 27th to 21st bits are all constants “0”, the 7th, 3rd, 1st and 0th bits are constant “1”, the 6th, 5th and 4th bits. The first and second bits are the constant “0”.

  In the instruction decoding process using the instruction table and the instruction word as input, the instruction table is circulated and the instruction is identified by finding an instruction table entry matching the instruction word.

  FIG. 3 is a flowchart of instruction decoding processing in which instruction set simulator 91 (FIG. 1) decodes instructions. Steps S91 to S94 are loop processing that cycles through the instruction table entries. At each iteration of the loop, the variable i increases by 1 from 1 to the number of entries in the instruction table (4 in the case of FIG. 2). In step S92, it is determined whether or not the instruction word matches the pattern of the i-th instruction table entry. If the instruction word matches, the process branches to step S93; otherwise, the conditional branch process branches to step S94. is there. Whether or not the instruction word matches the instruction table entry is determined based on whether or not the logical product for each bit of the instruction word and the mask pattern matches the opcode pattern. In step S93, the instruction identifier of the i-th instruction table entry is stored as the instruction identifier. When step S90 is completed, an instruction identifier corresponding to the instruction word is obtained.

  FIG. 4 is a TriCore instruction encoding diagram corresponding to the instruction table (FIG. 2). Each of the ADD instruction, EQ instruction, SUB instruction, and ABS instruction is defined in an instruction format having a plurality of instruction fields.

  For example, the instruction encoding diagram of the ADD instruction is expressed by five rectangular areas separated by vertical bars, each corresponding to five instruction fields. The instruction field includes, for example, an instruction field “0x00” and an instruction field “c” that are adjacent to each other. In the command field, a hexadecimal character string starting with “0x”, an alphanumeric character string, or “-” is described. The hexadecimal character string in the instruction field is the value of the operation code that is a constant of the instruction word. The alphanumeric character string in the instruction field is the name of the operand field. For example, “a” and “b” represent data registers, and “const9” represents a 9-bit arbitrary value. In the ADD instruction, the contents of the data register “a” are added to the contents of “const9”, and the result is stored in the data register “c”. In addition, “-” in the instruction field indicates unused (empty).

  FIG. 5 shows EBNF representing the grammar of the instruction definition body in the present embodiment. The instruction definition body is a text string and is derived from the non-terminal symbol “DEFINITION”. The instruction definition body has an entry “ENTRY” for each instruction to be decoded. Each entry is a pair of an instruction identifier “ID” and an instruction format “FORMAT”. The instruction identifier “ID” is an alphanumeric character string, and the instruction format “FORMAT” is a character string in which character strings representing information for each instruction field are arranged in the same order as the instruction fields appearing in the instruction word.

  The information for each instruction field is a pair of the instruction field number “DICIMAL_NUMER” and the content “CONTENT”. “DECIMAL_NUMBER” is a decimal character string, and means the size of the instruction field in this embodiment. The content “CONTENT” of the field is a content character string of the instruction field of the instruction definition body, and is a constant character string “CONSTANT”, an operand character string “OPERAND”, or empty. The constant character string “CONSTANT” is a hexadecimal character string representation and has “0x” as a prefix. The operand character string “OPERAND” is an alphanumeric character string starting with an alphabetic character.

  When the content “CONTENT” is a constant “CONSTANT”, it means that the corresponding instruction field is a constant, that is, an opcode field for instruction identification. When the content “CONTENT” is the operand character string “OPERAND”, it means that the corresponding instruction field is an operand field. If "CONTENT" is empty, it means that the command field has an arbitrary value.

For example, the expression of the ADD instruction in the instruction definition is
4 [c] 7 [0x00] 9 [const9] 4 [a] 8 [0x8B]
It is.

  FIG. 6 shows an example of the instruction format of the ADD instruction (upper part in the figure) and the description of the corresponding instruction definition entry (lower part in the figure) in the present embodiment. The part “4 [c]” means that the 31st to 28th bits of the instruction are a 4-bit operand field identified by “c” and have an arbitrary value. The part “7 [0x00]” means that the 27th to 21st bits of the instruction are a 7-bit opcode field and a constant 0. The “9 [const9]” portion means that the 20th to 12th bit portions of the instruction are a 9-bit operand field identified by “const9” and have an arbitrary value. The part “4 [a]” means that the 11th to 8th bits of the instruction are an operand field and have an arbitrary value. The portion “8 [0x8B]” means that the 7th to 0th bits of the instruction are an 8-bit opcode field and have “8B” in hexadecimal, that is, “10001101” in binary as a constant. As described above, the instruction definition body includes a description string representing the instruction format.

  In the present embodiment, this description string is a position / size related character string (for example, “8” in the figure) representing the size of each instruction field, and a content character string representing the contents specified in each instruction field ( For example, a pair with “0x8B” in the figure (for example, “8 [0x8B]” in the figure) is described in the order of the instruction fields. The position / size related character string represents a size as described above in the present embodiment, but may represent any one item of an LSB position, an MSB position, and a size.

  FIG. 7 is a flowchart schematically showing an instruction set simulation method according to the first embodiment of the present invention. The instruction field position / size resolution process (step S30) receives the instruction definition stored in the instruction definition storage 50 (FIG. 1) as an input, and positions and sizes of all instruction fields described in the instruction definition. Is a process for solving the above by calculation. Step S60T is a process of generating an instruction table. The instruction table is generated based on the input instruction definition information and the instruction field size information calculated in step S30. The instruction table is a table having a combination of an instruction identifier, an operation code pattern, and a mask pattern as an entry. The generated instruction table is stored in the instruction table storage unit 51 (FIG. 1). The instruction set simulator 91 (FIG. 1) simulates and executes the execution target program with the contents of the instruction table storage unit 51 and the execution target program storage unit 60 (FIG. 1) as inputs.

  FIG. 8 is a flowchart showing more details of the instruction field position / size resolution process (FIG. 7: step S30). The entire process is a loop process between steps S31 and S32. This loop processing is a process of cycling through the entries of the instruction definition body, and processes one entry of the instruction definition body for each repetition.

  In the syntax analysis process (step S3000), the syntax corresponding to the non-terminal symbol “FORMAT” in FIG. 5 in the instruction definition is parsed by the syntax analysis unit 111 (FIG. 1). Thereby, the information of the instruction format described in the instruction definition body is read. In the present embodiment, in this processing, the syntax analysis unit 111 acquires a value related to the size of each instruction field based on the description string of the instruction definition body. More generally speaking, the description string describes a position / size related character string representing any one of the LSB position, the MSB position, and the size for each of the instruction fields. To obtain a value for the one item for each of the instruction fields.

  In the field position / size calculation process (step S5000), the information for each instruction field read in step S3000 is input, and the calculation unit 112 (FIG. 1) calculates the position for each instruction field. In the case of the present embodiment, since the syntax analysis unit 111 has acquired the size of the instruction field in step S3000, in step S5000, for each of the instruction fields, an item different from the size using the value related to the size, that is, The LSB position or MSB position is calculated. More generally speaking, the calculation unit 112 uses the value related to any one item of the LSB position, the MSB position, and the size acquired by the syntax analysis unit 111, for each of the instruction fields, the LSB position, the MSB position, and A value related to another item different from the one item in the size is calculated. Details of the calculation method will be described later.

  FIG. 9 is a flowchart showing more details of the syntax analysis process (FIG. 8: step S3000). This flow is a loop for reading all the "DECIMAL_NUMBER" and "CONTENT" pairs included in one entry in the instruction definition body.

  Step S3100 is processing to substitute a numerical value “1” for the variable i. Here, the variable i is an identification number assigned to the instruction field, and is assigned in order from the higher bit side (left side in FIG. 6).

  In step S3200, the “DECIMAL_NUMBER” portion of the instruction field is read. The “DECIMAL_NUMBER” portion is a character string representation of a decimal number, and represents the size of the instruction field in this embodiment.

  In step S3300, the decimal character string representation data read in step S3200 is converted into a numerical value and stored as the size of the i-th instruction field.

  Step S3400 is processing for reading the content information of the instruction field. The content information is a pair of field value and field type. Details of step S3400 are as described later.

  In step S3500, the content information of the instruction field read in step S3400 is stored as the content information of the i-th instruction field.

  In step S3600, the variable i, which is the instruction field number, is updated to a value increased by one.

  Step S3700 determines whether the end of the entry has been reached. If it is not the end, the process branches to step S3200 to read the next pair of “NUMBER” and “CONTENT”. If it is the end of the entry, the process ends.

  FIG. 10 is a flowchart showing more details of the “CONTENT” part reading process (FIG. 9: step S3400).

  In step S3401, the character “[” in the instruction definition entry is skipped.

  In step S3402, the first character at the reading position is prefetched one character, and branch processing is performed according to the value of the first character. The branch destination is step S3410 if the first character at the position is a number, step S3440 if it is an alphabetic character, and step S3470 if it is "]". Each of these three cases corresponds to the case where the content of “CONTENT” is a constant “CONSTANT”, an operand “OPERAND”, and an empty case.

  Steps S3410 to S3430 are a processing flow when the content of “CONTENT” is a constant “CONSTANT”. In step S3410, a numerical value is acquired by reading the “CONSTANT” portion. In step S3420, the value read in step S3410 is stored as a field value. In step S3430, the word “constant” is stored as the field type. The word “constant” is identification information indicating that the field has a constant.

  Steps S3440 to S3460 are processes when the content of “CONTENT” is the operand “OPERAND”. In step S3440, an alphanumeric character string starting with an alphabetic character is read from the reading position of the instruction definition body. In step S3450, the character string read as the field value is stored. In step S3460, “arbitrary value” is stored as the field type. “Arbitrary value” is identification information indicating that the field has an arbitrary value.

  Step S3470 is processing when the content of “CONTENT” is empty, and stores “arbitrary value” as the field type.

  Finally, in step S3480, the character “]” is skipped and the reading position is advanced.

  FIG. 11 is a flowchart showing more details of the “CONSTANT” part reading process (FIG. 10: step S3410).

  In step S3411, the non-terminal symbol “HEX_NUMBER” in FIG. 5, that is, a hexadecimal character string starting with “0x” is read.

  In step S3414, the character string read in step S3411 is converted into a numerical value. That is, the constant character string is converted into a numerical value by the syntax analysis unit 111 (FIG. 1).

  FIG. 12 is a diagram showing information obtained as a result of applying the syntax analysis process (FIG. 8: step S3000) to the instruction definition entry (lower part of FIG. 6) of the ADD instruction. The ADD instruction has five fields, and each size, type, and value have been acquired.

  FIG. 13 is a flowchart showing more details of the position / size calculation process (FIG. 8: step S5000). In this process, the LSB positions of all the instruction fields constituting one instruction are obtained by calculation using the result of the syntax analysis process (FIG. 8: step S3000). The value of the LSB position is a value obtained by counting up the LSB of the instruction word from the 0th bit toward the upper bit. In the calculation of the LSB position, the fact that the LSB position of the instruction field located at the lowest position in the instruction is 0 and the sizes of all the instruction fields are known are used. In the field position / size calculation process, the position of the instruction field is calculated in order from the LSB side of the instruction.

  In step S5100, variable i is initialized with the number of instruction fields. The variable i is an identification number given to the instruction field according to the same rule as the parsing process.

  In step S5300, 0 is stored as the LSB position of the i-th instruction field. Here, 0 is used because i corresponds to the lowest instruction field in the instruction at the time of step S5300.

  Steps S5400 to S5800 are a loop for sequentially obtaining the LSB position of the instruction field higher than the lowest instruction field. In this loop, the LSB positions of all instruction fields are obtained by sequentially obtaining the LSB positions of the instruction field adjacent to the instruction field whose size and LSB position are known.

  Step S5400 is a conditional branch process that performs S5700 if the value of the variable i is greater than 1, and ends the process otherwise.

In step S5700, the LSB position of the (i−1) -th field is calculated by the following calculation: LSB position of the i-th field + size of the i-th field. That is, the calculation unit 112 (FIG. 1) determines the i−1th (second) instruction field from the value regarding the LSB position for the ith (first) instruction field and the size of the ith instruction field. The value of the LSB position is calculated.

  In step S5800, variable i is updated with the value reduced by one, and the process returns to step S5400.

  FIG. 14 shows information obtained as a result of applying the field position / size calculation process (FIG. 13: step S5000) to the syntax analysis result (FIG. 12). In the field position / size calculation process, a sequence of LSB positions is acquired in the order of the arrows in the figure.

  As shown in step S5700 above, the value of the adjacent i-1th instruction field is calculated from the LSB position of the i-th instruction field and the size of the i-th instruction field. Thereby, even if the position of the field is not included in the instruction definition body, the position of the instruction field can be acquired from the size of the instruction field.

  In step S5700 (FIG. 13), calculation related to the LSB position is performed, but similarly, calculation related to the MSB position can also be performed. Specifically, the calculation unit 112 (FIG. 1) calculates the i + 1th (second) instruction field from the value regarding the MSB position for the i-th (first) instruction field and the size of the i-th instruction field. The value of the MSB position for can be calculated. In this case, the value obtained by subtracting 1 from the sum of the sizes of all the instruction fields is set as the MSB position of the first instruction field, and the MSB position is sequentially obtained from this position as a base point (in the direction opposite to the arrow in FIG. 14). May be. In this way, the LSB (MSB) position and size pair of the constant instruction field is circulated, and only the size is stored as a constant bit from the LSB position bit of the instruction field to the MSB side (from the MSB position bit to the LSB side). By providing the step of repeating the above, it is possible to acquire the position of a bit that becomes a constant in the instruction.

  More generally speaking, the calculation unit 112 calculates a value for one of the second instruction fields from a value related to one item of the LSB position and the MSB position for the first instruction field and the size of the first instruction field. The value of the item can be calculated.

  FIG. 15 is a flowchart showing more details of the instruction table generation process (FIG. 7: step S60T). The input to the instruction table generation process is information on the instruction definition body and information on the LSB position of the instruction field. The output of the instruction table generation process is an instruction table.

  Step S60T is a loop process for generating an opcode pattern and a mask pattern for all instructions included in the instruction definition body, and the variable i increases from 1 to the number of entries in the instruction definition body every time the loop is repeated. In the loop processing, an opcode pattern and a mask pattern are calculated for the i-th instruction per one iteration.

  In step S6000, an opcode pattern of the i-th instruction is generated. Details of this processing will be described later.

  In step S63T, the opcode pattern acquired in step S6000 is set as the opcode pattern of the i-th entry in the instruction table.

  In step S8000, a mask pattern for the i-th instruction is generated. Details of this processing will be described later.

  In step SS64T, the mask pattern acquired in step S8000 is set as the mask pattern of the i-th entry in the instruction table.

  In step SS65T, the instruction identifier of the i-th instruction definition body is set as the instruction identifier of the i-th instruction table entry.

  FIG. 16 is a flowchart showing more details of the operation code pattern generation process (FIG. 15: step S6000). This process takes the instruction field information as input and outputs the instruction opcode pattern.

  In step S6100, the opcode pattern is initialized with zero. The initialized opcode pattern is updated to the final opcode pattern in steps S6200 to S6800.

  Steps S6200 to S6800 are a loop that repeats the process for the number of times of the instruction field included in one instruction. The variable i increases from 1 to 1 for each iteration of the loop.

  Step S6300 is a conditional branch process that branches to step S6600 if the i-th instruction field is a constant, and branches to step S6800 otherwise. Whether or not the i-th instruction field is a constant can be determined by confirming whether or not the type of the instruction field acquired in the processing of the “CONTENT” part reading process S3400 (FIG. 9) is “constant”.

  In step S6600, the i-th instruction field constant is stored at the LSB position of the i-th instruction field in the opcode pattern.

  In this way, using the LSB (or MSB) position and size of the instruction field, the value of each bit is stored in order of the size from the LSB position bit of the instruction field to the MSB side (or from the MSB position bit to the LSB side). By providing the step of repeating the process, all constants for each bit having a fixed value in the instruction word can be obtained.

  FIG. 17 is a flowchart showing more details of the mask pattern generation process (FIG. 15: step S8000). This process takes the information in the instruction field as input and outputs a mask pattern of the instruction.

  In step S8100, the mask pattern is initialized with zero. The initialized opcode pattern is updated to a final mask pattern in steps S8200 to S8500.

  Steps S8200 to S8500 are a loop that repeats the process for the number of instruction folds included in one instruction. The variable i increases from 1 to 1 for each iteration of the loop.

  Step S8300 is a conditional branch process that branches to step S8400 if the i-th instruction field is a constant, and branches to step S8500 otherwise. Whether or not the i-th instruction field is a constant can be determined by checking whether or not the type of the instruction field acquired in the parsing process is “constant”.

  In step S8400, 1 is stored in bits corresponding to the number of sizes of the i-th field from the LSB position of the i-th field in the mask pattern toward the upper bits.

Next, instruction table generation of a comparative example will be described. In this comparative example, in order to create an instruction table entry for the TriCore ADD instruction,
cccc0000000nnnnnnnnnaaaa10001011
It is described. For this description, a character ("c", "n" or "a") representing "1", "0" or others is input with reference to the instruction encoding diagram as shown in FIG. . At this time, it is necessary to manually perform an error-prone operation such as converting an operation code described in hexadecimal to binary, or inputting characters while counting bits. In addition, it is necessary to perform error-prone operations such as counting the number of bits and converting from a binary number to another radix in order to visually check whether the instruction definition is correctly described. . Furthermore, when the name of the operation code is written in two or more characters in the instruction encoding diagram, it is necessary to omit it to one character. For example, in the case of the ADD instruction of FIG. 4, the creator of the instruction definition body must shorten the name “const9” of the operand field representing the immediate operand to one character (“n” in the above instruction definition body).

  On the other hand, according to the present embodiment, the description string of the instruction definition body describes the position / size related character string representing the size for each instruction field. Therefore, it is not necessary to include the bit position of the instruction field in the instruction definition body, and the instruction definition body can be easily described manually. Based on this size information, the LSB position (or MSB position) is calculated. Thereby, sufficient information related to the position / size of the instruction field necessary for generating the instruction table or the instruction decoding program can be obtained from the instruction definition body giving priority to descriptiveness and readability. Therefore, an instruction table or an instruction decoding program can be automatically generated from an instruction definition body excellent in descriptiveness and readability. Therefore, the development of an instruction set simulator for each CPU can be made efficient.

For one command field, between the LSB position, MSB position and size,
There is a relationship of LSB position + size-1 = MSB position. For this reason, if the values for two items of the LSB position, the MSB position, and the size are obtained, the value of the remaining one item can be easily obtained by the above formula. Thus, if one of the LSB position or size has been calculated, the other can be easily obtained. In the present embodiment, since the LSB position is calculated from the size, the MSB position can be obtained immediately by the above formula as necessary.

  Further, in the present embodiment, the case where the instruction table output by the instruction table generation device 101 is input to the instruction set simulator 91 (FIG. 1) has been described. For example, it may be input to a disassembler device.

  In the above description, the instruction table generation process (step S60T) is performed after the instruction field position / size resolution process (FIG. 7: step S30), but both processes may be performed for each entry of the instruction definition body. Good. That is, the process in which the instruction table generation process is performed after the instruction field position / size resolution process may be repeated. This is because the instruction field position and size can be resolved and the instruction table entry can be created for each entry of the instruction definition body.

(Embodiment 2)
The instruction table generation apparatus 101 (FIG. 1: Embodiment 1) receives an instruction definition body as an input and outputs an instruction table to be input to the instruction set simulator 91. On the other hand, in the present embodiment, the instruction decode program generation device outputs an instruction decode program constituting a part of the instruction set simulator 92 with the instruction definition body as an input.

  FIG. 18 is a block diagram schematically showing a configuration of an instruction set simulation system 902 including the instruction decode program generation apparatus 102 in the present embodiment. The instruction set simulation system 902 includes an instruction definition body storage unit 50, an execution target program storage unit 60, an instruction set simulator 92, and an instruction decode program generation device 102. The instruction decode program generation apparatus 102 has an instruction decode program generation unit 122. The instruction decode program generation unit 122 generates the instruction decode program 52. The instruction set simulator 92 is executed by a program including the instruction decoding program 52.

  FIG. 19 shows the C language code of the instruction decode program 52 (FIG. 18) equivalent to the instruction decode process that receives the instruction table (FIG. 2). The instruction decode program 52 is a function “Decode”. The function “Decode” inputs an instruction word as an argument “word” and calls a subfunction corresponding to each instruction type. Each subfunction is a code that simulates the operation of an instruction.

FIG. 20 is a flowchart schematically showing a method for generating an instruction decode program in the present embodiment. FIG. 21 is a flowchart showing more details of the instruction decode program generation process (FIG. 20: step S60P). In step S61P, a program start part is generated. The beginning of the program is the first half of the function. For example, the code fragment for a function that takes a 32-bit instruction word as an argument and returns an instruction identifier is:
void Decode (uint32_t word) {
It is.

The processing between steps S62P and S68P is a loop that circulates the syntax analysis instruction that has been parsed, and the variable i increases by 1 from 1 to the number of instruction table entries each time the loop is repeated. Step S6000 is processing to generate an opcode pattern by using the analyzed field information of the i-th instruction definition entry as an input. Details of step S6000 are the same as those in the first embodiment. Step S8000 is a process of generating a mask pattern using the analyzed instruction field information of the i-th instruction definition end entry as an input. Step S66P is a process of outputting a determination statement as to whether or not the instruction word matches the pattern of the instruction definition entry. This is a template like
if ((instruction & MASK_PATTERN) == OPCODE_PATTERN) {
ID (word);
}
Can be generated.

  Here, "MASK_PATTERN", "OPCODE_PATTERN", and "ID" are template parameters. In step S66P, the mask pattern acquired in step S8000 is assigned to “MASK_PATTERN”, the opcode pattern acquired in step S6000 is assigned to “OPCODE_PATTERN”, and the instruction identifier of the i-th instruction definition entry is set to “ID”. substitute. Finally, in step S69P, “}” representing the end of the function is generated.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  According to the present embodiment, the same effect as in the first embodiment can be obtained in generating an instruction decoding program instead of generating an instruction table.

  In the present embodiment, the case where the instruction decode program generating apparatus 102 outputs the instruction decode program 52 constituting a part of the instruction set simulator 92 has been described, but the program output by the instruction decode program generating apparatus is For example, an instruction decoding program that constitutes a part of the disassembler may be output. In this case, the C instruction decode program 52 (FIG. 19) is a code for outputting the instruction disassemble result.

  In the present embodiment, a C language decoding function is generated as the instruction decoding program 52 (FIG. 19), but the programming language and decoding algorithm are not limited to such.

(Embodiment 3)
According to the first embodiment, the hexadecimal opcode described in the instruction encoding diagram can be used as the hexadecimal number. However, in the instruction encoding diagram, decimal numbers or binary numbers may be used in addition to hexadecimal numbers. For this reason, if the grammar of the instruction definition body does not support anything other than hexadecimal numbers, even if it is sufficient to describe a single instruction set architecture, the radix is required manually to support multiple CPUs. Need to be converted. On the other hand, the parsing process in the present embodiment is extended to switch the process for each radix of the description of the constant in the instruction field, as will be described in detail below.

  FIG. 22 shows EBNF representing the grammar of the instruction definition body in the present embodiment. The difference from the EBNF of the first embodiment (FIG. 5) is that a binary character string “BIN_NUMBER” and a decimal character string “DECIMAL_NUMBER” are included as the contents of a non-terminal symbol “CONSTANT” of a constant character string representing a constant of an instruction field. It is a point that has been added. In the example shown in the figure, the binary character string "BIN_NUMBER" is a numeric character string with "0b" appended to the beginning for identifying the radix, and "DECIMAL_NUMBER" is a number beginning with a number from the beginning. It is a string.

  FIG. 23 is a flowchart schematically showing a configuration of the “CONSTANT” part reading process (step S3410C) in the present embodiment. This step S3410C replaces step S3410 (FIG. 10) of the first embodiment, thereby realizing switching of the radix. In other words, in this embodiment, the syntax analysis unit 111 (FIG. 1) converts the constant character string into a numerical value in consideration of the radix.

  Specifically, first, in step S3411c, the constant character string is read from the reading position, and the reading position is advanced. Here, a character string only of numbers is treated as a decimal number “DECIMAL_NUMBER”, a number character string beginning with “0x” is treated as a hexadecimal number “HEX_NUMBER”, and a number character string beginning with “0b” is treated as a binary number “BIN_NUMBER”, step S3411c. Then, these character strings are read out.

  In step S3413, branch processing is performed according to the head portion of the numeric character string read in step S3411c. Specifically, it is determined that the radix is 2 when the beginning of the numeric character string is “0b”, the radix is 16 when it is “0x”, and the radix is 10 otherwise. If the radix is 2, the process branches to step S3414b. If the radix is 10, the process branches to step S3414d. If the radix is 16, the process branches to step S3414h. In this way, the radix is determined by the syntax analysis unit 111 (FIG. 1) analyzing the constant character string in the instruction field of the instruction definition body.

  In step S3414b, the numeric character string is converted to a numeric value as a binary number. In step S3414d, the numeric character string is converted to a numeric value as a decimal number. In S3414h, the numerical character string is converted into a numerical value as a hexadecimal number. The output of the “CONSTANT” part reading process is a numerical value obtained as a result of conversion in any of steps S3414b, S3414d, and S3414h.

  Since the configuration other than the above is substantially the same as the configuration of the first or second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  According to this embodiment, by analyzing the constant character string in the instruction field of the instruction definition body, the radix used when converting the constant character string into a numerical value can be switched. This allows multiple radixes to be used when describing instruction field constants in an instruction definition. Therefore, the descriptiveness of the instruction definition body is improved. Therefore, it is possible to more easily describe instruction definition bodies for a plurality of CPUs manually.

(Embodiment 4)
In the third embodiment, the radix is determined based on the analysis of the numeric character string. In the present embodiment, the radix is determined by a configuration option given from the outside during processing.

  FIG. 24 is a block diagram schematically showing the syntax analysis unit 111C and the input thereto in the present embodiment. The syntax analysis unit 111C is configured to receive an input of the configuration option 59 separately from the instruction definition body. Configuration option 59 includes a setting that specifies a radix. In the present embodiment, the radix is determined by referring to the configuration option 59 in step S3413 (FIG. 23).

  According to the present embodiment, in the numerical character string of the “CONSTANT” part in the instruction definition body, the head part for identifying the radix as used in the third embodiment can be omitted, but the instruction definition Numeric character strings can be written in different radix for each field. For example, instead of writing “0xBEEF” in one instruction definition, “BEEF” can be written, and in another instruction definition, “0101” can be written instead of “0b0101”. That is, it is possible to generate an instruction table (or an instruction decoding program) from a plurality of instruction definition bodies having different radixes used by a single generation device.

  In other words, since the constant character string is converted into a numerical value by an external configuration option at the time of execution, the constant character string in the instruction field can be described in a different radix for each instruction definition body. In addition, since it is not necessary to represent the radix in the constant character string format itself, an instruction definition body can be created simply.

(Embodiment 5)
In the first embodiment, the instruction definition body and the instruction encoding diagram are common, and the instruction field of “4”, “7”, “9”, “4”, and “8” (FIG. 6) is used. Holds size information. On the other hand, in this embodiment, the case where the position of the instruction field is held instead of the size in the instruction definition body is handled.

FIG. 25 shows an example of the instruction format of the ADD instruction (lower part in the figure) and the description of the corresponding instruction definition entry (upper part in the figure) in the present embodiment. The instruction definition body and instruction encoding diagram share the bit position information of the MSB of the instruction field, that is, the MSB position of “31”, “27”, “20”, “11” and “7”. ing. Compared to Embodiment 1, the instruction format in the instruction definition body is the same as that of EBNF (FIG. 5) in that it is an array of “DECIMAL_NUMBER [CONTENT]”, but in the parsing, “DECIMAL_NUMBER” is not the size. It is treated as representing the position. For example, the expression of the instruction format “FORMAT” in the instruction definition body of the ADD instruction is as shown in FIG.
31 [c] 27 [0x00] 20 [const9] 11 [a] 7 [0x8B]
It is.

  FIG. 26 shows a result of applying the expression of the above instruction definition body to the parsing process described in the first embodiment. This result includes the MSB position for each field, but does not include information about the size.

  FIG. 27 is a flowchart schematically showing a configuration of position / size calculation processing (step S5000D) in the present embodiment. In the present embodiment, step S5000D is performed in an instruction field position / size resolution process (step S30) instead of step S5000 (FIG. 13). In this case, the syntax analysis result of the syntax analysis unit 111 (FIG. 1) input to the calculation unit 112 (FIG. 1) is the MSB position (FIG. 26) of each instruction field. In step S5000D, the LSB position is calculated based on this input.

  Step S5100 is processing for initializing the variable i with the number of instruction fields. Step S5200 is processing for acquiring and storing the size of the i-th instruction field based on the result of adding 1 to the MSB position of the i-th instruction field. Step S5300 is processing to store the 0th bit as the LSB position of the i-th field.

  Steps S5400 to S5800 are a processing loop for calculating the size and LSB position of the i-1st to 1st instruction fields. Step S5400 is a conditional branch process that branches to step S5500 if i is greater than 1 and ends the process otherwise. In step S5500, the size of the (i−1) -th field is obtained by subtracting the MSB position of the i-th field from the MSB position of the i−1-th field, and the value is stored. In the next step S5700, the LSB position of the (i−1) -th field is obtained by adding the LSB position of the i-th field and the size of the i-th field, and the value is stored.

  FIG. 28 shows information obtained as a result of applying the field position / size calculation process (FIG. 27: step S5000D) to the syntax analysis result (FIG. 26). In the field position / size calculation processing, each column of the LSB position and size is acquired in the order of the arrows in the figure.

  Details of the above-described processing loop (steps S5400 to S5800) performed in this syntax analysis will be described in detail below, taking an example in which the number of instruction fields is three or more as in the case of an ADD instruction.

In the loop including step S5000D (FIG. 27), when i = k + 2 (k is a natural number), in step S5500,
The size of the (k + 1) th field ← The MSB position of the (k + 1) th field−the MSB position of the (k + 2) th field is calculated.

In the next loop, i = k + 1, in step S5700,
kth field LSB position ← (k + 1) th field LSB position + (k + 1) th field size is calculated.

Summarizing the above two calculations, the following calculation is performed between the k-th, (k + 1) -th and (k + 2) -th instruction fields which are consecutively arranged instruction fields: k-th field LSB position ← (k + 1) LSB position of the second field
+ {(K + 1) th field MSB position
-MSB position of (k + 2) -th field}
Will be performed. That is, using the LSB position of the (k + 1) th instruction field and the MSB position of each of the (k + 1) th and (k + 2) th instruction fields, the LSB position of the kth instruction field is calculated by the calculation unit 112 ( Fig. 1).

For example, if k = 1,
First field LSB position ← Second field LSB position + {MSB position of second field-3 MSB position of third field}
It is. This calculation is performed by substituting specific numerical values with reference to FIG.
First field LSB position ← 21+ {27-20} = 28
Result.

When i = k + 1, in step S5500,
the size of the kth field
← MSB position of kth field − The MSB position of the (k + 1) th field is calculated. That is, the calculation unit 112 (FIG. 1) calculates the size of the kth instruction field from the difference between the MSB positions of the kth and (k + 1) th instruction fields adjacent to each other.

  Since the configuration other than the above is substantially the same as the configuration of any of Embodiments 1 to 4 described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  The instruction encoding diagram (FIG. 4) referred to in the first embodiment describes the size of each instruction field. However, an instruction definition body may be created with reference to an instruction encoding diagram without size description. In this case, the creator of the instruction definition body needs to calculate the size of the instruction field, and an error may be mixed at this time.

  On the other hand, according to the present embodiment, the LSB position and size are acquired from the MSB position of each instruction field described in the instruction definition body. Thus, the instruction definition body can be described without including the size of the instruction field. Therefore, it is possible to prevent the above errors from being mixed.

(Embodiment 6)
FIG. 29 is a block diagram schematically showing the configuration of the instruction table generation unit 121 of the present embodiment. In the present embodiment, the instruction table generation unit 121 includes a detection unit 121D. The detection unit 121D detects whether or not the instruction field that is paired with the constant character string has a size that can represent a numerical value.

  FIG. 30 is a flowchart schematically showing a configuration of the operation code pattern generation processing S6000D in the present embodiment. The difference from the step S6000 (FIG. 16) of the first embodiment is that an error detection of the instruction definition body (step S6400) is added. Step S6400 performs step S6600 if the value of the i-th instruction field can be expressed by the number of bits of the size of the i-th instruction field, but if not, reports an error and ends.

  Since the configuration other than the above is substantially the same as the configuration of any of Embodiments 1 to 5 described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

According to the present embodiment, for example, as an instruction format in an instruction definition body
4 [c] 7 [0x00] 9 [const9] 4 [a] 8 [0x8B]
Should be stated,
4 [c] 7 [0x00] 9 [const9] 4 [a] 8 [0x18B]
Can be found. In this example, “8 [0x18B]” corresponding to the fifth instruction field specifies that the 8-bit instruction field has a constant “0x18B”. However, “0x18B” is 9-bit “110001011” in binary notation and cannot be expressed in the 8-bit instruction field, so it is determined that there is an error in the description.

  As described above, by using the step of detecting that the constant of the instruction field cannot be expressed by the size of the instruction field, that is, the bit width, the user can know that the instruction definition includes an error. . It is also possible to prevent generation of an erroneous instruction table.

  When the instruction decode program is generated instead of the instruction table, the detection unit 121D may be provided in the instruction decode program generation unit 122 (FIG. 18).

(Embodiment 7)
FIG. 31 is a block diagram schematically showing a system including a computer that executes generation of an instruction table or an instruction decoding program in the present embodiment. The generation of the instruction table or instruction decoding program described in each of the above embodiments can be executed by a dedicated generation apparatus or a general-purpose computer 6000. The computer 6000 includes a CPU 6100 (processor), a RAM (Random Access Memory) 6200, a ROM (Read Only Memory) 6300, a display 6400, a storage unit 6500, an input unit 6600, a network I / F (Interface) 6700, and a recording medium reading unit 6800. Have

  The storage unit 6500 is an auxiliary storage device having an internal recording medium 6510. For example, the storage unit 6500 is a disk drive having a recording disk as the internal recording medium 6510 or a solid state drive (SSD) having a solid memory as the internal recording medium 6510. The disk drive is typically a hard disk drive having a magnetic disk. The SSD typically includes a semiconductor element memory such as a RAM or an EEPROM (Electrically Erasable Programmable Read-Only Memory).

  The network I / F 6700 can be connected to the server 8000 via the network 7700. As a result, the computer 6000 can acquire information from the server 8000. The server 8000 includes a recording medium 8010 similar to the internal storage medium 6510 described above.

  A recording medium reading unit 6800 reads an external recording medium 9010. The external recording medium 9010 is a portable recording medium, for example, a recording disk, a solid-state memory, or a recording tape. The recording disk as the external recording medium 9010 is specifically an optical disk, a magneto-optical disk, a magnetic disk, or the like. For example, a CD-ROM (Compact Disk-Read Only Memory), a DVD-ROM (Digital Versatile Disc-Read). Only Memory) or Blu-ray Disc. The solid-state memory as the external recording medium 9010 is, for example, the same as the solid-state memory included in the SSD or a ROM.

  Each of the embodiments described above can be performed by causing the CPU 6100 of the computer 6000 to execute processing for generating an instruction table or an instruction decoding program. When the computer 6000 and the server 8000 constitute a system, the program may cause the processor included in the system to execute the above processing.

  The program is typically recorded on at least one of the recording media described above. The recorded program can be provided as a program product by a recording medium or by download via the network 7700. That is, the program product includes a recording medium on which the program is recorded and the program itself.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  50 instruction definition storage unit, 51 instruction table storage unit, 52 instruction decode program, 59 configuration option, 60 execution target program storage unit, 91, 92 instruction set simulator, 101 instruction table generation device (generation device), 102 instruction decode Program generation device (generation device), 110 instruction field position / size resolution unit, 111, 111C syntax analysis unit, 112 calculation unit, 121 instruction table generation unit, 121D detection unit, 122 instruction decode program generation unit, 901, 902 instruction set Simulation system, 6000 computer, 6100 CPU, 6500 storage unit, 6510 internal recording medium, 6800 recording medium reading unit, 7700 network, 8000 server, 8010 recording medium, 90 10 External recording medium.

Claims (20)

A syntax analysis unit configured to perform syntax analysis on an instruction definition body defining an instruction set, the instruction set including an instruction defined in an instruction format having a plurality of instruction fields, wherein the instruction definition body includes the instruction A description string representing a format, wherein the description string is a position / size related character string representing any one of an LSB position, an MSB position, and a size for each of the instruction fields, and is specified in each of the instruction fields A pair with a content character string representing the content to be processed is described in the order of the instruction field, and the syntax analysis unit calculates a value related to the one item for each of the instruction fields based on the description string. Acquired,
A calculation unit that calculates a value related to another item different from the one item among the LSB position, the MSB position, and the size for each of the instruction fields by using the value related to the one item acquired by the parsing unit; Prepare
Instruction table generator. The content string of the instruction field of the instruction definition includes a constant string;
The instruction table generation device according to claim 1, wherein the syntax analysis unit converts the constant character string into a numerical value in consideration of a radix.   The instruction table generation device according to claim 2, wherein the syntax analysis unit determines the radix by analyzing a constant character string in an instruction field of the instruction definition body.   The instruction table generation device according to claim 2, wherein the syntax analysis unit receives an input specifying the radix separately from the instruction definition body. The instruction field includes first and second instruction fields adjacent to each other;
The calculation unit calculates the value of the one item for the second instruction field from the value for one item of the LSB position and the MSB position for the first instruction field and the size of the first instruction field. The instruction table generation device according to claim 1, wherein The instruction field includes kth and (k + 1) th instruction fields, where k is a natural number,
2. The instruction table generation device according to claim 1, wherein the calculation unit calculates a size of a k-th instruction field from a difference between MSB positions of the k-th and (k + 1) -th instruction fields. The instruction field includes kth, (k + 1) th and (k + 2) th instruction fields, where k is a natural number,
The calculation unit calculates the LSB position of the k-th instruction field using the LSB position of the (k + 1) -th instruction field and the MSB position of each of the (k + 1) -th and (k + 2) -th instruction fields. The instruction table generation device according to claim 1. The content string of the instruction field of the instruction definition includes a constant string;
The parsing unit converts the constant character string into a numerical value,
The instruction table generation device according to claim 1, further comprising: a detection unit configured to detect whether a pair of the instruction field that is paired with the constant character string has a size capable of expressing the numerical value. A syntax analysis unit configured to perform syntax analysis on an instruction definition body defining an instruction set, the instruction set including an instruction defined in an instruction format having a plurality of instruction fields, wherein the instruction definition body includes the instruction A description string representing a format, wherein the description string is a position / size related character string representing any one of an LSB position, an MSB position, and a size for each of the instruction fields, and is specified in each of the instruction fields A pair with a content character string representing the content to be processed is described in the order of the instruction field, and the syntax analysis unit calculates a value related to the one item for each of the instruction fields based on the description string. Acquired,
A calculation unit that calculates a value related to another item different from the one item among the LSB position, the MSB position, and the size for each of the instruction fields by using the value related to the one item acquired by the parsing unit; Prepare
Instruction decode program generator. The content string of the instruction field of the instruction definition includes a constant string;
The instruction decoding program generation device according to claim 9, wherein the syntax analysis unit converts the constant character string into a numerical value in consideration of a radix.   The instruction decoding program generation apparatus according to claim 10, wherein the syntax analysis unit determines the radix by analyzing a constant character string in an instruction field of the instruction definition body.   The instruction decoding program generation apparatus according to claim 10, wherein the syntax analysis unit receives an input specifying the radix separately from the instruction definition body. The instruction field includes first and second instruction fields adjacent to each other;
The calculation unit calculates the value of the one item for the second instruction field from the value for one item of the LSB position and the MSB position for the first instruction field and the size of the first instruction field. 10. The instruction decode program generation device according to claim 9, wherein The instruction field includes kth and (k + 1) th instruction fields, where k is a natural number,
The instruction decoding program generation device according to claim 9, wherein the calculation unit calculates the size of the k-th instruction field from a difference between MSB positions of the k-th and (k + 1) -th instruction fields. The instruction field includes kth, (k + 1) th and (k + 2) th instruction fields, where k is a natural number,
The calculation unit calculates the LSB position of the k-th instruction field using the LSB position of the (k + 1) -th instruction field and the MSB position of each of the (k + 1) -th and (k + 2) -th instruction fields. The instruction decoding program generation device according to claim 9. The content string of the instruction field of the instruction definition includes a constant string;
The parsing unit converts the constant character string into a numerical value,
The instruction decoding program generation device according to claim 9, further comprising a detection unit configured to detect whether or not a pair of the instruction field and the constant character string has a size capable of expressing the numerical value. . The instruction analysis unit includes a step of performing parsing with respect to an instruction definition body defining an instruction set, the instruction set including an instruction defined in an instruction format having a plurality of instruction fields, and the instruction definition body includes: A description string representing the instruction format, wherein the description string includes a position / size related character string representing any one of an LSB position, an MSB position, and a size for each of the instruction fields; and each of the instruction fields A description is given of a pair with a content character string representing the content specified in the order of the instruction fields, and the step of performing the syntax analysis is performed by the syntax analysis unit based on the description sequence. Obtaining a value for said one item for each;
The calculation unit calculates a value related to another item different from the one item among the LSB position, the MSB position, and the size for each of the instruction fields using the value related to the one item acquired by the parsing unit. Further comprising
Instruction table generation method. The instruction analysis unit includes a step of performing parsing with respect to an instruction definition body defining an instruction set, the instruction set including an instruction defined in an instruction format having a plurality of instruction fields, and the instruction definition body includes: A description string representing the instruction format, wherein the description string includes a position / size related character string representing any one of an LSB position, an MSB position, and a size for each of the instruction fields; and each of the instruction fields A description is given of a pair with a content character string representing the content specified in the order of the instruction fields, and the step of performing the syntax analysis is performed by the syntax analysis unit based on the description sequence. Obtaining a value for said one item for each;
The calculation unit calculates a value related to another item different from the one item among the LSB position, the MSB position, and the size for each of the instruction fields using the value related to the one item acquired by the parsing unit. Further comprising
Instruction decoding program generation method. A program for causing a computer to generate an instruction table, wherein the program is
A step of performing a parsing by the parsing unit on an instruction definition that defines an instruction set, wherein the instruction set includes an instruction defined in an instruction format having a plurality of instruction fields; , Including a description string representing the instruction format, and the description string includes, for each of the instruction fields, a position / size related character string representing any one item of an LSB position, an MSB position, and a size; A pair with a content character string representing a content designated in each is described in the order of the instruction fields, and the step of performing the syntax analysis is performed by the syntax analysis unit based on the description sequence. Obtaining a value for said one item for each of
The calculation unit calculates a value related to another item different from the one item among the LSB position, the MSB position, and the size for each of the instruction fields using the value related to the one item acquired by the parsing unit. To make it run,
program. A program for causing a computer to generate an instruction decoding program, the program being executed by the computer,
A step of performing a parsing by the parsing unit on an instruction definition that defines an instruction set, wherein the instruction set includes an instruction defined in an instruction format having a plurality of instruction fields; , Including a description string representing the instruction format, and the description string includes, for each of the instruction fields, a position / size related character string representing any one item of an LSB position, an MSB position, and a size; A pair with a content character string representing a content designated in each is described in the order of the instruction fields, and the step of performing the syntax analysis is performed by the syntax analysis unit based on the description sequence. Obtaining a value for said one item for each of
The calculation unit calculates a value related to another item different from the one item among the LSB position, the MSB position, and the size for each of the instruction fields using the value related to the one item acquired by the parsing unit. To make it run,
program.

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