JP2011090434A - Image processing controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To properly perform a refresh operation according to the status of the use of each DRAM. <P>SOLUTION: An image processing controller includes a plurality of DRAMs requiring a refresh operation, a storage means for storing an individual transition time for effecting the transition of each of the DRAMs to self-refresh, a monitoring means for monitoring access to the DRAMs, and a memory control means for making the DRAM non-accessed within the transition time to perform self-refresh accompanied by the suspension of the supply of an operation clock. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing controller including a memory that requires a refresh operation.

  Conventionally, an image processing controller for performing predetermined processing on input data is mounted on an image forming apparatus such as a printing apparatus or a scanner. The image processing controller includes a plurality of DRAMs, and performs various processes on input data based on data or programs developed in each DRAM.

  The DRAM needs to be rewritten (refreshed) in a predetermined period in order to keep the stored contents. This refresh operation is executed after the elapse of a predetermined period or when access to the DRAM is not performed for a predetermined period, and the stored content can be maintained for a long period of time (see, for example, Patent Document 1). ).

JP 2008-44223 A

  When the image processing controller includes a plurality of DRAMs and performs a refresh operation according to a time when access is not performed (hereinafter referred to as a transition time), the transition period is increased for a DRAM having a high access frequency. However, if the transition period is collectively set based on a DRAM having a high access frequency, a waiting time occurs in a DRAM having a low access frequency, and an appropriate refresh operation may not be performed.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an image processing controller capable of appropriately performing a refresh operation in accordance with the use state of each DRAM.

  In order to solve the above problems, in the present invention, a plurality of DRAMs that require a refresh operation, storage means for storing individual transition times until each DRAM is shifted to self-refresh, and access to the DRAMs are provided. Monitoring means for monitoring, and memory control means for executing self-refreshing with stopping supply of the operation clock for the DRAM that does not generate access within the transition time are configured.

In the invention configured as described above, in the image processing controller including a plurality of DRAMs that require a refresh operation, the monitoring unit monitors accesses to the DRAM based on the individual transition times stored in the storage unit. The memory control means executes a self-refresh that accompanies the stop of the supply of the operation clock for the DRAM that does not access within the transition time. Here, for a DRAM having a high access frequency, the transition time stored in the storage means is lengthened, and for a DRAM having a low access frequency, the stored transition time is shortened, thereby using the DRAM. Can be set individually.
Therefore, since the DRAM shifts to self-refresh according to the transition time set for each DRAM, it is possible to appropriately perform the refresh operation according to the usage status of each DRAM. In addition, since this self-refreshing involves stopping the supply of the operation clock, the refresh operation can be executed while reducing power consumption.

In addition, various settings can be made as the transition time set for each DRAM. As an example, the plurality of DRAMs may have different transition times for shifting to self-refresh.
In the invention configured as described above, it is possible to set the transition time according to the usage status of the DRAM by changing the transition time according to each DRAM.

  As an example of a method for storing data in the DRAM, the memory control unit may store data having a high access frequency in the DRAM having a long transition time. In the invention configured as described above, by collecting and storing frequently accessed data in a frequently accessed DRAM, it is possible to reduce the access frequency of other DRAMs and facilitate the transition to self-refresh. Become.

Further, as an example of a transition time setting method, the memory control unit may change the transition time according to the access frequency of each DRAM.
In the invention configured as described above, it is possible to set the transition time according to the actual use state of the DRAM, and it is possible to execute the refresh operation more appropriately.

The memory control means may be configured to shift the image processing controller to a power saving mode when all DRAMs shift to self-refresh.
In the invention configured as described above, the power consumption can be further reduced by setting the condition for shifting to the power saving mode when all the DRAMs shift to the self-refresh.

  In addition, various products can be assumed as products on which the image processing controller is mounted. As an example, the image processing controller may be mounted on a printing apparatus that forms an image, and includes a scanner unit. The image reading apparatus may be mounted on an image reading apparatus, or may be mounted on a multi-function peripheral having an image reading unit including a printing unit that forms an image and a scanner unit.

FIG. 2 is a block configuration diagram for explaining a configuration of the printing apparatus 10. 2 is a block configuration diagram for explaining functions of an ASIC 90. FIG. It is an image figure for demonstrating the time table T. FIG. 5 is a state transition diagram illustrating a refresh operation executed by the image processing controller 100. FIG. It is a figure explaining the relationship between the access request | requirement with respect to each DRAM, the time which the timer 72 measures, and self refresh. 10 is a flowchart for explaining processing in which the first memory controller according to the second embodiment distributes a development destination DRAM according to data access frequency. It is a block block diagram which shows the reader 20 by which the image processing controller 100 concerning this invention is mounted.

Hereinafter, embodiments of the present invention will be described in the following order.
(1) First embodiment:
(2) Second embodiment:
(3) Third embodiment:
(4) Other embodiments:

(1) First embodiment:
Hereinafter, a first embodiment of an image processing controller according to the present invention will be described with reference to the drawings. In the first embodiment, the image processing controller is used as a part of the printing apparatus.

  FIG. 1 is a block diagram for explaining the configuration of the printing apparatus 10. The printing apparatus 10 includes an image processing controller 100, a CPU 91, a print engine 92, and an input IF 93. The image processing controller 100 includes an ASIC 90 and DRAMs 1 to n. Here, the ASIC 90 is connected to the CPU 91, the DRAMs 1 to n, the print engine 92, and the input IF 93 via a bus. In this embodiment, the CPU 91 is connected to the outside of the ASIC 90, but the CPU 91 may be mounted inside the ASIC 90.

  The CPU 91 controls driving in the printing apparatus 10. For example, the CPU 91 causes the ASIC 90 to execute image processing based on the data input through the input IF 93 and causes the print engine 92 to execute print processing based on the processed data.

  The DRAMs 1 to n store various data for driving the printing apparatus 10. This data is downloaded from a ROM (not shown) when the printing apparatus 10 is turned on. The DRAMs 1 to n are connected to the ASIC 90 via a memory bus, and addresses and commands to be accessed by the DRAMs 1 to n are specified in a control signal output from the ASIC 90 in response to an access request from the CPU 91. Is executed.

  Further, the DRAMs 1 to n require a refresh operation for holding stored contents. This refresh operation includes CBR refresh that is executed after an access request is issued to SDRAMs 1 to n and self-refresh that is executed when there is no access request for SDRAMs 1 to n for a predetermined time. Here, since the self refresh stops the supply of the internal clock to the SDRAM at the time of execution, the power consumption is lower than the CBR refresh. The SDRAMs 1 to n are not particularly limited as long as they require a refresh operation, and examples thereof include “Synchronous SDRAM” and “Rambus SDRAM”. Hereinafter, description will be made based on the SDRAM.

  The ASIC 90 accesses the SDRAMs 1 to n and executes predetermined processing on the referenced data. Therefore, the ASIC 90 includes a CPU_I / F 81 for connecting to the CPU 91, an image processing circuit 82 for performing predetermined processing on input data, a first memory controller 83 and a second memory controller 83 for accessing the SDRAMs 1 to n. And a memory controller 84. Further, each part constituting the ASIC 90 is connected via a bus and can communicate data with each other.

  FIG. 2 is a block configuration diagram for explaining the function of the ASIC 90. The first memory controller 83 is connected to the input IF 93, the CPU_I / F 81, and the image processing circuit 82, receives an access request from the CPU 91, and controls access to the DRAMs 1 to n. The first memory controller 83 also stores a time table T for storing the time until each SDRAM 1 to n shifts to the refresh operation, 71 and the time until an access request to the SDRAM 1 to n is input. A timer 72 for counting, a monitoring unit (monitoring means) 73 for monitoring the transition time of the SDRAMs 1 to n based on the time information timed by the timer 72, and for controlling access and refresh operations to the SDRAMs 1 to n A memory control unit (memory control means) 74.

  FIG. 3 is an image diagram for explaining the time table T. As shown in FIG. 3, the time table T stores SDRAM 1 to n and the transition time of each SDRAM 1 to n in association with each other. As described above, the SDRAMs 1 to n execute self-refresh when an access request is not made for a predetermined time, so this transition time defines a time during which no access request is made. In the first embodiment, the transition time is set to an individual time set in advance according to the use of the SDRAMs 1 to n. That is, a long transition time is set for an SDRAM having a high access frequency, and a short transition time is set for an SDRAM having a low access frequency.

  The second memory controller 84 is connected to the first memory controller 83 via a bus, and is connected to the SDRAMs 1 to n via a memory bus. The second memory controller 84 receives the refresh signal output from the memory control unit 74 of the first memory controller 83, and causes the SDRAMs 1 to n to execute the refresh operation. The second memory controller 84 selects the clock generator 61 that supplies a clock to the SDRAMs 1 to n and the SDRAMs 1 to n to be accessed or refreshed in accordance with a control signal output from the first memory controller 83. And a selector 62 for this purpose.

  The print engine 92 forms an image based on data that has been subjected to predetermined processing by the image processing circuit 82 of the ASIC 90. The print engine 92 is, for example, an optical system that forms a latent image on the photosensitive member, a fixing device that fixes each color of cyan, magenta, yellow, and black included in the toner to the photosensitive member. A transfer roller for transferring each color is used. Hereinafter, the refresh operation in the printing apparatus 10 having such a configuration will be described.

  FIG. 4 is a state transition diagram for explaining a refresh operation executed by the image processing controller 100. In the idle state (step S1) when the main power supply of the printing apparatus 10 is turned on and the predetermined period has passed, since there is no access request from the CPU 91 to the first memory controller 83, each of the SDRAMs 1 to n does not shift to the refresh operation.

  When an access request is issued from the CPU 91 to the SDRAM 1 (step S2), the SDRAM 1 shifts to an access state (step S3). Specifically, the first memory controller 83 that has received an access request from the CPU 91 via the CPU_I / F 81 outputs a command (read / write access) to the second memory controller 84. In this read / write access, an address at which the CPU 91 requests access is designated, and the second memory controller 84 outputs a read / write access to the SDRAM having this address. Thereafter, the second memory controller 84 executes access to the SDRAM having the address corresponding to the access type (read or write). Hereinafter, as an example, description will be given based on self-refresh in the SDRAM 1.

  When the access to the SDRAM 1 is completed, the first memory controller 83 causes the SDRAM 1 to perform CBR refresh (step S4). That is, the memory control unit 74 of the first memory controller 83 outputs a CBR refresh signal to the second memory controller 84. The second memory controller 84 receives this CBR refresh signal and causes the corresponding SDRAM 1 to execute CBR refresh. At this time, the clock generator 61 of the second memory controller 84 generates an internal clock from a clock signal supplied from an external clock (not shown) (for example, a clock obtained by 1 / n the clock period output from the first memory controller 83). Then, the corresponding SDRAM is caused to execute CBR refresh synchronized with the internal clock.

  The monitoring unit 73 of the first memory controller 83 counts the time (transition time) until an access request from the CPU 91 is input according to the time information counted by the timer 72, and this count time is the time. When the transition time stored in the table T is exceeded (step S5), the corresponding SDRAM is caused to execute self-refresh (step S6). As described above, the transition time corresponding to each SDRAM 1 to n is set in the time table T, and the monitoring unit 73 of the first memory controller 83 determines each SDRAM 1 according to the time information measured by the timer 72. The time of ~ n is monitored.

  FIG. 5 is a diagram for explaining the relationship between an access request to each SDRAM, the time measured by the timer 72, and self-refresh. In the following description, the transition time of SDRAM 1 is 10 clocks, the transition time of SDRAM 2 is 20 clocks, and the transition time of SDRAMn is 5 clocks. As shown in FIG. 5, for the SDRAM 1, when an access request is input from the CPU 91 after the timer 72 measures 0 to 4 clocks, the time during which the access request is not made is stored in the time table T. Since the transition time is not reached, the SDRAM 1 does not execute self refresh.

On the other hand, when the measurement time of the timer 72 reaches 10 clocks, the ASIC 90 shifts the SDRAM 1 to the self-refresh because the time when the access request to the SDRAM 1 is not made reaches the transition time stored in the time table T. At this time, the memory control unit 74 of the first memory controller 83 outputs a self-refresh signal for the SDRAM 1 to the second memory controller 84. For this reason, the second memory controller 84 receives this self-refresh signal, and selects the SDRAM 1 as the SDRAM for executing the self-refresh by the selector 62. At this time, the clock generator 61 receives the external clock signal but does not transmit the internal clock to the selector 62. Therefore, the SDRAM 1 executes self refresh without synchronizing with the internal clock (step S6).
Similarly, the SDRAM 2 shifts to self-refresh only when the transition time reaches 20 clocks, and the SDRAM n shifts to self-refresh only when the transition time reaches 5 clocks.

  Thereafter, when an access request is made from the CPU 91 to the SDRAM 1 (step S7), the first and second memory controllers stop the SDRAM 1 self-refresh and shift to the idle state (step S1).

  As described above, the use time in the DRAM may be individually set by increasing the transition time for a DRAM having a high access frequency and shortening the transition time for a DRAM having a low access frequency. A refresh operation can be appropriately executed in accordance with the usage status of each DRAM. Further, since this self-refreshing involves stopping the supply of the operation clock, the refresh operation can be executed while reducing power consumption. The first embodiment has been described above.

=== Modification ===
In addition to the configuration of the printing apparatus 10 according to the first embodiment described above, when all the SDRAMs 1 to n shift to the self-refresh operation, the image processing controller 100 may shift to the standby mode. That is, all the SDRAMs 1 to n shift to the self-refresh state because no access request is made for the SDRAMs 1 to n for a predetermined time. Therefore, even if the image processing controller 100 shifts to the standby mode with low power consumption, there is a problem. There is no. By using the self-refresh in the SDRAMs 1 to n as a condition for shifting to the standby mode in the printing apparatus 10, it is possible to further reduce power consumption without affecting the operation of the printing apparatus 10.

(2) Second embodiment:
The access frequency to the SDRAM changes according to the use frequency of the data stored in the SDRAM. For example, when the data expanded in the SDRAM 1 is a program that is always executed in the printing process in the printing apparatus 10, the access frequency to the SDRAM 1 is high. For this reason, in the printing apparatus 10 according to the first embodiment, by frequently allocating frequently accessed data to a predetermined SDRAM, the access frequency of other SDRAMs can be reduced and the self-refresh operation can be easily performed. Is possible. Hereinafter, the printing apparatus 10 according to the second embodiment will be described.

  FIG. 6 is a flowchart for explaining a process in which the first memory controller 83 according to the second embodiment distributes the development destination SDRAM according to the data access frequency. In the flowchart shown in FIG. 6, a process for distributing data to SDRAMs 1 to 3 having different access frequencies will be described. The access frequencies of the SDRAMs 1 to 3 are assumed to be lower in the order of SDRAM1, SDRAM2, and SDRAM3 in accordance with the transition time stored in the time table T.

  In step S11 of FIG. 6, the first memory controller 83 determines the access frequency of the SDRAMs 1 to 3. As an example, the memory control unit 74 determines the access frequency of the SDRAMs 1 to 3 based on the transition time stored in the time table T.

  In step S <b> 12, the first memory controller 83 determines whether there is data having the “highest” access frequency of data developed in the SDRAMs 1 to 3. As an example, the first memory controller 83 stores the access frequency of each data in advance, and makes a determination for each data input. In the second embodiment, data read / written at the time of printing or a program downloaded from a ROM (not shown) is set as data having the highest access frequency. That is, when the printing apparatus 10 generates bitmap data using the PDL language, the reference value or program used to generate the bitmap data is set as data having the highest access frequency. In the case where the printing apparatus 10 is a host-based system, similarly, data and programs that are referred to for print processing are set as data having the highest access frequency.

  In step S <b> 13, the first memory controller 83 stores in the SDRAM 1 data determined to be “highest” access frequency to the second memory controller 84. Therefore, the SDRAM 1 stores the program determined to have the highest access frequency in step S12.

  In step S <b> 14, the first memory controller 83 determines whether there is data with “medium” access frequency. Here, the “medium” access frequency is lower than the access frequency determined in step S12, and is a preset value. Thereafter, in step S15, the first memory controller 83 stores in the SDRAM 2 the data that the access frequency of the second memory controller 84 is determined to be “medium”.

  In step S16, the first memory controller 83 stores the remaining data in the SDRAM 3. The data stored in the SDRAM 3 is lower than the access frequency determined in step S14.

  In the above series of processing, the SDRAMs 1 to 3 each store data according to the access frequency. Therefore, although access to the SDRAM 1 is concentrated, the access frequencies of the SDRAMs 2 and 3 and the other SDRAMs 4 to N decrease in order, so that the self-refresh can be easily performed. Even in the SDRAM 1 whose access frequency is high, since the CBR refresh is executed for each access as shown in FIG. 3, the data stored in the SDRAM 1 is not impaired. The second embodiment has been described above.

(3) Third embodiment:
In the printing apparatus 10 according to the first and second embodiments, the transition time for the SDRAMs 1 to n is a fixed value. However, the transition time may be variable according to the use status of the SDRAM. That is, the first memory controller 83 counts the number of accesses of the SDRAMs 1 to n, and updates each transition time stored in the time table T according to the count result. Specifically, the memory control unit 74 increases the transition time for an SDRAM with a large number of accesses, and shortens the transition time for an SDRAM with a small number of accesses. By combining the configuration according to the third embodiment described above with the configuration according to the first and second embodiments, it is possible to set the transition time according to the actual usage status of the SDRAMs 1 to n. It is possible to execute the refresh operation more appropriately.

(4) Other embodiments:
A product on which the image processing controller 100 is mounted is not limited to a printing apparatus. FIG. 7 is a block diagram showing a reading device 20 in which the image processing controller 100 according to the present invention is mounted. In the reading device 20 shown in FIG. 7, a scanner engine 21 including a scanner unit is configured to be connected to the ASIC 90, and the function thereof is the same as that of the first to third embodiments described above.
Further, the product on which the image processing controller 100 is mounted may be a multi-function machine including the reading device 20 and the printing device 10.

  Further, the processing executed by the first memory controller 83 may be executed by a program stored in the CPU 91 and a ROM (not shown).

  Needless to say, the present invention is not limited to the above embodiments. That is, the mutually replaceable members and configurations disclosed in the above embodiments are applied by changing their combinations as appropriate. The members and configurations disclosed in the examples can be replaced with the members and configurations interchangeable with each other as appropriate, and the combination thereof is changed and applied. It is one of the present invention that a person skilled in the art can appropriately substitute the members and configurations that can be assumed as substitutes for the members and configurations disclosed in the above-described embodiments based on the above, and change the combination to apply. It is disclosed as an example.

  DESCRIPTION OF SYMBOLS 10 ... Printing apparatus, 20 ... Reading apparatus, 21 ... Scanner engine, 61 ... Clock generator, 62 ... Selector, 71 ... Memory, 72 ... Timer, 73 ... Monitoring part, 74 ... Memory control part, 81 ... CPU_I / F, 82 ... Image processing circuit 83 ... First memory controller 84 ... Second memory controller 91 ... CPU 92 ... Print engine 93 ... Input IF 100 ... Image processing controller

Claims (8)

A plurality of DRAMs that require a refresh operation;
Storage means for storing individual transition times until each DRAM is shifted to self-refresh;
Monitoring means for monitoring access to the DRAM;
An image processing controller, comprising: memory control means for executing a self-refresh that accompanies an operation clock supply stop for a DRAM that does not generate an access within the transition time.   The image processing controller according to claim 1, wherein the plurality of DRAMs have different transition times for shifting to self-refresh.   The image processing controller according to claim 1, wherein the memory control unit stores data having a high access frequency in a DRAM having a long transition time.   The image processing controller according to any one of claims 1 to 3, wherein the memory control unit changes a transition time according to an access frequency of each DRAM.   5. The image according to claim 1, wherein the memory control unit shifts the image processing controller to a power saving mode when all the DRAMs shift to self-refresh. 6. Processing controller.   The image processing controller according to any one of claims 1 to 5, wherein the image processing controller is mounted on a printing apparatus that forms an image.   The image processing controller according to any one of claims 1 to 5, wherein the image processing controller is mounted on an image reading device including a scanner unit.   6. The image processing controller according to claim 1, wherein the image processing controller is mounted on a multifunction peripheral having a printing unit that forms an image and an image reading unit including a scanner unit. Image processing controller.

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