JP2011087397A - Differential protective relay device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential protective relay device for suppressing a delay of operation output in a sound phase even if a failure develops from a one-phase external failure to an another-phase internal failure. <P>SOLUTION: The presence or absence of a failure is detected based on a differential current computed by a line current obtained from each current transformer installed in each line connected to a bus to be protected. When the detected failure is an external failure, a faulty phase in the external failure is determined. When the faulty phase is another phase, a control for stopping processing for extending a detection state, where the detected failure has been determined to be the external failure, is made. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a differential protection relay device having a current transformer (hereinafter abbreviated as “CT”) saturation countermeasure function.

  The conventional differential protection relay device is configured not to malfunction even if CT is saturated to some extent by the CT saturation countermeasure function. Specifically, when a failure is detected, a determination is made as to whether the failure is an external failure or an internal failure (hereinafter referred to as “internal / external determination”). It is common to employ a method of suppressing the operation or locking the operation.

  As a differential protection relay device to which the above method is applied, for example, there is one shown in Patent Document 1 below. In this Patent Document 1, timer means and one-shot multi-timer means are provided at an output stage of a signal for locking an operation output, and outputs of these timer means and one-shot multi-timer means are connected to an inhibit means which is an output means of the apparatus. By operating as an input, the lock time is shortened, and the operation output is prevented from being significantly delayed when progressing from an external failure to an internal failure.

Japanese Patent Laid-Open No. 10-42455

  However, in the conventional differential protection relay device represented by the above-mentioned Patent Document 1, since the inside / outside determination is performed for each phase individually, for example, in the case of a one-phase failure, the influence of the failure phase is the health of the other phase. There is also a possibility that an external failure may be detected even in a healthy phase of the other phase. In this case, since the operation output is locked for a certain period of time even in the healthy phase in which an external failure is detected, if the failure progresses from one-phase external failure to another phase internal failure, the healthy phase that has already determined the external failure There was a problem that operation output was delayed.

  The present invention has been made in view of the above, and even when a failure progresses from a one-phase external failure to another phase internal failure, a differential that can suppress a delay in operation output in a healthy phase An object is to provide a protective relay device.

  In order to solve the above-described problems and achieve the object, the differential protection relay device according to the present invention uses a line current obtained from each current transformer installed in each line connected to the bus to be protected. A failure detection unit that detects the presence or absence of a failure based on the calculated differential current; an external failure detection unit that detects whether the failure is an external failure based on the line current and the differential current; and An external failure detection state extension unit that extends the detection state that the external failure detection unit is an external failure, and an operation output lock unit that locks the operation output from the failure detection unit by the output of the external failure detection state extension unit, A fault phase process activation control unit that determines a fault phase in an external fault based on each line current and controls the validity / invalidity of the processing of the external fault detection state extension unit corresponding to the fault phase. The features.

  According to the differential protection relay device according to the present invention, even when the failure progresses from one-phase external failure to another-phase internal failure, it is possible to suppress the delay in the operation output in the healthy phase. Play.

FIG. 1 is a diagram illustrating a configuration of a power system (protected system) in which a differential protection relay device according to a first embodiment of the present invention is arranged. FIG. 2 is a functional block diagram of the differential protection relay device according to the first embodiment of the present invention. FIG. 3 is a diagram schematically showing an external one-phase ground fault occurring in the power system. FIG. 4 is a diagram showing an equivalent circuit when the external one-phase ground fault in the system of FIG. 3 is an A-phase ground fault. FIG. 5 is a flowchart showing the processing of the failure phase determination unit. FIG. 6 is a functional block diagram of the differential protection relay device according to the second exemplary embodiment of the present invention. FIG. 7 is a functional block diagram of the differential protection relay device according to the third embodiment of the present invention. FIG. 8 is a functional block diagram illustrating an example of the function of the change width detection unit. FIG. 9 is a functional block diagram of the differential protection relay device according to the fourth embodiment of the present invention.

  Exemplary embodiments of a differential protection relay device according to the present invention will be explained below in detail with reference to the accompanying drawings. In addition, this invention is not limited by embodiment shown below.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration of a power system (protected system) in which a differential protection relay device according to a first embodiment of the present invention is arranged. In the example shown in FIG. 1, each line 60 (60 ₁ , 60 ₂ ,..., 60 _N : N is the number of lines) connected to the bus 50 to be protected and drawn from the bus 50 is CT62 (62 ₁ , CT60 ₂ ,..., CT60 _N ), while power sources P ₁ and P ₂ are connected to the lines 60 ₁ and 60 ₂ , respectively. Each CT 62 detects currents (primary currents I ₁₁ , I ₁₂ ,..., I _1N ) flowing through the respective lines 60 and detects the detected currents (secondary currents I ₂₁ , I ₂₂ ,..., I _2N ). Input to the differential protection relay device 40. The differential protection relay device 40 generates and outputs a relay operation signal for operating a circuit breaker (not shown) using the secondary currents I ₂₁ , I ₂₂ ,..., I _2N .

  FIG. 2 is a functional block diagram of the differential protection relay device according to the first embodiment of the present invention. As shown in FIG. 2, the differential protection relay device according to the first embodiment is provided for each phase, and each phase determination circuit (A phase determination circuit, B phase determination circuit, and C) each having the same configuration. Phase determination circuit) and a common determination circuit provided in common.

  Each phase determination circuit includes a differential current deriving unit (DF) 1, a differential current detecting unit (DOC) 2, a change width detecting unit (ΔOC) 4, a maximum value current deriving unit (MAX) 9, and a waveform discrimination ratio differential. Unit (WRDF) 10 as a main component, a differential current detection unit 2, a change width detection unit 4, and a logical sum (OR) circuit 5 provided on the output side of the waveform discrimination ratio differential unit 10, a logical product An AND circuit 6, an AND circuit with an inhibit terminal (hereinafter referred to as “inhibit AND circuit”) 8, a timer circuit 3, and a timer circuit 7 are provided. The common determination circuit includes a differential current calculation unit (DLC) 11 and a failure phase determination unit (DLRF) 12.

  Here, the differential current deriving unit 1, the differential current detecting unit 2 and the timer circuit 3 constitute a failure detecting unit, and the maximum value current deriving unit 9 and the waveform discrimination ratio differential unit 10 are an external failure detecting unit. The change width detection unit 4, the OR circuit 5, the AND circuit 6, and the timer circuit 7 constitute an external failure detection state extension unit that extends a detection state that the external failure detection unit is an external failure. The value current deriving unit 9, the difference current calculation unit 11, and the failure phase determination unit 12 constitute a failure phase process activation control unit that controls the validity / invalidity of the process of the external failure detection state extension unit corresponding to the determined failure phase. The inhibit-and-circuit 8 constitutes an operation output lock unit.

  2 discloses a configuration in which the differential current calculation unit 11 and the failure phase determination unit 12 are provided in the common determination circuit. However, these configuration units are provided in each phase determination circuit, and the failure phase determination unit 12 has a self-phase. It may be a configuration in which only a failure (external failure) is in charge.

  Next, the operation of the differential protection relay device according to the first embodiment will be described. Here, the principle of determining a fault phase using a difference current between two phases in a three-phase current will be described with reference to FIG. This will be described with reference to the drawings in FIG. Here, FIG. 3 is a diagram schematically showing an external one-phase ground fault occurring in the power system. In FIG. 3, the buses for three phases are collectively shown in one system. FIG. 4 is a diagram showing an equivalent circuit when the external one-phase ground fault in the system of FIG. 3 is an A-phase ground fault.

  First, the phase currents Ia, Ib, and Ic flowing in the CT of FIG. 3 can be expressed as the following equations using the zero-phase current I0, the in-phase current I1, and the negative-phase current I2 in the AC vector theory.

Ia = I0 + I1 + I2 = I0 + 2 × I1
Ib = I0 + a ² I1 + aI2 = I0 + (a ² + a) I1 = I0−I1
^{Ic = I0 + aI1 + a 2} I2 = I0 + (a + a 2) I1 = I0-I1
...... (1)

In the above equation (1), a = (− 1 + j√3) / 2 and a ² = (− 1−j√3) / 2. Further, in the deformation process of the above equation (1), the condition of I1 = I2 established in the equivalent circuit of FIG. 4 is used.

  In the above equation (1), the zero-phase current I0 can be expressed by the following equation using the impedances Z1, Z2, Z01, Z02 on the equivalent circuit and the electromotive force Ea on the equivalent circuit.

I0 = {Ea / (Z01 // Z02 + Z2 + Z1)} × {Z02 / (Z01 + Z02)}
(2)

  In the above equation (2), Z01 // Z02 means the total impedance when Z01 and Z02 are connected in parallel, and can be expressed as the following equation.

  Z01 // Z02 = (Z01 × Z02) / (Z01 + Z02) (3)

  Here, if the difference current between the two phases in the three-phase current is expressed by Iab, Ibc, Ica (Iab is the difference current between the A-phase current and the B-phase current, and so on), one-phase ground fault The formula representing the difference current can be expressed as the following formula using the formula (1).

Iab = Ia−Ib = (I0 + 2 × I1) − (I0−I1) = 3 × I1
Ibc = Ib-Ic = (I0-I1)-(I0-I1) = 0
Ica = Ic−Ia = (I0−I1) − (I0 + 2 × I1) = − 3 × I1
...... (4)

  In the above equation (4), the case where there is a load current is not taken into account. However, if there is a load current, the change before and after the occurrence of the failure is calculated and the calculation excluding the consideration of the load current is performed. Good. Therefore, the calculation formula when the load current is taken into consideration is as follows.

ΔIbc = Ibc (after failure) −Ibc (before failure)
ΔIca = Ica (after failure) −Ica (before failure)
ΔIab = Iab (after failure) −Iab (before failure)
...... (5)

As apparent from the above equation (4) or (5), in the case of a phase A ground fault,
ΔIbc << (ΔIca, ΔIab) (6)
The relationship is established.

  In the case of an A-phase ground fault, as can be understood from the equation (1), not only the A-phase current Ia, which is the fault phase, but also the B-phase current Ib and the C-phase current Ic change. However, according to the equation (4), it can be seen that, among the differential currents between the two phases, the differential current Ibc is a current component that does not change. In this case, the influence of the load current can be eliminated by performing the calculation of equation (5). That is, the failure phase can be determined by calculating the difference current between the two phases in the three-phase current.

  Next, the operation of the differential protection relay device according to the first embodiment shown in FIG. 2 will be described with reference to each of FIGS. FIG. 5 is a flowchart showing processing of the failure phase determination unit 12.

First, the secondary currents I ₂₁ , I ₂₂ ,..., I _2N detected by each CT 62 are input to the differential current deriving unit 1 and the maximum value current deriving unit 9. The secondary currents I ₂₁ , I ₂₂ ,..., I _2N are current data obtained by sampling at an electrical angle of 30 °, for example, and are a function of time t.

  Based on these current data, the differential current deriving unit 1 calculates a differential current ID (t) (IDa (t), IDb (t), IDc (t)) defined by Output to the current detection unit 2 and the waveform discrimination ratio differential unit 10 respectively.

  Further, the maximum value current deriving unit 9 calculates the effective value | IR (t) | of the maximum value suppression current IR (t), which is the maximum value in the current data flowing in each line, based on the following equation: The change width detection unit 4, the waveform discrimination ratio differential unit 10, and the difference current calculation unit 11 output the result. That is, the maximum value current deriving unit 9 outputs the maximum value of the line current at a certain time (current value of the maximum current line).

  The differential current detection unit 2 detects that the differential current ID (t) calculated by the above equation (7) is greater than or equal to the determination value IP1. For example, a value of about 50% of the minimum fault current in the power system is selected as the determination value IP1.

  The waveform discriminating ratio differential unit 10 is based on the following conditional expression using the effective value | IR (t) | of the maximum value suppression current and the effective value | ID (t) | Determine an external failure.

  | ID (t) |> K1 · | IR (t) | (9)

  Note that K1 in the above equation is a coefficient for determining the ratio characteristic. For example, if K1 = 0.5, the ratio characteristic is 50%.

  The difference current calculation unit 11 calculates the difference current between the two phases shown in the above equation (4), and outputs the calculation result to the failure phase determination unit 12. Since the input to the difference current calculation unit 11 is the current value of the maximum current line derived by the maximum value current deriving unit 9, Iab, Ibc, Ica in the equation (4) are respectively IMab, IMbc, IMca. Represented by

  The process of the failure phase determination unit 12 is executed according to the flowchart of FIG. First, the failure phase discriminating unit 12 calculates the time change (ΔIAB, ΔIBC, ΔICA) of each two-phase difference current (IMab, IMbc, IMca) calculated by the difference current calculation unit 11 from the time t, for example, an electrical angle 720. As a difference current from the time (°) (two cycles) before, it is calculated based on the following equation (step S0).

ΔIAB = | IMab (t) −IMab (t−720 °) |
ΔIBC = | IMbc (t) −IMbc (t−720 °) |
ΔICA = | IMca (t) −IMca (t−720 °) |
...... (10)

  In the next step S1, it is determined whether or not a failure has occurred by determining whether or not at least one of ΔIAB, ΔIBC, and ΔICA is equal to or higher than a certain determination level α.

  Here, if it is determined that any of ΔIAB, ΔIBC, and ΔICA is less than the determination level α (step S1, No), it is determined that there is no failure (step S12), and the process exits this flow. On the other hand, when at least one of ΔIAB, ΔIBC, and ΔICA is equal to or higher than the determination level α (step S1, Yes), the process proceeds to step S2.

  In step S2, a determination process is performed to determine whether or not the condition ΔIAB> ΔICA + A is satisfied. Here, “A” is a determination constant for indicating that ΔIAB is sufficiently larger than ΔICA.

  If the condition of step S2 is satisfied (step S2, Yes), the process proceeds to step S3. If the condition is not satisfied (step S2, No), the process proceeds to step S5.

  In step S3, a process for determining whether or not the condition of ΔIBC> ΔICA + A is satisfied is executed. If the condition is satisfied (step S3, Yes), it is determined that a B-phase failure has occurred (step S4), and the process exits this flow. If the condition is not satisfied (step S3, No), the process proceeds to step S5. When it is determined in step S4 that the phase B failure has occurred, the failure phase determination unit 12 generates a failure phase signal (output (B) in FIG. 2) representing the phase B failure, and the change width detection unit of the phase B determination circuit. 4 is output.

  In step S5, a process for determining whether or not the condition of ΔIBC> ΔIAB + A is satisfied. If the condition is not satisfied (step S5, No), the process proceeds to step S8, and if the condition is satisfied (step S5, step S5). Yes), the process proceeds to step S6.

  In step S6, a determination process is performed to determine whether or not the condition ΔICA> ΔIAB + A is satisfied. If the condition is satisfied (step S6, Yes), it is determined that a C-phase failure has occurred (step S7), and the process exits this flow. If the condition is not satisfied (step S6, No), the process proceeds to step S8. If it is determined in step S7 that a C phase failure has occurred, the failure phase determination unit 12 generates a failure phase signal indicating the C phase failure (output (C) in FIG. 2) to detect a change width detection unit of the C phase determination circuit. 4 is output.

  In step S8, a determination process is performed to determine whether the condition ΔICA> ΔIBC + A is satisfied. If the condition is not satisfied (No in step S8), the process proceeds to step S11, and if the condition is satisfied (step S8, Yes), the process proceeds to step S9.

  In step S9, a process for determining whether or not the condition ΔIAB> ΔIBC + A is satisfied is executed. If the condition is satisfied (Yes in step S9), it is determined that a phase A failure has occurred (step S10), and the process exits this flow. If the condition is not satisfied (No at Step S9), the process proceeds to Step S11. If it is determined in step S10 that the phase A failure has occurred, the failure phase determination unit 12 generates a failure phase signal (output (A) in FIG. 2) representing the phase A failure, and a change width detection unit of the phase A determination circuit. 4 is output.

  In addition, when not transferring to any of step S4, S7, and S10, it is considered that it is not a one-phase failure. For this reason, in the process of step S11, it determines with a two-phase failure or a three-phase failure, and outputs a failure phase signal to all the change width detection parts 4 in each phase determination circuit.

  Returning to FIG. 2, the change width detection unit 4 executes arithmetic processing based on, for example, the following expression only when the failure phase signal from the failure phase determination unit 12 is input.

  || IR (t) |-| IRt-180 ° ||> IP2 (11)

  In the above equation (11), with respect to the effective value | IR (t) | of the maximum value suppression current, the value at the time t is compared with the value at the time before the electrical angle 180 ° (half cycle), and the time change amount is compared. Is determined to be greater than or equal to the determination value IP2.

  Here, the numerical symbols “1/1”, “1/120”, “2/1” shown on the right side of the differential current detection unit 2, the change width detection unit 4, and the waveform discrimination ratio differential unit 10 are used. The meaning of “” will be described.

  In these numerical symbols “p / q”, “p” is the number of verifications when the operation signal is output, and “q” is the number of verifications when the operation signal is returned. For example, the meaning of “2/1” given to the waveform discrimination ratio differential unit 10 is that the operation signal is output if the calculation result is satisfied twice, and the output is returned if it is not satisfied even once. That is, the waveform discrimination ratio differential unit 10 detects the occurrence of an external failure when the condition of the above equation (9) is satisfied for two sampling times.

  The same numerical symbols are attached to the timer circuits 3 and 7, but the meaning of the numerical symbols here is that the left side is the operation time (the time when the output is “1”) and the right side is the return time (the output “0”). It is time to become "." For example, the timer circuit 3 has an operation time and a return time of 6 sample times (0.5 cycles), and the timer circuit 7 has an operation time of 1 sample time and a return time of 36 sample times (3 cycles). It is.

  Note that the operation time set in the timer circuit 3 is determined in consideration of the fact that an operation signal is not output unnecessarily by a noisy input or the like when healthy. Further, the recovery time set in the timer circuit 3 is determined in consideration of the fact that it does not return unnecessarily due to noise input or the like when a failure occurs.

  The time set in the timer circuit 7 is determined in consideration of the differential current generated by CT saturation. For example, when a ground fault or the like occurs, CT saturation may occur due to a current concentrated on the outflow line. In this case, the differential current detector 2 may alternately detect operation and non-operation by a differential current due to CT saturation. For this reason, the timer circuit 7 is set with a return time of, for example, about 36 sample times (3 cycles) so as to stop the signal output only during the period of the influence of CT saturation.

  In FIG. 2, the output of the differential current detector 2 is input to the timer circuit 3, and the outputs of the differential current detector 2 and the change width detector 4 are input to the OR circuit 5. The outputs of the OR circuit 5 and the waveform discrimination ratio differential unit 10 are input, the output of the AND circuit 6 is input to the timer circuit 7, and the inhibit AND circuit 8 is input to the timer circuit 3 and the timer circuit 7. Each output is configured to be input.

  In this configuration, for example, when an internal failure occurs, a large differential current ID (t) is detected by the differential current deriving unit 1 due to a sudden change in current after the failure occurs. As the operation changes, the output of the differential current detection unit 2 is extended by 6 sample times through the timer circuit 3 and input to the inhibit and circuit 8 which is the output unit of the differential protection relay device. In addition, it is expected that there is no output of the timer circuit 7 at the time of an internal failure. Therefore, the output of the inhibit and circuit 8 is not blocked by the output of the timer circuit 7, and the differential protection relay device operates. A signal is output.

  Further, for example, when a failure progresses from an external one-phase failure to another phase internal failure, the waveform discrimination ratio differential unit 10 may determine an external failure in all three phases by the first external one-phase failure. In this case, the waveform discrimination ratio differential unit 10 also has an output for the healthy phase. On the other hand, the failure phase discriminating unit 12 reliably detects the failure phase of the first external phase failure and outputs a failure phase detection signal only to the failure phase change width detection unit 4. If it is not a phase, there is no output from the change width detector 4. For this reason, according to the differential protection relay device of the first embodiment, even when the failure progresses from the one-phase external failure to the other-phase internal failure, it is possible to suppress the delay of the operation output in the healthy phase. it can.

  As described above, according to the differential protection relay device of the first embodiment, the difference calculated using the line current obtained from each current transformer installed in each line connected to the protection target bus. The presence or absence of a failure is detected based on the dynamic current. If the detected failure is an external failure, the failure phase in the external failure is determined. If the failure phase is a self-phase, the processing of the change width detector is effective. If the failure phase is another phase, control is performed so that the process of the change width detection unit is invalidated, and the process of extending the detection state that is an external failure is stopped. As a result, it is possible to cope with a progressive failure from an external one-phase failure to an internal failure in another phase, and an effect of realizing busbar protection with little operation delay can be obtained.

Embodiment 2. FIG.
In the first embodiment, when a fault phase at the time of an external fault is detected based on a difference current between the two phases of the three-phase current in the maximum current line, a fault phase detection signal is input to the change width detection unit 4 of each phase. When the first external failure is not a self-phase, the change width detection unit 4 is not operated. On the other hand, in the second embodiment, as shown in FIG. 6, the same fault phase detection signal as that in the first embodiment is provided and the same fault phase detection signal is input to the timer circuit 7. . In FIG. 6, the same or equivalent components as those in FIG. 2 are given the same reference numerals, and duplicate descriptions are omitted.

  In the differential protection relay device according to the second embodiment, for example, when it is determined that the external failure is an A-phase failure, the failure phase detection signal is input only to the A-phase determination circuit, and the timer of the A-phase determination circuit The circuit 7 performs a normal timer operation, that is, a timer operation with a return time of 36 sample times. On the other hand, since the failure phase detection signal is not input to the timer circuit 7 of the B phase determination circuit and the C phase determination circuit, it is placed in a reset state. For this reason, even if the external failure (external 1-phase failure) progresses to the internal failure of the other phase, in the healthy phase, it is possible to immediately start the internal / external determination again. It is possible to suppress the delay of the operation output in the healthy phase when the failure progresses to the internal phase failure.

  As described above, according to the differential protection relay device of the second embodiment, the difference calculated using the line current obtained from each current transformer installed in each line connected to the protection target bus. The presence or absence of a failure is detected based on the dynamic current. If the detected failure is an external failure, the failure phase in the external failure is determined. If the failure phase is another phase, the detection status is an external failure. Since the process to extend the detection state that is considered to be an external failure is stopped by forcibly resetting the timer circuit that extends the operating time, the progress failure from the external one-phase failure to the other-phase internal failure It is possible to cope with this, and it is possible to achieve an effect that busbar protection with little operation delay can be realized.

Embodiment 3 FIG.
In the first and second embodiments, the output of the maximum value current deriving unit 9 is used as an input signal, and the failure phase at the time of external failure is detected by the differential current between the two phases of the three-phase current in the maximum current line. However, in the third embodiment, as shown in FIG. 7, the current of each line is used as an input signal, and the same function as in the first and second embodiments is realized. In the third embodiment, the function of the failure phase determination unit 12 provided in the common determination circuit and the function of the change width detection unit 4 provided in each phase determination circuit are integrated, and then the common determination circuit. The change width detector 34 is provided. Further, on the input side of the change width detection unit 34, a difference current calculation unit 32 that operates using the current of each line as an input signal is provided. In FIG. 7, the same or equivalent components as those in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.

  Next, the operation of the differential protection relay device according to the third embodiment shown in FIG. 7 will be described with reference to FIGS. 7 and 8. FIG. 8 is a functional block diagram illustrating an example of the function of the change width detection unit 34.

Secondary currents I ₂₁ , I ₂₂ ,..., I _2N detected by each CT 62 are input to the difference current calculation unit 32. The difference current calculation unit 32 performs difference currents Iab (Iab1, Iab2,..., IabN), Ibc (Ibc1, Ibc2,..., IbcN), Ica (Ica1, Ica2,..., IcaN) for each of N lines. ) And the effective value sum of each difference current is calculated based on the following equation.

IAB (t) = | Iab1 (t) | + | Iab2 (t) | + …… + | IabN (t) |
IBC (t) = | Ibc1 (t) | + | Ibc2 (t) | + …… + | IbcN (t) |
ICA (t) = | Ica1 (t) | + | Ica2 (t) | + …… + | IcaN (t) |
(12)

  Further, the difference current calculation unit 32 is configured so that each phase current Ia (Ia1, Ia2,..., IaN), Ib (Ib1, Ib2,..., IbN), Ic (Ic1, Ic2,. Based on the following equation, the effective value sum of each phase current is calculated.

IA (t) = | Ia1 (t) | + | Ia2 (t) | + …… + | IaN (t) |
IB (t) = | Ib1 (t) | + | Ib2 (t) | + …… + | IbN (t) |
IC (t) = | Ic1 (t) | + | Ic2 (t) | + …… + | IcN (t) |
(13)

  Further, the difference current calculation unit 32 calculates the sum of the effective values (IAB (t), IBC (t), ICA (t)) and the phase currents of the difference currents calculated by the above equations (12) and (13). The change in time (ΔIAB, ΔIBC, ΔICA, ΔIA, ΔIB, ΔIC) of the effective value sum (IA (t), IB (t), IC (t)) of time t and, for example, an electrical angle of 720 ° (2 The difference current from the previous time is calculated based on the following equation.

ΔIAB = | IAB (t) −IAB (t-720 °) |
ΔIBC = | IBC (t) −IBC (t-720 °) |
ΔICA = | ICA (t) −ICA (t-720 °) |
ΔIA = | IA (t) −IA (t-720 °) |
ΔIB = | IB (t) -IB (t-720 °) |
ΔIC = | IC (t) -IC (t-720 °) |
(14)

  The calculation result according to the above equation (14) is input to the change width detection unit 34 as an output of the difference current calculation unit 32.

The function of the change width detector 34 is implemented by each functional block shown in FIG. For example, the conditions shown in the function blocks 13, 15, and 16 (where X and Y are positive constants satisfying X >> Y), that is, ΔIAB> X
ΔICA> X
ΔIBC <Y
If each determination result is input to the AND circuit 19, an output of “1” from the AND circuit 19 means an A-phase failure at the time of one-phase failure.

Further, the conditions shown in the function blocks 13, 14, and 17 (the conditions of X and Y are the same as above), that is, ΔIAB> X
ΔIBC> X
ΔICA <Y
If each determination result is input to the AND circuit 20, an output of “1” from the AND circuit 20 means a B-phase failure at the time of one-phase failure.

Further, the conditions shown in the functional blocks 14, 15, 18 (the conditions of X, Y are the same as above), that is, ΔIBC> X
ΔICA> X
ΔIAB <Y
If each determination result is input to the AND circuit 21, an output of “1” from the AND circuit 21 means a C-phase failure at the time of one-phase failure.

On the other hand, in the function block 22,
ΔIA> Z (Z is a positive constant independent of X and Y)
The conditional expression means that a one-phase A-phase fault has occurred or that there is a current change in the A-phase at the time of a two-phase or three-phase fault. Therefore, by inputting the outputs of the AND circuits 20 and 21 and the function block 22 to the inhibit AND circuit 25, the case of a B-phase failure due to a one-phase failure and a C-phase failure due to a one-phase failure is excluded. The output (A) of the inhibit-and-circuit 25 is a signal indicating that the A-phase current has changed due to an A-phase failure or a failure of two or more phases.

Further, the condition shown in the function block 23 (the condition of Z is the same as above), that is, ΔIB> Z
This means that a one-phase B-phase fault has occurred or that there is a current change in the B-phase at the time of a two-phase or three-phase fault. Therefore, by inputting the outputs of the AND circuits 19 and 21 and the function block 23 to the inhibit AND circuit 26, the case of the C-phase failure by the one-phase failure and the A-phase failure by the one-phase failure is excluded. The output (B) of the inhibit-and-circuit 26 is a signal indicating that the B-phase current has changed due to a B-phase failure or a failure of two or more phases.

Further, the condition shown in the function block 24 (the condition of Z is the same as above), that is, ΔIC> Z
The conditional expression means that a one-phase C-phase fault has occurred or that there is a current change in the C-phase at the time of a two-phase or three-phase fault. Therefore, by inputting the outputs of the AND circuits 19 and 20 and the function block 24 to the inhibit AND circuit 27, the case of the A-phase failure by the one-phase failure and the B-phase failure by the one-phase failure is excluded. The output (B) of the inhibit-and-circuit 26 is a signal indicating that the B-phase current has changed due to a B-phase failure or a failure of two or more phases.

  The output (A) of the inhibit-and-circuit 25 becomes an input signal to the OR circuit 5 in the A-phase determination circuit of FIG. Similarly, the output (B) of the inhibit-and-circuit 26 becomes an input signal to the OR circuit 5 in the B-phase determination circuit, and the output (C) of the inhibit-and-circuit 27 is input to the OR circuit 5 in the C-phase determination circuit. Signal. In this case, even if the waveform discrimination ratio differential unit 10 determines an external failure, if the external failure is not a self-phase failure, there is no output signal from the self-phase OR circuit 5. As a result, when the first external failure is not a self-phase, the AND circuit 6 does not operate, and the operation of the timer circuit 7 is not extended meaninglessly. For this reason, according to the differential protection relay device of the third embodiment, even when the failure progresses from the one-phase external failure to the other-phase internal failure, it is possible to suppress the delay of the operation output in the healthy phase. it can.

  In the differential protection relay device according to the third embodiment, the functional configuration illustrated in FIG. 8 is illustrated as a configuration for realizing the function of the change width detection unit 34, but the configuration is not limited to this configuration. For example, the content of the processing flow illustrated in FIG. 3 may be embodied as processing performed by the change width detection unit 34.

  On the contrary, the functional configuration shown in FIG. 8 may be applied as a configuration that embodies the function of the failure phase determination unit 12 in the first embodiment.

Embodiment 4 FIG.
FIG. 9 is a functional block diagram of the differential protection relay device according to the fourth embodiment of the present invention. In the functional block of FIG. 9, in the configuration shown in FIG. 2, the common determination circuit is omitted, while the output of the differential current detection unit 2 is input to the timer circuit 7 via the inverting circuit 28 and the timer circuit 29. It is said. In addition, about another structure, it is the same as that of Embodiment 1 shown in FIG. 2, or the same code | symbol is attached | subjected and shown to those common components, and the overlapping description is abbreviate | omitted. .

  Here, the inverting circuit 28 and the timer circuit 29 are forcibly resetting the extension process performed by the external failure detection state extension unit described in the first embodiment, while the maximum value current deriving unit 9 and the waveform discrimination ratio differential unit 10 are A detection state extension process resetting unit is configured.

  Next, the operation of the differential protection relay device according to the fourth embodiment shown in FIG. 9 will be described. First, since the differential current is not detected in the healthy phase at the time of an external failure, the output (logic “0”) of the differential current detection unit 2 is inverted (logic “1”) by the inversion circuit 28, and the timer circuit 29 Is input. The timer circuit 29 determines that an external failure has occurred, for example, after 18 sample times (1.5 cycles), and outputs a forced reset signal to the timer circuit 7 that is the output of the CT saturation countermeasure means. The timer circuit 7 performs a timer stop process by a forced reset signal from the timer circuit 29.

  That is, in the differential protection relay device according to the fourth embodiment, when it is detected that a differential current does not occur in the healthy phase for a certain time or more after the failure occurs, the timer circuit outputs a signal for preventing external determination. 7 is forcibly reset, and the external determination can be activated again when the failure progresses thereafter. With this configuration, when an external failure progresses to an internal failure, it is possible to start external determination again, so it is possible to cope with a progressive failure from an external failure to an internal failure, and realize bus protection with little operational delay can do.

  As described above, the differential protection relay device according to the present invention is useful as an invention that can suppress a delay in operation output in a healthy phase when a failure progresses from a one-phase external failure to another phase internal failure. is there.

DESCRIPTION OF SYMBOLS 1 Differential current derivation | leading-out part 2 Differential current detection part 3,7,29 Timer circuit 4,34 Change width detection part 5 OR circuit 6,19-21 AND circuit 8,25-27 Inhibit AND circuit 9 Maximum value current derivation part 10 waveform discrimination ratio differential unit 11, 32 a difference current calculation unit 12 failure phase discriminator 13～18,22～24 functional block 28 inverting circuit 40 a differential protective relay device 50 bus 60 (60 ₁ ~60 _N) line 62 Current transformer (CT)
P ₁ and P ₂ power supplies

Claims (9)

A fault detection unit that detects the presence or absence of a fault based on a differential current calculated using a line current obtained from each current transformer installed in each line connected to the bus to be protected;
An external fault detector for detecting whether the fault is an external fault based on the line current and the differential current;
An external failure detection state extension that extends the detection state that the external failure detection unit is an external failure; and
An operation output lock unit that locks the operation output from the failure detection unit by the output of the external failure detection state extension unit;
A fault phase process activation control unit that determines the fault phase in the external fault based on each line current and controls the validity / invalidity of the process of the external fault detection state extension unit corresponding to the fault phase;
A differential protection relay device comprising:   2. The differential protection relay according to claim 1, wherein the fault phase processing activation control unit determines a fault phase based on a difference current between each two phases at a maximum value among the line current effective values. Electrical equipment. The failure phase process activation control unit is
A maximum value current deriving unit for calculating a maximum value of the line current effective values;
A difference current calculation unit for calculating a difference current between the two phases in the output of the maximum value current deriving unit;
A failure phase determination unit that determines the failure phase of the external failure detected by the external failure detection unit based on the output of the difference current calculation unit;
The differential protection relay device according to claim 1, further comprising: The external failure detection state extension unit includes a change width detection unit that detects that the time change of the maximum value of the line current effective value is equal to or greater than a predetermined determination value,
When the fault phase detected by the fault phase determination unit is a self-phase, control is performed so that the processing of the change width detection unit is effective, and when the fault phase is another phase, the change width detection unit The differential protection relay device according to claim 3, wherein the control is controlled so as to be invalid. The external failure detection state extension unit includes a timer circuit that extends a detection state that an external failure has occurred,
4. The differential protection relay device according to claim 3, wherein when the fault phase detected by the fault phase determination unit is another phase, control for forcibly resetting the timer circuit is performed. 5.   The differential protection relay device according to any one of claims 3 to 5, wherein the maximum value current deriving unit is shared by the external fault detection unit and the fault phase process activation control unit. .   2. The differential protection relay device according to claim 1, wherein the failure phase processing activation control unit determines a failure phase based on an effective value sum of a difference current between each two phases in the line current. The failure detection unit, the external failure detection unit, the external failure detection state extension unit, and the operation output lock unit are provided in an individual determination circuit for each phase,
The differential protection relay device according to any one of claims 1 to 7, wherein the failure phase process activation control unit is provided in a common determination circuit for each phase. A fault detection unit that detects the presence or absence of a fault based on a differential current calculated using a line current obtained from each current transformer installed in each line connected to the bus to be protected;
An external fault detector for detecting whether the fault is an external fault based on the line current and the differential current;
An external failure detection state extension that extends the detection state that the external failure detection unit is an external failure; and
An operation output lock unit that locks the operation output from the failure detection unit by the output of the external failure detection state extension unit;
A detection state extension process reset unit for forcibly resetting the extension process performed by the external failure detection state extension unit;
A differential protection relay device comprising:

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