JP2011082916A - Semiconductor relay - Google Patents

Semiconductor relay Download PDF

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Publication number
JP2011082916A
JP2011082916A JP2009235379A JP2009235379A JP2011082916A JP 2011082916 A JP2011082916 A JP 2011082916A JP 2009235379 A JP2009235379 A JP 2009235379A JP 2009235379 A JP2009235379 A JP 2009235379A JP 2011082916 A JP2011082916 A JP 2011082916A
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JP
Japan
Prior art keywords
conductor
conductor portion
light emitting
package
semiconductor relay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009235379A
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Japanese (ja)
Other versions
JP5502422B2 (en
Inventor
Naritoshi Hoshino
就俊 星野
Yoshihiro Fujiwara
嘉宏 藤原
Shinsuke Ko
真祐 高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
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Panasonic Electric Works Co Ltd
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Filing date
Publication date
Application filed by Panasonic Electric Works Co Ltd filed Critical Panasonic Electric Works Co Ltd
Priority to JP2009235379A priority Critical patent/JP5502422B2/en
Priority to CN201080045218.9A priority patent/CN102656803B/en
Priority to PCT/IB2010/002533 priority patent/WO2011042796A1/en
Priority to US13/500,710 priority patent/US8816310B2/en
Priority to KR1020127009016A priority patent/KR101351737B1/en
Publication of JP2011082916A publication Critical patent/JP2011082916A/en
Application granted granted Critical
Publication of JP5502422B2 publication Critical patent/JP5502422B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
  • Electronic Switches (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an available frequency band from becoming narrow owing to effects of a stab. <P>SOLUTION: A semiconductor relay 1 includes a light emitting element 2, a light receiving element 2, MOSFETs 4, 5, a terminal piece 6, first to third conductor parts 7, 8, 9 and a package 10. The light receiving element 3 receives light emitted from the light emitting element 2 in response to an input signal and generates a photovoltaic force. The MOSFETs 4, 5 are connected in inverse series by connecting gate electrodes 4a, 5a and source electrodes 4b, 5b to both terminals of the light receiving element 3, respectively, and connecting the source electrodes 4b, 5b with each other. The terminal piece 6 connects an electrode of the light emitting element 2 and an input-side external circuit. The light receiving element 3 is mounted in the first conductor portion 7, and a projecting portion 7a is disposed therein. Drain electrodes (not illustrated) of the MOSFETs 4, 5 are surface-mounted at one terminal side of the second and third conductor portions 8 and 9, and another terminal side is connected with an output-side external circuit. The projecting portion 7a is disposed between the second conductor portion 8 and the third conductor portion 9 when seen from a longitudinal direction. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体リレーに関するものである。   The present invention relates to a semiconductor relay.

従来よりスイッチング素子としてMOSFETを用いた種々の半導体リレーが提供され
ている(例えば、特許文献1参照)。
Conventionally, various semiconductor relays using MOSFETs as switching elements have been provided (for example, see Patent Document 1).

また、この様な半導体リレーの一例として図12〜図14に示すような半導体リレー9
0がある。半導体リレー90は、発光素子91と受光素子92と一対のMOSFET93
,94と端子片95と第1、第2及び第3の導体部96,97,98とこれらを内部に収
納する箱型のパッケージ99とを備える。尚、以下の説明では図14において上下左右方
向を規定し、図14の正面を前面として説明を行う。
Further, as an example of such a semiconductor relay, a semiconductor relay 9 as shown in FIGS.
There is zero. The semiconductor relay 90 includes a light emitting element 91, a light receiving element 92, and a pair of MOSFETs 93.
94, a terminal piece 95, first, second and third conductor portions 96, 97, 98, and a box-shaped package 99 which accommodates them. In the following description, the up / down / left / right directions are defined in FIG. 14, and the front of FIG.

発光素子91(例えば発光ダイオード)は入力信号に応じて発光する。受光素子92は
、図13に示すように発光素子91と対向して配置されて発光素子91から放射される光
を受光して光起電力を発生する。MOSFET93,94は、図12〜図14に示すよう
にボンディングワイヤ100a〜100fを介して、ゲート電極93a,94a及びソー
ス電極93b,94bが各々受光素子92の両端に接続され、且つ互いのソース電極93
b,94b同士が接続されて逆直列接続される。端子片95は、図12〜図14に示すよ
うに各々細長の矩形板が段状に4回曲折されてなる第1及び第2の端子片95a,95b
から構成される。また、第1及び第2の端子片95a,95bの上端部側はそれぞれパッ
ケージ99の外部に露出するとともに、パッケージ99の内部にてその互いの長手方向を
上下方向に向けて並設される。そして、第1の端子片95aの下端部には右方へ延出する
延出部95dを介して平板状に形成される実装部95cを有している。実装部95cは、
前後方向から見たときに第1の端子片95aと第2の端子片95bとの間に配置され、そ
の後面には発光素子91が実装される。発光素子91のアノード電極またはカソード電極
のうち一方は第1の端子片95aの実装部95cにダイボンディングされ、他方は第2の
端子片95bにワイヤボンディングされる。そして、発光素子91の電極は、端子片95
を介して入力側の外部回路(図示せず)と電気的に接続される。
A light emitting element 91 (for example, a light emitting diode) emits light according to an input signal. As shown in FIG. 13, the light receiving element 92 is disposed facing the light emitting element 91 and receives light emitted from the light emitting element 91 to generate a photovoltaic force. The MOSFETs 93 and 94 have gate electrodes 93a and 94a and source electrodes 93b and 94b connected to both ends of the light receiving element 92 through bonding wires 100a to 100f as shown in FIGS. 93
b and 94b are connected to each other and connected in reverse series. The terminal piece 95 includes first and second terminal pieces 95a and 95b each formed by bending an elongated rectangular plate four times stepwise as shown in FIGS.
Consists of Further, the upper end portions of the first and second terminal pieces 95a and 95b are exposed to the outside of the package 99, and are arranged in parallel inside the package 99 with their longitudinal directions directed vertically. The lower end portion of the first terminal piece 95a has a mounting portion 95c formed in a flat plate shape via an extending portion 95d extending to the right. The mounting part 95c is
When viewed from the front-rear direction, the light-emitting element 91 is mounted on the rear surface of the first terminal piece 95a and the second terminal piece 95b. One of the anode electrode and the cathode electrode of the light emitting element 91 is die-bonded to the mounting portion 95c of the first terminal piece 95a, and the other is wire-bonded to the second terminal piece 95b. The electrode of the light emitting element 91 is connected to the terminal piece 95.
Is electrically connected to an external circuit (not shown) on the input side.

第1の導体部96は、図12〜図14に示すように略平板状に形成されてその前面には
受光素子92が実装されており、受光素子92と発光素子91とが対向するように実装部
95cの真後ろに配置される。第2及び第3の導体部97,98は、図12〜図14に示
すように略帯板状に形成されて上端側にはMOSFET93,94のドレイン電極(図示
せず)が各々表面実装されるとともに、下端側がパッケージ99の外部に露出して出力側
の外部回路の左右方向に延びる信号パターン101,102に各々接続される。
The first conductor portion 96 is formed in a substantially flat plate shape as shown in FIGS. 12 to 14, and a light receiving element 92 is mounted on the front surface thereof, so that the light receiving element 92 and the light emitting element 91 face each other. Arranged just behind the mounting portion 95c. The second and third conductor portions 97 and 98 are formed in a substantially strip shape as shown in FIGS. 12 to 14, and the drain electrodes (not shown) of the MOSFETs 93 and 94 are surface-mounted on the upper ends, respectively. At the same time, the lower end side is exposed to the outside of the package 99 and connected to the signal patterns 101 and 102 extending in the left-right direction of the external circuit on the output side.

そして、受光素子92の光起電力がMOSFET93のゲート電極93a−ソース電極
93b間、並びにMOSFET94のゲート電極94a−ソース電極94b間に印加され
ることで、MOSFET93の図示しないドレイン電極−ソース電極93b間、並びにM
OSFET94の図示しないドレイン電極−ソース電極94b間のインピーダンスが変化
して、第2及び第3の導体部97,98の間が導通/非導通に切り換えられる。
Then, the photoelectromotive force of the light receiving element 92 is applied between the gate electrode 93a and the source electrode 93b of the MOSFET 93 and between the gate electrode 94a and the source electrode 94b of the MOSFET 94, so that between the drain electrode and the source electrode 93b (not shown) of the MOSFET 93. And M
The impedance between the drain electrode and the source electrode 94b (not shown) of the OSFET 94 changes, and the second and third conductor portions 97 and 98 are switched between conductive and non-conductive.

特開2003−8050号公報JP 2003-8050 A

しかしながら、従来の半導体リレー90は、図14に示すように前後方向から見たとき
第2及び第3の導体部97,98が左右方向に延びる信号パターン101,102に対し
て長手方向を垂直方向に向けて並設され、更に第1の導体部96が第2及び第3の導体部
97,98の真上に配設されることから、信号パターン101,102から第1の導体部
96の上端までに亘ってスタブが形成されて、当該スタブが共振することにより共振周波
数付近でのインサーションロス(挿入損失)が増加して、使用可能な周波数帯域が狭くな
るという問題があった。
However, the conventional semiconductor relay 90 has a longitudinal direction perpendicular to the signal patterns 101, 102 in which the second and third conductor portions 97, 98 extend in the left-right direction when viewed from the front-rear direction as shown in FIG. Since the first conductor portion 96 is disposed immediately above the second and third conductor portions 97 and 98, the signal patterns 101 and 102 are connected to the first conductor portion 96. There is a problem that a stub is formed over the upper end, and the stub resonates, thereby increasing an insertion loss (insertion loss) near the resonance frequency and narrowing a usable frequency band.

本発明は上記事由に鑑みて為されたものであり、その目的は、スタブの影響により使用
可能な周波数帯域が狭くなるのを防止することができる半導体リレーを提供することにあ
る。
The present invention has been made in view of the above reasons, and an object of the present invention is to provide a semiconductor relay capable of preventing a usable frequency band from becoming narrow due to the influence of a stub.

請求項1の発明は、上記目的を達成するために、入力信号に応じて発光する発光素子と
、発光素子と対向して配置され発光素子から放射される光を受光して光起電力を発生する
受光素子と、ボンディングワイヤを介してゲート電極及びソース電極が各々受光素子の両
端に接続され且つ互いのソース電極同士が接続されて逆直列接続された一対のMOSFE
Tと、発光素子が実装される平板状の実装部を有して発光素子の電極と入力側の外部回路
とを電気的に接続する端子片と、略平板状に形成されて受光素子が実装される第1の導体
部と、略帯板状に形成されて一端側にはMOSFETのドレイン電極が各々表面実装され
るとともに他端側が出力側の外部回路と接続される第2及び第3の導体部と、これらを内
部に収納する箱型のパッケージと、を備え、第2及び第3の導体部の間は、前記光起電力
がMOSFETの各ゲート−ソース電極間に印加されることで各ドレイン−ソース電極間
のインピーダンスが変化して導通/非導通に切り換えられ、第1の導体部の少なくとも一
部は、第2及び第3の導体部のMOSFETが各々実装される実装面の法線方向から見た
ときに第2の導体部と第3の導体部との間に配置されることを特徴とする。
In order to achieve the above object, the invention according to claim 1 generates a photovoltaic power by receiving a light emitting element that emits light in response to an input signal and light emitted from the light emitting element that is disposed facing the light emitting element. A pair of MOSFEs that are connected in reverse series with a gate electrode and a source electrode connected to both ends of the light receiving element via a bonding wire and with the source electrodes connected to each other.
T, a flat strip-shaped mounting portion on which the light-emitting element is mounted, a terminal piece that electrically connects the electrode of the light-emitting element and the input-side external circuit, and a light-receiving element mounted on the substantially flat plate The first and second conductor portions are formed in a substantially strip-like shape, and the drain electrode of the MOSFET is surface-mounted on one end side and the other end side is connected to the external circuit on the output side. A conductor part and a box-type package that accommodates the conductor part, and between the second and third conductor parts, the photovoltaic power is applied between each gate-source electrode of the MOSFET. The impedance of each drain-source electrode is changed to be switched between conduction / non-conduction, and at least a part of the first conductor portion is a method of a mounting surface on which the MOSFETs of the second and third conductor portions are respectively mounted. When viewed from the line direction, the second conductor and the third conductor Characterized in that it is disposed between the body portion.

この発明によれば、第1の導体部の少なくとも一部は、第2及び第3の導体部のMOS
FETが各々実装される実装面の法線方向から見たときに第2の導体部と第3の導体部と
の間に配置されるので、第1の導体部の前記一部、並びに第2及び第3の導体部が略一列
に並ぶにように配置されて出力側の外部回路の信号パターンから第1の導体部までに亘っ
て形成されるスタブを短くすることができ、従ってスタブの影響により使用可能な周波数
帯域が狭くなるのを防止することができる。
According to this invention, at least a part of the first conductor portion is the MOS of the second and third conductor portions.
Since the FET is disposed between the second conductor portion and the third conductor portion when viewed from the normal direction of the mounting surface on which each FET is mounted, the part of the first conductor portion and the second conductor portion And the third conductor portions are arranged so as to be arranged in a line, and the stub formed from the signal pattern of the external circuit on the output side to the first conductor portion can be shortened. Therefore, it is possible to prevent the usable frequency band from becoming narrow.

請求項2の発明は、請求項1の発明において、第1、第2及び第3の導体部の受光素子
、及び一対のMOSFETが各々実装される各実装面と端子片の発光素子が実装される実
装面とは互いに対向するとともに、これらの実装面は、パッケージの第2及び第3の導体
部、並びに端子片が外部に露出する一端部に対して垂直方向に向けられていることを特徴
とする。
According to a second aspect of the present invention, in the first aspect of the invention, the light receiving elements of the first, second, and third conductor portions, the mounting surfaces on which the pair of MOSFETs are mounted, and the light emitting elements of the terminal pieces are mounted. The mounting surfaces are opposed to each other, and these mounting surfaces are oriented in a direction perpendicular to the second and third conductor portions of the package and one end portion where the terminal pieces are exposed to the outside. And

この発明によれば、これらの実装面は、パッケージの第2及び第3の導体部、並びに端
子片が外部に露出する一端部に対して従来のように平行方向に向けられているのではなく
垂直方向に向けられているので、パッケージの前記一端部を外部回路の回路基板に表面実
装することで従来よりも実装面積の小型化を図ることができる。
According to the present invention, these mounting surfaces are not oriented in the parallel direction as in the prior art with respect to the second and third conductor portions of the package and the one end portion where the terminal pieces are exposed to the outside. Since it is oriented in the vertical direction, it is possible to reduce the mounting area as compared with the prior art by surface-mounting the one end of the package on the circuit board of the external circuit.

請求項3の発明は、請求項1または2の発明において、第1の導体部には、周縁部から
外側に向かって略棒状に突出する凸部が配設され、前記凸部は、第1の導体部の前記一部
として前記法線方向から見たときに第2の導体部と第3の導体部との間に配置され、MO
SFETのソース電極と各々電気的に接続されることを特徴とする。
According to a third aspect of the present invention, in the first or second aspect of the present invention, the first conductor portion is provided with a convex portion that protrudes in a substantially rod shape from the peripheral portion to the outside, and the convex portion is The conductor portion is disposed between the second conductor portion and the third conductor portion when viewed from the normal direction as the part of the conductor portion, and MO
Each is electrically connected to the source electrode of the SFET.

この発明によれば、前記凸部は、第1の導体部の前記一部として前記法線方向から見た
ときに第2の導体部と第3の導体部との間に配置され、MOSFETのソース電極と各々
電気的に接続されるので、前記凸部、並びに第2及び第3の導体部が略一列に並ぶによう
に配置されて、請求項1と同様の効果を奏することができる。
According to this invention, the convex portion is disposed between the second conductor portion and the third conductor portion when viewed from the normal direction as the part of the first conductor portion, Since each of them is electrically connected to the source electrode, the convex portion and the second and third conductor portions are arranged so as to be arranged in a line, and the same effect as in the first aspect can be obtained.

請求項4の発明は、請求項1または2の発明において、第1の導体部は、前記法線方向
から見たときに略全体が第2の導体部と第3の導体部との間に配置され、MOSFETの
ソース電極と各々電気的に接続されることを特徴とする。
According to a fourth aspect of the invention, in the first or second aspect of the invention, the first conductor portion is substantially entirely between the second conductor portion and the third conductor portion when viewed from the normal direction. It is arrange | positioned and each is electrically connected with the source electrode of MOSFET, It is characterized by the above-mentioned.

この発明によれば、第1の導体部は、前記法線方向から見たときに略全体が第2の導体
部と第3の導体部との間に配置され、MOSFETのソース電極と各々電気的に接続され
るので、第1、第2及び第3の導体部が略一列に並ぶにように配置されて、請求項1と同
様の効果を奏することができる。
According to the present invention, the first conductor portion is substantially entirely disposed between the second conductor portion and the third conductor portion when viewed from the normal direction, and each of the first conductor portion and the source electrode of the MOSFET is electrically connected. Therefore, the first, second, and third conductor portions are arranged so as to be aligned in a row, and the same effect as in the first aspect can be obtained.

請求項5の発明は、請求項1〜4の何れか1項の発明において、第2及び第3の導体部
、並びに端子片のパッケージより外部に露出する部位は、パッケージの外面と各々面一と
していることを特徴とする。
The invention of claim 5 is the invention of any one of claims 1 to 4, wherein the second and third conductor portions and the portion of the terminal piece exposed to the outside from the package are flush with the outer surface of the package. It is characterized by that.

この発明によれば、第2及び第3の導体部、並びに端子片のパッケージより外部に露出
する部位は、パッケージの外面と各々面一としているので、パッケージを外部回路の回路
基板に表面実装したときに、前記部位のインピーダンスの不整合を抑制してより使用可能
な周波数帯域を広げることができる。
According to the present invention, the portions of the second and third conductor portions and the terminal pieces exposed to the outside from the package are flush with the outer surface of the package, so the package is surface-mounted on the circuit board of the external circuit. Sometimes, it is possible to expand the usable frequency band by suppressing the impedance mismatch of the part.

本発明では、スタブの影響により使用可能な周波数帯域が狭くなるのを防止することが
できるという効果がある。
The present invention has an effect that it is possible to prevent a usable frequency band from becoming narrow due to the influence of a stub.

本発明の実施形態1のパッケージ内部の斜視図である。It is a perspective view inside the package of Embodiment 1 of this invention. 同上における断面図である。It is sectional drawing in the same as the above. 同上におけるインサーションロスの解析結果を示す説明図である。It is explanatory drawing which shows the analysis result of the insertion loss in the same as the above. 本発明の実施形態2のパッケージ内部の斜視図である。It is a perspective view inside the package of Embodiment 2 of this invention. 同上における断面図である。It is sectional drawing in the same as the above. 同上におけるインサーションロスの解析結果を示す説明図である。It is explanatory drawing which shows the analysis result of the insertion loss in the same as the above. 同上における別の一例のパッケージ内部における斜視図である。It is a perspective view inside the package of another example same as the above. 同上における別の一例のインサーションロスの解析結果を示す説明図である。It is explanatory drawing which shows the analysis result of the insertion loss of another example in the same as the above. 本発明の実施形態3のパッケージ内部の斜視図である。It is a perspective view inside the package of Embodiment 3 of this invention. 同上における断面図である。It is sectional drawing in the same as the above. 同上におけるインサーションロスの解析結果を示す説明図である。It is explanatory drawing which shows the analysis result of the insertion loss in the same as the above. 従来の半導体リレーの一例のパッケージ内部の斜視図である。It is a perspective view inside the package of an example of the conventional semiconductor relay. 同上におけるパッケージ内部の左側面図である。It is a left view inside a package in the same as the above. 同上における断面図である。It is sectional drawing in the same as the above.

(実施形態1)
以下、本発明の実施形態1について、図1〜図3を参照して説明する。尚、以下の説明
では図2において上下左右方向を規定し、図2の正面を前面として説明を行う。本実施形
態の半導体リレー1は、図1及び図2に示すように発光素子2と受光素子3と一対のMO
SFET4,5と端子片6と第1、第2及び第3の導体部7,8,9とこれらを内部に収
納するパッケージ10とを備える。パッケージ10は、図1に示すように合成樹脂材料に
より矩形箱状に形成され、後端部10aの外面が外部回路(図示せず)の回路基板(図示
せず)に対して表面実装される。
(Embodiment 1)
Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS. In the following description, the vertical and horizontal directions are defined in FIG. 2, and the front of FIG. As shown in FIGS. 1 and 2, the semiconductor relay 1 of the present embodiment includes a light emitting element 2, a light receiving element 3, and a pair of MOs.
SFETs 4 and 5, a terminal piece 6, first, second, and third conductor portions 7, 8, and 9 and a package 10 that accommodates them are provided. The package 10 is formed in a rectangular box shape using a synthetic resin material as shown in FIG. 1, and the outer surface of the rear end portion 10a is surface-mounted on a circuit board (not shown) of an external circuit (not shown). .

発光素子2は、従来技術で述べた発光素子91と同様に、例えば発光ダイオードからな
り入力信号に応じて発光する。また、発光素子2の外郭は、図1に示すように筒状に形成
されており、その前後両端面に各々電極(アノード電極及びカソード電極)を有する。
The light emitting element 2 is composed of, for example, a light emitting diode, and emits light according to an input signal, like the light emitting element 91 described in the prior art. Further, the outer shape of the light emitting element 2 is formed in a cylindrical shape as shown in FIG. 1, and has electrodes (an anode electrode and a cathode electrode) on both front and rear end faces thereof.

受光素子3は、図1及び図2に示すように発光素子2と対向して配置されて、発光素子
2から放射される光を受光して光起電力を発生するフォトダイオードアレイ(図示せず)
と、MOSFET4,5に対して光起電力による充放電制御を行う充放電回路(図示せず
)とを備える。また、受光素子3は、図1及び図2に示すように前記フォトダイオードア
レイの陽極及び陰極たる電極3a,3bと、制御信号出力用電極(以下、電極)3cとを
前面に有している。
As shown in FIGS. 1 and 2, the light receiving element 3 is arranged to face the light emitting element 2, and receives a light emitted from the light emitting element 2 to generate a photoelectromotive force (not shown). )
And a charge / discharge circuit (not shown) for performing charge / discharge control by photovoltaic power on the MOSFETs 4 and 5. As shown in FIGS. 1 and 2, the light receiving element 3 has electrodes 3a and 3b which are anodes and cathodes of the photodiode array, and a control signal output electrode (hereinafter referred to as an electrode) 3c on the front surface. .

そして、発光素子2と受光素子3は、パッケージ10の内部が図示しない透明樹脂で封
止されることによって光学的に結合される。尚、外乱光の入射を防ぐために前記透明樹脂
の表面は遮光性を有する薄膜(図示せず)で覆われている。
The light emitting element 2 and the light receiving element 3 are optically coupled by sealing the inside of the package 10 with a transparent resin (not shown). Note that the surface of the transparent resin is covered with a light-shielding thin film (not shown) in order to prevent disturbance light from entering.

MOSFET4,5は、図1及び図2に示すように各々前面にゲート電極4a,5a及
びソース電極4b,5bを備え、後面にドレイン電極(図示せず)を備える。
As shown in FIGS. 1 and 2, each of the MOSFETs 4 and 5 includes gate electrodes 4a and 5a and source electrodes 4b and 5b on the front surface, and a drain electrode (not shown) on the rear surface.

端子片6は、図1及び図2に示すように各々細長の矩形板が段状に4回曲折されてなる
第1及び第2の端子片6a,6bから構成される。第1の端子片6aの左端部、及び第2
の端子片6bの右端部は、パッケージ10の後端部10a上方の左右両縁部に貫設された
挿通孔(図示せず)を通じてパッケージ10の外部に露出する。また、第1の端子片6a
の右端部には平板状に形成される実装部6cが突設される。そして、第1及び第2の端子
片6a,6bは、パッケージ10の内部にてその長手方向を左右方向に向けて、第1の端
子片6aの右端部と第2の端子片6b左端部とが互いに対向するように配置される。すな
わち端子片6は、前後方向から見たときに全体として略一直線状に形成される。
The terminal piece 6 includes first and second terminal pieces 6a and 6b, each of which is formed by bending an elongated rectangular plate four times stepwise as shown in FIGS. The left end of the first terminal piece 6a, and the second
The right end of the terminal piece 6b is exposed to the outside of the package 10 through insertion holes (not shown) penetrating the left and right edges above the rear end 10a of the package 10. Also, the first terminal piece 6a
A mounting portion 6c that is formed in a flat plate shape protrudes from the right end portion. The first and second terminal pieces 6a and 6b are arranged so that the longitudinal direction of the first terminal piece 6a and the second terminal piece 6b and the left end portion of the first terminal piece 6b are set to the left and right directions inside the package 10, respectively. Are arranged so as to face each other. That is, the terminal piece 6 is formed in a substantially straight line as a whole when viewed from the front-rear direction.

ここで発光素子2の前端面にあるアノード電極またはカソード電極の一方の電極は実装
部6cの後面にダイボンディングされ、後端面にある他方の電極は第2の端子片6bにワ
イヤボンディングされる。そして、発光素子2の電極は、端子片6を介して入力側の外部
回路(図示せず)とを電気的に接続される。
Here, one of the anode electrode and the cathode electrode on the front end face of the light emitting element 2 is die-bonded to the rear face of the mounting portion 6c, and the other electrode on the rear end face is wire-bonded to the second terminal piece 6b. The electrodes of the light emitting element 2 are electrically connected to an external circuit (not shown) on the input side via the terminal piece 6.

第1の導体部7は、図1及び図2に示すように導電性材料により略平板状に形成されて
その前面には上述した受光素子3が実装され、受光素子3が発光素子2と対向して配置さ
れるように実装部6cの真後ろに配置される。また、第1の導体部7には、下方周縁部か
ら外側へ略棒状に突出する凸部7aが設けられ、更に左方周縁部から外側へ略矩形板状に
突出する突片7bが配設される。
As shown in FIGS. 1 and 2, the first conductor portion 7 is formed of a conductive material in a substantially flat plate shape, the light receiving element 3 described above is mounted on the front surface thereof, and the light receiving element 3 faces the light emitting element 2. It arrange | positions just behind the mounting part 6c so that it may arrange | position. Further, the first conductor portion 7 is provided with a convex portion 7a that protrudes outward in a substantially rod shape from the lower peripheral edge portion, and further has a protruding piece 7b that protrudes outward in a substantially rectangular plate shape from the left peripheral edge portion. Is done.

第2及び第3の導体部8,9は、図1〜図2に示すように各々導電性材料により形成さ
れた帯板が段状に2回曲折されてなる。第2の導体部8の左端側と第3の導体部9の右端
側は、パッケージ10の後端部10a下方の左右両縁部に貫設された挿通孔(図示せず)
を通じてパッケージ10の外部に露出して、出力側の外部回路の左右方向に延びる信号パ
ターン13,14に各々接続される。また、第2及び第3の導体部8,9は、パッケージ
10の内部にてその長手方向を左右方向に向けて、第2の導体部8の右端と第3の導体部
9の左端とが所望の隙間12を空けて対向するように配置される。そして、第2の導体部
8の右端側と第3の導体部の左端側には、上述したMOSFET4,5の後面に有する図
示しないドレイン電極が各々表面実装される。
As shown in FIGS. 1 to 2, the second and third conductor portions 8 and 9 are each formed by bending a strip formed of a conductive material twice in a step shape. The left end side of the second conductor portion 8 and the right end side of the third conductor portion 9 are insertion holes (not shown) penetrating the left and right edges below the rear end portion 10a of the package 10.
To the signal patterns 13 and 14 that are exposed to the outside of the package 10 and extend in the left-right direction of the external circuit on the output side. In addition, the second and third conductor portions 8 and 9 are arranged such that the right end of the second conductor portion 8 and the left end of the third conductor portion 9 are in the package 10 with the longitudinal direction thereof being directed in the left-right direction. They are arranged so as to face each other with a desired gap 12 therebetween. The drain electrodes (not shown) on the rear surfaces of the MOSFETs 4 and 5 are surface-mounted on the right end side of the second conductor portion 8 and the left end side of the third conductor portion, respectively.

ここで本実施形態の第1の導体部7は、図1及び図2に示すように第2及び第3の導体
部8,9の真上にて各々の前面を面一として配設されるとともに、前後方向から見たとき
に凸部7aが第2の導体部8と第3の導体部9との間にある隙間12に配置される。そし
て、MOSFET4,5のゲート電極4a,5aは、ボンディングワイヤ11a,11b
を介して各々受光素子3の電極3a,3bに接続される。また、ソース電極4b,5bは
、ボンディングワイヤ11c〜11fを介して凸部7aに接続されることで、ソース電極
4b,5b同士が電気的に接続される。更に突片7bがボンディングワイヤ11gを介し
て受光素子3の電極3cに接続されることで、ソース電極4b,5bが受光素子3の電極
3cと電気的に共通接続される。
Here, as shown in FIGS. 1 and 2, the first conductor portion 7 of the present embodiment is disposed with the respective front surfaces flush with each other immediately above the second and third conductor portions 8 and 9. At the same time, when viewed from the front-rear direction, the convex portion 7 a is disposed in the gap 12 between the second conductor portion 8 and the third conductor portion 9. The gate electrodes 4a and 5a of the MOSFETs 4 and 5 are bonded to the bonding wires 11a and 11b.
Are connected to the electrodes 3a and 3b of the light receiving element 3, respectively. The source electrodes 4b and 5b are electrically connected to each other by being connected to the convex portion 7a via bonding wires 11c to 11f. Further, the projecting piece 7b is connected to the electrode 3c of the light receiving element 3 through the bonding wire 11g, so that the source electrodes 4b and 5b are electrically connected to the electrode 3c of the light receiving element 3 in common.

本実施形態の半導体リレー1の動作について簡単に説明する。先ず、入力側の外部回路
から入力信号が入力されてくると発光素子2が光を後方へ放射する。受光素子3のフォト
ダイオードアレイは、この光を受光して光起電力を発生する。すると前述の図示しない充
放電回路は、フォトダイオードアレイの光起電力の発生によりMOSFET4のゲート電
極4a−ソース電極4b、並びにMOSFET5のゲート電極5a−ソース電極5b間に
効率良く電荷を充電するように制御する。そして、MOSFET4のドレイン電極(図示
せず)−ソース電極4b、並びにMOSFET5のドレイン電極(図示せず)−ソース電
極5bの間が導通して、第2及び第3の導体部8,9の間がMOSFET4,5を介して
導通する。尚、MOSFET4,5は、上述の通り凸部7aを介してソース電極4b,5
b同士を互いに接続することにより逆直列接続されているので、半導体リレー1はMOS
FET4,5を介して高周波の信号を双方向に伝達することが可能となっている。
The operation of the semiconductor relay 1 of this embodiment will be briefly described. First, when an input signal is input from an external circuit on the input side, the light emitting element 2 emits light backward. The photodiode array of the light receiving element 3 receives this light and generates a photovoltaic force. Then, the above-described charging / discharging circuit (not shown) efficiently charges charges between the gate electrode 4a and the source electrode 4b of the MOSFET 4 and between the gate electrode 5a and the source electrode 5b of the MOSFET 5 by the generation of the photovoltaic power of the photodiode array. Control. Then, the drain electrode (not shown) of the MOSFET 4-the source electrode 4 b and the drain electrode (not shown) of the MOSFET 5-the source electrode 5 b are electrically connected, and between the second and third conductor portions 8 and 9. Is conducted through MOSFETs 4 and 5. Note that the MOSFETs 4 and 5 are connected to the source electrodes 4b and 5 via the projection 7a as described above.
Since the b are connected in reverse series by connecting each other, the semiconductor relay 1 is a MOS
High-frequency signals can be transmitted bidirectionally via the FETs 4 and 5.

一方、入力側の外部回路から入力信号が入力されなくなると発光素子2が光を放射しな
くなり、受光素子3のフォトダイオードアレイは光起電力を発生しなくなる。このときM
OSFET4のゲート電極4a−ソース電極4b、並びにMOSFET5のゲート電極5
a−ソース電極5b間に充電されていた電荷が先の充放電回路により放電される。これに
よりMOSFET4のドレイン電極(図示せず)−ソース電極4b、並びにMOSFET
5のドレイン電極(図示せず)−ソース電極5bの間が遮断されて、第2及び第3の導体
部8,9の間は導通から非導通へと切り換えられる。
On the other hand, when the input signal is not input from the external circuit on the input side, the light emitting element 2 does not emit light, and the photodiode array of the light receiving element 3 does not generate photovoltaic power. At this time M
The gate electrode 4a-source electrode 4b of the OSFET 4 and the gate electrode 5 of the MOSFET 5
The charge charged between the a-source electrode 5b is discharged by the previous charge / discharge circuit. As a result, the drain electrode (not shown) of the MOSFET 4-the source electrode 4b and the MOSFET
5 between the drain electrode (not shown) and the source electrode 5b is cut off, and the second and third conductor portions 8 and 9 are switched from conduction to non-conduction.

以下、本実施形態の半導体リレー1の作用について説明する。本実施形態の第1の導体
部7には上述の通り凸部7aが設けられ、凸部7aは前後方向から見たときに第2の導体
部8と第3の導体部9との間にある隙間12に配置される。すなわち、凸部7a、並びに
第2及び第3の導体部8,9が左右方向に沿って一列に並ぶにように配置されて出力側の
外部回路の信号パターン13,14から第1の導体部7の上端までに亘って形成されるス
タブ(図2中の破線矢印)を短くすることができる。従ってスタブの影響により使用可能
な周波数帯域が狭くなるのを防止することができる。
Hereinafter, the operation of the semiconductor relay 1 of the present embodiment will be described. The first conductor portion 7 of the present embodiment is provided with the convex portion 7a as described above, and the convex portion 7a is located between the second conductor portion 8 and the third conductor portion 9 when viewed from the front-rear direction. It is arranged in a certain gap 12. That is, the convex portion 7a and the second and third conductor portions 8 and 9 are arranged in a line along the left-right direction, and the first conductor portion from the signal patterns 13 and 14 of the external circuit on the output side. The stub formed over the upper end of 7 (broken line arrow in FIG. 2) can be shortened. Therefore, it is possible to prevent the usable frequency band from becoming narrow due to the influence of the stub.

また、本実施形態の半導体リレー1と従来の半導体リレー90のインサーションロスに
ついて解析より求めた結果を図3に示している。尚、図3中のaは半導体リレー1の特性
曲線でbは半導体リレー90の特性曲線である。この解析結果が示すように従来の半導体
リレー90は、スタブにより共振が発生して共振周波数付近でインサーションロスが増加
することで使用可能な周波数帯域が狭くなっている。一方、本実施形態の半導体リレー1
は、前記共振周波数付近でのインサーションロスの増加が抑制されていて、半導体リレー
90よりも使用可能な周波数帯域が広くなっている。
Moreover, the result calculated | required by the analysis about the insertion loss of the semiconductor relay 1 of this embodiment and the conventional semiconductor relay 90 is shown in FIG. 3 is a characteristic curve of the semiconductor relay 1, and b is a characteristic curve of the semiconductor relay 90. As shown by the analysis result, the conventional semiconductor relay 90 has a narrow usable frequency band due to resonance generated by the stub and an insertion loss increasing near the resonance frequency. On the other hand, the semiconductor relay 1 of this embodiment
The increase in the insertion loss near the resonance frequency is suppressed, and the usable frequency band is wider than that of the semiconductor relay 90.

尚、本実施形態の半導体リレー1は、第1の端子片6aと第2の導体部7とが各々パッ
ケージ10の後端部10aの左縁部から露出し、第2の端子片6bと第2の導体部8とが
各々パッケージ10の後端部10aの右縁部から露出している。しかしこの限りではなく
従来の半導体リレー90と同様に第1及び第2の端子片6a,6bが各々後端部10aの
上縁部から露出し、第2及び第3の導体部7,8が各々後端部10aの下縁部から露出し
ていてもよい。
In the semiconductor relay 1 of this embodiment, the first terminal piece 6a and the second conductor portion 7 are exposed from the left edge portion of the rear end portion 10a of the package 10, respectively, and the second terminal piece 6b and the second conductor portion 7 are exposed. The two conductor portions 8 are exposed from the right edge portion of the rear end portion 10 a of the package 10. However, the present invention is not limited to this, and the first and second terminal pieces 6a and 6b are exposed from the upper edge portion of the rear end portion 10a, respectively, and the second and third conductor portions 7 and 8 are exposed as in the conventional semiconductor relay 90. You may expose from the lower edge part of the rear-end part 10a, respectively.

(実施形態2)
以下、本発明の実施形態2について、図4〜8を参照して説明する。尚、本実施形態は
基本的な構成が実施形態1と共通であるので、共通の構成要素には、同一の符号を付して
説明を省略する。
(Embodiment 2)
Hereinafter, Embodiment 2 of the present invention will be described with reference to FIGS. Since the basic configuration of the present embodiment is the same as that of the first embodiment, common components are denoted by the same reference numerals and description thereof is omitted.

本実施形態の半導体リレー1は、第1の導体部7の略全体が前後方向から見たときに第
2の導体部8と第3の導体部9との間にある隙間12に配置される点に特徴がある。
The semiconductor relay 1 according to the present embodiment is disposed in the gap 12 between the second conductor portion 8 and the third conductor portion 9 when substantially the entire first conductor portion 7 is viewed from the front-rear direction. There is a feature in the point.

第1の導体部7は、図4及び図5に示すように導電性材料により略平板状に形成されて
その前面には上述した受光素子3が実装される。但し、実施形態1の凸部7aや突片7b
は配設されていない。また、前後方向から見たときの受光素子3の配置される位置が実施
形態1に比べて下方寄りとなることから、発光素子2と受光素子3とが対向して配置され
るように端子片6の実装部6cの上下方向の長さ寸法を実施形態1の実装部6cよりも大
きく設定している。
As shown in FIGS. 4 and 5, the first conductor portion 7 is formed in a substantially flat plate shape with a conductive material, and the light receiving element 3 described above is mounted on the front surface thereof. However, the convex part 7a and the protruding piece 7b of Embodiment 1 are used.
Is not arranged. In addition, since the position where the light receiving element 3 is arranged when viewed from the front-rear direction is closer to the lower side than in the first embodiment, the terminal piece is arranged so that the light emitting element 2 and the light receiving element 3 are arranged to face each other. The length dimension in the vertical direction of the mounting portion 6c of 6 is set larger than that of the mounting portion 6c of the first embodiment.

MOSFET4,5のゲート電極4a,5aは、ボンディングワイヤ11a,11bを
介して各々受光素子3の電極3a,3bに接続される。ソース電極4bは、ボンディング
ワイヤ11c,11dを介して第1の導体部7の左周縁部近傍に接続され、ソース電極5
bは、ボンディングワイヤ11e,11fを介して第1の導体部7の右周縁部近傍に接続
されることで、ソース電極4b,5b同士が電気的に接続される。更に第1の導体部7の
左上端部からからボンディングワイヤ11gを介して受光素子3の電極3cに接続される
ことで、ソース電極4b,5bが受光素子3の電極3cと電気的に共通接続される。
Gate electrodes 4a and 5a of MOSFETs 4 and 5 are connected to electrodes 3a and 3b of light receiving element 3 through bonding wires 11a and 11b, respectively. The source electrode 4b is connected to the vicinity of the left peripheral edge portion of the first conductor portion 7 via bonding wires 11c and 11d, and the source electrode 5
b is connected to the vicinity of the right peripheral edge of the first conductor portion 7 via the bonding wires 11e and 11f, so that the source electrodes 4b and 5b are electrically connected to each other. Furthermore, the source electrodes 4b and 5b are electrically connected in common with the electrode 3c of the light receiving element 3 by being connected to the electrode 3c of the light receiving element 3 from the upper left end of the first conductor part 7 through the bonding wire 11g. Is done.

以下、本実施形態の半導体リレー1の作用について説明する。本実施形態の第1の導体
部7は、略全体が前後方向から見たときに第2の導体部8と第3の導体部9との間にある
隙間12に配置される。すなわち、第1の導体部7、並びに第2及び第3の導体部8,9
が左右方向に沿って一列に並ぶにように配置されて出力側の外部回路の信号パターン13
,14から第1の導体部7の上端までに亘って形成されるスタブ(図5中の破線矢印)を
短くすることができる。従ってスタブの影響により使用可能な周波数帯域が狭くなるのを
防止することができる。
Hereinafter, the operation of the semiconductor relay 1 of the present embodiment will be described. The first conductor portion 7 of the present embodiment is disposed in the gap 12 between the second conductor portion 8 and the third conductor portion 9 when viewed substantially from the front-rear direction. That is, the first conductor portion 7 and the second and third conductor portions 8, 9
Are arranged in a line along the left-right direction, and the signal pattern 13 of the external circuit on the output side
, 14 to the upper end of the first conductor portion 7 can be shortened (broken arrows in FIG. 5). Therefore, it is possible to prevent the usable frequency band from becoming narrow due to the influence of the stub.

また、本実施形態の半導体リレー1と従来の半導体リレー90とのインサーションロス
について解析より求めた結果を図6に示している。尚、図6中のaは半導体リレー1の特
性曲線でbは半導体リレー90の特性曲線である。この解析結果が示すように従来の半導
体リレー90は、スタブにより共振が発生して共振周波数付近でインサーションロスが増
加することで使用可能な周波数帯域が狭くなっている。一方、本実施形態の半導体リレー
1は、前記共振周波数付近でのインサーションロスの増加が抑制されていて半導体リレー
90よりも使用可能な周波数帯域が広くなっている。
Moreover, the result calculated | required by the analysis about the insertion loss of the semiconductor relay 1 of this embodiment and the conventional semiconductor relay 90 is shown in FIG. In FIG. 6, a is a characteristic curve of the semiconductor relay 1, and b is a characteristic curve of the semiconductor relay 90. As shown by the analysis result, the conventional semiconductor relay 90 has a narrow usable frequency band due to resonance generated by the stub and an insertion loss increasing near the resonance frequency. On the other hand, in the semiconductor relay 1 of this embodiment, an increase in insertion loss in the vicinity of the resonance frequency is suppressed, and the usable frequency band is wider than that of the semiconductor relay 90.

ところで、本実施形態の第2及び第3の導体部8,9、並びに端子片6のパッケージ1
0より外部に露出する部位は、段状に曲折しながらパッケージ10の外面から突出してい
る。このように露出する部位は、外部回路の回路基板(図示せず)へ表面実装したときに
インピーダンスの不整合を招く恐れがある。これに対して、図7に示すように前記部位を
パッケージ10の外面と各々面一とすれば、前記部位のインピーダンスの不整合を抑制し
てより使用可能な周波数帯域を広げることができる。
By the way, the package 1 of the 2nd and 3rd conductor parts 8 and 9 of this embodiment, and the terminal piece 6 is shown.
The part exposed to the outside from 0 protrudes from the outer surface of the package 10 while being bent in a step shape. Such exposed portions may cause impedance mismatch when surface-mounted on a circuit board (not shown) of an external circuit. On the other hand, as shown in FIG. 7, if the portions are flush with the outer surface of the package 10, impedance mismatches at the portions can be suppressed and a usable frequency band can be expanded.

尚、上述の様な面一とした半導体リレー1と面一としていない半導体リレー1とのイン
サーションロスについて解析より求めた結果を図8に示している。図8中のaは面一とし
た半導体リレー1の特性曲線で、bは面一としていない半導体リレー1の特性曲線であり
上述の図6中の特性曲線aと同じものである。そして、この解析結果から分かるように、
面一とした半導体リレー1の使用可能な周波数帯域の方が、面一としていない半導体リレ
ー1よりも広くなっている。
In addition, the result calculated | required by the analysis about the insertion loss of the semiconductor relay 1 which was the same as the above and the semiconductor relay 1 which was not the same is shown in FIG. In FIG. 8, a is a characteristic curve of the semiconductor relay 1 that is flush, and b is a characteristic curve of the semiconductor relay 1 that is not flush, which is the same as the characteristic curve a in FIG. And as you can see from this analysis result,
The usable frequency band of the semiconductor relay 1 that is flush is wider than that of the semiconductor relay 1 that is not flush.

(実施形態3)
以下、本発明の実施形態3について、図9〜11を参照して説明する。尚、本実施形態
は基本的な構成が実施形態1と共通であるので、共通の構成要素には、同一の符号を付し
て説明を省略する。
(Embodiment 3)
Hereinafter, Embodiment 3 of the present invention will be described with reference to FIGS. Since the basic configuration of the present embodiment is the same as that of the first embodiment, common components are denoted by the same reference numerals and description thereof is omitted.

本実施形態の半導体リレー1は、第1の導体部7の受光素子3が実装される実装面7c
、第2及び第3の導体部8,9のMOSFET4,5が各々実装される実装面8a,9a、
及び端子片6の発光素子2が実装される実装面6dが、パッケージ10の後端部10aに
対して各々垂直方向に向けられている点に特徴がある。
The semiconductor relay 1 of the present embodiment has a mounting surface 7c on which the light receiving element 3 of the first conductor portion 7 is mounted.
Mounting surfaces 8a and 9a on which the MOSFETs 4 and 5 of the second and third conductor portions 8 and 9 are mounted, respectively.
And the mounting surface 6d on which the light emitting element 2 of the terminal piece 6 is mounted is characterized in that it is directed in the vertical direction with respect to the rear end portion 10a of the package 10, respectively.

端子片6は、図9に示すように細長の矩形板が上下方向から見たときにL字状に形成さ
れる第1の端子片6aと細長の矩形板に形成される第2の端子片6bとから構成される。
そして、第1及び第2の端子片6a,6bは、互いの長手方向を前後方向に向けてパッケ
ージ10内の後端部10a上方で起立するように配設される。第1及び第2の端子片6a
,6bの後端部は、後端部10a上方の左右端に貫設される挿通孔(図示せず)を通じて
パッケージ10の外部に露出する。尚、前記露出する部位はパッケージ10の外面と各々
面一としている。
As shown in FIG. 9, the terminal piece 6 includes a first terminal piece 6a formed in an L shape when the elongated rectangular plate is viewed from above and below, and a second terminal piece formed in the elongated rectangular plate. 6b.
The first and second terminal pieces 6a and 6b are arranged so as to stand above the rear end portion 10a in the package 10 with their longitudinal directions facing in the front-rear direction. First and second terminal pieces 6a
, 6b is exposed to the outside of the package 10 through insertion holes (not shown) penetrating the left and right ends above the rear end 10a. The exposed parts are flush with the outer surface of the package 10.

第1の導体部7は、図9及び図10に示すように導電性材料により略平板状に形成され
て後方周縁部から外側へ略棒状に突出する凸部7aが設けられ、更に前方左右両端部から
外側へ角筒状に延出する延出片7d,7dが配設される。そして、第1の導体部7は、凸
部7aの先端部または延出片7d,7dの先端部のいずれかまたは両方を、パッケージ1
0内の後端部10aまたは左右端部に当接させて、後端部10a下方で起立するように配
設される。尚、実施形態1の突片7bに代わって延出片7dがボンディングワイヤ11g
を介して受光素子3の電極3cに接続される。
As shown in FIGS. 9 and 10, the first conductor portion 7 is formed in a substantially flat plate shape with a conductive material and is provided with a convex portion 7 a that protrudes in a substantially rod shape from the rear peripheral edge portion to the outside. Extending pieces 7d and 7d extending in a rectangular tube shape from the portion to the outside are disposed. And the 1st conductor part 7 is either the front-end | tip part of the convex part 7a, or the front-end | tip part of the extension pieces 7d and 7d, or both.
The rear end portion 10a is placed in contact with the rear end portion 10a or the left and right end portions of the 0 so as to stand up below the rear end portion 10a. In addition, instead of the projecting piece 7b of the first embodiment, the extended piece 7d is bonded to the bonding wire 11g.
To the electrode 3 c of the light receiving element 3.

第2及び第3の導体部8,9は、図9及び図10に示すように各々導電性材料により形
成された帯板が後方で曲折されてなる。そして、第2及び第3の導体部8,9は、パッケ
ージ10の後端部10a下方の左右両端で各々起立するように配設される。第2及び第3
の導体部8,9の後端部は、パッケージ10の後端部10a下方の左右端に貫設される挿
通孔(図示せず)を通じてパッケージ10の外部に露出する。尚、前記露出する部位はパ
ッケージ10の外面と各々面一としている。
As shown in FIGS. 9 and 10, the second and third conductor portions 8 and 9 are each formed by bending a strip formed of a conductive material at the rear. The second and third conductor portions 8 and 9 are disposed so as to stand at both the left and right ends below the rear end portion 10a of the package 10, respectively. 2nd and 3rd
The rear end portions of the conductor portions 8 and 9 are exposed to the outside of the package 10 through insertion holes (not shown) penetrating the left and right ends below the rear end portion 10 a of the package 10. The exposed parts are flush with the outer surface of the package 10.

すなわち、第1、第2及び第3の導体部7,8,9の実装面7c,8a,9aと、端子
片6の実装面6dとは互いに対向し、更にこれらの実装面6d,7c,8a,9aはパッ
ケージ10の後端部10aに対して、実施形態1や2のように平行方向に向けられている
のではなく垂直方向に向けられているので、実施形態1や2の半導体リレー1よりも実装
面積(後端部10aの外面積)の小型化を図ることができる。
That is, the mounting surfaces 7c, 8a, and 9a of the first, second, and third conductor portions 7, 8, and 9 and the mounting surface 6d of the terminal piece 6 face each other, and these mounting surfaces 6d, 7c, and Since 8a and 9a are directed not in the parallel direction as in the first and second embodiments but in the vertical direction with respect to the rear end portion 10a of the package 10, the semiconductor relay according to the first and second embodiments. The mounting area (outer area of the rear end portion 10a) can be made smaller than 1.

また、本実施形態の半導体リレー1と従来の半導体リレー90のインサーションロスに
ついて解析より求めた結果を図11に示している。尚、図11中のaは半導体リレー1の
特性曲線でbは半導体リレー90の特性曲線である。この解析結果が示すように本実施形
態の半導体リレー1は、インサーションロスの増加が抑制されていて半導体リレー90よ
りも使用可能な周波数帯域が広くなっている。更に、本実施形態の半導体リレー1(図1
1の特性曲線a)と、実施形態1や2の半導体リレー1(図3の特性曲線aや図6の特性
曲線a)とを比較しても、本実施形態の半導体リレー1の使用可能な周波数帯域の方がよ
り広くなっていることが分かる。
Moreover, the result calculated | required by the analysis about the insertion loss of the semiconductor relay 1 of this embodiment and the conventional semiconductor relay 90 is shown in FIG. In FIG. 11, a is a characteristic curve of the semiconductor relay 1, and b is a characteristic curve of the semiconductor relay 90. As shown in the analysis result, the semiconductor relay 1 according to the present embodiment suppresses an increase in insertion loss and has a wider usable frequency band than the semiconductor relay 90. Furthermore, the semiconductor relay 1 of this embodiment (FIG. 1
1 and the semiconductor relay 1 of the first and second embodiments (characteristic curve a of FIG. 3 and characteristic curve a of FIG. 6) can be used for the semiconductor relay 1 of the present embodiment. It can be seen that the frequency band is wider.

1 半導体リレー
2 発光素子
3 受光素子
4 MOSFET
4a ゲート電極
4b ソース電極
5 MOSFET
5a ゲート電極
5b ソース電極
6 端子片
7 第1の導体部
7a 凸部
8 第2の導体部
9 第3の導体部
10 パッケージ
10a 後端部




DESCRIPTION OF SYMBOLS 1 Semiconductor relay 2 Light emitting element 3 Light receiving element 4 MOSFET
4a Gate electrode 4b Source electrode 5 MOSFET
5a Gate electrode 5b Source electrode 6 Terminal piece 7 First conductor portion 7a Convex portion 8 Second conductor portion 9 Third conductor portion 10 Package 10a Rear end portion




Claims (5)

入力信号に応じて発光する発光素子と、発光素子と対向して配置され発光素子から放射
される光を受光して光起電力を発生する受光素子と、ボンディングワイヤを介してゲート
電極及びソース電極が各々受光素子の両端に接続され且つ互いのソース電極同士が接続さ
れて逆直列接続された一対のMOSFETと、発光素子が実装される平板状の実装部を有
して発光素子の電極と入力側の外部回路とを電気的に接続する端子片と、略平板状に形成
されて受光素子が実装される第1の導体部と、略帯板状に形成されて一端側にはMOSF
ETのドレイン電極が各々表面実装されるとともに他端側が出力側の外部回路と接続され
る第2及び第3の導体部と、これらを内部に収納する箱型のパッケージと、を備え、第2
及び第3の導体部の間は、前記光起電力がMOSFETの各ゲート−ソース電極間に印加
されることで各ドレイン−ソース電極間のインピーダンスが変化して導通/非導通に切り
換えられ、
第1の導体部の少なくとも一部は、第2及び第3の導体部のMOSFETが各々実装さ
れる実装面の法線方向から見たときに第2の導体部と第3の導体部との間に配置されるこ
とを特徴とする半導体リレー。
A light emitting element that emits light in response to an input signal, a light receiving element that is disposed opposite to the light emitting element and that receives light emitted from the light emitting element and generates a photovoltaic force, and a gate electrode and a source electrode through bonding wires Are connected to both ends of the light receiving element and have a pair of MOSFETs connected in reverse series with the source electrodes connected to each other, and a flat mounting portion on which the light emitting element is mounted, and the electrodes of the light emitting element and the input A terminal piece for electrically connecting the external circuit on the side, a first conductor portion formed in a substantially flat plate shape on which the light receiving element is mounted, and formed in a substantially strip plate shape on one end side with a MOSF
ET drain electrodes are mounted on the surface, and the other end is connected to an external circuit on the output side, and a box-shaped package that houses these is provided in the second package.
And between the third conductor portions, the photoelectromotive force is applied between each gate-source electrode of the MOSFET, whereby the impedance between each drain-source electrode is changed to be switched between conductive and non-conductive,
At least a part of the first conductor portion is formed between the second conductor portion and the third conductor portion when viewed from the normal direction of the mounting surface on which the MOSFETs of the second and third conductor portions are respectively mounted. A semiconductor relay characterized by being disposed between.
第1、第2及び第3の導体部の受光素子、及び一対のMOSFETが各々実装される各
実装面と端子片の発光素子が実装される実装面とは互いに対向するとともに、これらの実
装面は、パッケージの第2及び第3の導体部、並びに端子片が外部に露出する一端部に対
して垂直方向に向けられていることを特徴とする請求項1記載の半導体リレー。
The mounting surfaces on which the light receiving elements of the first, second, and third conductor portions and the pair of MOSFETs are respectively mounted and the mounting surfaces on which the light emitting elements of the terminal pieces are mounted face each other, and these mounting surfaces 2. The semiconductor relay according to claim 1, wherein the second and third conductor portions of the package and the terminal piece are oriented in a direction perpendicular to one end portion exposed to the outside.
第1の導体部には、周縁部から外側に向かって略棒状に突出する凸部が配設され、
前記凸部は、第1の導体部の前記一部として前記法線方向から見たときに第2の導体部
と第3の導体部との間に配置され、MOSFETのソース電極と各々電気的に接続される
ことを特徴とする請求項1または2記載の半導体リレー。
The first conductor portion is provided with a convex portion protruding in a substantially rod shape from the peripheral portion to the outside,
The convex portion is disposed between the second conductor portion and the third conductor portion as viewed from the normal direction as the part of the first conductor portion, and is electrically connected to the source electrode of the MOSFET. The semiconductor relay according to claim 1, wherein the semiconductor relay is connected to the relay.
第1の導体部は、前記法線方向から見たときに略全体が第2の導体部と第3の導体部と
の間に配置され、MOSFETのソース電極と各々電気的に接続されることを特徴とする
請求項1または2記載の半導体リレー。
The first conductor portion is disposed substantially between the second conductor portion and the third conductor portion when viewed from the normal direction, and is electrically connected to the source electrode of the MOSFET. The semiconductor relay according to claim 1 or 2.
第2及び第3の導体部、並びに端子片のパッケージより外部に露出する部位は、パッケ
ージの外面と各々面一としていることを特徴とする請求項1〜4の何れか1項に記載の半
導体リレー。




5. The semiconductor according to claim 1, wherein the second and third conductor portions and the portion of the terminal piece exposed from the package are flush with the outer surface of the package. relay.




JP2009235379A 2009-10-09 2009-10-09 Semiconductor relay Active JP5502422B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2009235379A JP5502422B2 (en) 2009-10-09 2009-10-09 Semiconductor relay
CN201080045218.9A CN102656803B (en) 2009-10-09 2010-10-07 Semiconductor relay
PCT/IB2010/002533 WO2011042796A1 (en) 2009-10-09 2010-10-07 Semiconductor relay
US13/500,710 US8816310B2 (en) 2009-10-09 2010-10-07 Semiconductor relay
KR1020127009016A KR101351737B1 (en) 2009-10-09 2010-10-07 Semiconductor relay

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021125620A (en) * 2020-02-07 2021-08-30 株式会社東芝 Optical coupling device and high frequency device
WO2023189918A1 (en) * 2022-04-01 2023-10-05 パナソニックIpマネジメント株式会社 Semiconductor relay and semiconductor relay module provided with same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7216678B2 (en) 2020-02-10 2023-02-01 株式会社東芝 optical coupler

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JPH1154787A (en) * 1997-07-30 1999-02-26 Matsushita Electric Works Ltd Optically coupled semiconductor relay
JP2002050950A (en) * 2000-07-31 2002-02-15 Matsushita Electric Works Ltd Semiconductor relay
JP2007165621A (en) * 2005-12-14 2007-06-28 Toshiba Corp Optical coupling device

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Publication number Priority date Publication date Assignee Title
JPH1154787A (en) * 1997-07-30 1999-02-26 Matsushita Electric Works Ltd Optically coupled semiconductor relay
JP2002050950A (en) * 2000-07-31 2002-02-15 Matsushita Electric Works Ltd Semiconductor relay
JP2007165621A (en) * 2005-12-14 2007-06-28 Toshiba Corp Optical coupling device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021125620A (en) * 2020-02-07 2021-08-30 株式会社東芝 Optical coupling device and high frequency device
JP7273741B2 (en) 2020-02-07 2023-05-15 株式会社東芝 Optical coupling device and high frequency device
WO2023189918A1 (en) * 2022-04-01 2023-10-05 パナソニックIpマネジメント株式会社 Semiconductor relay and semiconductor relay module provided with same

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