JP2011082865A - Decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a decoder that can calculate an accurate posterior probability during data collision in Layered algorithm. <P>SOLUTION: The decoder decodes parity-check decoded reception signals by conducting probability operation processing for each of a plurality of hierarchies of test matrixes in parallel by Layered decoding algorithm, and it includes a probability operation processing section for conducting probability operation processing in parallel, and a probability operation processing control section that controls the probability operation processing section to divide the probability operation processing within one hierarchy among the plurality of hierarchies into probability operation processing in plural steps while keeping the parallelism and taking data collision into account, conduct a plurality of probability operation processing in parallel including probability operation that are calculated without being influenced by the data collision in the first-step processing, and conduct probability operation processing in parallel that are calculated while using the results of probability operation up to the (n-1)-th step processing in the n-th processing. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present disclosure relates generally to a decoding device, and more particularly to a decoding device for an LDPC code.

  LDPC (Low Density Parity Check) is one of techniques for correcting an error when a transmission signal is erroneously received due to channel noise. In a transmission / reception scheme using an LDPC code, an LDPC check matrix H is used to perform error correction. The transmission signal Tx is transmitted so that H × Tx = 0 on the transmission side. Therefore, when the transmitted signal is correctly received on the receiving side, the received signal Rx satisfies the condition of H × Rx = 0. This calculation of H × Rx is called a parity check.

  FIG. 1 is a diagram illustrating a transmission / reception model using an LDPC code. A transmission signal Tx = [001001] transmitted from the transmission side 10 so that H × Tx = 0 is received by the reception side 12 as a reception signal Rx = [011001], receiving channel noise in the transmission path. The result of the parity check H × Rx for the received signal Rx is not zero, and it can be seen that the received signal Rx has an error. On the receiving side 12, error correction is performed so that H × Rx = 0 using an LDPC decoder that performs LDPC decoding. As a result, the error-corrected received signal Rx ′ = [001001] is obtained.

  FIG. 2 is a diagram illustrating the definition of matrix calculation used in the parity check. As shown in FIG. 2, in the parity check matrix calculation, “product” is a logical product (&) operation and “sum” is an exclusive logical sum (XOR) in a normal product-sum calculation. To do.

FIG. 3 is a diagram for explaining an LDPC parity check matrix and a probability message. As shown in FIG. 3, the LDPC parity check matrix is an M × N matrix, each column is denoted by b1 to bN, and each row is denoted by c1 to cM. b1 to bN are called bit nodes, and c1 to cM are called check nodes. If the element of m rows and n columns of the check matrix H is “1”, a probability message α _mn from the check node cm to the bit node bn and a probability message β _mn from the bit node bn to the check node cm are defined. The That is, probability messages α _mn and β _mn are defined for a set of bit node bn and check node cm corresponding to an element whose value is “1” in parity check matrix H. These probability messages are exchanged between the check node and the bit node to increase the probability of the received signal. A posterior probability sum _{n of the} received signal is defined for each bit node bn.

  In the LDPC decoding process, the probability information calculated from the probabilistic reliability information of the received signal is updated to obtain a received signal with a parity check result of zero. As the LDPC decoding algorithm, a Layered decoding algorithm having a good correction capability is generally used.

FIG. 4 is a diagram showing an example of the configuration of an LDPC decoder using the Layered algorithm. The LDPC decoder 20 includes a probability calculation processing unit 21 and a parity check unit 22. The input λ to the LDPC decoder 20 is a value derived from the received signal, which is a priori probability that represents whether the transmission signal is 0 or 1 and is called LLR (Log-Likelihood Ratio). The output Rx ′ of the LDPC decoder 20 is a received signal after error correction. The probability calculation processing unit 21 obtains the posterior probability sum _n based on the prior probability λ _n and updates the posterior probability sum by iterative processing, thereby performing a process for increasing the probability. This probability calculation processing corresponds to obtaining the posterior probability from the prior probability representing the probabilistic reliability of the received signal in consideration of the constraint condition of the received signal based on the parity check. The parity check unit 22 calculates Rx ′ using the posterior probability sum and performs a parity check H × Rx ′ calculation. Based on whether the result of this parity check is zero or not, it is controlled whether to end the decoding process or feed back the posterior probability sum to repeat the iterative process once more.

The probability calculation processing unit 21 includes a bit node processing unit 25, a check node processing unit 26, and a posterior probability update processing unit 27. The bit node processing unit 25 calculates the probability message β _mn using the prior probability λ _n or the posterior probability sum _n and the probability message α _mn . Specifically, to calculate the probability that the message beta _mn with prior probability lambda _n as posterior probabilities sum _n in the initial state, probability that the message using the sum _n posterior probability updating unit 27 is determined in a subsequent iteration β _mn is calculated. The check node processing unit 26 updates the probability α _mn using the probability β _mn . The posterior probability update processing unit 27 updates the posterior probability sum _n using β _mn calculated by the bit node processing unit 25 and α _mn calculated by the check node processing unit 26.

The bit node processing f _b (sum _n , α _mn ) executed by the bit node processing unit 25 is specifically calculated as follows.
β _mn = f _b (sum _n , α _mn ) = sum _n −α _mn (1)
Further, the posterior probability update processing f _s (α _mn , β _mn ) calculated by the posterior probability update processing unit 27 is specifically calculated as follows.
sum _n = f _s (α _mn , β _mn ) = β _mn + α _mn (2)
The updated α _mn is calculated by the check node process between the bit node process and the posterior probability update process, and the posterior probability update process is executed using the updated α _mn , so that the posterior probability sum _n Probability can be increased sequentially by iterative processing. Note that the Layered algorithm includes a Layered BP algorithm, a Layered Min-sum algorithm, a Layered Normalized Min-sum algorithm, and the like _{depending on} the calculation formula of α _mn in the check node processing.

  The Layered decoding algorithm is an algorithm that divides a parity check matrix into a plurality of row blocks called hierarchies and performs a probability calculation process. For example, the M × N LDPC parity check matrix is divided into L hierarchies each having P rows, and the probability calculation process is performed.

FIG. 5 is a diagram illustrating an LDPC parity check matrix that is divided into L layers each having P rows. FIG. 6 is a diagram showing the execution order of the Layered algorithm in one layer. FIG. 7 is a diagram illustrating the execution order of the Layered algorithm in a plurality of layers. As described above, the probability calculation process is performed on the position where the element of the parity check matrix is “1” (the position where α _mn and β _mn are defined). At this time, in one layer, as shown in FIG. 6, the probability calculation processing (bit node processing unit, check node processing unit, and posterior probability update processing unit) of the Layered decoding algorithm is executed in order. In addition, each of the bit node processing unit, the check node processing unit, and the posterior probability update processing unit is executed in parallel for P rows in one hierarchy. Here, the posterior probability of the nth column obtained by the probability calculation processing for the hierarchy ^l is represented as sum _n ^l . As shown in FIG. 6, the process of obtaining the posterior probability of the hierarchy l based on the posterior probability of the hierarchy l-1, that is, the process of sequentially calculating sum _n ^l-1 → β _mn → α _mn → sum _n ^l is 1 Executed in the hierarchy.

When the above sum _n ^l-1 → β _mn → α _mn → sum _n ^l are sequentially _expressed as sum _n ^l = fl (sum _n ^l−1 ), the probability calculation processing in a plurality of layers is shown in FIG. 7 can be shown. As shown in FIG. 7, the posterior probability sum _n ¹ of the first layer is calculated based on the initial value sum _n ^0, and the posterior probability sum _n ² of the ^second layer is based on the posterior probability sum _n ¹ of the first layer. The third layer posterior probability sum _n ³ is calculated based on the first layer posterior probability sum _n ² . Thereafter, the posterior probability is obtained in the same manner for each layer.

In the above processing, the posterior probability sum _n ^l of the l-th layer is calculated based on the posterior probability sum _n ^{l- 1} of the ^l- 1th layer, and the posterior probability sum _n ^l in this l-th layer is It is executed simultaneously for the position of the value “1” in the P row. Such processing may cause a problem of data collision due to the check matrix.

FIG. 8 is a diagram illustrating the occurrence of data collision. Consider a case where two “1” s exist in the same column in one hierarchy l as shown in FIG. In the Layered algorithm, the posterior probability sum _n ^l (shown as sum _n ^l (1)) for the position “1” on the upper side is calculated based on the posterior probability sum _n ^l−1 of the previous layer. The In parallel with this, the calculation of the posterior probability sum _n ^l (shown as sum _n ^l (2)) for the position of “1” on the lower side is also based on the posterior probability sum _n ^l−1 of the previous hierarchy. Calculated. It would otherwise, since the posterior probabilities _sum ^{n l} by calculation of the upper posterior probabilities _sum ⁿ l (1) has been updated, the calculation of the posterior probability _sum ⁿ l (2) with respect to the position of the lower side "1" Preferably, this is performed based on the value of the updated posterior probability sum _n ^l (1). However, in the Layered algorithm, parallel processing is performed on P rows in order to increase the efficiency of calculation processing. Therefore, when multiple “1” s exist in the same column, probability calculation is performed using an incorrect value. A data collision problem occurs. When this data collision occurs, an incorrect value is used, so that an error occurs, and as a result, the error correction capability is affected. Such a data collision problem occurs for a check matrix having a plurality of “1” s in the same column in the same hierarchy.

  Non-Patent Document 1 discloses a method for solving data collision by approximation. This method subtracts the posterior probability of the previous hierarchy from the sum obtained by adding the two posterior probabilities after the update for the column where data collision occurs in a hierarchy. Execute the process. By this post-processing, approximate calculation of the posterior probability is performed. In this processing, only approximation processing is performed, and calculation is not performed using correct posterior probability values. In such an a posteriori probability approximation process, the reception BER (Bit Error Rate) characteristics deteriorate, and stable reception cannot be performed in a poor reception environment.

International Publication No. WO2004 / 107585 Pamphlet JP 2006-191246 A JP 2004-186940 A JP 2006-304130 A

Arthur Segard, Francois Verdier, David Declercq and Pascal Urard, “ADVB-S2 Compliant LDPC Decoder Integrating the Horizontal Shuffle Scheduling,” ISPACS 2006, pp. 1013-1016, Dec. 2006

  In view of the above, a decoding device that can calculate a correct posterior probability value at the time of data collision in the Layered algorithm is desired.

  A decoding apparatus that performs a decoding process on a parity check encoded received signal by executing a probability calculation process in parallel for each of a plurality of hierarchies of a check matrix using a Layered decoding algorithm. By controlling the probability calculation processing unit executed in parallel and the probability calculation processing unit, the probability calculation processing in one of the plurality of layers is considered in consideration of data collision while maintaining parallelism. In the first stage process, a plurality of probability calculation processes including a probability calculation that is calculated without being affected by data collision are executed in parallel. A probability calculation processing control unit for executing in parallel the probability calculation processing calculated using the probability calculation result of the process up to −1 stage.

  According to at least one embodiment of the present disclosure, a correct posterior probability value can be calculated at the time of data collision in the Layered algorithm.

It is a figure which shows the transmission / reception model using a LDPC code. It is a figure which shows the definition of the matrix calculation used by a parity check. It is a figure for demonstrating a LDPC check matrix and a probability message. It is a figure which shows an example of a structure of a LDPC decoder. It is a figure which shows the LDPC check matrix divided | segmented into the L hierarchy. It is a figure which shows the execution order of the Layered algorithm within one hierarchy. It is a figure which shows the execution order of the Layered algorithm in a some hierarchy. It is a figure which shows generation | occurrence | production of data collision. It is a figure which shows the data collision solution method. It is a figure which shows the 1st Example of the probability calculation process performed by a process of multiple times in consideration of a data collision, maintaining parallelism as much as possible. It is a flowchart which shows the 1st Example of the probability calculation process performed by considering a data collision, maintaining a parallelism as much as possible, and performing multiple processes. It is a figure which shows the 1st Example of a structure of the LDPC decoder which performs a probability calculation process by considering a data collision, maintaining a parallelism as much as possible, and performing a process multiple times. It is a figure which shows the 2nd Example of the probability calculating process performed by considering a data collision and maintaining a parallelism as much as possible, and performing by multiple processes. It is a figure which shows calculation of (alpha) _mn in a check node process. It is a flowchart of the concrete process which judges the necessity of code recalculation and absolute value recalculation. It is a flowchart of the general process which judges the necessity of code recalculation and absolute value recalculation. It is a flowchart which shows the 2nd Example of the probability calculating process performed by considering a data collision, and performing by multiple times processing, maintaining parallelism as much as possible. It is a figure which shows the 2nd Example of a structure of the LDPC decoder which performs a probability calculation process by considering a data collision, maintaining a parallelism as much as possible, and performing a process multiple times. It is a figure which shows the BER characteristic result obtained by simulation. It is a figure which shows an example of a system structure provided with the LDPC decoder.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 9 is a diagram illustrating a data collision solution method. As shown in FIG. 9, when there are two “1” s in the same column in the hierarchy 1 of the parity check matrix H, the post-stage process 151 is performed after the pre-stage process 150 is performed. At this time, in the pre-stage processing 150, the posterior probability sum _n ^l (1) of “1” on the upper side may be calculated, and the posterior probability sum _n ^l (2) for the position of “1” on the lower side may not be calculated. . Alternatively, in the pre-processing 150, the posterior probability sum _n ^l (2) for the upper stage “1” is calculated and the posterior probability sum _n ^l (2) for the position “1” on the lower stage is calculated. Good. In the post-processing 151, the posterior probability sum _n ^l (2) for the position of “1” on the lower side is calculated using the posterior probability sum _n ^l (1) on the upper side. If “1” on the lower side is the last “1” in the same column in the hierarchy l, this posterior probability sum _n ^l (2) becomes the posterior probability sum _n ^l after the probability calculation processing of the hierarchy l. If “1” on the lower side is not the last “1” in the same column in the hierarchy l, and there is a third “1” on the lower level, further post-processing 151 is executed in the same manner, and the third The posterior probability sum _n ^l (3) for “1” is obtained.

  The pre-stage process 150 and the post-stage process 151 are executed in consideration of data collision while maintaining parallelism as much as possible. That is, if the probability calculation processing for other columns and other rows can be executed in parallel with the pre-stage process 150 and the post-stage process 151, these processes are executed in parallel. In the first embodiment, which will be described in detail below, in the first stage of processing, all probability calculations that can be calculated correctly without being affected by data collision are executed in parallel. Further, in the subsequent processing, the probability calculation that is not calculated in the first processing and can be correctly calculated for the first time by using the execution result of the first processing in order to be affected by the data collision is executed in parallel. . More generally, in a multi-stage process, all probability calculation processes that can be calculated correctly without being affected by data collision in the first stage process are executed in parallel, and the subsequent n-th stage (n: 2 or more) In the process of (integer), processes using the probability calculation results of the processes up to the (n-1) th stage are executed in parallel. In the second embodiment, all probability calculations are executed in parallel in the first stage process. Further, in the subsequent processing, probability calculation processing that requires recalculation in order to be affected by data collision is executed in parallel. More generally, in multi-stage processing, all probability calculation processes are executed in parallel in the first stage process, and the probability calculation results of processes up to the (n-1) -th stage in the subsequent n-th stage process. Execute processes that require recalculation in parallel.

  As described above, in the Layered algorithm, the probability calculation process in one layer is divided into a plurality of probability calculation processes in consideration of data collision while maintaining parallelism. In the first stage, a plurality of probability calculation processes including a probability calculation that can be calculated correctly without being affected by data collision are executed in parallel. In the n-th stage process, the probability calculation results of the processes up to the (n-1) -th stage are executed. Probabilistic calculation processing that can be correctly calculated using is executed in parallel. Here, maintaining parallelism means maintaining as much as possible, and when parallelism cannot be maintained, it is allowed that parallel processing is not performed. For example, if there is only one probability calculation process to be executed in the n-th stage process, of course, only that one process is executed. Moreover, the probability calculation that can be calculated correctly is a probability calculation that yields the same result as when the probability calculation processing is performed line by line in order from the top in the target hierarchy.

  FIG. 10 is a diagram showing a first example of a probability calculation process executed by a plurality of processes in consideration of data collision while maintaining parallelism as much as possible. A matrix 30 is shown as an example of the hierarchy l. A plurality of “1” s in the same column at a total of four positions: the position of the second row and the first column, the position of the third row and the first column, the position of the fourth row and the fourth column, and the position of the fourth row and the sixth column. A data collision occurs. That is, at these four positions, it is impossible to calculate a correct posterior probability value by using only the result of the probability calculation process of the previous hierarchy l-1. Also, a correct posterior probability value cannot be obtained even at a position affected by the probability β of these four positions.

In FIG. 10, a set S (βi) is a set of probability messages β to be calculated by i-stage processing. A set S (αi) is a set of probability messages α to be calculated by i stages of processing. Furthermore, the set S (sumi) is a set of posterior probabilities sum to be calculated by i-stage processing. In the case of the example of the matrix 30, first, the first stage probability calculation process is executed in parallel for each set shown in the set group 31. That is, the entire probability calculation process that can correctly calculate the posterior probability without being affected by the data collision is executed. In this case, the probability calculation processing (that is, bit node processing) for obtaining the probability β corresponding to the position of “1” that first appears in each column can be correctly calculated. That is, the set S (β1) = {β ₁₁ , β ₁₆ , β ₂₄ , β ₂₅ , β ₃₃ } can be correctly calculated using only the result of the probability calculation process of the previous hierarchy l-1. In addition, the probability calculation processing (that is, check node processing) for obtaining the probability α in the row in which the bit node processing is correctly calculated at all “1” positions can be correctly calculated. That is, the set S (α1) = {α ₁₁ , α ₁₆ } can be correctly calculated using the result of the already executed bit node processing. In addition, the probability calculation process (that is, the posterior probability update process) for obtaining the posterior probability sum for the column in which the bit node process and the check node process are correctly performed can be calculated correctly for the time being. That is, the set S (sum1) = {sum ₁ , sum ₆ } can be calculated correctly using the result of the already executed bit node processing and check node processing. Note that the “correct calculation for the time being” mentioned here is a calculation that can be further updated in the subsequent stage although it is a correct update operation for the process in this stage.

Next, the second-stage probability calculation process is executed in parallel for each set shown in the set group 32. That is, the probability calculation process that can correctly calculate the posterior probability using the probability calculation result of the process up to the first stage is executed in parallel. In this case, the probability calculation process (that is, the bit node process) for updating the probability β for the column in which the posterior probability sum and the probability α are correctly updated in the probability calculation process up to the first stage is the probability of the process up to the first stage. It is possible to calculate correctly using the calculation result. That is, the set S (β2) = {β ₂₁ , β ₄₆ } can be correctly calculated using the result of the probability calculation processing up to the first stage. In addition, the probability calculation processing (that is, check node processing) for obtaining the probability α in the row in which the bit node processing is correctly calculated at all “1” positions can be correctly calculated. That is, the set S (α2) = {α ₂₁ , α ₂₄ , α ₂₅ } can be correctly calculated using the result of the already executed bit node processing. In addition, the probability calculation process (that is, the posterior probability update process) for obtaining the posterior probability sum for the column in which the bit node process and the check node process are correctly performed can be calculated correctly for the time being. That is, the set S (sum2) = {sum ₁ , sum ₄ , sum ₅ } can be calculated correctly for the time being using the results of the already executed bit node processing and check node processing.

Next, for each set shown in the set group 33, the third-stage probability calculation process is executed in parallel. That is, the probability calculation process that can correctly calculate the posterior probability using the probability calculation result of the process up to the second stage is executed in parallel. In this case, the probability calculation process (that is, the bit node process) for updating the probability β for the column in which the posterior probability sum and the probability α are correctly updated in the probability calculation process up to the second stage is the probability of the process up to the second stage. It is possible to calculate correctly using the calculation result. That is, the set S (β3) = {β ₃₁ , β ₄₄ } can be correctly calculated using the result of the probability calculation processing up to the second stage. In addition, the probability calculation processing (that is, check node processing) for obtaining the probability α in the row in which the bit node processing is correctly calculated at all “1” positions can be correctly calculated. That is, the set S (α3) = {α ₃₁ , α ₃₃ , α ₄₄ , α ₄₆ } can be correctly calculated using the result of already executed bit node processing. In addition, the probability calculation process (that is, the posterior probability update process) for obtaining the posterior probability sum for a column in which the bit node process and the check node process are correctly performed can be correctly calculated. That is, for the set _{S (sum3) = {sum 1} , sum 3, sum 4, sum 6}, can be correctly calculated by using already results of executed bit node processing and check node processing.

FIG. 11 is a flowchart showing a first embodiment of a probability calculation process executed by a plurality of processes in consideration of data collision while maintaining parallelism as much as possible. In step S1, initialization processing is performed. That is, the prior probability λ _n is substituted for the posterior probability sum _n as an initial value. Thereafter, the processes in and after step S2 are repeated for each hierarchy of the check matrix. In step S2, it is determined whether there is a data collision in the target hierarchy. That is, it is determined whether or not there are a plurality of “1” s in the same column of the target hierarchy. If there is no data collision, the process proceeds to step S3. If there is a data collision, the process proceeds to step S6.

  In step S3, bit node processing is executed for the set S. Here, the set S is a set of all elements having a parity check matrix value “1” in the target hierarchy. In step S4, check node processing is executed for the set S. In step S5, a posteriori probability update process is executed for the set S. The processes in steps S3 to S5 are processes for executing each probability calculation process in parallel on all the rows in the target hierarchy, as in the conventional Layered algorithm. When each of these probability calculation processes ends, the process proceeds to step S12.

  In step S6, which is executed when there is a data collision, a variable i indicating what stage of processing is initialized to 1. In step S7, bit node processing is executed for the set S (βi). As described above, the set S (βi) is a set of probability messages β to be calculated by i-stage processing. In step S8, check node processing is executed for the set S (αi). The set S (αi) is a set of probability messages α to be calculated by i-stage processing. In step S9, a posteriori probability update process is executed for the set S (sumi). A set S (sumi) is a set of posterior probabilities sum to be calculated by i-stage processing. In step S10, it is determined whether or not the probability calculation process for the target hierarchy is completed. When the probability calculation process for the target hierarchy is not completed, the value of the variable i is incremented by 1 in step S11, and the process returns to step S7 to repeat the subsequent processes. When the probability calculation process for the target hierarchy is completed, the process proceeds to step S12.

In step S12, it is determined whether or not the probability calculation process for the last layer of the parity check matrix has been completed. When the probability calculation process of the last hierarchy is not completed, the process returns to step S2, and the processes after step S2 are repeated for the next hierarchy. When the probability calculation process of the last hierarchy is completed, a parity check is executed in step S13. That is, Rx ′ calculated from the obtained posterior probability sum _n is multiplied by a check matrix to determine whether or not the calculation result is zero. If the parity check result is zero, by repeating the processes after the process returns to step S2, and updates the posterior probabilities sum _n again. The above process is repeatedly executed until the parity check result becomes zero, and the process ends when the parity check result becomes zero.

FIG. 12 is a diagram illustrating a first example of a configuration of an LDPC decoder that executes probability calculation processing by a plurality of processes in consideration of data collision while maintaining parallelism as much as possible. The LDPC decoder 40 of FIG. 12 includes a bit node processing unit 41, a check node processing unit 42, a posterior probability update processing unit 43, and a parity check unit 44 as a basic configuration. The bit node processing unit 41 calculates the probability message β _mn using the prior probability λ _n or the posterior probability sum _n and the probability message α _mn . Specifically, to calculate the probability that the message beta _mn with prior probability lambda _n as posterior probabilities sum _n in the initial state, probability that the message using the sum _n posterior probability updating unit 43 is determined in a subsequent iteration β _mn is calculated. The check node processing unit 42 updates the probability α _mn using the probability β _mn . The posterior probability update processing unit 43 updates the posterior probability sum _n using β _mn calculated by the bit node processing unit 41 and α _mn calculated by the check node processing unit 42. The parity check unit 44 calculates Rx ′ using the posterior probability sum and performs a parity check H × Rx ′ calculation. Based on whether the result of this parity check is zero or not, it is controlled whether to end the decoding process or feed back the posterior probability sum to repeat the iterative process once more.

  The LDPC decoder 40 further includes a bit node process start control unit 45, a check node process start control unit 46, a posterior probability update process start control unit 47, a data collision detection unit 48, a β memory 49, an α memory 50, and an LLR memory 51. including. The LDPC decoder 40 further includes a β set operation start table 52, an α set operation start table 53, and a sum set operation start table 54. Each process start control part 45 thru | or 47 functions as a probability calculation process control part, and controls the probability calculation process part containing each process part 41 thru | or 43 mentioned above.

  The data collision detection unit 48 determines whether or not there is a data collision for the target hierarchy of the check matrix indicated by the hierarchy counter. The data collision detection unit 48 controls the bit node process start control unit 45, the check node process start control unit 46, and the posterior probability update process start control unit 47 according to the presence or absence of data collision. When there is no data collision, these processing start control units 45 to 47 control the bit node processing unit 41, the check node processing unit 42, and the posterior probability update processing unit 43, respectively, and perform all bit node processing and check in the hierarchy. Node processing and posterior probability update processing are executed.

  When there is a data collision, the bit node processing start control unit 45 sends the bit node processing unit 41 to the bit node processing unit 41 based on the data read from the necessary addresses of the LLR memory 51 and the α memory 50 indicated by the β set operation start table 52. Execute the process. That is, in the i-th stage process, the bit node processing unit 41 executes the bit node process for the set S (βi). Data indicating a set S (βi) of the i-th process is stored in the β set calculation start table 52. The check node processing start control unit 46 causes the check node processing unit 42 to execute the check node processing based on data read from a necessary address in the β memory 49 indicated by the α set calculation start table 53. That is, in the i-th stage process, the check node processing unit 42 performs a bit node process for the set S (αi). Data indicating a set S (αi) of the i-th process is stored in the α set calculation start table 53. Further, the posterior probability update processing start control unit 47 performs posterior probability update processing on the posterior probability update processing unit 43 based on data read from necessary addresses in the α memory 50 and the β memory 49 indicated by the sum set calculation start table 54. Let it run. That is, in the i-th stage process, the posterior probability update processing unit 43 executes the posterior probability update process for the set S (sumi). Data indicating a set S (sumi) of the i-th process is stored in the sum set calculation start table 54.

  FIG. 13 is a diagram showing a second embodiment of the probability calculation process executed by a plurality of processes in consideration of data collision while maintaining parallelism as much as possible. A matrix 60 is shown as an example of the hierarchy l. A plurality of “1” s in the same column at a total of four positions: the position of the second row and the first column, the position of the third row and the first column, the position of the fourth row and the fourth column, and the position of the fourth row and the sixth column. A data collision occurs. That is, at these four positions, it is impossible to calculate a correct posterior probability value by using only the result of the probability calculation process of the previous hierarchy l-1. In addition, a correct posterior probability value cannot be obtained even at a position affected by the probability β of these four positions.

  In the second embodiment of the probability calculation process, all probability calculations are executed in parallel in the first stage process. Further, in the subsequent processing, probability calculation processing that requires recalculation in order to be affected by data collision is executed in parallel. In FIG. 13, C (βi) is a set of probability messages β to be recalculated in the i-th recalculation process in the recalculation process that is the latter stage process. C (αi) and C (sumi) are a set of probability messages α and a set of posterior probabilities sum that need to be determined whether recalculation is necessary according to the result of recalculation of C (βi). E (βi), E (αi), and E (sumi) are C (βi), C (αi), and C (sumi) when C (αi) and C (sumi) need to be recalculated. ) Is a set of β, α, and sum affected by recalculation. C ′ (sumi) is a set of posterior probabilities sum whose values change due to recalculation of C (βi) when recalculation of C (αi) and C (sumi) is not necessary. E ′ (βi), E ′ (αi), and E ′ (sumi) have values obtained by recalculating C (βi) when recalculation of C (αi) and C (sumi) is not necessary. A set of β, α, and sum affected by changing C ′ (sumi).

In the first recalculation process, recalculation for the set group 61 is executed. As C (β1), β _{21 in the} uppermost row among “1” having data conflict becomes a target of recalculation. As a result of recalculation of β ₂₁ , when C (α 1) and C (sum 1) need to be recalculated, C (α 1), C (sum 1), E (β 1), E (α 1), and E (Sum1) is recalculated. Conversely, when recalculation of C (α1) and C (sum1) is not necessary, C ′ (sum1), E ′ (β1), E ′ (α1), and E ′ (sum1) are recalculated. . Similarly, in the second recalculation process, a recalculation is performed on the set group 61, and β _{31 in the} second row of “1” with data collision becomes a recalculation target. Further, in the third recalculation process, recalculation is performed on the set group 63, and β _{44 on} the leftmost side of the third row among “1” having data collision becomes a recalculation target. In the fourth recalculation process, recalculation is performed on the set group 64, and β _46, which is the second from the left in the third row among “1” having data collision, is the object of recalculation. .

  Hereinafter, the determination of the necessity of recalculation processing for C (αi) and C (sumi) will be described. The check node calculation generally used in the Layered algorithm is a Min-sum check node calculation. As a representative of this Min-sum system check node calculation formula, the check node calculation formula of the Min-sum algorithm is as shown in the following formula (3).

ここでＡ（ｍ）は、タナーグラフにおいてチェックノードｃｍに接続する全てのビットノ
ードの集合を表わす。即ち、Ａ（ｍ）は、チェックノードｃｍに対応する検査行列の行に
おいて“１”である列の位置に対応するビットノードの集合である。Ａ（ｍ）＼ｎは、Ａ（ｍ）からｂｎを除いたビットノードの集合を表わす。即ち、図１４に示すように、α_ｍｎを計算するときにはβ_ｍｎを使わず、残りの集合Ａ（ｍ）＼ｎのβを用いる。

Here, A (m) represents a set of all bit nodes connected to the check node cm in the Tanner graph. That is, A (m) is a set of bit nodes corresponding to the position of the column that is “1” in the row of the check matrix corresponding to the check node cm. A (m) \ n represents a set of bit nodes obtained by removing bn from A (m). That is, as shown in FIG. 14, when α _mn is calculated, β _mn is not used, and β of the remaining set A (m) \ n is used.

The Min-sum check node calculation formula is divided into two parts, an absolute value calculation part and a sign calculation part. The absolute value of α _mn is equal to the minimum absolute value of β of the set A (m) \ n. Therefore, if β _mn is not the minimum value, the absolute value of α _mn is the same as the minimum value of the absolute value of β in the entire set A (m). If β _mn is the minimum value, α _mn The absolute value is the same as the second minimum value of the absolute values of β in the entire set A (m). The sign of α _mn is calculated by multiplying the sign of β of A (m) \ n. _{Depending on} the sign multiplication characteristic, the code of α _mn may be obtained by multiplying the β code of the entire set A (m) and then multiplying by the code of β _mn .

FIG. 15 is a flowchart of specific processing for determining the necessity of code recalculation and absolute value recalculation. The flowchart shown in FIG. 15 explains the set group 61 in the first recalculation process shown in FIG. In step S1, β ′ ₂₁ = f _b (sum ₁ ^l (1), α ₂₁ ) is recalculated using the above equation (1). Β ′ represents a value after recalculation with respect to β before recalculation. Here, sum ₁ ^l (1) is the first column (column corresponding to the bit node bn) obtained by the probability calculation process performed on the first row (row corresponding to the check node c1) of the hierarchy l. A posteriori probability. In the check node processing of the check node c2, as can be seen from the above equation (3), α ₂₁ is obtained from β ₂₄ and β ₂₅ , α ₂₄ is obtained from β ₂₁ and β ₂₅ , and α ₂₅ is obtained from β ₂₁ and β It will be obtained from ₂₄ . Therefore, the recalculation of β ′ ₂₁ will affect at least the calculation of α ₂₄ and α ₂₅ .

First, as a premise, in the second embodiment of the probability calculation process, all probability calculations are executed in parallel in the first stage process. For example, it is known that the check node c2 is a target of recalculation. Check node processing is calculated without using β ₂₁ . That is, the minimum value and the second minimum value are calculated from | β ₂₄ | and | β ₂₅ | excluding β ₂₁ , and α ₂₁ , α ₂₄ , and The absolute value of α ₂₅ is calculated. However, the codes α ₂₁ , α ₂₄ , and α ₂₅ are calculated using the codes β ₂₁ , β ₂₄ , and β ₂₅ . It is assumed that the absolute value of α ₂₁ is the same value as the minimum value. After the parallel processing of all probability calculations in the first stage processing is completed, recalculation as the subsequent stage processing is executed.

First, in step S2, it is determined whether or not the sign of β ₂₁ calculated from sum ₁ ^l-1 of the previous layer is different from the sign of β ′ ₂₁ recalculated from sum ₁ ^l (1). If the signs are different, as can be seen from the above equation (3), the signs of α ₂₄ and α ₂₅ will change due to the recalculation of β ′ ₂₁ , so the signs of α ₂₄ and α ₂₅ are recalculated. (Step S3). If the sign is not different in the determination in step S2, it is not necessary to recalculate the sign (step S4).

In step S5, 'absolute value of ₂₁ | beta' recalculated beta _{21 |} is, | beta _{24 |} and | beta _{25 |} less determines whether the minimum value of. If smaller than the minimum value, the absolute values of α ₂₄ and α ₂₅ are re-established with | β ′ ₂₁ | as the new minimum value and the minimum values of | β ₂₄ | and | β ₂₅ | as the new second minimum value. Calculate (step S6). If the result of determination in step S5 is NO (if not smaller than the minimum value), the process proceeds to step S7.

In step S7, 'absolute value of ₂₁ | beta' recalculated beta _{21 |} is, | beta _{24 |} and | beta _{25 |} minimum than large and of | beta _{24 |} and | than a second minimum value of _| beta ₂₅ Judge whether it is small or not. When the determination result is YES, absolute values of α ₂₄ and α ₂₅ are recalculated using | β ′ ₂₁ | as a new second minimum value (step S8). The determination result in step S7 is the case of NO, alpha recalculation is not necessary in absolute value of ₂₄ and alpha _25.

In the flowchart of FIG. 15, in order to simplify the explanation, it is assumed that the check node processing is calculated for the check node c2 without using β ₂₁ that is known to be recalculated. However, normal check node processing including β ₂₁ may be performed. Is this case, 'In examining the effect of the recalculation of _21, beta' beta with ₂₁ determines whether the minimum value or the second minimum value, beta ₂₁ is the smallest value or the second minimum value It may be determined whether or not. That is, in step S9 in FIG. 15, it is determined that absolute value recalculation is not necessary, but when β ₂₁ is the minimum value or the second minimum value, α ₂₄ and α ₂₅ calculated using β ₂₁ are obtained. Since recalculation is required, recalculation may be performed as appropriate.

By executing the processing of the flowchart of FIG. 15, recalculation for the set group 61 is executed in the first recalculation processing shown in FIG. 13. In the case of steps S3, S6, and S8 in FIG. 15, recalculation of C (α1) and C (sum1) is required in FIG. 13, and C (α1) = {α ₂₄ , α ₂₅ } is recalculated as described above. And C (sum1) = {sum ₁ , sum ₂ , sum ₃ } is recalculated. Also, E (β1), E (α1), and E (sum1) affected by these recalculations are recalculated. In the case of steps S4 and S9 in FIG. 15, it is not necessary for recalculation of the check node processing of C ([alpha] 1) in FIG. 13, _{'because 21} is recalculated, C' β (sum1) = {sum ₁ } posterior probability update processing is recalculated. Further, E ′ (β1), E ′ (α1), and E ′ (sum1) that are affected by the recalculation are recalculated.

FIG. 16 is a flowchart of a general process for determining the necessity of code recalculation and absolute value recalculation. In step S1, β ′ _mn = f _b (sum _n ¹ (i), α _mn ) is recalculated using the above-described equation (1). In step S2, the sign of β _mn calculated from sum _n ^l-1 or sum _n ^l (i-2) of the previous layer is different from the sign of β ′ _mn recalculated from sum _n ^l (i) of the target layer. Determine whether or not. If the signs are different, as can be seen from the above equation (3), the sign of α is changed by recalculation of β ′ _mn , so the sign of α is recalculated (step S3). If the sign is not different in the determination in step S2, it is not necessary to recalculate the sign (step S4).

In step S5, _'the absolute value of _mn | _beta' recalculated beta _mn | determines whether or not the minimum value min1 is smaller than the beta of the set A (m) \n. If it is smaller than the minimum value, the absolute value of α is recalculated with | β ′ _mn | as the new minimum value and the original minimum value min1 as the new second minimum value (step S6). If the result of determination in step S5 is NO (if not smaller than the minimum value), the process proceeds to step S7.

In step S7, _'the absolute value of _mn | _beta' recalculated beta _mn | is set A (m) greater than the minimum value min1 the beta of \n and set A (m) second minimum value of beta for \n It is determined whether it is smaller than min2. If the determination result is YES, the absolute value of α is recalculated using | β ′ _mn | as the new second minimum value (step S8). When the determination result in step S7 is NO, it is not necessary to recalculate the absolute value of α.

FIG. 17 is a flowchart showing a second embodiment of the probability calculation process executed by a plurality of processes in consideration of data collision while maintaining parallelism as much as possible. In step S1, initialization processing is performed. That is, the prior probability λ _n is substituted for the posterior probability sum _n as an initial value. Thereafter, the processes in and after step S2 are repeated for each hierarchy of the check matrix. In step S2, bit node processing is executed for the set S. Here, the set S is a set of all elements having a parity check matrix value “1” in the target hierarchy. In step S3, check node processing is executed for the set S. In step S4, a posteriori probability update process is executed for the set S. In the processes in steps S2 to S4, each probability calculation process may be executed in parallel for all the rows in the target hierarchy, similarly to the conventional Layered algorithm. Note that the probability calculation that is surely required to be recalculated later may be left uncalculated without being executed.

  Next, in step S5, it is determined whether or not there is a data collision in the target hierarchy. That is, it is determined whether or not there are a plurality of “1” s in the same column of the target hierarchy. If there is no data collision, the process proceeds to step S19. If there is a data collision, the process proceeds to step S6.

  In step S6, a variable i indicating what stage of processing is initialized to 1. In step S7, bit node processing is executed for the set C (βi). As described above, the set C (βi) is a set of probability messages β to be recalculated. In step S8, it is determined whether or not recalculation is required for C (αi) and C (sumi). As described above, C (αi) and C (sumi) are a set of probability messages α and a set of posterior probabilities sum that need to be determined whether recalculation is necessary according to the result of recalculation of C (βi). It is.

  If the determination result in step S8 is YES, recalculation is performed on C (αi) and C (sumi) in step S9. In step S10, the bit node processing is recalculated for the set E (βi). In step S11, check node processing is recalculated for the set E (αi). In step S12, the posterior probability update process is recalculated for the set E (sumi). As described above, E (βi), E (αi), and E (sumi) can be calculated when C (αi) and C (sumi) need to be recalculated. ) And C (sumi) are affected by recalculating β, α, and sum. When the above processing is completed, the process proceeds to step S17.

  If the determination result in step S8 is NO, recalculation is performed on C ′ (sumi) in step S13. As described above, C ′ (sumi) is a set of posterior probabilities sum whose values change due to recalculation of C (βi) when recalculation of C (αi) and C (sumi) is not necessary. is there. In step S14, the bit node processing is recalculated for the set E ′ (βi). In step S15, check node processing is recalculated for the set E ′ (αi). In step S16, the posterior probability update process is recalculated for the set E ′ (sumi). As described above, E ′ (βi), E ′ (αi), and E ′ (sumi) are recalculated when C (αi) and C (sumi) need not be recalculated. This is a set of β, α, and sum affected by C ′ (sumi) whose value is changed by calculation. When the above processing is completed, the process proceeds to step S17.

  In step S17, it is determined whether determination and recalculation for the set to be recalculated are completed. If not completed, the value of variable i is incremented by 1 in step S18, and the process returns to step S7 to repeat the subsequent processing. As a result of the determination in step S17, if determination and recalculation for the set to be recalculated are completed, the process proceeds to step S19.

In step S19, it is determined whether the probability calculation process for the last layer of the parity check matrix is completed. When the probability calculation process of the last hierarchy is not completed, the process returns to step S2, and the processes after step S2 are repeated for the next hierarchy. When the probability calculation process of the last hierarchy is completed, a parity check is executed in step S20. That is, Rx ′ calculated from the obtained posterior probability sum _n is multiplied by a check matrix to determine whether or not the calculation result is zero. If the parity check result is zero, by repeating the processes after the process returns to step S2, and updates the posterior probabilities sum _n again. The above process is repeatedly executed until the parity check result becomes zero, and the process ends when the parity check result becomes zero.

FIG. 18 is a diagram showing a second example of the configuration of an LDPC decoder that executes probability calculation processing by a plurality of processes in consideration of data collision while maintaining parallelism as much as possible. The LDPC decoder 70 in FIG. 18 includes a bit node processing unit 71, a check node processing unit 72, a posterior probability update processing unit 73, and a parity check unit 78 as a basic configuration. When there is no data collision, the operation is the same as the normal Layered algorithm. That is, the bit node processing unit 71 calculates the probability message β _mn using the prior probability λ _n or the posterior probability sum _n and the probability message α _mn . Specifically, to calculate the probability that the message beta _mn with prior probability lambda _n as posterior probabilities sum _n in the initial state, probability that the message using the sum _n posterior probability updating unit 73 is determined in a subsequent iteration β _mn is calculated. The check node processing unit 72 updates the probability α _mn using the probability β _mn . The posterior probability update processing unit 73 updates the posterior probability sum _n by using β _mn calculated by the bit node processing unit 71 and α _mn calculated by the check node processing unit 72. The parity check unit 78 calculates Rx ′ using the posterior probability sum and performs a parity check H × Rx ′. Based on whether the result of this parity check is zero or not, it is controlled whether to end the decoding process or feed back the posterior probability sum to repeat the iterative process once more.

  The LDPC decoder 70 further includes a data collision detection unit 74, a bit node recalculation unit 75, a check node recalculation unit 76, a posterior probability update recalculation unit 77, a bit node recalculation control unit 79, and a check node recalculation control unit 80. And a posterior probability update recalculation control unit 81. The LDPC decoder 70 further includes a recalculation determination unit 82, a β set recalculation table 83, an α set recalculation table 84, a sum set recalculation table 85, a β memory 86, an α memory 87, an LLR memory 88, a minimum A value & second minimum value & code memory 89 is included. The β memory 86 stores the calculated β and the recalculated β. The α memory 87 stores the calculated α and the recalculated α. The LLR memory 88 stores the initial value λ, the calculated sum, and the recalculated sum. Each of the recalculation control units 79 to 81 and the recalculation determination unit 82 functions as a probability calculation processing control unit, and controls the operation of the probability calculation processing unit including each of the recalculation units 75 to 77.

  The same operation as the normal Layered algorithm by the bit node processing unit 71, the check node processing unit 72, and the posterior probability update processing unit 73 is performed for all probability calculation processes in the target hierarchy regardless of the presence or absence of data collision. Executed. In this operation, the minimum value, the second minimum value, and the sign calculated by the check node processing unit 72 are stored in the minimum value & second minimum value & sign memory 89. The data collision detection unit 74 determines whether or not there is a data collision for the target hierarchy of the check matrix indicated by the hierarchy counter. When there is no data collision, the data collision detection unit 74 overwrites the LLR memory 88 with all posterior probabilities sum of the target hierarchy. If there is a data collision, the data collision detection unit 74 issues a recalculation instruction to the bit node recalculation control unit 79. Based on the instruction from the data collision detection unit 74, the bit node recalculation control unit 79 recalculates the bit node recalculation unit 75 to perform bit node processing for β to be recalculated indicated by the β set recalculation table 83. Let The recalculation determination unit 82 performs recalculation determination based on the data read from the minimum value & second minimum value & code memory 89 and the result of β recalculation. The recalculation determination unit 82 issues an instruction to the bit node recalculation control unit 79, the check node recalculation control unit 80, and the posterior probability update recalculation control unit 81 based on the result of the recalculation determination. In response to an instruction from the recalculation determination unit 82, the bit node recalculation control unit 79 causes the bit node recalculation unit 75 to recalculate the bit node processing for β to be recalculated indicated by the β set recalculation table 83. . The check node recalculation control unit 80 causes the check node recalculation unit 76 to recalculate check node processing for α to be recalculated indicated by the α set recalculation table 84 in response to an instruction from the recalculation determination unit 82. . The posterior probability update recalculation control unit 81 performs the posterior probability update processing on the recalculation target sum indicated by the sum set recalculation table 85 in response to an instruction from the recalculation determination unit 82. Recalculate. When the recalculation for the set to be recalculated in the target hierarchy is completed, the probability calculation process for the next hierarchy is executed.

FIG. 19 is a diagram illustrating a BER characteristic result obtained by simulation. Probabilistic calculation processing that is executed by multiple processing in consideration of data collision while maintaining parallelism as much as possible, ISDB-S2 (Integrated Services Digital Broadcasting via Satellite-Second
Generation). At this time, a simulation was performed using a 7/8 check matrix having the largest data collision among the 11 coding rates of ISDB-S2. The simulation was executed by setting the modulation method QPSK, the communication model AWGN, the number of input bits 10,771,200 bits, and the LDPC decoding process maximum repetition count 50 times. If the parity check value cannot be satisfied even when the number of repetitions of the LDPC decoding process reaches 50, the decoding process is set to end. As shown in the BER characteristic result of FIG. 19, the proposed method can obtain better BER characteristics than the conventional method. When compared with a BER characteristic of 10 ⁻⁴ , the proposed method was able to obtain a gain of about 0.2 dB over the conventional method. Since both the first embodiment and the second embodiment of the probability calculation processing described above perform the probability calculation processing using the correct update value, the result between the first embodiment and the second embodiment is the result. Are the same.

  FIG. 20 is a diagram illustrating an example of a system configuration including an LDPC decoder. In the system shown in FIG. 20, the demodulation unit 100, the LDPC decoder 101, and the decoded data processing unit 102 are sub-fetched. The demodulator 100 demodulates and AD converts the analog reception signal and supplies the digital reception data to the LDPC decoder 101. The LDPC decoder 101 performs LDPC decoding processing by the probability calculation processing of the first embodiment or the second embodiment described above, and performs error correction of digital received data. The data after error correction by the LDPC decoder 101 is supplied to the decoded data processing unit 102, and a desired process is executed by the decoded data processing unit 102.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

  In the probability calculation process of the first embodiment or the second embodiment, it does not matter what calculation is specifically performed as the check node process. It may be a check node process using a Min-sum algorithm, or a check node process using a Normalized Min-sum algorithm or an Offset Min-sum algorithm.

The present invention includes the following contents.
(Appendix 1)
A decoding apparatus that performs a decoding process on a received signal that has been subjected to a low density parity check encoding by executing a probability calculation process in parallel for each of a plurality of layers of a parity check matrix using a layered decoding algorithm,
A probability calculation processing unit for executing the probability calculation processing in parallel;
By controlling the probability calculation processing unit, the probability calculation processing in one of the plurality of layers is divided into a plurality of stages of probability calculation processing in consideration of data collision while maintaining parallelism, In the first-stage process, a plurality of probability calculation processes including a probability calculation that can be correctly calculated without being affected by data collision are executed in parallel. In the n-th process, the probability calculation of the processes up to the (n-1) -th stage is performed. A decoding device including a probability calculation processing control unit that executes in parallel probability calculation processing that can be calculated correctly using the result.
(Appendix 2)
The probability calculation processing unit controlled by the probability calculation processing control unit executes a probability calculation that can be correctly calculated without being affected by data collision in the first-stage processing in parallel. Note that the probability calculation that is not calculated in the processing of the first stage and that can be correctly calculated only by using the execution result of the process up to the previous stage because of the influence of data collision is executed in parallel. The decoding apparatus as described.
(Appendix 3)
The probability calculation processing unit controlled by the probability calculation processing control unit executes all probability calculations in parallel in the first stage process, and re-executes in order to be affected by data collision in the second and subsequent stages. The decoding apparatus according to appendix 1, wherein probability calculation processes that require calculation are executed in parallel.
(Appendix 4)
The probability calculation processing unit controlled by the probability calculation processing control unit specifies a probability calculation process that needs to be recalculated in order to be affected by data collision in the second and subsequent stages of processing. The decoding apparatus according to appendix 3, wherein the probability calculation processes are executed in parallel.
(Appendix 5)
The probability calculation processing unit controlled by the probability calculation processing control unit determines the probability calculation processing that requires the recalculation, and the probability that recalculation is required according to the value of the result that has already been recalculated. The decoding device according to appendix 4, characterized by specifying an arithmetic processing.
(Appendix 6)
The probability calculation process is a process for obtaining a posterior probability in consideration of a constraint condition of a received signal based on a parity check from an a priori probability representing a probabilistic reliability of the received signal,
A bit node process for obtaining a second probability message from the posterior probability and the first probability message having the prior probability as an initial value;
A check node process for obtaining an update value of the first probability message based on the second probability message obtained by the bit node process;
A posterior probability update process for obtaining an update value of the posterior probability based on the second probability message obtained by the bit node process and an update value of the first probability message obtained by the check node process; The decoding device according to any one of appendices 1 to 5, wherein the decoding device includes:
(Appendix 7)
A decoding method for performing a decoding process on a received signal subjected to a low density parity check encoding by executing a probability calculation process in parallel for each of a plurality of hierarchies of a check matrix using a Layered decoding algorithm,
Dividing probability calculation processing in one of a plurality of layers into a plurality of stages of probability calculation processing in consideration of data collision while maintaining parallelism,
In the first stage of processing, a plurality of probability calculation processes including a probability calculation that can be calculated correctly without being affected by data collision are executed in parallel.
In the n-th stage processing, a decoding method including each stage for executing in parallel a probability calculation process that can be calculated correctly using the probability calculation results of the processes up to the (n-1) -th stage.
(Appendix 8)
Probability calculation that can be correctly calculated without being affected by data collision in the first stage processing is executed in parallel, and in the second and subsequent stages, the first stage processing is uncalculated and the influence of data collision The decoding method according to appendix 7, wherein a probability calculation that can be correctly calculated for the first time is executed in parallel using the execution result of the process up to the previous stage in order to receive the error.
(Appendix 9)
In the first stage processing, all probability calculations are executed in parallel, and in the second stage and subsequent processes, probability calculation processes that require recalculation in order to be affected by data collision are executed in parallel. The decoding method according to appendix 7.

40 LDPC decoder 41 bit node processing unit 42 check node processing unit 43 posterior probability update processing unit 44 parity check unit 44
45 bit node process start control unit 46 check node process start control unit 47 posterior probability update process start control unit 48 data collision detection unit 49 β memory 50 α memory 51 LLR memory 52 β set operation start table 53 α set operation start table 54 sum Set operation start table

Claims (5)

A decoding device that performs a decoding process on a parity check encoded received signal by executing a probability calculation process in parallel for each of a plurality of layers of a parity check matrix using a Layered decoding algorithm,
A probability calculation processing unit for executing the probability calculation processing in parallel;
By controlling the probability calculation processing unit, the probability calculation processing in one of the plurality of layers is divided into a plurality of stages of probability calculation processing in consideration of data collision while maintaining parallelism, In the first-stage process, a plurality of probability calculation processes including a probability calculation that is calculated without being affected by data collision are executed in parallel. In the n-th process, the probability calculation results of the processes up to the (n-1) -th stage are performed. A decoding unit including a probability calculation processing control unit that executes in parallel the probability calculation processing to be calculated using   The probability calculation processing unit controlled by the probability calculation processing control unit executes a probability calculation to be calculated without being affected by data collision in the first stage process in parallel, and in the processes after the second stage, 2. The probability calculation which is not calculated in the first stage processing and is calculated for the first time using the execution result of the processing up to the previous stage in order to be affected by data collision, is executed in parallel. Decryption device.   The probability calculation processing unit controlled by the probability calculation processing control unit executes all probability calculations in parallel in the first stage process, and re-executes in order to be affected by data collision in the second and subsequent stages. 2. The decoding apparatus according to claim 1, wherein probability calculation processes requiring calculation are executed in parallel.   The probability calculation processing unit controlled by the probability calculation processing control unit specifies a probability calculation process that needs to be recalculated in order to be affected by data collision in the second and subsequent stages of processing. 4. The decoding apparatus according to claim 3, wherein the probability calculation processes are executed in parallel.   The probability calculation processing unit controlled by the probability calculation processing control unit determines the probability calculation processing that requires the recalculation, and the probability that recalculation is required according to the value of the result that has already been recalculated. 5. The decoding apparatus according to claim 4, wherein an arithmetic processing is specified.

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