JP2011082306A - Zinc oxide-based semiconductor light emitting element and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-performance zinc oxide-based semiconductor light emitting element that ensures a uniform light emission intensity distribution and high light emission efficiency by making a current density distribution uniform, and is superior in mass-productivity, and a method of manufacturing the same. <P>SOLUTION: A ZnO-based crystal layer grown on a substrate of sapphire (Al<SB>2</SB>O<SB>3</SB>) single crystal includes a solid solution layer having aluminum (Al) solid-dissolved in an interface with the substrate to have a concentration of 8×10<SP>20</SP>pieces/cm<SP>3</SP>, and a high-concentration diffusion layer of ≥1×10<SP>19</SP>cm<SP>3</SP>in Al concentration. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a zinc oxide based semiconductor device and a method for growing the same, and more particularly to a zinc oxide based semiconductor light emitting device formed on a sapphire substrate by MOCVD and a method for manufacturing the same.

  Zinc oxide (ZnO) is a direct transition type semiconductor having a band gap energy of 3.37 eV at room temperature, and is expected as a material for optical elements in the blue or ultraviolet region. In particular, the exciton binding energy is 60 meV and the refractive index n = 2.0, which is very suitable for a semiconductor light emitting device. Further, the present invention can be widely applied not only to light emitting elements and light receiving elements but also to surface acoustic wave (SAW) devices, piezoelectric elements, and the like. In addition, the raw material is inexpensive and harmless to the environment and the human body. In particular, it is expected to realize a semiconductor light emitting device with high efficiency and low power consumption by such a material system.

  By the way, zinc oxide (ZnO) single crystals can be grown on sapphire substrates, SiC single crystal substrates, SCAM (ScAlMgO4: scandium / aluminum / magnesium / oxide) single crystal substrates, ZnO single crystal substrates, and the like. is there. In the manufacture of a semiconductor element, for example, a semiconductor light emitting element, when a SiC substrate or a ZnO substrate as a conductive substrate is used, a laminated structure generally composed of an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer is used. An element structure is used in which a current flows in the vertical direction (vertical direction). On the other hand, when an insulating substrate such as a sapphire substrate or SCAM substrate is used, an element structure is used in which electrodes are formed on the same surface and current flows in the horizontal direction. However, when a current is passed in the horizontal direction using an insulating substrate, there is a problem in that a current density distribution is generated in the light emitting section (region), resulting in uneven luminance distribution.

  For example, Patent Documents 1 to 4 disclose that such unevenness of the light emission luminance distribution in the light emitting surface is suppressed. However, these methods are designed to make the current distribution and emission intensity distribution uniform by devising the shape of the electrode and the position of the electrode, the manufacturing process is complicated, the yield decreases, and the light emitting region There is a problem in that the area of the substrate becomes narrow and the current density becomes high.

JP 2000-164930 A JP 2001-345480 JP 2004-221529 JP 2005-328080 JP

  The present invention has been made in view of the above-described points, and an object of the present invention is to provide a semiconductor element having a uniform current density distribution, in particular, a uniform current density distribution, a uniform light emission intensity distribution, and a high light emission efficiency. An object of the present invention is to provide a high-performance semiconductor light emitting device excellent in mass productivity and a method for manufacturing the same.

The semiconductor element of the present invention is a semiconductor element obtained by growing a ZnO-based crystal on a sapphire (Al ₂ O ₃ ) single crystal substrate,
A solid solution layer in which aluminum (Al) of the substrate is dissolved at a concentration of 8 × 10 ²⁰ pieces / cm ³ or more at the interface with the substrate, and a concentration of Al diffused from the substrate is 1 × 10 ¹⁹ cm ³ or more. A ZnO-based crystal layer having a high-concentration diffusion layer;
And a device layer formed on the ZnO-based crystal layer.

The substrate with a growth layer of the present invention is a substrate with a growth layer obtained by growing a ZnO-based crystal on a sapphire (Al ₂ O ₃ ) single crystal substrate,
A solid solution layer in which aluminum (Al) of the substrate is dissolved at a concentration of 8 × 10 ²⁰ pieces / cm ³ or more at the interface with the substrate, and a high concentration of Al diffused from the substrate is 1 × 10 ¹⁹ cm ³ or more. It is characterized by having a ZnO-based crystal layer having a concentration diffusion layer.

The present invention also relates to a method of manufacturing a semiconductor device by growing a ZnO-based crystal on a sapphire (Al ₂ O ₃ ) single crystal substrate,
A solid solution layer in which aluminum (Al) of the substrate is dissolved at a concentration of 8 × 10 ²⁰ pieces / cm ³ or more at the interface with the substrate, and a high concentration of Al diffused from the substrate is 1 × 10 ¹⁹ cm ³ or more. Forming a ZnO-based crystal layer having a concentration diffusion layer;
Forming a device layer formed on the ZnO-based crystal layer,
The step of forming the ZnO-based crystal layer is performed by MOCVD using an organic metal compound not containing oxygen and water vapor.
(A) performing crystal growth at a first low growth temperature within a range of 250 ° C. to 450 ° C. and a low growth pressure within a range of 1 kPa to 30 kPa to form a first single crystal layer;
(B) Crystal growth is performed at a second low growth temperature higher than the first low growth temperature and a pressure higher than the low growth pressure to form a second single crystal layer on the first single crystal layer. Forming step;
(C) performing a crystal growth at a high growth temperature and a pressure higher than the low growth pressure to form a third single crystal layer on the second single crystal layer.

  According to the present invention, the solid solution layer in which aluminum (Al) derived from the substrate is dissolved and the high concentration diffusion layer in which Al is diffused at a high concentration are provided at the interface with the substrate. The layer composed of the solid solution layer and the high concentration diffusion layer has a low electric resistance, and a uniform current density distribution can be obtained. Therefore, the light emission intensity distribution in the light emitting region is uniform, the current injection efficiency is increased, and the light emission intensity is also improved.

It is a figure which shows typically the structure of the MOCVD apparatus used for crystal growth. It is sectional drawing which shows the ZnO type | system | group crystal layer grown on the sapphire substrate by this invention. It is a figure which shows the crystal growth sequence used for the crystal growth by MOCVD method. It is sectional drawing which shows typically the structure of the semiconductor light-emitting device (LED) wafer which is Example 2 of this invention. It is a figure which shows the crystal growth sequence used for the crystal growth of the board | substrate with an LED device layer. It is a top view of a board | substrate with an LED device layer. It is sectional drawing which shows the outline of the element separation process of a board | substrate with an LED device layer. It is the top view and sectional drawing of a semiconductor light emitting element (LED). It is sectional drawing which shows typically the structure of the crystal growth layer of the comparative example formed by RF-MBE method. It is a SIMS analysis result of the crystal growth layer of the board | substrate with a growth layer of Example 1. FIG. It is a figure which expands and shows the profile in the interface (X) vicinity of Al concentration and Zn ion intensity which are shown in FIG. It is a SIMS analysis result of the sample of a comparative example. 2 is a differential microscope image of the growth layer surface of Example 1. FIG. 2 is a SEM image of the growth layer surface of Example 1. FIG. These are (002) ω and (100) ω rocking curves when the thickness (t) of the ZnO layer is 1 μm. These are (002) ω and (100) ω rocking curves when the thickness (t) of the ZnO layer is 3 μm.

  Hereinafter, a method for manufacturing a wafer in which a zinc oxide (ZnO) -based element structure (device layer) is formed on a sapphire substrate by MOCVD will be described in detail with reference to the drawings. Further, a semiconductor light emitting element (LED: Light Emitting Diode) will be described as an example of the semiconductor element. In the drawings described below, substantially the same or equivalent parts are denoted by the same reference numerals.

  FIG. 1 schematically shows the configuration of the MOCVD apparatus 5 used for crystal growth. Details of the apparatus configuration of the MOCVD apparatus 5 will be described below. The crystal growth material will be described in detail later.

[Device configuration]
The MOCVD apparatus 5 includes a gas supply unit 5A, a reaction vessel unit 5B, and an exhaust unit 5C. 5 A of gas supply parts are comprised from the part which vaporizes and supplies organometallic compound material, the part which supplies gaseous material gas, and the transport part provided with the function to convey these gas.

  An organometallic compound material that is liquid (or solid) at room temperature is vaporized and supplied as vapor. In this example, DMZn (dimethylzinc) was used as the zinc (Zn) source, Cp2Mg (biscyclopentadienylmagnesium) was used as the magnesium (Mg) source, and TEGa (triethylgallium) was used as the gallium (Ga) source.

  First, the supply of DMZn will be described. As shown in FIG. 1, the nitrogen gas is adjusted to a predetermined flow rate by a flow rate adjusting device (mass flow controller) 121S and sent to the DMZn storage container 121C through the gas supply valve 121M to saturate the DMZn vapor in the nitrogen gas. Then, the DMZn saturated nitrogen gas is taken out through the valve 121E and the pressure adjusting device 121P to the first vent pipe (hereinafter referred to as the first VENT line (VENT1)) 128V during the growth standby, and to the first run pipe (hereinafter referred to as the first RUN) during the growth. Line (RUN1).) Supply to 128R. At this time, the internal pressure of the storage container is adjusted to be constant by the pressure adjusting device 121P. Further, the DMZn storage container is kept at a constant temperature in the thermostatic chamber 121T.

  The same applies to other organometallic compound materials Cp2Mg and TEGa. That is, nitrogen gas having a predetermined flow rate is supplied to the storage containers 122C (Cp2Mg) and 123C (TEGa) for storing these materials through the flow rate adjusting devices 122S and 123S, and the take-off valves 122E and 123E and the pressure adjusting device 122P are supplied. , 123P, these gases are supplied to the first VENT line (VENT1) 128V during growth standby and to the first RUN line (RUN1) 128R during growth.

In addition, H ₂ O (water vapor), which is a liquid material as an oxygen source, is supplied with a predetermined flow rate of nitrogen gas through the flow rate adjusting device 124S to the containment vessel 124C, and waits for growth through the take-off valve 124E and the pressure adjusting device 124P. Sometimes it is supplied to the second vent pipe (hereinafter referred to as the second VENT line (VENT2)) 129V, and at the time of growth to the second run pipe (hereinafter referred to as the second RUN line (RUN2)) 129R.

As the p-type impurity source, NH ₃ (ammonia) gas, which is a gaseous material, was used. The NH ₃ gas is supplied at a predetermined flow rate by the flow rate adjusting device 125S. The power is supplied to the second VENT line 129V during standby and to the second RUN line 129R during growth. Note that the gas may be diluted with an inert gas such as nitrogen or Ar (argon).

  The liquid or solid material vapor and the gas material (hereinafter referred to as material gas) are supplied to the shower head 130 of the reaction vessel 5B through the first RUN line 128R and the second RUN line 129R. The first RUN line 128R and the second RUN line 129R are also provided with flow rate adjusting devices 120C and 120B, respectively, and the material gas is a shower attached to the upper part of the reaction vessel (chamber) 139 by a carrier gas (nitrogen gas). It is sent to the head 130.

  The shower head 130 has an ejection surface that faces the main surface (growth surface) of the substrate 10, and a large number of material gas ejection holes in the row and row directions (for example, several 10 to 10). 100) formed. The effective ejection diameter of the ejection surface is larger than the outer diameter of the substrate.

The ejection holes include a first ejection hole from which the organometallic compound material gas (group II gas) supplied from the first RUN line 128R is ejected, and H ₂ O (water vapor) (VI) supplied from the second RUN line 129R. A second ejection hole from which a group gas) is ejected. The gas from the first RUN line 128R and the gas from the second RUN line 129R are configured to be ejected from the first ejection hole and the second ejection hole, respectively, without being mixed. The first ejection holes and the second ejection holes are provided in substantially the same number and at intervals of several mm from each other, and are alternately arranged in each column and each row so that the organometallic compound gas and H ₂ O are uniformly mixed. ing.

  In the reaction vessel 139, a shower head 130 that blows a material gas onto the substrate 10, a substrate 10, a susceptor 119 that holds the substrate 10, and a heater 149 that heats the susceptor 119 are installed. The heater 149 can heat the substrate from room temperature to about 1100 ° C.

  Note that the substrate temperature in this embodiment refers to the temperature of the surface of the susceptor 119 on which the substrate is placed. That is, in the case of the MOCVD method, heat transfer from the susceptor 119 to the substrate 10 is performed by direct contact and a gas existing between the susceptor 119 and the substrate 10. Between the growth pressures of 1 kPa to 120 kPa (Pa: Pascal) used in this example, the surface temperature of the substrate 10 is about 0 ° C. to 10 ° C. lower than the surface temperature of the susceptor 119.

  The reaction vessel 139 is provided with a rotation mechanism for rotating the susceptor 119. More specifically, the susceptor 119 is supported by a susceptor support cylinder 148, and the susceptor support cylinder 148 is rotatably supported on the stage 141. Then, the rotation motor 43 rotates the susceptor support cylinder 148 to rotate the susceptor 119 (that is, the substrate 10). The heater 149 is installed in the susceptor support cylinder 148.

  The exhaust part 5C includes a container internal pressure adjusting device 151 and an exhaust pump 152. The internal pressure adjusting device 151 can adjust the pressure in the reaction container 139 to about 0.01 kPa to 120 kPa. .

[Crystal growth material]
In this example, a material that does not contain oxygen in the constituent molecules was used as the organometallic compound material (or organometallic material). An organometallic material that does not contain oxygen is highly reactive with water vapor (oxygen material or oxygen source), and has a low growth pressure, or a flow rate ratio of water vapor to organometallic (MO) (F _H2O / _FMO ratio) or VI / ZnO-based crystals can be grown even in a region where the II ratio is low.

  In this example, DMZn, Cp2Mg, and TEGa were used, but DEZn (diethylzinc), MeCp2Mg (bismethylpentadienylmagnesium), EtCp2Mg (bisethylpentadienylmagnesium), etc., were used as group II materials. Can do. Further, TMGa (trimethylgallium), TMAl (trimethylaluminum), TEAl (triethylaluminum), TIBA (triisobutylaluminum), or the like can be used as the group III material.

As the oxygen material (hereinafter referred to as oxygen source), a polar oxygen material (polar oxygen source) is suitable. In particular, H ₂ O (water vapor) is greatly polarized to δ ⁺ and δ ⁻ on the side where hydrogen atoms are bonded in the molecule and on the side of the lone pair, and has an excellent adsorption ability to the oxide crystal surface.

The H ₂ O molecule has a tetrahedral structure with a hydrogen atom bond and a lone pair, and an oxide of sp ³ type hybrid orbital (Zincblende / Cubic) and wurtzite (Wurtzeite / Hexagonal). Crystal growth is an excellent oxygen source that is preferentially oriented and adsorbed to oxygen sites. Similarly, other oxygen sources may be lower alcohols having a large dipole moment and O atoms taking sp ³ type hybrid orbitals. Specifically, as an oxygen source, in addition to H ₂ O (water vapor), lower alcohols, in particular, lower alcohols having 1 to 5 carbon atoms such as methanol, ethanol, propanol, butanol and pentanol can be used. . In this example, H ₂ O was used, and O ₂ (oxygen) and N ₂ O (nitrous oxide) were used in the comparative example.

As the p-type impurity source, a compound that can easily be substituted for the O (oxygen) site of the zinc blende structure or the wurtzite structure in the crystal growth process is suitable. In particular, NH ₃ is suitable because it has the same action as the above H ₂ O. Specifically, as a p-type impurity material, hydrazines such as NH ₃ (ammonia), (CH ₃ ) ₂ NNH ₂ (dimethylhydrazine), (CH ₃ ) NHNH ₂ (monomethylhydrazine), PH3 (phosphine), R ₁ PH _{2, R 2} PH, alkyl phosphorus compounds, such as _{R 3} P, AsH3 _{(arsine), R 1 PH 2, R} 2 PH, available as alkyl arsenic compounds, such as _{R 3} P. Further, TEGa (triethylgallium) was used as the n-type impurity source. Note that these gases may be diluted with an inert gas such as nitrogen or Ar (argon).

As the carrier gas (atmosphere gas), an inert gas that does not react with the crystal growth material described above is suitable. Further, a gas that does not prevent adsorption of the crystal growth material such as H ₂ O (water vapor) and NH _{3 on} the substrate surface is preferable. Specifically, a chemically inert gas such as He (helium), Ne (neon), Ar (argon), or N ₂ (nitrogen) can be used as the carrier gas and the atmospheric gas. Liquid or solid material vapor and gaseous material (hereinafter referred to as material gas) are fed into the showerhead by the carrier gas and supplied to the substrate.

The substrate 10 is a sapphire single crystal sapphire (Al ₂ O ₃ ) substrate having a corundum structure. Typical substrate cut-out surfaces of the sapphire crystal are a c-plane that is a {0002} plane, an a-plane that is a {11-20} plane, an m-plane that is a {10-10} plane, and a {10-12} plane. There is an R side. In this example, the a-plane (hereinafter also referred to as sapphire a-plane) that is the {11-20} plane was used as the crystal growth plane. In the following, a substrate having a sapphire a-plane as a main surface (crystal growth surface) is also referred to as an a-plane sapphire substrate. Here, the Miller index {} indicates a representative value of an equivalent surface.

FIG. 2 schematically shows the structure of a substrate 15 with a ZnO-based crystal growth layer having a zinc oxide-based semiconductor crystal layer (hereinafter referred to as a ZnO-based semiconductor layer or a ZnO-based crystal layer) grown on the substrate 10 according to the present invention. FIG. More specifically, the first ZnO layer 11A, the second ZnO layer 11B, and the ZnO-based semiconductor layer 12 were grown on the sapphire substrate using the MOCVD method. In the following, a case where Mg _x Zn _{(1-x) 2} O (0.1 ≦ x ≦ 0.68) is grown as the ZnO-based semiconductor layer 12 will be described as an example.

  In the following, the ZnO-based semiconductor may be another compound crystal based on ZnO. For example, a ZnO-based compound crystal in which a part of Zn (zinc) is replaced with calcium (Ca) may be used. Alternatively, a ZnO-based compound crystal in which part of O (oxygen) is replaced with selenium (Se), sulfur (S), tellurium (Te), or the like may be used.

  FIG. 3 shows a crystal growth sequence used for crystal growth by the MOCVD method. First, the a-plane sapphire substrate 10 was set on the susceptor 119 in the MOCVD apparatus, and the reaction vessel pressure was adjusted to 10 kPa (kilopascal) (time T = T1). Further, the sapphire substrate 10 was rotated at a rotation speed of 10 rpm by a rotation mechanism.

Next, nitrogen (N ₂ ) gas was supplied from the first RUN line 128R and the second RUN line 129R to the shower head 130 at a flow rate of 2000 cc / min (total 4000 cc / min) and sprayed onto the sapphire substrate 10.

  The gas flow rate supplied from the first RUN line 128R and the second RUN line 129R to the shower head 130 was always kept constant. That is, when supplying the organometallic material gas and the gaseous material, the flow rates of the flow control devices 120C and 120B provided in the first RUN line 128R and the second RUN line 129R are increased or decreased by the flow rate of the organometallic material gas and the gaseous material. The gas flow rate supplied to the shower head 130 was kept constant.

Next, supply of H ₂ O (water vapor) as an oxygen source from the shower head to the substrate 10 at a flow rate of 640 μmol / min was started (T = T2). Next, the substrate 10 was heated from room temperature (RT) to 900 ° C. with a heater, and the sapphire substrate 10 was heat-treated for 10 minutes (T = T3 to T4). Thereafter, H ₂ O (water vapor) was kept flowing at the same flow rate until the growth was completed. Thereafter, H ₂ O (water vapor) continued to flow at the same flow rate until the end of growth.

  After the heat treatment of the substrate 10, the substrate temperature was lowered to 300 ° C. (first low growth temperature), and DMZn (dimethylzinc) as a zinc raw material was supplied to the substrate 10 at a flow rate of 3 μmol / min for 5 minutes (T = T5− T6: Growth period of the first ZnO layer 11A, period G1A in FIG.

  Thus, a ZnO layer (first low-temperature grown single crystal layer, which has a growth temperature (Tg) of 300 ° C. under a reduced pressure growth condition (growth pressure Pg = 10 kPa), a growth rate of 5 nm / min, and a layer thickness of 25 nm. Hereinafter, it is also simply referred to as a first single crystal layer.) 11A was grown.

  In the present specification, a crystal growth temperature suitable for growing a ZnO single crystal is generally referred to as a “high growth temperature”, and a temperature lower than the temperature is referred to as a “low growth temperature”.

  After the growth of the ZnO layer 11A, the substrate temperature was raised to 1000 ° C., and heat treatment (annealing) for 20 minutes was performed (T = T7 to T8). This heat treatment further improved the crystallinity and flatness of the ZnO layer 11A.

After the heat treatment (annealing) of the first ZnO layer (first low-temperature grown single crystal layer) 11A is completed, the second ZnO layer 11B is grown at a higher temperature and higher pressure than in the case of the first ZnO layer 11A. did. More specifically, the substrate temperature was lowered from the heat treatment temperature (1000 ° C.) to 600 ° C. (second low growth temperature) higher than the first low growth temperature in 3 minutes. The reaction vessel pressure was increased from 10 kPa (low growth pressure) to 80 kPa (high growth pressure). Then, after waiting for 1 minute and the substrate temperature was stabilized, DMZn was supplied onto the ZnO layer 11A from the shower head at a flow rate of 10 μmol / min (T = T9 to T10: growth period of the second ZnO layer 11B, FIG. 3 period G1B). DMZn was supplied for about 2.5 minutes, the growth rate was 16 nm / min, and the thickness of the second ZnO layer (the second low-temperature grown single crystal layer, hereinafter simply referred to as the second single crystal layer) was 40 nm. ) 11B was formed. The flow rate ratio _(F H2O _/ F _MO ratio) of water vapor flow rate and organometallic this time (DMZn), so-called VI / II ratio is 64.

After the growth of the second ZnO layer (second low-temperature grown single crystal layer) 11B was completed, the ZnO-based semiconductor layer 12 was grown at a temperature (high growth temperature) higher than that of the second ZnO layer 11B. More specifically, the substrate temperature was raised from 600 ° C. (second low growth temperature) to 800 ° C. (high growth temperature) while maintaining the reaction vessel pressure at 80 kPa. Then, after waiting for 1 minute and the substrate temperature was stabilized, DMZn was supplied onto the ZnO layer 11B from the shower head at a flow rate of 10 μmol / min (T = T11 to T12: growth period of the ZnO-based semiconductor layer 12, FIG. Period G2). DMZn was supplied to the substrate 10 for about 30 minutes, and a ZnO-based semiconductor layer (ZnO single crystal layer) 12 having a growth rate of 17 nm / min and a layer thickness of 0.5 μm was formed. The flow rate ratio _(F H2O _/ F _MO ratio) of water vapor flow rate and organometallic this time (DMZn), so-called VI / II ratio is 64.

  Note that the waiting time until the substrate temperature is stabilized before the growth of the ZnO-based semiconductor layer 12 can also be used as the heat treatment of the second ZnO layer 11B.

In this embodiment, the case where ZnO is grown as the ZnO-based semiconductor layer 12 will be described as an example, but the present invention is not limited to this. For example, in addition to DMZn, a Mg _x Zn _(1-x) O crystal that is a ternary crystal is grown by using Cp2Mg (biscyclopentadienylmagnesium) that is an organometallic compound that does not contain an oxygen atom. be able to.

  After the growth of the ZnO-based semiconductor layer 12 was completed, the pressure of 80 kPa was maintained while flowing water vapor until the substrate temperature reached 300 ° C. When the substrate temperature became 300 ° C. or lower, the water vapor was stopped (T = T13), and the substrate was waited until the substrate temperature reached room temperature, and then taken out from the reaction vessel.

  As described above, the first ZnO layer (first single crystal layer) 11A, the second ZnO layer (second single crystal layer) 11B, and the ZnO-based semiconductor layer (third single crystal) are formed on the substrate. A substrate 15 with a ZnO-based crystal growth layer on which the (layer) 12 was grown (hereinafter, also simply referred to as a substrate 15 with a growth layer) was manufactured.

  FIG. 4 is a cross-sectional view schematically showing the structure of a semiconductor light emitting device (LED) wafer 25 that is Embodiment 2 of the present invention. FIG. 5 shows a crystal growth sequence used for crystal growth of an LED wafer (hereinafter also referred to as a substrate with an LED device layer) 25.

  More specifically, the first ZnO layer (first single crystal layer) 11A and the second ZnO layer (second single crystal layer) are formed by the same method as the growth of the substrate 15 with the ZnO-based crystal growth layer of Example 1 above. A crystal layer) 11B and a ZnO-based semiconductor layer 12, and further, a first n-type ZnO-based semiconductor layer 21, a second n-type ZnO-based semiconductor layer 22, a ZnO-based semiconductor light-emitting layer 23, and a p-type ZnO-based semiconductor. A light emitting device layer (hereinafter also referred to as an LED device layer) 20 composed of the layer 24 was formed. The first ZnO layer 11A, the second ZnO layer 11B, and the ZnO-based semiconductor layer 12 are undoped semiconductor layers.

  Here, in this specification, the device layer refers to a layer composed of a semiconductor to be included for the semiconductor element to perform its function. For example, a simple transistor includes an n-type semiconductor layer, a p-type semiconductor layer, and a structural layer constituted by these pn junctions. A semiconductor structure layer that includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer and emits light by recombination of injected carriers is particularly referred to as a light-emitting device layer.

As shown in FIG. 5, after the growth of the ZnO-based semiconductor layer 12 was finished, the n-type ZnO-based semiconductor layer 21 was grown. More specifically, the DMZn flow rate was increased from 10 μmol / min to 30 μmol / min while maintaining a growth temperature of 800 ° C., a growth pressure of 80 kPa, and a H ₂ O (water vapor) flow rate of 640 μmol / min. At the same time, TEGa as an n-type impurity material was supplied to the substrate 15 with a growth layer (T = T12). Thus, the first n which is a Ga-doped ZnO single crystal semiconductor layer having a layer thickness of 2 μm and a Ga concentration of 1 × 10 ¹⁸ cm ⁻³ in a growth time of 40 minutes (T = T12 to T21: period D1 in FIG. 5). A type ZnO-based semiconductor layer 21 was grown on the ZnO-based semiconductor layer 12 (T = T21).

Next, the pressure was reduced to 10 kPa at a substrate temperature of 800 ° C. Further, the flow rate of DMZn was 10 μmol / min, the flow rate of Cp2Mg was 0.5 μmol / min, and TEGa was simultaneously supplied as an n-type impurity material to grow MgZnO crystals (T = T22 to T23: period D2). That is, the second n-type ZnO-based semiconductor layer 22 which is a Mg _x Zn _(1-x) O (x = 0.15) single crystal semiconductor layer having a layer thickness of 70 nm and a Ga concentration of 3 × 10 ¹⁷ cm ^−3. Grew up.

  Next, a ZnO-based semiconductor light emitting layer 23 was grown. Specifically, the substrate temperature is maintained at 800 ° C., the growth pressure is set to 80 kPa, the supply amount of DMZn is reduced to 1 μmol / min, and the ZnO-based semiconductor light emitting layer which is a ZnO single crystal semiconductor layer having a layer thickness of 30 nm. (ACT) 23 was formed (T = T24 to T25: period D3).

After the light emitting layer 23 was grown, a p-type ZnO based semiconductor layer 24 was grown. Specifically, the substrate temperature is maintained at 800 ° C., the growth pressure is set to 10 kPa, the supply amount of DMZn is set to 10 μmol / min, and at the same time, NH ₃ (ammonia) is supplied as a p-type impurity material at a flow rate of 180 μmol / min. Then, the p-type ZnO-based semiconductor layer 24 which is a Mg _x Zn _(1-x) O (x = 0.15) single crystal semiconductor layer having a layer thickness of 70 nm and a nitrogen impurity concentration of 8 × 10 ¹⁹ cm ⁻³ is grown. (T = T26 to T27: period D4).

  After the growth of the p-type ZnO-based semiconductor layer 24 is completed, the pressure of 80 kPa is maintained with water vapor flowing until the substrate temperature reaches 300 ° C. (T = T28), and the substrate temperature is increased to room temperature. The extracted points are the same as in the first embodiment.

[Manufacture of semiconductor light emitting devices]
Using the substrate 25 with the LED device layer manufactured in the above process, a semiconductor light emitting element (LED) was manufactured by the following process.

  FIG. 6 is a top view of the substrate 25 with an LED device layer. FIG. 7 is a cross-sectional view illustrating an outline of an element separation process for performing an electrode formation process, which will be described later, on the substrate 25 with an LED device layer and separating the LED into individual pieces. FIG. 8A is an element top view of the semiconductor light emitting element (LED) 30, and FIG. 8B is a cross-sectional view of the LED 30. FIG. 8B shows that two LEDs 30 and an element partitioning groove 32 for separating them by braking are formed.

  First, using a photolithography technique, a resist mask having a shape covering the region (element region) in the element section 31 was formed. Next, using wet etching, the p-type ZnO-based semiconductor layer 24, the light-emitting layer 23, and the n-type ZnO-based semiconductor layer 22 in the opening outside the element section 31 were partially removed to a predetermined depth. Finally, the resist was removed by washing to form element partition grooves 32 (step 2 in FIGS. 6 and 7). As shown in FIG. 6, the element section 31 was formed with an inclination of 36.3 ° with respect to the OF (orientation flat). Further, the element partition groove 31 was formed so that the depth was 200 nm deeper than the interface position between the light emitting layer 23 and the n-type ZnO-based semiconductor layer 22.

  Next, a resist mask having a shape opened to a p-side electrode shape was formed using a photolithography technique. Then, EB (electron beam) deposition was used to form a p-side electrode 33 with a thickness of Ni (nickel) of 0.3 to 10 nm and Au (gold) of 5 to 20 nm. Finally, the vapor deposition material other than the p-side electrode 33 was removed by a lift-off method, and a p-side electrode 507 was formed on the surface of the p-type Zn oxide semiconductor layer 505. The formed p-side electrode 33 was treated with RTA (Rapid Thermal Annealer) in a 10% oxygen atmosphere at 500 ° C. for 30 seconds to form a translucent electrode.

  Next, a resist mask opened in the shape of the p-side connection electrode 34 was formed so as to be in contact with a partial region of the p-side electrode 33 by using a photolithography technique. And by EB vapor deposition, the Ni / Pt / Au electrode pad material was laminated | stacked in this order with the thickness of 10 nm / 100 nm / 1000 nm, respectively, and the p side connection electrode 34 was formed (FIG.8 (B)). The notation of Ni / Pt / Au means the first layer / second layer / third layer from the p-side electrode 34 side.

  Further, a resist mask having an opening in the shape of the n-side connection electrode 35 was formed on the exposed surface of the n-type ZnO-based semiconductor layer 22 by using a photolithography technique. Then, Ti / Au was laminated at a thickness of 10 nm / 1000 nm by EB vapor deposition, and then the vapor deposition material other than the mask opening was removed by a lift-off method to form the n-side connection electrode 35.

  The electrode-formed LED operation layer 20 side on which the electrodes were formed was attached to a protective substrate, set on a grinding machine, and ground until the substrate thickness was 120 μm. Then, the polishing material was gradually lowered and polished until the ground surface became a mirror surface by a polishing apparatus, and formed into a wafer having a thickness of about 100 μm.

  Next, after a protective sheet is pasted on the surface side on which the electrodes are formed, for example, scribe grooves 36 that are orthogonal to each other are formed on the back surface corresponding to the central portion of the element partition groove 32 by a scribe device using diamond points (see FIG. 7 step 2, FIG. 8 (B)).

  As will be described in detail later, in braking, the knife edge 37 was applied from the element partitioning groove 32 side of the opposing surface of the scribe groove 36, loaded with the knife edge 37, and cleaved in the scribe groove direction. Similarly, the substrate was rotated 90 ° and cleaved in the direction of the scribe groove 36 perpendicular to the substrate.

  In this way, the semiconductor light emitting element 30 was manufactured (FIGS. 8A and 8B). Various sizes of the semiconductor light emitting element 30 are not limited to this, but for example, the die size is 400 μm square (FIG. 6, L1 = L2 = 400 μm), the element partition size is 300 μm square, and the diameter of the p-side electrode pad is φ100 μm, the diameter of the n-side electrode pad is φ100 μm, and the thickness is about 100 μm.

Although described as an example the case of a composition X = 0.15 as a crystalline layer containing _{Mg (Mg x Zn 1-x} O layer) it is not limited thereto. What is necessary is just to select the composition (band gap) of each semiconductor layer in the range of 0 <= x <= 0.68 according to the required characteristic etc. of a semiconductor element. Also, the layer thickness, conductivity type, dope concentration (carrier concentration), and the like can be appropriately modified or selected according to the required characteristics of the semiconductor light emitting device.

[Comparative example]
For comparative evaluation with the ZnO-based single crystal layer of the growth layer-provided substrate 15 grown according to the above-described embodiment, crystal growth was performed as a comparative example under the following growth method and growth conditions.

  FIG. 9 is a cross-sectional view schematically showing the structure of the crystal growth layer of the comparative example. Specifically, the ZnO single crystal layer 101 and the ZnO-based crystal layer 102 were formed on the a-plane sapphire substrate 100 by an RF-MBE (radical source MBE) apparatus.

  That is, the RF-MBE apparatus used for the crystal growth of the comparative example irradiates Zn (zinc), Mg (magnesium), and Ga (gallium) with a Knudsen cell, and O (oxygen) and N (nitrogen) which is a p-type impurity. ) Is configured to irradiate with an RF radical gun (generator). Each Knudsen cell and the exit of the RF radical gun are provided with a shutter, which can individually irradiate the substrate with molecular beams. Further, the substrate is structured to be heated by a resistance heater. More specifically, the substrate 105 with a crystal growth layer of the comparative example was grown by the following procedure.

  First, the a-plane sapphire substrate 100 was subjected to a heat treatment at a temperature of 900 ° C. for 10 minutes under vacuum to dissipate and desorb adsorbed material on the substrate surface.

  Next, the substrate temperature was lowered from 900 ° C. to 300 ° C. When the temperature was stabilized, the O (oxygen) radical gun shutter was opened and the substrate was irradiated with O radicals. Subsequently, the Zn Knudsen cell shutter was opened and the substrate was irradiated with a Zn beam to form a ZnO single crystal layer (buffer layer) having a thickness of 30 nm as the first ZnO layer 101 at a low temperature (300 ° C.).

  Next, heat treatment of the first ZnO layer 101 was performed. More specifically, while the substrate is irradiated with O radicals, the substrate temperature is raised from 300 ° C. to 800 ° C., heat treatment is performed for 5 minutes, and a ZnO single crystal layer (first ZnO layer) formed at a low temperature of 300 ° C. 101) was recovered.

  After the heat treatment of the first ZnO layer 101, the substrate temperature was lowered again from 800 ° C. to 700 ° C. When the substrate temperature was stabilized, the Zn Knudsen cell shutter was opened, and the first ZnO layer 101 was irradiated with a Zn beam to form a ZnO single crystal layer having a thickness of 1 μm as the second ZnO layer. As described above, the substrate 105 with the ZnO crystal layer of the comparative example was formed by the steps described above.

1. Evaluation Results of Crystal Growth Layer of Substrate 15 with Growth Layer 1.1 Evaluation of Crystal Growth Layer of Substrate 15 with Growth Layer Hereinafter, evaluation results and physical properties of the substrate 15 with growth layer and the crystal growth layer of the comparative example will be described below. This will be described in detail with reference to the drawings. Further, the crystal growth layer described above was evaluated and analyzed by the following method.

  The surface morphology was evaluated by a differential polarization microscope, SEM (Scanning Electron Microscope) and AFM (Atomic Force Microscope). Crystal orientation and flatness were evaluated by RHEED (reflection high-energy electron diffraction). The crystal orientation and the defect / dislocation density were evaluated by X-ray diffraction (XRD). The impurity concentration in the crystal was evaluated by secondary ion mass spectrometry (SIMS).

  FIG. 10 shows SIMS analysis results of the crystal growth layer (hereinafter also referred to as <EMB1>) of the substrate 15 with the growth layer. That is, concentration profiles in the depth direction of Al (aluminum) and Si (silicon) are shown. In the figure, LM (Al) indicates the lower limit of detection of Al.

As shown in FIG. 10, the concentration of Al (aluminum) decreases from the interface (X) between the sapphire substrate and the ZnO crystal growth layer (indicated as “ZnO epi” in the figure) in the growth direction. The interface (X) between the sapphire substrate (denoted as “Sub” in the figure) and the ZnO crystal growth layer was identified as a position where the Zn ion intensity sharply decreased. Moreover, the upper limit of SIMS measurement is 1 × 10 ²¹ (pieces / cm ³ ). In the figure, 1E + n is an exponential notation, and for example, 1E17 or 1E + 17 represents 1 × 10 ¹⁷ .

  That is, it was found that Al, which is a constituent element of sapphire, which is a substrate, does not decrease completely steeply (stepwise) at the interface (X) but diffuses into the ZnO crystal growth layer. . More specifically, due to diffusion of Al into the ZnO growth layer, a solid solution layer (section A in the figure) in which Al exists in the solid solution state in the vicinity of the interface (X) is formed in the ZnO growth layer. It was found that a high concentration diffusion layer (section B) in which Al was diffused at a high concentration was formed. This will be described in more detail below.

FIG. 11 is an enlarged view of the profile in the vicinity of the interface (X) between the Al concentration and the Zn ion intensity in FIG. The horizontal axis indicates the growth layer thickness and is zero at the interface (X). When the Al concentration in the ZnO growth layer is equal to or higher than a certain value (upper limit CC; point P1 in the figure), it can be said that Al is in a solid solution state in the crystal. Generally, the upper limit concentration (CC) at which Al acts as an n-type impurity is 8 × 10 ²⁰ / cm ³ , and it can be said that a region with an Al concentration higher than this is a solid solution state region. That is, from FIG. 10, the region from the interface (X) to the point P1 is an Al solid solution layer (section A), and when the upper limit concentration (CC) is 8 × 10 ²⁰ pieces / cm ³ , the solid solution layer The thickness of (Section A) is 20 nm. As described above, the Al concentration of the solid solution layer exceeds the upper limit value as an n-type impurity. Therefore, the resistance value is smaller in the solid solution layer regardless of the impurity concentration of the n-type layer, and the effect of spreading by the solid solution layer before the current reaches the n-type layer can be expected.

  Regarding the upper limit concentration (CC) acting as an n-type impurity, for example, “Low-temperature growth of ZnO thin film”, Shinya Akiba, 2006, Master's course, Department of Electrical and Electronic Engineering, Graduate School of Engineering, Mie University, H19 February 6, 2000, page 6 (see http://hdl.handle.net/10076/9109).

Further, as shown in FIG. 11, the Al concentration is composed of a region (R1) that decreases with a steep concentration gradient from the interface toward the growth direction and a region (R2) that decreases with a gradual concentration gradient. . If the intersection of the tangents of concentration change in these regions R1 and R2 is Q, the region from the interface (X) to the point Q is a transition layer from a solid solution layer to a diffusion layer (diffusion layer). It is a concentration diffusion layer (also referred to as a solid solution diffusion layer) (section B), and the thickness of the high concentration diffusion layer (section B) is 70 nm. The Al concentration (point P1) in the layer thickness at the intersection Q determined by the above method was 1 × 10 ¹⁹ pieces / cm ³ . Therefore, a region having an Al concentration of 1 × 10 ¹⁹ pieces / cm ³ or more (less than 8 × 10 ²⁰ pieces / cm ³ ) was defined as a high concentration diffusion layer (section B).

  As described above, according to the present invention, a layer in which the Al composition is continuously changed from the sapphire substrate to the ZnO growth layer is formed, and the Al solid solution layer (section A) and the high-concentration diffusion layer (section) are formed. B) is formed.

Further, an Al diffusion layer having an Al concentration of less than 1 × 10 ¹⁹ pieces / cm ³ and 4 × 10 ¹⁷ pieces / cm ³ or more is defined as section C (thickness 220 nm), and the Al concentration is less than 4 × 10 ¹⁷ pieces / cm ³ . The Al low concentration diffusion layer is defined as section D (thickness 600 nm). However, as will be described later, when the device layer is formed, the Al concentration is less than 1 × 10 ¹⁹ / cm ³ (the solid solution layer (section A) and the high concentration diffusion layer (section B) After the formation), doping may be performed to control the conductivity type. That is, a dopant can be added during the formation of the Al diffusion layer (section C) or the Al low-concentration diffusion layer (section D) to form, for example, an n-type ZnO-based crystal layer.

That is, the solid solution layer (section A) in which aluminum (Al) of the substrate is dissolved at a concentration of 8 × 10 ²⁰ pieces / cm ³ or more at the interface with the substrate, and the concentration of Al diffused from the substrate is 1 × 10 ^19. A ZnO-based crystal layer consisting of a high-concentration diffusion layer (section B), an Al diffusion layer (section C), and an Al low-concentration diffusion layer (section D) having a size of cm ³ or more is formed. The

Further, as shown in FIG. 10, in the diffusion layer (growth layer after the Q point in the figure) on the high concentration diffusion layer (section B), the Al concentration is further decreased, and the thickness of the ZnO single crystal layer is increased. It decreases to 3.0 × 10 ¹⁵ pieces / cm ^{3 in the} vicinity of 1 μm. Since the Al concentration from sapphire is proportional to the defect density, it can be considered that the defect density is also sufficiently reduced at 1 μm or more. Therefore, the ZnO layer grown to 1 μm or more has a sufficiently low defect density and does not cause a problem during manufacture. Note that when an n-type ZnO-based semiconductor layer, a light-emitting layer, and a p-type ZnO-based semiconductor layer are formed, the thickness may be 1 μm or more including the ZnO single crystal layer and the n-type ZnO-based semiconductor layer. Since Al also acts as an n-type dopant, there is no problem even if it is contained in the n-type ZnO-based semiconductor layer, and there is a region where the defect density of 1 μm or more is sufficiently reduced, and the light-emitting layer, p-type ZnO Al diffusion into the system semiconductor layer has a concentration that does not cause a problem. That is, for example, when manufacturing a semiconductor light emitting device such as an LED that forms an n-type ZnO-based semiconductor layer doped with impurities for controlling the conductivity type, a light-emitting layer, and a p-type ZnO-based semiconductor layer, Al diffusion is not a problem.

  On the other hand, FIG. 12 shows the SIMS analysis result of the sample of the comparative example. More specifically, SIMS analysis results of a ZnO-based crystal growth layer (hereinafter also referred to as <CMP>) formed on the a-plane sapphire substrate formed by the RF-MBE method are shown. That is, concentration profiles in the depth direction of Al (aluminum) and Si (silicon) are shown. When formed by the RF-MBE method, it was found that a steep interface was formed between the sapphire substrate and the ZnO growth layer, Al did not diffuse into the growth layer, and no solid solution layer was formed.

  In the present invention, it should be further noted that the surface morphology is good even though the Al solid solution layer is formed at the interface between the sapphire substrate and the ZnO layer. 13 and 14 show a differential microscope image and an SEM image of the growth layer surface of the growth layer-attached substrate 15, respectively. Thus, it was confirmed from the observation result of the differential microscope and SEM that it has high flatness from a wide area to a micro area (also macroscopically and microscopically).

  In addition, the introduction of defects and dislocations into the growth layer is reduced. 15A and 15B show the case where the layer thickness (t) of the ZnO layer 12 is 1 μm, and FIGS. 16A and 16B show the XRD when the layer thickness (t) is 3 μm. 002) ω rocking curve and (100) ω rocking curve. A comparison table of these measurement results is shown below.

  For example, the full width at half maximum (FWHM) of the (002) ω rocking curve is 274 arcsec at a layer thickness t = 1 μm, but is improved to 144 arcsec at t = 3 μm. It was also found that the FWHM of the (100) ω rocking curve improved from 631 arcsec (t = 1 μm) to 270 arcsec (t = 3 μm) as the growth layer thickness increased. The lattice mismatch between the c-axis direction <0001> of the sapphire substrate and the a-axis direction <11-20> of the ZnO growth layer is 0.07%, and the m-axis direction <10-10> of the sapphire substrate and the ZnO growth layer Although the lattice mismatch with the m-axis direction <10-10> is 2.46%, as described above, it was found from these measurement results that the lattice mismatch was relaxed and grew. Also, the surface morphology was good with a mirror surface.

By the way, in conventional semiconductor crystals such as GaN and GaAs, when impurities such as Zn and Mg are mixed in about 1 × 10 ²⁰ cm ⁻³ or more, the crystal arrangement starts to be disturbed, and defects and dislocation density increase. Furthermore, when about 5 × 10 ²⁰ cm ⁻³ or more is added, the surface morphology is deteriorated or polycrystallized. As described above, it is known that the non-oxygen-based compound semiconductor crystal deteriorates when the impurity element diffuses in the growth layer at a high concentration. In the present invention, as described above, it was found that the surface morphology and lattice matching are good, and a growth layer having high quality crystallinity such as reduction of defects and dislocations can be formed.

1.2 Electrical Characteristics of Crystal Growth Layer of Substrate 15 with Growth Layer The electrical characteristics of the crystal growth layer of substrate 15 with the growth layer will be described in detail below. The electrical characteristics of the crystal growth layer were measured by the van der Pauw method. The measurement was performed using HL5500 Hall System manufactured by Bio-Rad Microscience. Using this apparatus, the sheet resistance (R _S ) was determined from the current and voltage, and then the magnetic field was applied to determine the sheet Hall coefficient (R _HS ). The sheet carrier density (N _S ) and mobility (μ) were calculated using the values. In addition, the specific resistance (ρ) and the carrier density (N) were obtained in advance using the film thickness (t) measured by a stylus profilometer (DEKTAK).

The thickness of the crystal growth layer of the substrate with growth layer 15 is about 1 μm, the sheet resistance (Rs) is 132 Ω / □ (Ω / square), the specific resistance (ρ) is 0.0132 Ω · cm, and the carrier density (N) is 1. × 10 ¹⁹ cm ^-3 . However, the Al concentration in the film exceeds 1 × 10 ²¹ cm ⁻³ at the substrate interface, decreases toward the surface, and reaches 1 × 10 ¹⁶ cm ⁻³ or less at the surface. That is, the sheet resistance and specific resistance of the growth layer of the substrate with growth layer 15 are due to the characteristic values of the layer region (section A + section B = 90 nm) having at least an impurity density higher than 1 × 10 ¹⁹ cm ⁻³ .

By the way, if the plasma oscillation is ignored, the maximum carrier density is about 2 × 10 ²¹ cm ⁻³ (Hokkaido Industrial Technology Center research report No. 6 (2000), “ZnO-Based Transparent Conducting Oxide Film”). Even in consideration of plasma vibration or the like, it can be up to about 1 × 10 ²¹ cm ⁻³ . That is, the carrier density in the region where Al is dissolved (section A = 20 nm) is in a very high state.

Next, Table 2 shows the result of estimating the specific resistance for each section. The estimate is based on materials from the National Institute of Advanced Industrial Science and Technology (Japan MRS News Vol.13 No.3 Aug. 2001, Figure 3: "New Development of Zinc Oxide Semiconductor", National Institute of Advanced Industrial Science and Technology) Sakae Niki: http://www.mrs-j.org/mrsjnews/news13-3/2001_3topics.PDF) That is, the range of mobility and carrier density was read from the material, and the theoretical range of specific resistance in section A was obtained. The mobility is considered to be in the range of ¹⁵ to ²⁵ cm ² / (V · s), and the carrier density is considered to be in the range of 6 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ . From this, the specific resistance range is 2.5 × 10 ^{−4 to} 6.9 × 10 ⁻³ Ω · cm. The specific resistance value in the section A in the present embodiment is included in the above range. The value of the specific resistance does not change greatly at the upper limit and the lower limit, and a specific resistance value within this range can be expected even if the value varies slightly depending on the situation.

Similarly, the specific resistance range in section B was also determined. The mobility is considered to be in the range of 35 to 80 cm ² / (V · s), and the carrier density is considered to be in the range of 1 × 10 ¹⁹ to 4 × 10 ²⁰ cm ⁻³ . From this, the range of the specific resistance is 4.5 × 10 ^{−4 to} 7.8 × 10 ⁻³ Ω · cm. The specific resistance value of the present embodiment is also included in this range for the section B, and the specific resistance value does not change greatly regardless of the upper limit or the lower limit, and the specific resistance value within this range may vary slightly depending on the situation. Can be expected.

Section A (thickness 20 nm) in which Al is dissolved, Section B (thickness 70 nm) in which Al is diffused at high concentration, Al diffusion section = C (thickness 220 nm), Al low concentration diffusion section = D ( When the thickness is 600 nm), the specific resistances in sections A, B, C, and D are 4.2 × 10 ⁻⁴ Ω · cm, 3.1 × 0 ⁻³ Ω · cm, and 4.5 × 10 ^{−, respectively.} It was estimated to be ² Ω · cm and 8.9 × 10 ⁻¹ Ω · cm. The sheet resistances were estimated as 208Ω / □, 509Ω / □, 2027Ω / □, and 14860Ω / □, respectively. And the synthetic sheet resistance of the sections A to D can be calculated as 136Ω / □, and it was found that the synthetic sheet resistance agrees well with the actually measured value 132Ω / □.

As for the specific resistance range in section A, assuming that the mobility in section A is 25 cm ² / (V · s), the maximum carrier density in consideration of plasma vibration is assumed to be 1 × 10 ²¹ cm ^−3. The specific resistance in section A is 2.5 × 10 ⁻⁴ Ω · cm. Further, considering that the mobility is 15 cm ² / (V · s) and the influence of compensation by impurities is large, the specific resistance in section A is 6.9 when the carrier density is 6 × 10 ²⁰ cm ^−3. × 10 ⁻⁴ Ω · cm.

Similarly, regarding the specific resistance range of the section B, when the mobility of the section B is 35 cm ² / (V · s), the carrier density is 4 × 10 ²⁰ cm ^{−3 which} is half the impurity concentration limit due to impurity compensation or the like. If it is assumed, the specific resistance in the section B is 4.5 × 10 ⁻⁴ Ω · cm. Further, even when the mobility is 80 cm ² / (V · s) and the lowest carrier density in the section is 1 × 10 ¹⁹ cm ⁻³ , the specific resistance in the section B is 7.8 × 10 ⁻³ Ω · cm.

1.3 Layer thicknesses of the first and second single crystal layers 11A and 11B In order to promote current diffusion, the sheet resistance needs to be low. In order to reduce the sheet resistance when the specific resistance is sufficiently low, the film thickness may be increased. That is, the first and second single crystal layers 11A and 11B may be formed thick.

  Since the first single crystal layer 11A is an orientation control layer for laminating a ZnO single crystal on a sapphire crystal, it needs to have a thickness that does not disturb the orientation. If the thickness of the first single crystal layer 11A is in the range of 5 nm to 100 nm, the orientation can be increased without disturbing the orientation. Specifically, the film is grown up to a thickness of 30 nm at a growth rate of 0.4 to 0.8 nm / min at 400 ° C., and the next 30 nm is grown at a growth temperature of 350 ° C. and a growth rate of 0.8 to 3.2 nm / min. The last 40 nm is grown at a growth rate of 300 ° C. and a growth rate of 3.2 to 9 nm / min. By slowing the initial growth rate, the crystal orientation can be improved and Al elution (solid solution) can be promoted. Moreover, flatness can be maintained by lowering the growth temperature in the thickness direction.

  For example, when the layer thickness is 20 nm, the sheet resistance is 208Ω / □, but when the other conditions are the same and only the thickness of the first single crystal layer 11A is increased to 100 nm, the sheet resistance is 42Ω / □. Can be reduced. In particular, to reduce the sheet resistance of the Al solid solution layer and the solid solution diffusion layer (section A + section B), it is effective to increase the thickness of the first single crystal layer 11A.

  The second single crystal layer 11B is a functional layer for facilitating (promoting) the two-dimensional crystal growth process of the ZnO-based semiconductor layer 12 grown on the second single crystal layer 11B. The film conditions are relatively insensitive (slow) to the layer thickness. If the thickness of the second single crystal layer 11B is in the range of 5 nm to 200 nm, there is no problem even if the film thickness is increased. The film thickness of the second single crystal layer 11B can be increased to about 200 nm by a method of increasing the process time for heating to 600 ° C. to 800 ° C. Specifically, it grows by 40 nm at 600 ° C., and can grow by 160 nm by setting the temperature rising time to 800 ° C. to 10 minutes. By setting the rate of temperature increase from 100 ° C./min to 30 ° C./min, the thermal stress on the growth film becomes moderate, and the function (2D growth promoting function) of the second single crystal layer 11B can be grown without deteriorating. .

  For example, the sheet resistance is 510 Ω / □ when the layer thickness is 70 nm, but the sheet resistance is reduced to 178 Ω / □ when the thickness of only the second single crystal layer 11B is increased to 200 nm with other conditions being the same. it can.

1.4 Growth temperature and specific resistance of ZnO-based semiconductor layer 12 Growth substrate with growth layer 15 when the growth temperature of ZnO-based semiconductor layer 12 is 800 ° C., 700 ° C., 600 ° C. (# 1, # 2, # 3) Table 3 shows the Hall measurement results.

  The specific resistance values when the growth temperature is 600 ° C., 700 ° C., and 800 ° C. are 0.043, 0.034, and 0.013 Ω · cm, respectively, and the higher the growth temperature, the better the Al solid solution diffusion layer is formed. it can. Also, from the viewpoint of the crystallinity and surface morphology of the ZnO-based semiconductor layer 12, the higher the growth temperature, the better. Specifically, a temperature of 600 ° C. to 850 ° C. is suitable. In particular, the range of 740 ° C. to 810 ° C. is preferable from the viewpoint of crystallinity. Since this layer is a layer in which Al diffuses from the second single crystal layer 11B, the Al concentration decreases in the layer thickness direction. In addition, the resistance of the Al solid solution diffusion layer (section A + section B) and the first n-type Zn-based semiconductor layer (described later) can be adjusted using this characteristic.

1.5 Electrical Characteristics of Comparative Example As described above, Al diffusion from the sapphire substrate is not recognized in the comparative example prepared by the MBE method. Therefore, there is no Al solid solution diffusion layer corresponding to the single crystal transparent conductive film. The specific resistance value was found to be as high as 0.80 Ω · cm.

  As described above, the Al solid solution diffusion layer (solid solution layer and high-concentration diffusion layer) having a low specific resistance in the present invention is the first low-temperature by MOCVD using an organic metal material not containing oxygen and water vapor. The single crystal layer formation and the heat treatment, and the second low-temperature single crystal layer formation process enabled the formation. In particular, this is because Al in the sapphire substrate is eluted (solid solution) into the ZnO crystal layer in the first low-temperature single crystal formation step.

Specifically, there is a layer in which the Al impurity concentration is diffused at a high concentration at the interface between the sapphire substrate and the ZnO growth layer, and the specific resistance value from section A to section B is 2.5 × 10 ⁻⁴ Ω · cm. It can be said that the low layer is formed as ˜7.8 × 10 ⁻³ Ω · cm. In other words, it can be said that a transparent conductive film is formed at the interface between the insulating substrate and the Zn oxide layer. The first low-temperature single crystal layer 11A can be thickened up to 100 nm, the second low-temperature single crystal layer 11B can be thickened up to 200 nm, and the ZnO-based crystal layer 12 can be formed at a high temperature (such as 800 ° C.). An Al solid solution diffusion layer having a low specific resistance can be formed.

2. Crystal growth layer and specific resistance of LED wafer 25 The LED wafer 25 has an n-type ZnO-based crystal layer (first and second ZnO-based layers) on a ZnO-based crystal layer on which an Al solid solution layer and an Al high-concentration diffusion layer are formed. A semiconductor layer), a light emitting layer, and a p-type ZnO-based semiconductor layer.

  In order to make the current distribution in the light emitting region (region in the element section 31) of the LED element 30 uniform, a laminated structure composed of p-type ZnO-based semiconductor layer / light-emitting layer / n-type ZnO-based semiconductor layer is made conductive. A structure sandwiched between favorable layers may be used. However, the highly conductive layer must be a crystal layer that can be epitaxially grown on the substrate and the device layer can be epitaxially grown thereon. Further, in the present invention, since the good conductive layer existing on the substrate side is an Al solid solution layer and an Al high concentration diffusion layer, it is possible to epitaxially grow on the substrate and epitaxially grow a device layer thereon. It is.

Even in the prior art, it is possible to form a p-side translucent electrode on the p-type ZnO-based crystal layer side, but it is not possible to form a transparent electrode on the n-type ZnO-based crystal layer side. That is, the ZnO crystal can form an AZO, GZO, and IZO transparent conductive film by substituting Zn sites with Al, Ga, and In atoms on the order of several percent. These transparent conductive films can be formed on glass or resin (acrylic, polyimide, etc.) by a sputtering method or the like, and are used for electrodes for LCDs, organic ELs, solar cells, and the like. These films are made of polycrystal having the c-axis oriented perpendicular to the substrate surface. Depending on the growth conditions, constituent elements, and composition, a specific resistance value on the order of 10 ⁻⁴ to 10 ⁻³ can be obtained. However, a single crystal ZnO-based crystal layer cannot be formed on these transparent conductive films. That is, the present invention enables the formation of a single crystal transparent conductive film layer with an Al solid solution diffusion layer, and further allows the formation of a single crystal ZnO-based semiconductor layer thereon, depending on the transparent conductive film. It has an effect that cannot be obtained.

2.1 Sheet Resistance and Radiation Intensity Distribution The specific resistance and sheet resistance value of each layer of the LED wafer 25 of this example are shown in the following table.

  Here, the layer thickness of the section C was 0.220 μm, and the combined sheet resistance of the sections A to C was 138Ω / □. The thickness of the first n-type ZnO-based semiconductor layer 21 was 2.0 μm, and the sheet resistance was 312 Ω / □. At this time, the synthetic sheet resistance of the sections A to C and the first n-type ZnO-based semiconductor layer was 96Ω / □. The thickness of the second n-type ZnO-based semiconductor layer 22 was 0.070 μm, and the sheet resistance was 22863 Ω / □.

  The emission intensity distribution (emission intensity distribution) in the emission zone screen of the LED element formed in this way was greatly improved as compared with the case where the Al solid solution layer and the Al high concentration diffusion layer) were not provided. In addition, since the current density distribution is made uniform, the current injection efficiency into the light emitting layer is increased, and the light emission intensity is also improved.

  As described above, in this embodiment, the device layer is laminated on the ZnO-based crystal layer (section A, B, C) in which the Al solid solution layer and the high concentration diffusion layer (transparent conductive layer) are formed. Have. In order to make the current distribution uniform in the n-type semiconductor layer, the combined sheet resistance value of the layer closer to the substrate than the n-type semiconductor layer needs to be smaller than that of the n-type semiconductor layer. The composite sheet resistance value (SR (AB)) of the Al solid solution layer and the high concentration diffusion layer (sections A and B) is smaller than the sheet resistance value (SR (1)) of the first n-type ZnO-based semiconductor layer 21. It is most desirable that the composite sheet resistance value (SR (ABC1)) of the ZnO-based crystal layer 12 (sections A, B, C) and the first n-type ZnO-based semiconductor layer 21 is the second n-type ZnO-based semiconductor. If the sheet resistance value (SR (2)) of the layer 22 is smaller, the current distribution in the second n-type ZnO based semiconductor layer 22 can be made uniform. Under the conditions shown in Table 4, SR (ABC1) <SR (2). In addition, the first n-type ZnO-based semiconductor layer 21 can be thinned by the Al solid solution diffusion layer (sections A and B). That is, for example, in order to obtain the same sheet resistance as in the present embodiment when there is no Al solid solution diffusion layer, the thickness of the first n-type ZnO-based semiconductor layer 21 needs to be 6 μm. In this case, the film formation time becomes long and the productivity decreases.

  In this embodiment, when the ZnO-based crystal layer 12 is grown, since the n-type impurity is doped in the middle of the growth of the section C, the section D is included in the first n-type ZnO-based semiconductor layer 21. When the doping of the n-type impurity is started in the middle of the growth of the section D, the section D further exists in the ZnO-based crystal layer 12. Similarly, in this case, the combined sheet resistance value (SR (ABCD1)) of the ZnO-based crystal layer 12 and the first n-type ZnO-based semiconductor layer 21 is the sheet resistance value (SR) of the second n-type ZnO-based semiconductor layer 22. If it is smaller than (2)) (SR (ABCD1) <SR (2)), the current distribution in the second n-type ZnO-based semiconductor layer 22 can be made uniform.

2.2 Modification of this example Table 5 shows the layer structure, sheet resistance, and the like of the modification of this example.

  In this modified example, an LED element having a section A of 100 nm, a section B of 200 nm, and a section C of 100 nm was manufactured. The luminous intensity distribution and luminous intensity in the luminous zone screen of the LED element thus formed were further improved as compared with the case of the above-mentioned example (Table 4). Further, the forward voltage (Vf) was also reduced as compared with the above example.

  As described above in detail, in the semiconductor light emitting device structure, it was confirmed that the Al solid solution diffusion layer having a low electrical resistance has a current diffusion function and improves the light emission intensity distribution in the device section screen. In addition, it was confirmed that the light emission intensity distribution and the light emission intensity in the device area screen were further improved by adopting a layer structure that minimizes the sheet resistance of the Al solid solution diffusion layer.

3. Formation of Solid Solution Layer In the above embodiment, the case where an Al solid solution layer and a solid solution diffusion layer are formed by MOCVD is described as an example. However, other growth methods such as a PLD (Pulsed Laser Deposition) method, a halide, etc. A solid solution layer may be formed by a VPE (HVPE) method, a plasma CVD method, a sputtering method, or the like. In short, an Al solid solution layer may be provided at the interface between the sapphire substrate and the ZnO-based crystal growth layer. .

  In addition, the growth conditions of the ZnO-based crystal for forming the Al solid solution layer at the interface between the sapphire substrate and the ZnO-based crystal growth layer shown in the above examples are merely examples, and are not limited thereto. Below, details of the properties and growth conditions of the ZnO-based crystal growth layer for growing a ZnO-based crystal on the sapphire substrate using the MOCVD method and forming an Al solid solution layer at the interface between the substrate and the growth layer are described in detail. explain.

  In the following, for ease of explanation and understanding, the growth layer grown on the sapphire substrate is referred to as a connection layer (or first growth layer), and the crystal layer grown on the connection layer is referred to as a device layer ( Or a second growth layer).

3.1 Properties of ZnO-based crystal growth layer (connection layer) Properties and states of ZnO-based crystal growth layer (connection layer) in the case of dissolving Al in the substrate include a small domain diameter and a difference in surface roughness. Is better. That is, in the heat treatment step, the larger the change rate of the growth layer shape, the easier it is to dissolve Al of the sapphire substrate.

  However, when grown under excessive conditions, single crystallinity is impaired, and crystallinity recovery by heat treatment after growth becomes insufficient. That is, the crystallinity of a ZnO-based crystal layer such as a device layer grown on the connection layer is lowered, and diffusion of solid solution Al cannot be suppressed. In addition, when the connection layer is, for example, a polycrystal or an amorphous crystal, the Al component is segregated at the grain boundary in the heat treatment step, so that sufficient crystallinity cannot be recovered, and the device layer grows at a high growth temperature. This is because defects and dislocations are introduced at high density at this stage, and Al diffusion cannot be suppressed.

  In the above embodiment, the first ZnO layer (first single crystal layer) 11A and the second ZnO layer (second single crystal layer) 11B are formed on the sapphire substrate as a connection layer at a low growth temperature. The case where the ZnO-based semiconductor layer 12 is formed at a high growth temperature has been described. However, even if only the first single crystal layer (ZnO-based single crystal layer) is formed as a connection layer, and a ZnO-based crystal layer such as a device layer is grown on the first single crystal layer (connection layer). Good.

3.2 Growth conditions of first low-temperature grown single crystal layer 11A <Growth temperature>
The growth temperature of the first low-temperature grown single crystal layer 11A is generally lower than the crystal growth temperature (referred to as “high growth temperature”) for growing a ZnO single crystal (referred to as “low growth temperature”). Is appropriate. This is because at the high growth temperature, island-like growth is easy and layered single crystals are hardly formed.

  More specifically, the growth temperature is preferably in the range of 250 ° C to 450 ° C. Furthermore, it is more preferable that it exists in the temperature range of 300 to 400 degreeC. At 250 ° C. or lower, the migration length becomes short, so that it becomes easy to be amorphous or polycrystallized. Further, as described above, when the temperature is higher than 450 ° C., island-like growth is likely to occur, and the growth layer on the connection layer is difficult to become a layered single crystal.

<Growth pressure>
The first single crystal layer 11A does not cause segregation or the like due to the heat treatment after the growth, and sufficient crystallinity recovery is performed. In addition, the growth layer on the first single crystal layer 11A is single crystal grown. It is necessary that the single crystallinity of the first single crystal layer 11A is not impaired. That is, for the single crystal growth of the first single crystal layer 11A, reactive chemical species (DMZn, H ₂ O, intermediate products, Zn atoms before crystallization, O atoms before crystallization on the substrate surface) Etc.) should have a large migration length. Therefore, the reduced pressure growth is suitable, and specifically, the growth pressure is preferably 1 kPa to 30 kPa, more preferably 5 kPa to 20 kPa. When the growth pressure is 1 kPa or less, the growth rate is remarkably slowed.

<Growth rate>
The growth rate is preferably in the range of 0.4 nm / min to 9 nm / min. Furthermore, it is more preferable to be within the range of 0.8 nm / min to 4 nm / min. When the growth rate is 9 nm / min or more, the surface irregularities become large, and sufficient flatness may not be obtained.

<Material gas>
In order to form a ZnO single crystal layer under a low growth pressure and a low growth temperature and to promote the formation of a solid solution layer, it is necessary to select a material having high mutual reactivity. This is because if the mutual reactivity is low, the crystal does not grow, or becomes amorphous or polycrystallized. As the Zn source, an organometallic compound that does not contain oxygen in the constituent molecules and has high reactivity with the oxygen source material is suitable. In addition to the DMZn described above, for example, there is DEZn (diethyl zinc). As an oxygen source, H ₂ O (water vapor) having a large intramolecular polarization and high reactivity is suitable.

<Heat treatment conditions>
As described above, the formation of the solid solution layer requires the first single crystal layer 11A to be single crystallized and heat treatment in a polar oxygen source (H ₂ O: water vapor). More specifically, although the connection layer is a single crystal, it has domains and irregularities, and the crystal properties change in a direction that minimizes the interface energy by heat treatment. At this time, the Al element of the sapphire substrate is dissolved in a high concentration in the ZnO single crystal. Therefore, the higher the heat treatment temperature and the longer the treatment time, the higher the solid solution concentration of Al.

  Further, since sapphire is a very stable substance, it is difficult to sufficiently dissolve and diffuse Al in the first single crystal layer 11A at a low temperature. The heat treatment temperature can be in the range of 700 ° C. to 1000 ° C., but a high temperature of 800 ° C. or higher is preferable from the viewpoint of crystallinity recovery of the first single crystal layer 11A in a state containing Al at a high concentration. .

  Therefore, it is appropriate that the heat treatment of the connection layer is performed at a high temperature. Specifically, the temperature is more preferably 100 ° or higher than the growth temperature of a ZnO-based crystal layer such as a device layer, or 900 ° or higher. Moreover, the high temperature heat processing in the range of 950 degreeC or more and 1000 degreeC is especially preferable from a viewpoint of promoting the solid solution of Al more.

  In order to improve single crystallinity and flatness, it is preferable to perform the heat treatment under a low pressure where the migration length becomes long. Note that the pressure range suitable for the heat treatment is the same as the growth pressure range of the first single crystal layer 11A described above.

3.3 Growth conditions of second low-temperature grown single crystal layer 11B <Growth temperature>
As a condition for forming a uniform layer on the first single crystal layer 11A, 500 ° C. to 650 ° C. is preferable. If the growth temperature is lower than 500 ° C., the crystallinity is not sufficient and a heat treatment is required. Further, at 650 ° C. or higher, island growth occurs on the ZnO layer 11A. In this temperature region, the higher the stability site (kink point) selectivity of reactive chemical species (DMZn, H ₂ O, intermediate products, Zn atoms before crystallization, O atoms before crystallization) on the substrate surface, the higher the temperature. It is not expensive and has excellent coverage.

<Growth pressure>
The growth pressure of the second single crystal layer 11B is preferably 40 kPa to 120 kPa. This upper limit value is an upper limit value of the airtightness of the MOCVD apparatus and is not a film forming condition.

<Growth rate>
The growth rate is preferably 60 nm / min or less, and preferably in the range of 5 nm / min to 60 nm / min. This is to prevent the occurrence of abnormal growth.

3.3 Growth conditions of ZnO-based semiconductor layer (high temperature growth single crystal layer) 12 On the second ZnO layer (second single crystal layer) 11B, which is flat at the sub-nano level and excellent in single crystal properties, 2B A ZnO-based semiconductor layer (high temperature grown single crystal layer, third single crystal layer) 12 is grown using conditions under which growth in a dimensional crystal growth mode (lateral growth mode) is performed.

Here, in the present embodiment, the organic metal compound material (DMZn) not containing oxygen and water vapor are used on the ZnO layer 11B to achieve high temperature growth (800 ° C.), and the growth pressure is the same as in the case of the ZnO layer 11B. In addition, the case where the Mg _x Zn _(1-x) O crystal layer (second crystal layer) 12 is grown on the ZnO layer 11B at 80 kPa higher than the growth pressure of the ZnO layer 11A has been described as an example. Further, the case where the growth rate is 17 nm / min and the growth layer thickness is 1 μm has been described as an example.

  However, the growth conditions of the ZnO-based semiconductor layer 12 on the ZnO layer 11B shown in the above embodiment are merely examples, and are not limited thereto. The growth conditions were changed to grow a ZnO-based semiconductor layer on the ZnO layer 11B, and the conditions for growing the ZnO-based semiconductor layer 12 excellent in flatness and single crystal were examined. Below, the growth conditions for growing the ZnO-based semiconductor layer (third single crystal layer) 12 on the second ZnO layer (second single crystal layer) 11B will be described in detail.

<Growth pressure>
It was found that the crystallinity is improved by increasing the growth pressure. That is, when the growth pressure is increased, the H ₂ O (water vapor) density on the growth surface can be increased, so that point defects can be particularly prevented. It has been found that a high growth pressure is desirable for obtaining a flat crystal growth surface with good crystallinity and no irregularities or pits on the surface of the ZnO-based semiconductor layer (high temperature growth single crystal layer). Specifically, the growth pressure is preferably 40 kPa or more. Moreover, 60 kPa or more is more preferable, and it is further more preferable that it is 80 kPa or more. As an upper limit, about 120 kPa is appropriate. This upper limit value is an upper limit value of the airtightness of the MOCVD apparatus and is not a film forming condition.

<Growth temperature>
It has been found that as the growth temperature increases, the transition density decreases, the crystallinity improves, and the flatness improves. Specifically, 650 ° C. or higher at which lateral growth (two-dimensional growth mode) is promoted and a plane (C plane) orthogonal to the c-axis is flattened is preferable. The upper limit is about 850 ° C. where growth becomes difficult with H ₂ O (water vapor). In particular, it is preferably in the temperature range of 700 ° C. to 810 ° C., more preferably 740 ° C. to 810 ° C.

<Growth rate>
The growth rate is preferably in the range of 5 to 60 nm / min. When the growth rate is 60 nm / min or more, abnormal growth tends to occur.

<Crystal composition>
As the ZnO-based semiconductor layer 12, for example, Mg _x Zn _{(1-x) 2} O (0 ≦ x ≦ 0.43) crystal can be used. However, as the Mg composition x increases, the lattice constant difference in the a-axis direction increases and the defect density of the deposited semiconductor crystal layer increases, so it is more preferable that the range is 0 ≦ x ≦ 0.3.

  Further, as described above, the ZnO-based semiconductor layer 12 may be another compound crystal based on ZnO. For example, a ZnO-based compound crystal in which a part of Zn (zinc) is replaced by Ca may be used, or a ZnO-based compound crystal in which a part of O (oxygen) is replaced by Se, S, Te, or the like. There may be.

<Material gas>
Growth at a high temperature makes it possible to obtain a high-quality ZnO crystal by sufficiently obtaining the migration length of the reactive chemical species on the crystal growth surface. On the other hand, it becomes difficult for the gaseous material to be an oxygen source to adhere to the substrate surface, and growth is hindered. As the oxygen source, H ₂ O (water vapor) that has a large polarization in the molecule and is adsorbed on the substrate surface even at a high temperature is suitable.

  As the Zn source, an organometallic compound that does not contain oxygen and has high reactivity with the oxygen source material is suitable. In addition to the DMZn described above, for example, there is DEZn (diethyl zinc). As the Mg source, there is Cp2Mg (biscyclopentadienylmagnesium).

  As described above in detail, the current density distribution is obtained by forming a solid solution layer in which aluminum (Al) derived from the substrate is dissolved in the interface with the substrate and a high concentration diffusion layer in which Al is diffused in a high concentration. In-plane non-uniformity is improved. In the semiconductor light emitting device structure, the light emission intensity distribution in the light emitting region plane is greatly improved by the uniform current density distribution. In addition, since the current density distribution is made uniform, the current injection efficiency into the light emitting layer is increased, and the light emission intensity is also improved.

DESCRIPTION OF SYMBOLS 10 Substrate 11A 1st low temperature growth layer 11B 2nd low temperature growth layer 12 ZnO type compound semiconductor layer (high temperature growth single crystal layer)
15 substrate with growth layer 20 device layer 21 first n-type semiconductor layer 22 second n-type semiconductor layer 23 light emitting layer 24 p-type semiconductor layer 25 LED wafer

Claims (10)

A semiconductor element in which a ZnO-based crystal is grown on a sapphire (Al ₂ O ₃ ) single crystal substrate,
A solid solution layer in which aluminum (Al) of the substrate is dissolved at a concentration of 8 × 10 ²⁰ pieces / cm ³ or more at the interface with the substrate, and a concentration of Al diffused from the substrate is 1 × 10 ¹⁹ cm ³ or more. A ZnO-based crystal layer having a high-concentration diffusion layer,
And a device layer formed on the ZnO-based crystal layer.   The device layer includes an n-type semiconductor layer formed on the ZnO-based crystal layer, and a composite sheet resistance of the ZnO-based crystal layer is smaller than a sheet resistance of the n-type semiconductor layer. The semiconductor device according to claim 1. The semiconductor device according to claim 1, wherein the ZnO-based crystal layer further includes a layer having a diffused Al concentration of less than 1 × 10 ¹⁹ cm ³ . The n-type semiconductor layer has a first n-type semiconductor layer and a second n-type semiconductor layer formed on the first n-type semiconductor layer,
4. The semiconductor element according to claim 2, wherein a composite sheet resistance of the ZnO-based crystal layer and the first n-type semiconductor layer is smaller than a sheet resistance of the second n-type semiconductor layer. 5. .   5. The semiconductor element according to claim 1, wherein a thickness of the solid solution layer is in a range of 5 nm to 100 nm.   6. The semiconductor device according to claim 1, wherein the high-concentration diffusion layer has a thickness in a range of 5 nm to 200 nm. A substrate with a growth layer obtained by growing a ZnO-based crystal on a sapphire (Al ₂ O ₃ ) single crystal substrate,
A solid solution layer in which aluminum (Al) of the substrate is dissolved at a concentration of 8 × 10 ²⁰ pieces / cm ³ or more at the interface with the substrate, and a concentration of Al diffused from the substrate is 1 × 10 ¹⁹ cm ³ or more. A substrate with a growth layer, which has a ZnO-based crystal layer having a high concentration diffusion layer. A method for producing a semiconductor device by growing a ZnO-based crystal on a sapphire (Al ₂ O ₃ ) single crystal substrate,
A solid solution layer in which aluminum (Al) of the substrate is dissolved at a concentration of 8 × 10 ²⁰ pieces / cm ³ or more at the interface with the substrate, and a concentration of Al diffused from the substrate is 1 × 10 ¹⁹ cm ³ or more. Forming a ZnO-based crystal layer having a high-concentration diffusion layer,
Forming a device layer formed on the ZnO-based crystal layer,
The step of forming the ZnO-based crystal layer is performed by MOCVD using an organometallic compound not containing oxygen and water vapor.
(A) performing crystal growth at a first low growth temperature within a range of 250 ° C. to 450 ° C. and a low growth pressure within a range of 1 kPa to 30 kPa to form a first single crystal layer;
(B) Crystal growth is performed at a second low growth temperature higher than the first low growth temperature and a pressure higher than the low growth pressure to form a second single crystal layer on the first single crystal layer. Forming step;
(C) performing a crystal growth at a high growth temperature and a pressure higher than the low growth pressure to form a third single crystal layer on the second single crystal layer. .   The method according to claim 8, wherein the high growth temperature is a temperature within a range of 700C to 850C.   The method according to claim 8 or 9, wherein the second low growth temperature is a temperature within a range of 500C to 650C.