JP2011081681A - Access device and access method for flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device for accessing a flash memory to obtain a dual-channel flash memory set that increases a transmission band width and obtains data backup capability. <P>SOLUTION: The device for accessing a flash memory is provided with: a controller; a memory set of a first channel; and a memory set of a second channel. The memory set of the first channel is provided with a first flash memory and at least one first socket for memory extension. The memory set of the second channel is provided with a second flash memory and at least one second socket for memory extension. The controller determines an access method for the first flash memory and the second flash memory according to whether the flash memory is inserted into the first socket for memory extension and the second socket for memory extension. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an access device and an access method for a flash memory, and more particularly to an access device and an access method for a dual channel flash memory.

  Flash memory is an electrically programmable read-only memory that can be erased or programmed multiple times during operation. The flash memory usually includes a NOR flash memory or a NAND flash memory. Regardless of whether the flash memory is a NOR flash memory or a NAND flash memory, the number of times to erase or program the flash memory is limited. Considering NAND flash memory as an example, the number of times a multi-level cell NAND flash memory can be erased or programmed is typically about 10,000. Further, the number of times that the NAND flash memory of the single level cell can be erased or programmed is usually about 100,000 times.

  With current technology, there are dual channel flash memory access devices. When data is stored by the conventional dual channel flash memory access device, the data is divided into two data sections. These two data partitions are stored simultaneously in different flash memories via different channels. Therefore, the speed at which data is stored in the flash memory is effectively doubled. That is, the bandwidth for accessing data by the access device of the flash memory is doubled.

  However, flash memory can be damaged by being erased or programmed too many times. In the dual channel flash memory access device described above, when one channel of flash memory is damaged, data stored in the damaged flash memory is permanently lost. That is, once the flash memory in the conventional dual channel flash memory access device is damaged, there is a high possibility that the data in the flash memory cannot be recovered.

  An object of the present invention is to provide a flash memory access device and an access method for obtaining a dual channel flash memory set capable of increasing a transmission bandwidth and obtaining a data backup capability.

  According to the present invention, there is provided a flash memory access device comprising a controller, a first channel memory set, and a second channel memory set. The first channel memory set is coupled to the controller via the first channel and includes a first flash memory and at least a first memory expansion socket. The first flash memory is coupled to the controller, and the first memory expansion socket is coupled to the first flash memory and the controller. The second channel memory set is coupled to the controller via the second channel. The second channel memory set includes a second flash memory coupled to the controller, and a second memory expansion socket coupled to the second flash memory and the controller. The controller performs a read operation or a programming operation to be executed in the first flash memory and the second flash memory in response to detection of a flash memory insertion state of each of the first memory expansion socket and the second memory expansion socket. To decide.

  According to an example of the present invention, when the first memory expansion socket is connected to the third flash memory and the second memory expansion socket is connected to the fourth flash memory, the controller performs a read operation. Or the first flash memory, the second flash memory, depending on whether the programming operation is normally performed in the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory. The third flash memory and the fourth flash memory are determined as the main memory or the backup memory.

  According to an example of the present invention, a read operation or a programming operation is normally performed in each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory by the controller. When this is detected, the controller determines the first flash memory and the second flash memory as main memories, and determines the third flash memory and the fourth flash memory as backup memories. Alternatively, the controller can determine the third flash memory and the fourth flash memory as the main memory, and can determine the first flash memory and the second flash memory as the backup memory. It should be noted that flash memories configured in the same channel memory set can be backup memories of each other.

  According to an example of the present invention, a third flash memory is used to store a copy of the data stored in the first flash memory, and a fourth flash memory is used to store the second flash memory. Store a copy of the stored data.

  According to an example of the present invention, a copy of data stored in a third flash memory is stored using a first flash memory, and a fourth flash memory is stored using a second flash memory. Store a copy of the stored data.

  According to an example of the present invention, when the controller detects that a read operation or a programming operation is abnormally performed in each of the first flash memory and the third flash memory in the memory set of the first channel The controller determines the second flash memory as the main memory and the fourth flash memory as the backup memory. Alternatively, the controller can determine the fourth flash memory as the main memory and the second flash memory as the backup memory.

  According to an example of the present invention, when the controller detects that a read operation or a programming operation is abnormally performed in each of the second flash memory and the fourth flash memory in the memory set of the second channel The controller determines the first flash memory as the main memory and the third flash memory as the backup memory. Alternatively, the controller can determine the third flash memory as the main memory and the first flash memory as the backup memory.

  According to an example of the present invention, a first channel memory set, a second channel memory set, and a controller are configured on a circuit board.

  According to an example of the present invention, the memory set of the first channel and the controller are configured on a circuit board, and the memory set of the second channel is an open NAND flash memory interface set.

  According to an example of the present invention, the controller is configured on a circuit board, and each of the memory set of the first channel and the memory set of the second channel is an open NAND flash memory interface set.

  According to an example of the present invention, the controller is configured on a circuit board, and each of the first channel memory set and the second channel memory set is an open-type NAND flash memory interface set, and on the circuit board. Configure directly to.

  The invention further provides a read operation or programming to the first flash memory and the second flash memory in the first channel memory set and to the third flash memory and the fourth flash memory in the second channel memory set. There is also provided a flash memory access method comprising a step of providing a controller for performing an operation. In this case, the controller reads each of the first flash memory and the second flash memory in the first channel memory set and the third flash memory and the fourth flash memory in the second channel memory set. Determine if the operation or programming operation is normal. The controller determines whether the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory are operating normally, depending on whether each of the first flash memory, the second flash memory, and the fourth flash memory is operating normally. The memory, the third flash memory, and the fourth flash memory are determined as the main memory or the backup memory.

  As described above, a flash memory is provided as a backup memory in each of the flash memory sets of the present invention. Therefore, the data stored in the main flash memory can be copied into the backup memory. Further, when the flash memory is damaged due to too many erase and programming operations, the data in the flash memory can be effectively restored. Furthermore, in the present invention, by determining whether a read operation or a programming operation is normally performed, the flash memory in the dual channel memory set is stored in the main memory for storing data and in these main memories. It can be determined to be a backup memory that stores a copy of the data. Thus, an undamaged memory can be used effectively to maximize its efficiency.

  In order to make the aforementioned and other features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

  The accompanying drawings are included to provide a further understanding of the invention, and are a part of this specification. The drawings showing the embodiments of the present invention, together with the description of the specification, serve to explain the principle of the present invention.

FIG. 1 is a block diagram showing a flash memory access device 100 according to an embodiment of the present invention. FIG. 2 is a diagram showing a flash memory design method of the flash memory access device 100. FIG. 3 is a block diagram showing a flash memory access device 300 according to another embodiment of the present invention. FIG. 4 is an explanatory diagram illustrating a flash memory access method according to an embodiment of the present invention.

  FIG. 1 is a block diagram showing a flash memory access device 100 according to an embodiment of the present invention. As shown in FIG. 1, the flash memory access device 100 includes a controller 110, a first channel memory set 120, and a second channel memory set 130. In addition, the controller 110 is coupled to the first channel memory set 120 via the first channel 150 and is coupled to the second channel memory set 130 via the second channel 160. The first channel memory set 120 includes a flash memory 121 and a memory expansion socket 122, and the second channel memory set 130 includes a flash memory 131 and a memory expansion socket 132. The flash memory 121 and the memory expansion socket 122 are coupled to each other and coupled to the controller 110. The flash memory 131 and the memory expansion socket 132 are coupled to each other and coupled to the controller 110. Has been.

  When no memory is inserted into the memory expansion sockets 122 and 132, the controller 110 detects the flash memory non-insertion state of the memory expansion sockets 122 and 132 by a dual channel method. The flash memories 121 and 131 are accessed through the second channel 150 and the second channel 160, respectively.

  Alternatively, as shown in FIG. 1, when the memory expansion sockets 122 and 132 are connected to the flash memories 123 and 133, respectively, they are detected by the controller 110 during the actual operation of the flash memory access device 100. The flash memory 121, 123, and 131 in the first channel memory set 120 and the second channel memory set 130, respectively, according to the inserted state of the flash memory in the memory expansion sockets 122 and 132. A test for 133 is performed. The main purpose of this inspection is to determine whether the flash memories 121, 123, 131 and 133 are damaged. In other words, the controller 110 performs a reading operation and a programming operation regarding the flash memories 121, 123, 131 and 133, and the controller 110 can normally execute the reading operation or the programming operation regarding the flash memory 121, for example. In this case, it is determined that the flash memory 121 is not damaged. If the controller cannot successfully perform a read or programming operation on the flash memory 121, it is determined that the flash memory 121 is damaged.

  Thereafter, the controller 110 determines each of the flash memories as a main memory or a backup memory depending on whether a read operation or a programming operation can be normally executed with respect to the flash memories 121, 123, 131, and 133. The main memory is used to store data, and the backup memory is used to store a copy of the data stored in the main memory.

  It should be noted that the controller 110 periodically executes a determination process for determining whether the reading operation or the programming operation of the flash memories 121, 123, 131, and 133 is normal. Since the flash memory may be damaged due to too many erase and programming operations, the controller 110 determines whether the flash memories 121, 123, 131, and 133 in the flash memory access device 100 are damaged. It is necessary to dynamically adjust which flash memory is the main memory and which flash memory is the backup memory.

  In the following description, the design of these flash memories 121, 123, 131, and 133 in response to determining by the controller 110 whether a read or programming operation can be successfully performed on the flash memories 121, 123, 131, and 133. The controller 110 of an embodiment of the present invention that implements the method is described in detail to enable those skilled in the art to further understand the details of the embodiment of the present invention.

  As shown in FIGS. 1 and 2, FIG. 2 illustrates four possible allocation methods when the controller detects that a read or programming operation can be successfully performed on the flash memories 121, 123, 131, and 133. Show. The controller 110 can determine the flash memory 121 and the flash memory 131 as main memories. Further, the flash memory 123 and the flash memory 133 are determined as backup memories. The flash memory 123 can be used to store a copy of the data stored in the flash memory 121. Similarly, the flash memory 133 can be used to store a copy of the data stored in the flash memory 131. The controller 110 can also determine the flash memory 123 and the flash memory 133 as main memory (as indicated by the dashed line 220). Further, the flash memory 121 and the flash memory 131 are determined as backup memories. The flash memory 121 can be used to store a copy of the data stored in the flash memory 123. Similarly, the flash memory 131 can be used to store a copy of the data stored in the flash memory 133.

  Furthermore, the controller 110 can determine the flash memory 121 and the flash memory 133 as main memories (as indicated by the broken line 230). Further, the flash memory 123 and the flash memory 131 are determined as backup memories. The flash memory 123 can be used to store a copy of the data stored in the flash memory 121. Similarly, the flash memory 131 can be used to store a copy of the data stored in the flash memory 133. Alternatively, the controller 110 can determine the flash memory 123 and the flash memory 131 as the main memory (as indicated by the dashed line 240). Further, the flash memory 121 and the flash memory 133 are determined as backup memories. The flash memory 121 can be used to store a copy of the data stored in the flash memory 123. Similarly, the flash memory 133 can be used to store a copy of the data stored in the flash memory 131.

  As can be easily understood, if the flash memories 121, 123, 131, and 133 are not damaged, the controller 110 causes any flash memory in the memory set 120 of the first channel to become the main memory. In addition to the determination, another flash memory in the memory set 120 of the first channel can be determined to be a backup memory. On the other hand, the controller determines any flash memory in the memory set 130 of the second channel to be the main memory, and makes another flash memory in the memory set 130 of the second channel be the backup memory. Can be determined. Accordingly, the flash memory access device 100 divides the data to be stored, and then simultaneously divides the divided data into the main memory in the memory set 120 of the first channel and the memory set 130 of the second channel, respectively. The dual channel access method can be kept so that it can be stored.

  It should be noted that in the method of backing up the data in the main memory into the backup memory, the controller 110 can periodically copy the data in the main memory into the backup memory. That is, the time is calculated by a counter (not shown), and when the calculation time becomes equal to a predetermined cycle time, the controller 110 executes a backup process for copying the data in the main memory to the backup memory. Therefore, the data in the main memory is periodically backed up, and the data safety can be maintained.

  The data backup method described above is merely an example, and is not used to limit the present invention as using only the data backup method described above to back up data. Data backup methods well known to those skilled in the art can also be applied to the embodiments of the present invention.

  Alternatively, the controller 110 detects in real time whether a read operation or a programming operation is normally executed with respect to the flash memories 121, 123, 131, and 133, and executes the status of the flash memories 121, 123, 131, and 133. Since the time can be controlled, for example, when the flash memory 121 as the main memory is damaged, the controller 110 re-determines the flash memory 123 used as the backup memory of the flash memory 121 to become the main memory. Therefore, the flash memory access device 100 can still operate normally.

  As shown in FIG. 1, when the controller 110 detects that a read or programming operation is being performed abnormally in the flash memories 121 and 123 in the memory set 120 of the first channel, the controller 110 One of the flash memories 131 and 133 in the channel memory set 130 is determined as the main memory, and the other flash memory of the flash memories 131 and 133 in the second channel memory set 130 is the backup memory. Determine as. Similarly, if the controller 110 detects that a read or programming operation is being performed abnormally in the flash memories 131 and 133 in the second channel memory set 130, the controller 110 may detect the first channel memory set. One of the flash memories 121 and 123 in 120 is determined as the main memory, and the other flash memory in the flash memory 121 and 123 in the first channel memory set 120 is determined as the backup memory.

  FIG. 3 is a block diagram showing a flash memory access device 300 according to an embodiment of the present invention. As shown in FIG. 3, the flash memory access device 300 includes a controller 310, a first channel memory set 320, and a second channel memory set 330. The first channel memory set 320 has a flash memory 321 and a memory expansion socket 322, and the second channel memory set 330 has a flash memory 331. The difference between the flash memory access device 100 and the flash memory access device 300 of the present example is that the memory set 330 of the second channel of the flash memory access device 300 further includes several memory expansion sockets 3322 and 333. The flash memory connected to the memory expansion socket 333 can be used as a backup memory. Furthermore, several memory expansion sockets can be provided in the memory set 320 of the first channel.

  The controller 310, the first channel memory set 320, and the second channel memory set 330 in this example may be configured on a circuit board such as a motherboard. Alternatively, the controller 310 is configured on a circuit board, the first channel memory set 320 is configured on the same circuit board as the controller 310, and the second channel memory set 330 is configured as an open NAND flash memory interface. Set. Further, the controller 310 is configured on a circuit board, and each of the first channel memory set 320 and the second channel memory set 330 is an open-type NAND flash memory interface set, and these first channel memories are configured. The set 320 and the second channel memory set 330 may be configured on the same circuit board from which the controller is configured, but this is not necessarily so.

  FIG. 4 is a diagram showing a flash memory access method according to an embodiment of the present invention. As shown in FIG. 4, the first flash memory and the second flash memory of the memory set of the first channel, and the third flash memory and the fourth flash memory of the memory set of the second channel. In order to perform the reading operation or the programming operation, a controller is provided (step S410). Next, each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory in each of the first channel memory set and the second channel memory set performs a read operation or The controller determines whether or not the programming operation is normal (step S420). Further, depending on whether or not each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory is operating normally, the controller controls the first flash memory, the second flash memory, and the second flash memory. Each of the flash memory, the third flash memory, and the fourth flash memory is determined as a main memory or a backup memory (step S430).

  Further, depending on whether or not each of the flash memories is operating normally, the method by which the controller determines each of these flash memories as a main memory or a backup memory is the same as that described above with respect to the flash memory access devices 100 and 300. Examples are described in detail, and this method is not further described here.

  As described above, the present invention provides a flash memory access apparatus and access method for a dual channel memory set. Depending on whether each of the flash memory in the first channel memory set and the second channel memory set is damaged, the controller of the flash memory access device may designate each of these flash memories as main memory or backup memory. decide. Therefore, backup can be performed in the backup memory without losing data stored in the main memory. In addition, if the main memory is damaged, the controller may dynamically switch the backup memory to become the main memory to maintain normal operation of the flash memory access device.

  While the invention has been described with reference to the embodiments described above, it will be apparent to those skilled in the art that changes may be made to these embodiments without departing from the spirit of the invention. Therefore, the scope of the present invention is not limited to the above-described embodiments, but is defined by the claims.

100, 300 Flash memory access device 110, 310 Controller 120, 320, 330 Memory set 121, 123, 131, 133, 321, 331 Flash memory 122, 132, 322, 332, 333 Memory expansion socket 150 First channel 160 Second channel

Claims (19)

A controller,
A first channel memory set coupled to the controller via a first channel, the first channel memory set coupled to the first flash memory coupled to the controller; A memory set of the first channel having a flash memory and at least a first flash memory expansion socket coupled to the controller;
A second channel memory set coupled to the controller via a second channel, the second channel memory set comprising: a second flash memory coupled to the controller; A flash memory access device comprising: a flash memory and a memory set of the second channel having at least a second flash memory expansion socket coupled to the controller;
In response to detection of the flash memory insertion state of each of the first flash memory expansion socket and the second flash memory expansion socket, the controller causes the first flash memory and the second flash memory to A flash memory access device adapted to determine a read or programming operation to be performed.   2. The flash memory access device according to claim 1, wherein the first flash memory expansion socket is connected to a third flash memory, and the second flash memory expansion socket is connected to a fourth flash memory. The controller determines whether the read operation or the programming operation is normally performed in the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory, A flash memory access device configured to determine a first flash memory, a second flash memory, a third flash memory, and a fourth flash memory as a main memory or a backup memory.   3. The flash memory access device according to claim 2, wherein the controller further sets the backup memory as the main memory when it is detected that the reading operation or the programming operation is abnormally performed with respect to the main memory. Flash memory access device that is designed to switch to   3. The flash memory access device according to claim 2, wherein the controller has a normal read operation or programming operation for each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory. The first flash memory and the second flash memory are determined as the main memory, and the third flash memory and the fourth flash memory are determined as the backup memory. Access device.   5. The flash memory access device according to claim 4, wherein the third flash memory is used to store a copy of data stored in the first flash memory, and the second flash memory is A flash memory access device adapted to be used for storing a copy of data stored in the fourth flash memory.   3. The flash memory access device according to claim 2, wherein the controller causes a read operation or a programming operation to be abnormal for each of the first flash memory and the third flash memory in the memory set of the first channel. An access device for a flash memory configured to determine the second flash memory as a main memory and the fourth flash memory as a backup memory when it is determined that the second flash memory is being implemented.   3. The flash memory access device according to claim 2, wherein the controller causes a read operation or a programming operation to be abnormal for each of the second flash memory and the fourth flash memory in the memory set of the second channel. An access device for a flash memory configured to determine the first flash memory as a main memory and the third flash memory as a backup memory when it is determined to be implemented.   2. The flash memory access device according to claim 1, wherein the first channel memory set, the second channel memory set, and the controller are configured on a circuit board. .   2. The flash memory access device according to claim 1, wherein the memory set of the first channel and the controller are configured on a circuit board, and the memory set of the second channel is an open type NAND flash. A flash memory access device which is a memory interface set.   The flash memory access device according to claim 1, wherein the controller is configured on a circuit board, and each of the memory set of the first channel and the memory set of the second channel is an open type. A flash memory access device which is a NAND flash memory interface set.   The flash memory access device according to claim 1, wherein the controller is configured on a circuit board, and each of the memory set of the first channel and the memory set of the second channel is an open type. A flash memory access device which is a NAND flash memory interface set and is configured directly on the circuit board. A read operation or a programming operation is performed on the first flash memory and the second flash memory of the first channel memory set and the third flash memory and the fourth flash memory of the second channel memory set. For providing a controller,
Each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory in each of the first channel memory set and the second channel memory set includes: The controller determining whether it is normal in a read or programming operation;
Depending on whether or not each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory is operating normally, the controller controls the first flash memory. And determining each of the second flash memory, the third flash memory, and the fourth flash memory as a main memory or a backup memory. The method of accessing a flash memory of claim 12, further comprising:
A flash memory comprising a step of switching the backup memory to become the main memory when the controller detects that the controller is abnormally performing a read operation or a programming operation on the main memory; Access method. 13. The flash memory access method according to claim 12, wherein each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory is operating normally. And the controller determines each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory as a main memory or a backup memory,
When the controller detects that a read operation or a programming operation is normally performed for each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory. In addition, the controller includes determining the first flash memory and the third flash memory as main memories, and determining the second flash memory and the fourth flash memory as backup memories. Flash memory access method.   13. The flash memory access method according to claim 12, wherein the second flash memory is used to store a copy of data stored in the first flash memory, and the fourth flash memory includes: A flash memory access method used for storing a copy of data stored in the third flash memory. 13. The flash memory access method according to claim 12, wherein each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory is operating normally. And the controller determines each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory as a main memory or a backup memory,
When the controller detects that a read or programming operation is abnormally performed for each of the first flash memory and the second flash memory in the first channel memory set, the controller A method for accessing a flash memory, comprising: determining the third flash memory as a main memory and determining the fourth flash memory as a backup memory. 13. The flash memory access method according to claim 12, wherein each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory is operating normally. And the controller determines each of the first flash memory, the second flash memory, the third flash memory, and the fourth flash memory as a main memory or a backup memory,
When the controller detects that a read or programming operation is being performed abnormally for each of the third flash memory and the fourth flash memory in the second channel memory set, the controller A method for accessing a flash memory, comprising: determining the first flash memory as a main memory and determining the second flash memory as a backup memory. The method of accessing a flash memory of claim 12, further comprising:
A method of accessing a flash memory comprising the step of providing at least one expansion memory to be a backup memory in the memory set of the first channel. The method of accessing a flash memory of claim 12, further comprising:
A flash memory access method comprising: providing at least one expansion memory to be a backup memory in the memory set of the second channel.

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