JP2011077969A - Image processor, image display system, electronic device and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: an image processor capable of further effectively utilizing an image memory; an image display system; an electronic device; and an image processing method, etc. <P>SOLUTION: The image processor for supplying image data to an image display device includes: a first compressor for compressing the image data of an area excluding a predetermined area within an image area; a first memory for storing the image data compressed by the first compressor; and a first expander for expanding the image data of the area excluding the given area within the image memory, which are stored in the first memory, wherein the image data after being expanded by the first expander is supplied to the image display device. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, an image display system, an electronic apparatus, an image processing method, and the like.

  2. Description of the Related Art Conventionally, an image processing apparatus that supplies image data to an image display apparatus typified by a liquid crystal display apparatus or an organic EL (Electro Luminescence) display apparatus temporarily buffers the original image data, and then executes it as needed. The processed image data is output. With regard to this image processing apparatus, by incorporating a compression unit, the capacity of buffered image data is reduced, or the amount of data transferred to the image display apparatus is reduced.

  For example, in Patent Documents 1 to 3, after compressing image data in units of scanning lines and temporarily storing it in an image memory, the compressed image data is read from the image memory, decompressed, and supplied to the image display device. Thus, an image output driver IC that makes effective use of the image memory is disclosed. Patent Document 4 discloses a frame buffer device that includes a compression unit and suppresses the data transfer fee by outputting a result compressed by the compression unit when the display data stored in the frame memory is output to the outside. It is disclosed.

JP 2007-178850 A JP 2007-181052 A JP 2007-178851 A JP 2001-22553 A

  In the image processing apparatus, it is necessary to provide as many functions as possible using limited resources. Therefore, it is desirable that the built-in memory such as an image memory can be used more effectively. In this regard, in Patent Documents 1 to 3, since image data is compressed by a compressor and temporarily stored in an image memory or the like, the image memory or the like can be effectively used. On the other hand, in patent document 4, since compression is performed when data is transferred to the image display device, an image memory or the like cannot be effectively used.

  However, in recent years, display screens of electronic devices such as mobile phones have become larger, and it has been demanded to increase the capacity of built-in memory and the like of the image processing apparatus, even if disclosed in Patent Documents 1 to 3. Even if this technology is applied, the storage capacity of the image memory or the like may be insufficient.

  The present invention has been made in view of the above technical problems. According to some aspects of the present invention, it is possible to provide an image processing apparatus, an image display system, an electronic apparatus, an image processing method, and the like that can further effectively use an image memory.

  (1) According to one aspect of the present invention, an image processing device that supplies image data to an image display device compresses image data in a region other than a given region in the image region; A first memory for storing the image data compressed by the first compressor; and a first memory for storing the image data in an area excluding a given area in the image area, which is stored in the first memory. And the image data after being decompressed by the first decompressor is supplied to the image display device.

  According to this aspect, image data in a region other than a given region in the image region is compressed by the first compressor and stored in the first memory, and the first decompressor is stored in the first memory. Since the image data is read and the image data of the area excluding the given area is expanded and supplied to the image display device, the data size of the image data stored in the first memory can be reduced. it can. As a result, other data can be stored in the first memory, and the first memory can be used more effectively.

  (2) In the image processing apparatus according to another aspect of the present invention, the first compressor compresses image data of an area excluding a given rectangular area in the image area in units of scanning lines, and The first decompressor decompresses the image data of the area excluding the rectangular area in units of the scanning lines.

  According to this aspect, the first compressor compresses the image data in the area excluding the rectangular area set in the image area in units of scan lines, and the first decompressor reads from the first memory. Since the image data is read out and the image data in the area excluding the rectangular area is expanded in units of scanning lines and supplied to the image display device, the real-time compression process has a relatively simple configuration. The first memory can be used more effectively with a small processing load in a simple configuration.

  (3) An image processing apparatus according to another aspect of the present invention includes a control register in which control data for specifying a rectangular area in the horizontal direction and the vertical direction of the image is set, and the first compressor includes the first compressor The image data of the area excluding the rectangular area specified based on the control data is compressed, and the first decompressor is configured to specify the rectangular area specified based on the control data common to the first compressor. Decompresses the image data in the area excluding.

  According to this aspect, since the first compressor and the first decompressor perform the compression process and the decompression process of the image data based on the common control data, in addition to the above effect, The configuration of the compressor and the first decompressor can be made common, and the configuration can be simplified.

  (4) In the image processing apparatus according to another aspect of the present invention, the first compressor stops the compression operation of the image data with respect to the image data of the scanning line in the rectangular area, and the first compressor The first decompressor stops reading of the image data from the first memory and adds given dummy data to the image data of the scanning line in the rectangular area.

  According to this aspect, the first compressor stops the compression operation on the image data to be uncompressed, and the first decompressor adds dummy data corresponding to the image data. Therefore, in addition to the above effects, the processing of the subsequent circuit can be simplified.

  (5) An image processing apparatus according to another aspect of the present invention includes a control register in which control data designating a horizontal size and a vertical size of a given rectangular region in the image region is set, The first compressor includes an identification code embedding circuit that embeds an identification code in the image data in the rectangular area designated based on the control data when the image data is compressed in units of scanning lines. Embedded in the image data in the rectangular area designated based on the control data, and the compression operation of the image data is stopped, and the first decompressor An identification code detection circuit for detecting a code, and is specified based on the control data on the condition that the identification code is detected when the image data is expanded in units of scanning lines. Stops the reading of image data from the corresponding first memory to the image data of the rectangular area that is, it adds a given dummy data.

  According to this aspect, the first compressor adds an identification code to the image data to be uncompressed, and the first decompressor detects the identification code and uses the identification code as a reference. Since the image data to be uncompressed can be specified based on the control data, in addition to the above effects, the configuration of the first decompressor can be greatly simplified. Further, since dummy data is added corresponding to the image data to be uncompressed, the processing of the subsequent circuit can be simplified.

  (6) An image processing apparatus according to another aspect of the present invention includes: a second compressor that compresses image data; a second memory that stores image data compressed by the second compressor; A second decompressor for decompressing the image data stored in the second memory; and an overlay process of the image data decompressed by the first decompressor and the image data decompressed by the second decompressor And a superposition processing circuit.

  According to this aspect, the first memory in the image processing circuit that performs the overlay process can be used more effectively.

  (7) In another aspect of the present invention, an image display system is supplied by any of the image processing apparatuses described above, a host apparatus that outputs image data to the image processing apparatus, and the image processing apparatus. And an image display device for displaying an image based on the image data.

  According to this aspect, the image processing apparatus that more effectively utilizes the first memory that is the image memory is applied, and a more complex and multifunctional image display system can be provided.

  (8) In another aspect of the present invention, the image display system outputs the image processing apparatus described above and image data compressed by the first compressor to the image processing apparatus. An apparatus, a second host device that outputs image data compressed by the second compressor to the image processing device, and an image that displays an image based on the image data supplied by the image processing device Display device.

  According to this aspect, the image processing apparatus that more effectively uses the first memory that is the image memory in the overlay process is applied, and a more complex and multifunctional image display system can be provided.

  (9) In another aspect of the present invention, the electronic device includes any of the image processing apparatuses described above.

  According to this aspect, an image processing apparatus that uses the first memory, which is an image memory, more effectively is applied, and a more complex and multifunctional electronic device can be provided.

  (10) In another aspect of the present invention, the electronic device includes any one of the image display systems described above.

  According to this aspect, an image display system that uses the first memory that is an image memory more effectively is applied, and a more complex and multifunctional electronic device can be provided.

  (11) In another aspect of the present invention, an image processing method for supplying image data to an image display device compresses image data in a region excluding a given region in the image region, and the compressed image data A first compression step for storing the image data in a first memory, and a first expansion step for expanding the image data stored in the first memory and excluding a given area in the image area. The image data after the expansion in the first expansion step is supplied to the image display device.

  According to this aspect, in the first compression step, the image data of the region excluding the given region in the image region is compressed and stored in the first memory, and in the first decompression step, the image data is stored from the first memory. Since the image data is read and the image data of the area excluding the given area is expanded and supplied to the image display device, the data size of the image data stored in the first memory can be reduced. it can. As a result, other data can be stored in the first memory, and the first memory can be used more effectively.

  (12) In the image processing method according to another aspect of the present invention, the first compression step compresses image data of a region excluding a given rectangular region in the image region in units of scanning lines, In the first extension step, the image data of the area excluding the rectangular area is extended in units of the scanning lines.

  According to this aspect, in the first compression step, the image data in the region excluding the rectangular region set in the image region is compressed in units of scanning lines, and in the first expansion step, the image data is compressed from the first memory. Since the image data is read out and the image data in the area excluding the rectangular area is expanded in units of scanning lines and supplied to the image display device, the compression process and the expansion process can be performed with a simple process. With this configuration, the first memory can be used more effectively with a small processing load.

  (13) In the image processing method according to another aspect of the present invention, the first compression step is performed on image data of a scan line in a rectangular area designated in a horizontal direction and a vertical direction of the image. The compression operation of the image data is stopped, and the first decompression step stops the reading of the image data from the first memory with respect to the image data of the scanning line in the rectangular area, and the given dummy Append data.

  According to this aspect, in the first compression step, the compression operation is stopped for the image data to be uncompressed, and in the first decompression step, dummy data is added corresponding to the image data. Therefore, in addition to the above effect, the subsequent processing can be simplified.

  (14) In the image processing method according to another aspect of the present invention, when the image data is compressed in units of scan lines, the first compression step includes an image in a given rectangular area in the image area. An identification code embedding step of embedding an identification code in the data, embedding the identification code in the image data in the rectangular area, stopping the compression operation of the image data, and the first decompressing step Includes an identification code detection step for detecting the identification code, and corresponds to the image data in the rectangular area on the condition that the identification code is detected when the image data is expanded on a scanning line basis. Then, the reading of the image data from the first memory is stopped and given dummy data is added.

  According to this aspect, in the first compression step, an identification code is added to the image data to be uncompressed, and in the first decompression step, this identification code is detected, and the identification code is used as a reference. Since the non-compression processing target image data can be specified based on the control data, in addition to the above effects, the processing of the first decompression step can be greatly simplified. Further, since the dummy data is added corresponding to the image data to be uncompressed, the subsequent processing can be simplified.

  (15) An image processing method according to another aspect of the present invention compresses image data, stores a second compression step in which the image data is stored in a second memory, and expands the image data stored in the second memory. A second decompression step, and an overlay processing step for performing an overlay process on the image data decompressed in the first decompression step and the image data decompressed in the second decompression step.

  According to this aspect, the first memory can be used more effectively when performing the overlay process.

1 is a block diagram of a configuration example of an image display system to which an image processing apparatus having a basic configuration is applied in an embodiment of the present invention. 1 is a diagram showing an outline of a basic configuration of an image processing apparatus according to the present invention. The block diagram of the structural example of the image display system different from FIG. FIG. 4 is a block diagram of a configuration example of the image processing apparatus in FIG. 3. Explanatory drawing of the operation example of the image processing apparatus of FIG. FIG. 6 is an operation explanatory diagram of the image processing apparatus of FIG. 5. 7A and 7B are diagrams schematically showing compressed image data stored in the first memory. 1 is a block diagram of a detailed configuration example of an image processing apparatus. Explanatory drawing of the control data for designating the rectangular area | region set in the control register of FIG. 4 or FIG. FIG. 10A and FIG. 10B are diagrams schematically showing timing diagrams of processing examples of compression processing with the configuration shown in FIG. 11A and 11B are diagrams illustrating the compression processing of FIGS. 10A and 10B. The block diagram of the structural example of the 1st compressor of FIG. 1 is a block diagram of a detailed configuration example of an image processing apparatus. 14A and 14B are diagrams schematically illustrating a timing diagram of a processing example of decompression processing with the configuration illustrated in FIG. FIG. 14 is a block diagram of a configuration example of a first decompressor in FIG. 13. FIG. 5 is a block diagram of a configuration example of a synthesis processing circuit in FIG. 4. FIG. 17 is a block diagram of a configuration example of the synthesis circuit in FIG. 16. The block diagram of the detailed structural example of the image processing apparatus in this modification. FIGS. 19A and 19B are diagrams schematically illustrating a timing diagram of a processing example of the compression processing with the configuration illustrated in FIG. 20 (A) and 20 (B) are diagrams illustrating the compression processing of FIGS. 19 (A) and 19 (B). The block diagram of the detailed structural example of the image processing apparatus in this modification. FIGS. 22A and 22B are diagrams schematically illustrating a timing diagram of a processing example of the decompression processing with the configuration illustrated in FIG. 21. 1 is a block diagram of a configuration example of a mobile phone as an electronic device according to an embodiment. 24A and 24B are perspective views illustrating the configuration of an electronic apparatus to which the image processing apparatus or the image display system according to this embodiment is applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily indispensable configuration requirements for solving the problems of the present invention.

  Hereinafter, a liquid crystal display device will be described as an example of the image display device according to the present invention, but the present invention is not limited to this.

FIG. 1 shows a block diagram of a configuration example of an image display system to which an image processing apparatus having a fundamental configuration in one embodiment of the present invention is applied.
FIG. 2 shows an outline of the basic configuration of the image processing apparatus according to the present invention. In FIG. 2, the same parts as those in FIG.

  The image display system 10 includes a liquid crystal display device (image display device in a broad sense) 20, an image processing device (display controller, image processing controller, image supply device) 50, and a host device 200. The host device 200 generates image data to be displayed on the liquid crystal display device 20 and outputs it to the image processing device 50. The image processing device 50 compresses the image data from the host device 200 and stores the compressed image data in the built-in image memory. Thereafter, when outputting image data to the liquid crystal display device 20, the image processing device 50 expands the image data read from the image memory and outputs the expanded image data to the liquid crystal display device 20. The liquid crystal display device 20 displays an image based on the image data from the image processing device 50.

  The host device 200 includes a central processing unit (hereinafter referred to as CPU) and a memory, and a CPU that reads a program stored in the memory executes a process corresponding to the program, for example, Image data corresponding to the content image is generated. For example, the content image includes a moving image, a still image, a natural image taken by a camera, a menu screen necessary for operation, character / graphic information such as an icon, and the like. The host apparatus 200 can control the image processing apparatus 50 by setting control data in a control register built in the image processing apparatus 50.

  As shown in FIG. 2, the image processing apparatus 50 includes a first host interface (InterFace: hereinafter abbreviated as I / F) 110, a first compressor 300, an image memory 400, and a first decompressor. 500, LCD I / F 120, and control register 600.

  The first host I / F 110 performs reception interface processing of a signal corresponding to image data or control data input via a bus connected to the host device 200. Control data from the host apparatus 200 received via the first host I / F 110 is set in the control register 600. A control signal is generated according to the control data set in the control register 600, and each part of the image processing apparatus 50 is controlled based on these control signals.

  The first compressor 300 compresses image data received from the host device 200 via the first host I / F 110 in units of scan lines. In other words, the first compressor 300 performs compression processing on the basis of image data for one horizontal scanning period of the image as one unit, and performs compression processing on the image data for the next one horizontal scanning period again. The compression processing in units of scan lines can be processed in real time with a relatively simple configuration. The first compressor 300 can perform compression processing on image data in an area designated by control data set in the control register 600. More specifically, the first compressor 300 performs compression processing only on the image data in the image area except for the rectangular area set in the control register 600, and the image data in the rectangular area is processed. Eliminates the compression process, thereby reducing the size of the compressed image data obtained by the compression process.

  The image memory 400 stores the compressed image data generated by the first compressor 300. The first decompressor 500 decompresses the compressed image data (image data) stored in the image memory 400 in units of scanning lines. In other words, the first decompressor 500 performs decompression processing with image data for one horizontal scanning period of the image as one unit. The first decompressor 500 performs decompression processing on the image data in the area compressed by the compressor 300.

  The LCD I / F 120 performs transmission interface processing of signals input / output via a bus connected to the liquid crystal driving circuit 40. The LCD I / F 120 generates a display timing control signal in the liquid crystal display device 20 and outputs the display timing control signal to each unit of the image processing device 50 and the liquid crystal display device 20. The display timing control signal includes a display vertical synchronization signal VSYNC, a display horizontal synchronization signal HSYNC, and a display pixel clock CLK. The LCD I / F 120 is configured to display the display timing control signal and the display timing control. The image data after transmission interface processing synchronized with the signal is output to the liquid crystal display device 20.

  As described above, the image processing apparatus 50 can designate an image area to be compressed in an image displayed on the liquid crystal display device 20, and the image processing apparatus 50 performs compression processing on the image data in the designated area. I do. Then, when outputting the image data to the liquid crystal display device 20, the image processing device 50 performs the decompression process only on the image data in the designated area and then outputs it. Thereby, the storage capacity of the compressed image data stored in the image memory 400 can be reduced, and the image memory 400 can be effectively used.

  The liquid crystal display device 20 includes a liquid crystal display panel 30 and a liquid crystal driving circuit 40. The liquid crystal display panel 30 has a liquid crystal sealed between a first glass substrate and a second glass substrate. The first glass substrate is an active matrix substrate, for example, and each pixel is provided with a thin film transistor (hereinafter referred to as TFT) which is an active element. A transparent pixel electrode is connected to the drain terminal of the TFT of each pixel, a source line that is a data line is connected to the source terminal, and a gate line that is a scanning line is connected to the gate terminal. A transparent electrode is provided on the second glass substrate facing the first glass substrate. On the second glass substrate, a liquid crystal driving circuit 40 for driving the liquid crystal display panel 30 is COG (Chip On Glass) mounted along the short side of the first glass substrate. The liquid crystal driving circuit 40 drives the liquid crystal display panel 30 by supplying a scanning signal to the gate line of the liquid crystal display panel 30 and a data signal to the source line.

  Next, a configuration in which the above-described image processing apparatus 50 is applied and the image memory can be used more effectively will be described.

  FIG. 3 shows a block diagram of a configuration example of an image display system different from FIG. In FIG. 3, the same parts as those in FIG.

  The image display system 12 in FIG. 3 is different from the image display system 10 in FIG. 1 in that the image processing device 50 is replaced with the image processing device 100, and the first host device 210 and the second host device are added to the image processing device 100. 220 is connected. Each of the first host device 210 and the second host device 200 has the same configuration as the host device 200 of FIG. 1 and supplies image data to the image processing apparatus 100. The first host device 210 has an application processor, and is responsible for processing that causes a heavy load only by the second host device 220. The second host device 220 has a main processor and controls the entire image display system 12 and the image processing apparatus 100.

  FIG. 4 shows a block diagram of a configuration example of the image processing apparatus 100 of FIG. In FIG. 4, the same parts as those in FIG. In FIG. 4, the control data set in the control register 610 is shown to be reflected only in the first compressor 300, the first decompressor 500, and the synthesis processing circuit 700, but for convenience of explanation. The control register 610 has a plurality of registers for controlling each part of the image processing apparatus 10, and illustration of control signals output from each register to each part is omitted.

  In addition to the first host I / F 110, the first compressor 300, the image memory 400, the first decompressor 500, and the LCD I / F 120 shown in FIG. F112, a second compressor 302, a second decompressor 502, a control register 610, and a synthesis processing circuit 700 (superposition processing circuit). The image memory 400 includes a first memory 410 and a second memory 412. In FIG. 4, the first memory 410 and the second memory 412 are described independently. However, the storage area allocated to one memory element is divided by an address to substantially store two memories. You may comprise so that a function may be provided.

  The first host I / F 110 is connected to the first host device 210 of FIG. 3 and performs reception interface processing of image data from the first host device 210. The compressed image data (image data) compressed by the first compressor 300 is stored in the first memory 410. The first decompressor 500 reads the compressed image data stored in the first memory 410 and performs decompression processing on the compressed image data. The image data decompressed by the first decompressor 500 is supplied to the composition processing circuit 700.

  The second host I / F 112 is connected to the second host device 220 shown in FIG. 3, and performs reception interface processing of control data or image data from the second host device 220. Control data received via the second host I / F 112 is set in the control register 610. The control register 610 has the function of the control register 600 of FIG. 2, and each unit of the image processing apparatus 100 is controlled by a control signal generated according to control data set in the control register 610. Image data received via the second host I / F 112 is compressed by the second compressor 302. The second compressor 302 may perform the compression process by a process different from that of the first compressor 300, but it is desirable to compress the image data in units of scan lines as in the first compressor 300. The compressed image data (image data) compressed by the second compressor 302 is stored in the second memory 412. The second decompressor 502 reads the compressed image data stored in the second memory 412 and performs decompression processing corresponding to the compression processing of the second compressor 302 on the compressed image data. The image data expanded by the second expander 502 is supplied to the composition processing circuit 700.

  The composition processing circuit 700 performs composition processing using the image data decompressed by the first decompressor 500 and the image data decompressed by the second decompressor 502. In the present embodiment, the composition processing circuit 700 performs an overlay process on images represented by both image data. The LCD I / F 120 outputs the display timing control signal and the image data synthesized by the synthesis processing circuit 700 and synchronized with the display timing control signal to the liquid crystal display device 20.

  FIG. 5 is an explanatory diagram of an operation example of the image processing apparatus 100 of FIG. In FIG. 5, the same parts as those in FIG.

  For example, it is assumed that the first host device 210 generates image data of the background image IMG1, and the second host device 220 generates image data of the content image IMG2. At this time, the second host device 220 having the main processor sets control data for designating the compression target area excluding the rectangular area AR1 in the control register 610 (not shown in FIG. 5). The first compressor 300 compresses image data in an area excluding the rectangular area AR1 specified in the control register 610 among the image data generated by the first host device 210 in units of scan lines. The compressed image data is stored in the first memory 410. The first decompressor 500 performs decompression processing on the compressed image data read from the first memory 410.

  On the other hand, the second compressor 302 directly compresses the image data of the content image generated by the second host device 220 and stores the compressed image data in the second memory 412. The second decompressor 502 performs decompression processing on the compressed image data read from the second memory 412.

  The synthesis processing circuit 700 performs a process of synthesizing the background image IMG1 excluding the rectangular area AR1 and the content image IMG2 using the image data of each of the first decompressor 500 and the second decompressor 502, and creates a synthesized image. Image data corresponding to IMG3 is generated.

  FIG. 6 is an operation explanatory diagram of the image processing apparatus 100 of FIG. FIG. 6 schematically shows the background image IMG1 generated by the first host device 210 in units of scan lines.

  The first host device 210 generates the image data of the background image IMG1 shown in FIG. 6, while the second host device 220 receives control data for designating the rectangular area AR1 in the background image IMG1 of FIG. Set to. The rectangular area AR1 can be designated by the horizontal image size (image H size), the vertical image size (image V size), and the cropping start position. In FIG. 6, the rectangular area AR1 is designated by the cutting start position and the cutting end position for each of the horizontal direction and the vertical direction.

  The first compressor 300 compresses in units of scanning lines in the areas AR2 and AR3, and compresses in units of scanning lines in the areas AR4 and AR5 excluding the rectangular area AR1 in the scanning lines straddling the rectangular area AR1.

  7A and 7B schematically show compressed image data stored in the first memory 410. FIG. FIG. 7A schematically shows the compressed image data stored in the first memory 410 in units of scanning lines, corresponding to FIG. FIG. 7B schematically shows compressed image data corresponding to the P (P is a positive integer, the same applies hereinafter) line in FIG. In FIG. 7A, parts corresponding to those in FIG.

  As described with reference to FIG. 6, the first compressor 300 compresses the image data in the area excluding the rectangular area AR1 in units of scan lines. Therefore, the compressed image data as shown in FIG. Stored in the memory 410. For the scan lines straddling the rectangular area AR1, compression is performed for each area, and for the P line, only the compressed image data in the area AR4 and the compressed image data in the area AR5 are stored in the first memory 410 as shown in FIG. Stored in Thus, the storage area corresponding to the compressed image data storage area BR1 can be used as a storage area for other data (image data or the like), and the first memory 410 (image memory 400) can be effectively used.

  Next, the image processing apparatus 100 in FIG. 4 will be described in detail. Since the second compressor 302 and the second decompressor 502 may compress the image data by a known compression process and then decompress the image data by a known decompression process, the image processing apparatus 100 will be described below. Description will be made by paying attention to the compression processing side by the first compressor 300 and the decompression processing side by the first decompressor 500.

FIG. 8 shows a block diagram of a detailed configuration example of the image processing apparatus 100. FIG. 8 shows a configuration for realizing the compression processing by the first compressor 300. In FIG. 8, the first host I / F 110 is also illustrated. In FIG. 8, the same parts as those in FIG.
FIG. 9 is an explanatory diagram of control data for designating a rectangular area set in the control register 610 of FIG. 4 or FIG.

  In the present embodiment, as shown in FIG. 9, a region excluding the rectangular region AR1 is specified from the region of the image represented by the compression target image data, and the compression processing is performed on the region excluding the rectangular region AR1. Make it. For this reason, in this embodiment, the area | region except this rectangular area AR1 is specified by designating rectangular area AR1. However, the present embodiment is not limited by the method for specifying the compression target area. In the present embodiment, the horizontal cut start position (hereinafter referred to as H cut start position), the horizontal cut end position (hereinafter referred to as H cut end position), the horizontal image size (hereinafter referred to as image H size), the image Control control data corresponding to each of a vertical cut start position (hereinafter referred to as V cut start position), a vertical cut end position (hereinafter referred to as V cut end position), and an image vertical size (hereinafter referred to as image V size). By setting the register 610, the rectangular area AR1 is designated.

  As illustrated in FIG. 8, the image processing apparatus 100 includes an H counter 310, a V counter 320, a cut area identification signal generation circuit 330, and a memory write circuit 340.

  The H counter 310 is a counter that is reset by the frame head signal and counts the number of pixels in the horizontal direction of the image in synchronization with the pixel clock CLK. Each of the image H size, the H crop start position, and the H crop end position Control data corresponding to is input. When the counting starts, the H counter 310 outputs a line head identification signal and outputs a horizontal cutting effective signal that is active from the H cutting start position to the count value corresponding to the H cutting end position.

  The V counter 320 is a counter that is reset by the frame head signal and counts the number of lines in the vertical direction of the image in synchronization with the line head identification signal. The V counter 320 counts the image V size, V crop start position, and V cut end position. Control data corresponding to each is input. When the count starts, the V counter 320 outputs a vertical cut valid signal that becomes active from the V cut start position to the count value corresponding to the V cut end position.

  The cut area identification signal generation circuit 330 outputs a cut effective signal corresponding to the cut area that is the rectangular area AR1 based on the horizontal cut effective signal from the H counter 310 and the vertical cut effective signal from the V counter 320. In the first compressor 300, whether or not the image data is valid is determined based on the data enable signal DataEnable. Then, the first compressor 300 applies to the image data in the region excluding the cut area specified by the cut valid signal on the condition that the image data is determined to be valid by the data enable signal DataEnable. Compression processing will be performed.

  The memory write circuit 340 performs control to store the image data compressed by the first compressor 300 in the first memory 410. More specifically, the memory write circuit 340 is reset by a frame head signal and outputs an address signal Add and image data Data to the first memory 410 in synchronization with the write signal WR.

FIGS. 10A and 10B schematically show timing charts of processing examples of the compression processing with the configuration shown in FIG. FIG. 10A shows a timing chart of a processing example of Q lines (Q is a positive integer, the same applies hereinafter) lines in the area excluding the rectangular area AR1 in FIG. FIG. 10B shows a timing chart of a processing example of the P line straddling the rectangular area AR1 which is the cut area in FIG.
FIGS. 11A and 11B are explanatory diagrams of the compression processing of FIGS. 10A and 10B. FIG. 11A shows an explanatory diagram of the compression process of the Q line in FIG. FIG. 11B illustrates an explanatory diagram of the compression process of the P line in FIG. 11A and 11B, the number of pixels in the horizontal direction of one scanning line is N (N is a positive integer, the same applies hereinafter), and the pixel value of each pixel is represented by a pixel number “p”. Is shown. The compression process is represented by a function f. In FIG. 11B, the area from the Lth pixel (L is a positive integer, the same applies hereinafter) to the (M−1) th pixel (M is a positive integer, the same applies hereinafter) of the P line is the cut-out area. Assume that it is a pixel.

When the data enable signal DataEnable becomes active and the image data in the horizontal direction of the image becomes valid, the H counter 310 activates the line head identification signal for one pulse. As shown in FIG. 10A, since the cut line does not cross the cut area in the Q line, the cut valid signal remains inactive, and the first compressor 300 performs the compression process of the image data of the Q line. Do. In the present embodiment, the first compressor 300 compresses the difference between the pixel values of adjacent pixels. That is, as shown in FIG. 11A, the Q-line leading pixel PF1 corresponding to the line leading identification signal is output as it is (p ₁ ), and then differential compression is performed (f (p ₂ −p _1). ), F (p ₃ −p ₂ ),..., F (p _N−1 −p _{N− 2} ), f (p _N− p _N−1 )) are stored in the first memory 410. Reduce the data size of compressed image data.

On the other hand, as shown in FIG. 10B, in the P line, the first cut effective signal is active for the image data corresponding to the cut area and the first cut effective signal is inactive. The compressor 300 performs image data compression processing for each region excluding the cut-out area. That is, as shown in FIG. 11B, the Q-line leading pixel PF2 corresponding to the line leading identification signal is output as it is (p ₁ ), and then differential compression is performed up to the (L−1) th pixel. (F (p ₂ −p ₁ ),..., F (p _L−1 −p _L−2 )). Further, differential compression is performed from the Mth pixel to the Nth pixel. At this time as well, the pixel value of the Mth pixel that is the first pixel PE1 is output as it is (p _M ), and then the difference is made to the Nth pixel. By performing compression (f (p _{M + 1} −p _{M + 2} ),..., F (p _N −p _N−1 )), the data size of the compressed image data stored in the first memory 410 is reduced. In the present embodiment, the compression operation of the first compressor 300 is stopped while the cut area effective signal is active, and the compression operation of the first compressor 300 is performed while the cut area effective signal is inactive. By doing so, the differential compression in units of scanning lines as described above is performed.

  The first compressor 300 that performs such compression processing can be realized by the following configuration, for example.

  FIG. 12 shows a block diagram of a configuration example of the first compressor 300 in FIG. The first compressor 300 performs compression processing (encoding) of image data for each of the R component, G component, and B component sub-pixels constituting one pixel. FIG. 12 shows a configuration in which the compression processing is performed on the image data of the R component sub-pixels in the first compressor 300, but the G component and B component sub-pixels are also processed in the first compressor 300. It is comprised similarly.

  The portion of the first compressor 300 that encodes the R component image data includes a subtractor 350R, a quantization table 352R, an inverse quantization table 354R, an adder 356R, selectors 358R and 360R, and a flip-flop. 362R and a pixel counter 364R.

  The subtractor 350R obtains a difference between the input image data and the image data of the immediately adjacent pixel held in the flip-flop 362R, and outputs difference data including a carry bit (borrow bit). This difference data is supplied to the quantization table 352R. In the quantization table 352R, an output value obtained by quantizing the input value corresponding to the input value is registered in advance, and the quantized data as the output value is output using the difference data as the input value. The quantized data is supplied to the inverse quantization table 354R.

  The inverse quantization table 354R is a table corresponding to the quantization table 352R, and an output value is registered in advance so that the input value is inversely quantized to become the input value of the quantization table 352R corresponding to the input value. Yes. The inverse quantization table 354R receives the quantized data from the quantization table 352R as an input value and outputs inverse quantized data that is an output value.

  The quantized data from the quantization table 352R is also input to the selector 358R. The selector 358R receives the quantized data and the original image data, and outputs any one data based on the selection control signal SEL generated by the pixel counter 364R. The output data of the selector 358R is stored in the first memory 410 as encoded data.

  The inversely quantized data from the inverse quantization table 354R is input to the adder 356R. The dequantized data and the image data held in the flip-flop 362R are input to the adder 356R. The adder 356R adds the inversely quantized data and the image data of the flip-flop 362R, and supplies the added data to the selector 360R. The selector 360R receives the addition data from the adder 356R and the original image data, and outputs any one data based on the selection control signal SEL generated by the pixel counter 364R. The selection data of the selector 360R is held in the flip-flop 362R. The flip-flop 362R can latch the selection data using the pixel clock CLK corresponding to the image data input via the first host I / F 110.

  The pixel counter 364R receives a pixel clock CLK, a data enable signal DataEnable, a frame head signal, a line head identification signal, and a cutout valid signal, and generates a selection control signal SEL so that encoding is performed in units of one scanning line. To do. The pixel counter 364R has a counter that is reset by a frame head signal or a line head identification signal, and is counted up by the pixel clock CLK while the data enable signal DataEnable is active. The counter is initialized when the cutout valid signal becomes active, and encoding is stopped during the period when the cutout valid signal is active. As a result, the pixel counter 364R outputs the first pixel in the differential compression in units of scan lines without performing the compression process, and generates the selection control signal SEL so as to perform the encoding process for the pixel following the first pixel.

  FIG. 13 shows a block diagram of a detailed configuration example of the image processing apparatus 100. FIG. 13 shows a configuration for realizing the decompression process by the first decompressor 500. In FIG. 13, the synthesis processing circuit 700 is also shown. In FIG. 13, the same parts as those in FIG.

  The image processing apparatus 100 includes an H counter 510, a V counter 520, a cut area identification signal generation circuit 530, and a memory read circuit 540.

  The H counter 510 is a counter that is reset by the frame head signal and counts the number of pixels in the horizontal direction of the image in synchronization with the pixel clock CLK. Each of the image H size, the H crop start position, and the H crop end position Control data corresponding to is input. When the counting starts, the H counter 510 outputs a line head identification signal and also outputs a horizontal cutting effective signal that becomes active from the H cutting start position to the count value corresponding to the H cutting end position.

  The V counter 520 is a counter that is reset by the frame head signal and counts the number of lines in the vertical direction of the image in synchronization with the line head identification signal. The V counter 520 includes an image V size, a V crop start position, and a V cut end position. Control data corresponding to each is input. When the count starts, the V counter 520 outputs a vertical cut valid signal that becomes active from the V cut start position to the count value corresponding to the V cut end position. The V counter 520 detects the end timing of one frame and generates a one-frame end signal corresponding to the end timing.

  The cut area identification signal generation circuit 530 outputs a cut valid signal corresponding to the cut area based on the horizontal cut valid signal from the H counter 510 and the vertical cut valid signal from the V counter 520. In the first decompressor 500, it is determined whether the image data is valid based on the data enable signal DataEnable. The first decompressor 500 performs the decompression process on the image data on the condition that the image data is determined to be valid by the data enable signal DataEnable, and is designated by the cut valid signal. Dummy data is added (or inserted) corresponding to the cut area. As a result, the compressed image data whose data size is reduced without being compressed in the first compressor 300 is complemented.

  The memory read circuit 540 controls to read the compressed image data stored in the first memory 410. More specifically, the memory read circuit 540 outputs the address signal Add to the first memory 410 in synchronization with the read signal RD until the one frame end signal from the V counter 520 becomes active. The compressed image data Data is read out. Further, the memory read circuit 540 stops the read control of the compressed image data when the cutout valid signal generated by the cutout area identification signal generation circuit 530 is input as a data output stop signal and the data output stop signal is active.

  FIGS. 14A and 14B schematically show timing charts of processing examples of the decompression processing with the configuration shown in FIG. FIG. 14A shows a timing chart of a processing example of the Q line in the area excluding the rectangular area AR1 in FIG. FIG. 14B shows a timing chart of a processing example of P lines that straddle the rectangular area AR1 that is the cut-out area of FIG.

  When the data enable signal DataEnable becomes active and the image data in the horizontal direction of the image becomes valid, the H counter 510 activates the line head identification signal for one pulse. As shown in FIG. 14A, in the Q line, since the cut area does not cross over, the cut valid signal remains inactive, and the first decompressor 500 performs the process of decompressing the image data of the Q line. Do. In the present embodiment, the first expander 500 expands using a difference from the pixel value of an adjacent pixel. That is, the first pixel PF3 of the Q line is output as it is, and the subsequent pixels are subjected to differential expansion processing corresponding to the differential compression shown in FIG.

  On the other hand, as shown in FIG. 14B, in the P line, the cut valid signal becomes active for the image data corresponding to the cut area, and the first decompressor 500 stops reading the image data. On the other hand, while adding dummy data, the image data difference expansion process is performed for each area excluding the cut-out area, corresponding to the difference compression shown in FIG. That is, the first pixel PF4 of the Q line corresponding to the line head identification signal is output as it is, and thereafter, differential expansion is performed up to the (L-1) th pixel. Further, dummy data is added from the Lth pixel to the (M−1) th pixel, and differential expansion is performed from the Mth pixel to the Nth pixel. Also at this time, the pixel value of the Mth pixel, which is the first pixel PE2, is output as it is, and thereafter, differential expansion is performed up to the Nth pixel.

  The first decompressor 500 that performs such decompression processing can be realized by the following configuration, for example.

  FIG. 15 shows a block diagram of a configuration example of the first decompressor 500 of FIG. The first decompressor 500 performs image data decompression processing (decoding) for each of the R component, G component, and B component sub-pixels constituting one pixel. FIG. 15 illustrates a configuration in which, in the first decompressor 500, the decompression process is performed on the image data of the R component sub-pixel. In the first decompressor 500, the G component and B component sub-pixels are illustrated. Is similarly configured.

  The parts of the first decompressor 500 that decode the R component image data are the inverse quantization table 550R, the adder 552R, the dummy data holding circuit 554R, the selector 556R, the flip-flop 558R, and the pixel counter 560R. including.

  The inverse quantization table 550R is the same as the inverse quantization table 354R in FIG. 12, and the inverse quantization table 550R converts encoded data into inversely quantized data. The adder 552R receives the inversely quantized data from the inverse quantization table 550R and the image data held in the flip-flop 558R. The adder 552R adds the inversely quantized data and the image data of the flip-flop 558R, and outputs the added data. The added data is input to the selector 556R. The selector 556R receives original image data (image data read from the first memory 410), dummy data held in advance in the dummy data holding circuit 554R, and addition data, and the pixel counter 560R. One of the data is output based on the selection control signal SEL1 generated by the above. Selection data of the selector 556R is held in the flip-flop 558R. The flip-flop 558R can latch the selection data using the pixel clock CLK corresponding to the image data input via the first host I / F 110.

  The pixel counter 560R receives the pixel clock CLK, the data enable signal DataEnable, the frame head signal, the line head identification signal, and the cutout valid signal, and generates a selection control signal SEL1 so that decoding is performed in units of one scanning line. . The pixel counter 560R includes a counter that is reset by a frame head signal or a line head identification signal, and is counted up by the pixel clock CLK while the data enable signal DataEnable is active. The counter is initialized with the count value when the cut valid signal becomes active. As a result, the pixel counter 560R outputs the first pixel in the differential expansion in units of scanning lines as it is without performing the expansion process, and outputs the dummy data from the dummy data holding circuit 554R when the cutting valid signal becomes active. In the area excluding the area, the selection control signal SEL1 is generated so that the decoding process is performed on the pixels following the head pixel.

  As described above, in the present embodiment, the first compressor 300 and the first decompressor 500 perform image data compression processing and decompression processing based on the common control data, and store them in the first memory 410. The data size of the compressed image data to be stored can be reduced, and the image memory 400 can be effectively used.

  Next, the composition processing circuit 700 in FIG. 4 that performs image composition processing using the decompressed image data from the first decompressor 500 and the decompressed image data from the second decompressor 502 will be described.

FIG. 16 is a block diagram showing a configuration example of the synthesis processing circuit 700 shown in FIG. The configuration of the synthesis processing circuit 700 is not limited to that shown in FIG.
FIG. 17 shows a block diagram of a configuration example of the synthesis circuit of FIG. The configuration of the synthesis circuit in FIG. 16 is not limited to that shown in FIG. In FIG. 17, the key color register is also shown.

  The composition processing circuit 700 includes a key color comparison circuit 710, a composition circuit 720, and a key color register 730. The key color register 730 may be built in the control register 610 of FIG. The key color 732 and the transmittance 734 are set in the key color register 730 by the second host device 220. The key color comparison circuit 710 compares the key color 732 set in the key color register 730 with the image data from the first decompressor 500 on a pixel-by-pixel basis, and uses the result as a coincidence detection signal for each pixel as a synthesis circuit 720. Output for.

  The transmittance 734 set in the key color register 730 is input to the synthesis circuit 720. The synthesizing circuit 720 synthesizes the output data of the first decompressor 500 and the output data of the second decompressor 502 based on the transmittance 734 for the pixels whose coincidence is detected based on the coincidence detection signal. Output image data corresponding to the image IMG3 is output. The combining circuit 720 also outputs the output data of the first decompressor 500 and the output data of the second decompressor 502 in accordance with a predetermined overwriting order for pixels in which a mismatch is detected based on the match detection signal. And output image data corresponding to the composite image IMG3 is output.

  As shown in FIG. 17, the synthesis circuit 720 includes a first multiplier 722, a second multiplier 724, and an adder 726. The first multiplier 724 receives the output data of the second expander 502, the coincidence detection signal, and the transmittance g set in the key color register 730. Then, when a match is detected by the match detection signal, the first multiplier 722 multiplies the transmission data by the output data of the second expander 502 and outputs the multiplication result. Further, when a match is detected by the match detection signal, the first multiplier 722 sets the transmittance to “0”, multiplies the transmittance by the output data of the second expander 502, and The multiplication result is output.

  Similarly, the output data of the first decompressor 500, the coincidence detection signal, and the transmittance g set in the key color register 730 are input to the second multiplier 724. When a match is detected by the match detection signal, the second multiplier 724 sets the transmittance to (1-g), multiplies the transmittance by the output data of the first expander 500, and Outputs the multiplication result. The second multiplier 724 sets the transmittance to “1” when the coincidence is detected by the coincidence detection signal, multiplies the transmittance by the output data of the first expander 500, and The multiplication result is output.

  Adder 726 adds the multiplication result of first multiplier 722 and the multiplication result of second multiplier 724, and outputs the addition result as output image data corresponding to synthesized image IMG3.

As a result, the synthesis circuit 720 assumes that the output data of the first decompressor 500 is D1, the output data of the second decompressor 502 is D2, and the output image data of the composite image IMG3 is D3. Output image data of the composite image IMG3 can be generated on a pixel basis.
D3 = D1 * g + D2 * (1-g)

  Note that a composite image shown in FIG. 5 can be generated by setting a gradation value corresponding to dummy data as a key color and always fixing the transmittance g to “0”.

  In the above embodiment, the first compressor 300 and the first decompressor 500 have been described as performing image data compression processing and decompression processing based on common control data. It is not limited to. In the modification of the present embodiment, an identification code indicating a cut area is embedded on the compression processing side, and the expansion processing side detects the identification code to determine that the area is a cut area, and performs expansion processing. The configuration of the image processing apparatus in this modification is the same as that shown in FIG. 4, and the configuration of the main part of the image processing apparatus in this modification will be described below.

  FIG. 18 is a block diagram showing a detailed configuration example of the image processing apparatus according to this modification. FIG. 18 shows a configuration for realizing the compression processing by the first compressor 800 provided in place of the first compressor 300 of FIG. In FIG. 18, the first host I / F 110 is also illustrated. In FIG. 18, the same parts as those in FIG.

  The image processing apparatus 100a shown in FIG. 18 differs from the image processing apparatus 100 shown in FIG. 8 in that a first compressor 800 is provided instead of the first compressor 300. The first compressor 800 has the function of the first compressor 300 and includes a cut identification code embedding circuit 810. The first compressor 800 stops the compression process when the cut valid signal becomes active, and the cut identification code embedding circuit 810 performs the cut identification code embedding process.

FIGS. 19A and 19B schematically show timing charts of processing examples of the compression processing with the configuration shown in FIG. FIG. 19A shows a timing chart of a processing example of the Q line in the area excluding the rectangular area AR1 in FIG. FIG. 19B shows a timing chart of a processing example of a P line straddling the rectangular area AR1 which is the cut area in FIG. 19A and 19B, parts that are the same as those in FIGS. 10A and 10B are given the same reference numerals, and descriptions thereof are omitted as appropriate.
20A and 20B are explanatory diagrams of the compression processing of FIGS. 19A and 19B. FIG. 20A shows an explanatory diagram of the compression process of the Q line in FIG. FIG. 20B illustrates an explanatory diagram of the compression process of the P line in FIG. 20A and 20B, as in FIGS. 11A and 11B, the number of pixels in the horizontal direction of one scanning line is N, and the pixel value of each pixel is “p”. "Is indicated with a pixel number. The compression process is represented by a function f.

In this modified example, as shown in FIG. 19B, in the P line, when the cut valid signal becomes active for the image data corresponding to the cut area, the cut identification code is embedded (QF1), and the cut valid signal is In the inactive period, the first compressor 800 performs image data compression processing for each region excluding the cut-out area. That is, as shown in FIGS. 19B and 20B, the first pixel PF2 of the P line corresponding to the line head identification signal is output as it is (p ₁ ), and then the (L-1) th (F (p ₂ −p ₁ ),..., F (p _L−1 −p _L−2 )). The image data corresponding to the cut area, cut after embedding an identification code q _L, performs the pixel difference compressed to M-th pixel from the N-th pixel of the pixels of the M is the head pixel PE1 In this case The value is output as it is (p _M ), and then differential compression is performed up to the Nth pixel (f (p _{M + 1} −p _{M + 2} ),..., F (p _N −p _N−1 )). The data size of the compressed image data stored in one memory 410 is reduced. In this modification, after embedding the cut identification code during the period when the cut area valid signal is active, the compression operation of the first compressor 300 is stopped, and during the period when the cut area valid signal is inactive, By performing the compression operation of the compressor 300, the above-described differential compression in units of scanning lines is performed.

  In the first compressor 800 that performs such compression processing, for example, in the configuration shown in FIG. 12, it is only necessary to embed a cut identification code when the cut valid signal becomes active, and thus detailed description thereof is omitted. To do.

  FIG. 21 is a block diagram showing a detailed configuration example of the image processing apparatus 100a according to this modification. FIG. 21 shows a configuration for realizing a decompression process by a first decompressor 850 provided in place of the first decompressor 500 of FIG. In FIG. 21, the synthesis processing circuit 700 is also shown. In FIG. 21, the same parts as those in FIG.

  The image processing apparatus 100a shown in FIG. 21 is different from the image processing apparatus 100 shown in FIG. 13 in that a first expander 850 is provided instead of the first expander 500, and the cut area identification signal generation circuit of FIG. 530 is omitted. The first decompressor 850 has the function of the first decompressor 500 and includes a cut identification code detection circuit 860. When the cut identification code is detected by the cut identification code detection circuit 860, the first decompressor 850 determines a cut area based on the cut identification code, and performs decompression processing on the compressed image data. Therefore, in this modification, only the image H size and the image V size are referred to in the control register 610 on the decompression processing side.

  FIGS. 22A and 22B schematically show timing charts of processing examples of the decompression processing with the configuration shown in FIG. FIG. 22A shows a timing chart of a processing example of the Q line in the area excluding the rectangular area AR1 in FIG. FIG. 22B shows a timing chart of a processing example of a P line straddling the rectangular area AR1 which is the cut area in FIG. 22A and 22B, parts that are the same as those in FIGS. 14A and 14B are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

  In this modification, as shown in FIG. 22B, when a cut identification code is detected in the P line, the image H size and the image V size of the control register 610 are based on the detection timing of the cut identification code. The cut area is determined based on the above. In the area excluding the cut-out area, the first decompressor 850 performs image data decompression processing as in the above-described embodiment. On the other hand, in the cut area, the first decompressor 850 stops reading the image data in the area corresponding to the cut area, adds dummy data, and outputs the decompressed image data to the subsequent circuit. . That is, the first decompressor 850 outputs the leading pixel PF4 of the P line corresponding to the line leading identification signal as it is, and then performs differential decompression to the (L−1) th pixel. When the cut identification code is detected, the first decompressor 850 adds dummy data from the Lth pixel to the (M−1) th pixel for the cut area, and then, in the area excluding the cut area. Differential expansion is performed from the Mth pixel to the Nth pixel. Also at this time, the pixel value of the Mth pixel, which is the first pixel PE2, is output as it is, and thereafter, differential expansion is performed up to the Nth pixel.

  The first decompressor 850 that performs such decompression processing may embed dummy data when a cut identification code is detected, for example, in the configuration shown in FIG.

  As described above, in this modification, when the image data in the cut area is compressed, the cut identification code is inserted on the compression processing side, and the cut identification code is detected on the expansion processing side to perform the expansion processing. As in the present embodiment, the data size of the compressed image data stored in the first memory 410 can be further reduced, so that the image memory 400 can be effectively used. Furthermore, according to this modification, the circuit configuration on the decompression processing side can be simplified.

  The image processing apparatus 100 according to the present embodiment, the image processing apparatus 100a according to the modification thereof, or the image display system including any one of the image processing apparatuses described above can be applied to, for example, the following electronic apparatus. Hereinafter, an example in which the image processing apparatus 100 according to the present embodiment or the image display system 10 including the image processing apparatus 100 is applied will be described. However, the image processing apparatus 100a according to the modification or an image display system including the image processing apparatus 100 can be similarly applied.

  FIG. 23 shows a block diagram of a configuration example of a mobile phone as an electronic apparatus in the present embodiment. In FIG. 23, the same parts as those in FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the image processing apparatus 100.

  In addition, the mobile phone 900 includes the liquid crystal display panel 30. The liquid crystal display panel 30 is driven by a liquid crystal driving circuit 40. The liquid crystal display panel 30 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels. The liquid crystal drive circuit 40 includes a gate driver 42, a source driver 44, and a power supply circuit 46. The gate driver 42 scans a plurality of gate lines of the liquid crystal display panel 30. The source driver 44 drives a plurality of source lines of the liquid crystal display panel 30 based on image data. The power supply circuit 46 generates voltages for the gate driver 42, the source driver 44, and the liquid crystal display panel 30. The power supply circuit 46 is connected to the source driver 44 and the gate driver 42 and supplies a driving power supply voltage to each driver. The power supply circuit 46 supplies the counter electrode voltage Vcom to the counter electrode of the liquid crystal display panel 30.

  The image processing apparatus 100 is connected to the liquid crystal drive circuit 40 and supplies the source driver 44 with RGB format image data that has undergone the above-described composition processing.

  The first host device 210 is connected to the image processing apparatus 100 and supplies image data corresponding to, for example, a background image to the image processing apparatus 100. The second host device 220 is connected to the image processing apparatus 100, supplies image data corresponding to, for example, a content image to the image processing apparatus 100, and controls the image processing apparatus 100. Further, the second host device 220 can demodulate the image data received via the antenna 960 by the modem unit 950 and then supply the image data to the image processing device 100. The image processing apparatus 100 displays the image data on the liquid crystal display panel 30 by the source driver 44 and the gate driver 42 based on the image data. Further, the second host device 220 can instruct transmission to another communication device via the antenna 960 after the image data generated by the camera module 910 is modulated by the modem unit 950. Further, the second host device 220 performs image data transmission / reception processing, imaging of the camera module 910, and display processing of the liquid crystal display panel 30 based on operation information from the operation input unit 970.

  24A and 24B are perspective views showing the configuration of an electronic apparatus to which the image processing apparatus 100 or the image display system 12a according to this embodiment is applied. FIG. 24A is a perspective view of the configuration of the mobile phone in FIG. FIG. 24B illustrates a perspective view of a structure of a mobile personal computer. 24A, the same portions as those in FIG. 23 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  A cellular phone 900 illustrated in FIG. 24A includes a main body portion 980 and a display portion 990. As the display unit 990, the liquid crystal display panel 30 of the image display system 12a in the present embodiment is mounted. The main body unit 980 includes the first host device 210 and the second host device 220 in the image display system 12a. The main body unit 980 is provided with a keyboard as the operation input unit 970. That is, the mobile phone 900 is configured to include at least the image processing apparatus 100 in the above embodiment. The operation information via the keyboard is analyzed by the second host device 220, and an image is displayed on the display unit 990 according to the operation information. According to the present embodiment, since the image memory built in the image processing apparatus 100 can be effectively used, more images and information can be stored, and a more versatile mobile phone can be provided at low cost.

  A personal computer 1000 illustrated in FIG. 24B includes a main body portion 1010 and a display portion 1020. As the display unit 1020, the liquid crystal display panel 30 of the image display system 12a in the present embodiment is mounted. The main body unit 1010 includes a first host device 210 and a second host device 220 in the image display system 12a, and the main body unit 1010 is provided with a keyboard 1030. That is, the personal computer 1000 is configured to include at least the image processing apparatus 100 in the above-described embodiment. The operation information via the keyboard 1030 is analyzed by the second host device 220, and an image is displayed on the display unit 1020 according to the operation information. According to the present embodiment, since the image memory built in the image processing apparatus 100 can be effectively used, more images and information can be stored, and a more versatile personal computer can be provided at low cost.

  24A and 24B are electronic devices to which the image processing apparatus 100 or the image display system 12a (the image processing apparatus in the present modification or an image display system including the same) according to the present embodiment is applied. It is not limited to the ones shown in the table, personal digital assistants (PDA), digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic paper, calculators, word processors, workstations, Examples include videophones, point of sale system (POS) terminals, printers, scanners, copiers, video players, and devices equipped with touch panels.

  As described above, the image processing apparatus, the image display system, the electronic device, the image processing method, and the like according to the present invention have been described based on the above-described embodiment or its modification. However, the present invention is limited to the above-described embodiment or its modification. However, the present invention can be implemented in various modes without departing from the gist of the invention. For example, the following modifications are possible.

  (1) In the above embodiment or its modification, the image processing apparatus that supplies image data to the liquid crystal display device has been described as an example, but the present invention is not limited to this. The image processing apparatus according to the present embodiment may supply image data to a display apparatus such as an organic EL display apparatus or a CRT (Cathode-Ray Tube) or an image projection apparatus.

  (2) In the above embodiment or its modification, the image processing device is provided outside the liquid crystal display device 20, the first host device 210, and the second host device 220. However, the present invention is not limited to this. Is not to be done. The image processing apparatus according to this embodiment or the modification thereof may be incorporated in any one of the liquid crystal display device 20, the first host device 210, and the second host device 220.

  (3) In the above-described embodiment or its modification, the electronic apparatus to which the image processing apparatus 100 or the image processing apparatus 100a is applied has been described as an example, but the present invention is not limited to this. The image display system 10 or the image processing device 50 in FIG. 1 may be applied.

  (4) In the above-described embodiment or its modification, the present invention is not limited to the compression processing performed by the first compressor. The first decompressor only needs to perform decompression processing corresponding to the compression processing performed by the first compressor. Further, the present invention is not limited to the compression processing performed by the second compressor, and compression processing different from that of the first compressor may be performed, or compression processing may be performed using the same algorithm as that of the first compressor. May be performed. The second decompressor only needs to perform decompression processing corresponding to the compression processing performed by the second compressor.

  (5) Although the present invention has been described as an image processing apparatus, an image display system, an electronic device, an image processing method, and the like in the above-described embodiment or its modification, the present invention is not limited to this. For example, it may be a program in which the processing procedure of the image processing method is described, or a recording medium on which the program is recorded.

DESCRIPTION OF SYMBOLS 10,12 ... Image display system 20 ... Liquid crystal display device 30 ... Liquid crystal display panel,
40 ... Liquid crystal drive circuit, 50, 100, 100a ... Image processing device,
110: First host I / F, 120: LCD I / F, 200: Host device,
210 ... first host device, 220 ... second host device,
300, 800 ... first compressor, 302 ... second compressor,
310, 510 ... H counter, 320, 520 ... V counter,
330, 530: Cut area identification signal generation circuit, 340: Memory write circuit,
400 ... Image memory 410 ... First memory 412 ... Second memory,
500,850 ... first stretcher, 502 ... second stretcher,
540 ... Memory read circuit 600,610 ... Control register,
700 ... Synthetic processing circuit, 810 ... Cut identification code embedding circuit,
860 ... cut-off identification code detection circuit, 900 ... mobile phone,
910 ... Camera module, 950 ... Modem, 960 ... Antenna,
970 ... operation input unit, 980, 1010 ... main body unit, 990, 1020 ... display unit,
1000 ... Personal computer, 1030 ... Keyboard

Claims (15)

An image processing device for supplying image data to an image display device,
A first compressor for compressing image data in an area excluding a given area in the image area;
A first memory for storing image data compressed by the first compressor;
A first decompressor that is stored in the first memory and decompresses image data in a region excluding a given region in the image region;
An image processing apparatus, characterized in that the image data expanded by the first expander is supplied to the image display apparatus. In claim 1,
The first compressor includes:
The image data of the area excluding a given rectangular area in the image area is compressed in units of scanning lines,
The first stretcher is
An image processing apparatus, wherein image data in an area excluding the rectangular area is expanded in units of the scanning lines. In claim 1 or 2,
A control register in which control data designating a rectangular area in the horizontal direction and the vertical direction of the image is set;
The first compressor includes:
Compressing the image data of the area excluding the rectangular area designated based on the control data;
The first stretcher is
An image processing apparatus that decompresses image data in an area excluding the rectangular area designated based on the control data common to the first compressor. In claim 3,
The first compressor includes:
For the image data of the scanning line in the rectangular area, stop the compression operation of the image data,
The first stretcher is
An image processing apparatus, wherein reading of image data from the first memory is stopped and given dummy data is added to image data of a scanning line in the rectangular area. In claim 1 or 2,
A control register in which control data specifying a horizontal size and a vertical size of a given rectangular area in the image area are set;
The first compressor includes:
An identification code embedding circuit that embeds an identification code for the image data in the rectangular area designated based on the control data when the image data is compressed in units of scanning lines, and based on the control data; Embedded in the image data in the specified rectangular area, and the compression operation of the image data is stopped,
The first stretcher is
The rectangular area specified on the basis of the control data on the condition that the identification code is detected when the image data is expanded in a scanning line unit, including an identification code detection circuit for detecting the identification code An image processing apparatus, wherein reading of image data from the first memory is stopped in correspondence with image data in the image data, and given dummy data is added. In any one of Claims 1 thru | or 5,
A second compressor for compressing the image data;
A second memory for storing the image data compressed by the second compressor;
A second decompressor for decompressing the image data stored in the second memory;
An image processing apparatus comprising: an overlay processing circuit that performs overlay processing of image data decompressed by the first decompressor and image data decompressed by the second decompressor. An image processing apparatus according to any one of claims 1 to 5,
A host device that outputs image data to the image processing device;
An image display system comprising: an image display device that displays an image based on image data supplied by the image processing device. An image processing apparatus according to claim 6;
A first host device that outputs image data compressed by the first compressor to the image processing device;
A second host device that outputs image data compressed by the second compressor to the image processing device;
An image display system comprising: an image display device that displays an image based on image data supplied by the image processing device.   An electronic apparatus comprising the image processing apparatus according to claim 1.   An electronic device comprising the image display system according to claim 7 or 8. An image processing method for supplying image data to an image display device,
A first compression step of compressing image data in a region excluding a given region in the image region, and storing the compressed image data in a first memory;
A first decompression step stored in the first memory and decompressing image data of an area excluding a given area in the image area,
An image processing method comprising: supplying the image data after decompression in the first decompression step to the image display device. In claim 11,
The first compression step includes
The image data of the area excluding a given rectangular area in the image area is compressed in units of scanning lines,
The first stretching step includes:
An image processing method characterized in that image data in an area excluding the rectangular area is expanded in units of the scanning lines. In claim 11 or 12,
The first compression step includes
Stops the compression operation of the image data with respect to the image data of the scanning line in the rectangular area designated in the horizontal direction and the vertical direction of the image,
The first stretching step includes:
An image processing method comprising: stopping reading of image data from the first memory and adding given dummy data to image data of scanning lines in the rectangular area. In claim 11 or 12,
The first compression step includes
An identification code embedding step of embedding an identification code for image data in a given rectangular area in the image area when the image data is compressed in units of scanning lines, and the image data in the rectangular area; Embedded with the identification code, and stopped the compression operation of the image data,
The first stretching step includes:
An identification code detecting step for detecting the identification code, and when the image data is expanded in units of scanning lines, on the condition that the identification code is detected, corresponding to the image data in the rectangular area, An image processing method, wherein reading of image data from the first memory is stopped and given dummy data is added. In any one of Claims 11 thru | or 14.
A second compression step of compressing the image data and storing it in a second memory;
A second expansion step of expanding the image data stored in the second memory;
An image processing method comprising: an overlay processing step for performing overlay processing of the image data decompressed in the first decompression step and the image data decompressed in the second decompression step.

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