JP2011077457A - Solid-state imaging element, method of manufacturing the same, and imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element that improves the efficiency of light condensing on a semiconductor region functioning as a photoelectric conversion portion by reducing a thickness of an interlayer insulating film on the photoelectric conversion portion of the pixel by an easy method, a method of manufacturing the same, and an imaging device. <P>SOLUTION: In the solid-state imaging element, a part of a conductive pattern formed of the same layer with a gate electrode pattern is disposed on an element isolation film, a thickness of the part of the conductive pattern disposed on the element isolation film is made smaller than a thickness of a gate electrode layer disposed on the gate insulating film to maintain the thickness of the interlayer insulating film at a film thickness for suppressing parasitic capacitance, thereby reducing the thickness of the interlayer insulating film on the photoelectric conversion portion of the pixel. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a manufacturing method thereof, and an imaging apparatus.

  In recent years, solid-state imaging devices such as CCD image sensors and CMOS sensors are used in imaging devices such as two-dimensional image input devices or one-dimensional image reading devices. As the two-dimensional image input device, for example, there is an image input device centering on a digital still camera and a video camcorder. On the other hand, examples of the one-dimensional image reading apparatus include an image reading apparatus mainly including a facsimile and a scanner. In particular, CMOS solid-state imaging devices are rapidly spreading as imaging devices that achieve both high image quality and high-speed output. In this CMOS type solid-state imaging device, a photodiode for performing photoelectric conversion and a CMOS circuit for reading a signal from the photodiode are integrated in one semiconductor device. The transistors used in this CMOS circuit are the same as the NMOS and PMOS used in ordinary CMOS circuits. The CMOS type solid-state imaging device is manufactured by a process flow in which a process for forming a photoelectric conversion unit is added to a normal CMOS process.

  In the process of the CMOS type solid-state imaging device, a LOCOS (Local Oxdation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like is used as an element isolation technique. In any method, the polysilicon film constituting the control electrode of the MOS transistor has a structure that continuously covers the gate insulating film and the element isolation oxide film of the MOS transistor. For example, Patent Document 1 shows a configuration in which a gate electrode layer is disposed across a gate insulating layer and an element isolation insulating layer in a solid-state imaging device. In Patent Document 2, in a solid-state imaging device, a vertical selection line made of a polysilicon gate wiring and a reset line made of a polysilicon gate wiring are arranged on the selective oxidation element isolation region. An example in which a gate electrode portion made of polysilicon gate wiring is arranged on a gate insulating film is shown.

JP 2000-353801 A Japanese Patent Laid-Open No. 11-307752

  However, the pixel pitch is reduced as the resolution of the solid-state imaging device increases. On the other hand, when a lens with the same numerical aperture is mounted in the imaging apparatus, it is necessary to reduce the height dimension of the pixels of the solid-state imaging device so that the sensitivity does not deteriorate even if the pixel pitch is reduced. The method of reducing the pixel height of a solid-state imaging device is generally called “reducing the height”, and various proposals such as reducing the number of wiring layers on the pixel and reducing the thickness of the interlayer insulating film have been made. Yes. However, as the pixel pitch of the solid-state image sensor is reduced, the conventional “low profile” technique is reaching the limit of height reduction. Therefore, it is necessary to reduce the height at a lower cost by combining various methods.

  In a conventional CMOS solid-state imaging device, when forming a conductive layer that spans between the element isolation insulating film and the gate insulating film, the upper surface of the element isolation insulating film is far from the upper surface of the gate insulating film as measured from the silicon substrate. It is in. Therefore, when the height of the structure stacked on the pixel is reduced, the height of the upper surface of the conductive layer on the element isolation insulating film limits the reduction in the height of the solid-state imaging device. An interlayer insulating film is further laminated on the upper surface of the conductive layer on the element isolation insulating film. In order to suppress the parasitic capacitance between the conductive layer on the element isolation insulating film and the wiring in the upper layer of the interlayer insulating film, The interlayer insulating film on the conductive layer must have a certain thickness. Accordingly, the height of the upper surface of the conductive film on the element isolation insulating film on the pixel and the lower limit value of the film thickness of the interlayer insulating film on the conductive layer define the lower limit of the height of the solid-state imaging device.

  The present invention relates to a solid-state imaging device that improves the light collection efficiency to a semiconductor region functioning as a photoelectric conversion unit by reducing the thickness of an interlayer insulating film on the photoelectric conversion unit of a pixel by a simple method, and its manufacture A method and an imaging device are provided.

  In view of the above problems, a solid-state imaging device according to the present invention includes a plurality of photoelectric conversion units formed on a semiconductor substrate, a plurality of gate insulating films formed on each of the plurality of photoelectric conversion units, A conductive pattern having a plurality of element isolation films surrounding each of the plurality of photoelectric conversion portions and a gate electrode pattern formed on the plurality of gate insulating films, and disposed in the same layer as the gate electrode pattern. In a solid-state imaging device in which a portion is disposed on the element isolation film, a thickness of a portion of the conductive pattern disposed on the element isolation film is disposed on the gate insulating film. The gate electrode pattern is thinner than the thickness of the gate electrode pattern.

  According to the present invention, the light collection efficiency to the semiconductor region functioning as the photoelectric conversion unit is improved by reducing the thickness of the interlayer insulating film on the photoelectric conversion unit of the pixel in the solid-state imaging device by a simple method. can do.

(A) is a figure which shows the circuit structural example of the pixel P in the solid-state image sensor which concerns on a present Example, (b) is a block diagram which shows the structural example of the imaging device to which the solid-state image sensor which concerns on a present Example is applied. is there. (A) is sectional drawing which shows the structural example of the solid-state image sensor which concerns on Example 1, (b) is sectional drawing which shows the structural example of the conventional solid-state image sensor. 6 is a cross-sectional view showing a characteristic process of a method for manufacturing a solid-state imaging device according to Example 1. FIG. 6 is a cross-sectional view illustrating a configuration example of a solid-state imaging element according to Embodiment 2. FIG. 6 is a cross-sectional view illustrating a characteristic process of a method for manufacturing a solid-state imaging device according to Example 2. FIG. 6 is a cross-sectional view illustrating a configuration example of a solid-state imaging element according to Embodiment 3. FIG. 6 is a cross-sectional view showing a characteristic process of a method for manufacturing a solid-state imaging device according to Example 3. FIG.

  <Circuit Configuration Example of Solid-State Imaging Device According to This Embodiment> FIG. 1A is a diagram illustrating a circuit configuration example of the pixel P of the solid-state imaging device 100, 200, 300 according to this embodiment. In an actual solid-state imaging device, pixels P are arranged in a two-dimensional or one-dimensional array, and a scanning circuit, a readout circuit, an output amplifier circuit, and the like that drive the pixels are arranged on the outer periphery of the array. 1A, the pixel P includes a photoelectric conversion unit 31, a transfer transistor 32, a floating diffusion (hereinafter referred to as FD) 33, a reset transistor 34, an amplification transistor 36, and a selection transistor 35.

  When light enters the light receiving surface, the photoelectric conversion unit 31 generates and accumulates charges (electrons here) corresponding to the light. The photoelectric conversion unit 31 is, for example, a photodiode, and accumulates charges generated by performing photoelectric conversion at the interface between the anode and the cathode on the cathode. The transfer transistor 32 transfers the charge generated in the photoelectric conversion unit 31 to the FD 33 when the channel is turned on (hereinafter referred to as turning on the transistor and turning it off). Forward. The FD 33 converts the transferred charge into a voltage. The reset transistor 34 resets the FD 33 when turned on. The amplification transistor 36 outputs a signal corresponding to the voltage of the FD 33 to the vertical signal line 37 by performing a source follower operation together with the constant current source 38 connected to the vertical signal line 37. The vertical signal line 37 is connected to other pixels in the column direction and is shared by a plurality of pixels. That is, the amplification transistor 36 outputs a noise signal corresponding to the voltage of the FD 33 to the vertical signal line 37 in a state where the FD 33 is reset by the reset transistor 34. The amplification transistor 36 outputs an optical signal corresponding to the voltage of the FD 33 to the vertical signal line 37 in a state where the charge generated in the photoelectric conversion unit 31 is transferred to the FD 33 by the transfer transistor 32. The selection transistor 35 brings the pixel P into a selected state when turned on, and puts the pixel P into a non-selected state when turned off. Note that when the selection state / non-selection state of the pixel P is controlled by the potential of the FD 33, the selection transistor 35 may be omitted from the pixel P, and a structure having a plurality of photoelectric conversion units 31 for one amplification transistor 36. But you can. Although not shown in detail, for example, the signals of a plurality of pixels in the column direction of the vertical signal line 37 are combined with the other vertical signal lines 37 in the row direction as two-dimensional imaging results. A three-dimensional imaging result is output as an output signal from the solid-state imaging device.

  <Configuration Example of Imaging Device of This Embodiment> FIG. 1B is an example of an imaging device to which the solid-state imaging device 100, 200, 300 of this embodiment is applied. Hereinafter, the solid-state imaging device 100 according to the first embodiment will be described as a representative, but the same applies to the solid-state imaging devices 200 and 300. The imaging device 90 mainly includes an optical system, an imaging unit 86, and a signal processing unit. The optical system mainly includes a shutter 91, a lens 92, and a diaphragm 93. The imaging unit 86 includes the solid-state imaging device 100 of the present embodiment. The signal processing unit mainly includes an imaging signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording. A medium 88 and a recording medium control I / F unit 94 are provided. The signal processing unit may not include the recording medium 88.

  The shutter 91 is provided in front of the lens 92 on the optical path, and controls exposure. The lens 92 refracts the incident light and forms an image of the subject on the imaging surface of the solid-state imaging device 100 of the imaging unit 86. The diaphragm 93 is provided between the lens 92 and the solid-state image sensor 100 on the optical path, and adjusts the amount of light guided to the solid-state image sensor 100 after passing through the lens 92.

  The solid-state imaging device 100 of the imaging unit 86 converts an image of a subject formed on the imaging surface of the solid-state imaging device 100 into an image signal. The imaging unit 86 reads out the image signal from the solid-state imaging device 100 and outputs it. The imaging signal processing circuit 95 is connected to the imaging unit 86 and processes the image signal output from the imaging unit 86. The A / D converter 96 is connected to the imaging signal processing circuit 95 and converts the processed image signal (analog signal) output from the imaging signal processing circuit 95 into an image signal (digital signal). The image signal processing unit 97 is connected to the A / D converter 96, and performs various kinds of arithmetic processing such as correction on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. The image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like. The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97. The external I / F unit 89 is connected to the image signal processing unit 97. Thus, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89.

  The timing generator 98 is connected to the imaging unit 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. Thereby, a timing signal is supplied to the imaging unit 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. The imaging unit 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal. The overall control / arithmetic unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F. The unit 94 is controlled as a whole. The recording medium 88 is detachably connected to the recording medium control I / F unit 94. As a result, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94.

  With the above configuration, if a good image signal is obtained in the solid-state imaging device 100, 200, 300 of the present embodiment, a good image (image data) can be obtained in the imaging device.

[Example 1]
<Example of Cross-Sectional Configuration of Pixel of Example 1> FIG. 2A is a cross-sectional view showing a configuration example of a solid-state imaging device of a portion of one pixel having the circuit configuration of FIG. Specifically, it is a cross-sectional view of the photoelectric conversion unit 31 and the reset transistor 34 in FIG. In FIG. 2A, electrodes and wirings connecting the MOS transistors are omitted. The solid-state imaging device 100 includes a semiconductor substrate SB, a first gate electrode 8, a second gate electrode 9-1, a third gate electrode 15-1, an interlayer insulating film 10, a wiring layer 14, and a contact plug 13.

  The semiconductor substrate SB includes a P well 1, an element isolation part (element isolation film) 2, a second semiconductor region 3, and a first semiconductor region 6. The P well 1 contains P-type impurities at a relatively low concentration. The element isolation unit 2 performs element isolation. The element isolation method includes a LOCOS method, a mesa type method, an STI method, etc., and any of the isolation methods is consistent with the gist of the present invention. The element isolation part 2 is made of, for example, silicon oxide. The first semiconductor region 6 functions as a photoelectric conversion unit 31 (see FIG. 1A) and is a region for accumulating charges generated by photoelectric conversion. The first semiconductor region 6 contains N-type impurities at a concentration higher than the concentration of P-type impurities in the P well 1. The second semiconductor region 3 functions as a source electrode or a drain electrode (for example, FD33 which is the drain electrode of the transfer transistor 32 shown in FIG. 1A). Second semiconductor region 3 contains N-type impurities at a concentration higher than the concentration of P-type impurities in P well 1. The third semiconductor region 5 is a region for protecting the first semiconductor region 6 and making the photoelectric conversion unit 31 (photodiode) have a buried structure. Third semiconductor region 5 contains P-type impurities at a higher concentration than P well 1.

  The first gate electrode 8 is disposed on the semiconductor substrate SB via the gate insulating film 7. The second gate electrode 9-1 of the first embodiment is disposed on the element isolation unit 2. The third gate electrode 15-1 of the first embodiment is disposed so as to run on the element isolation portion 2 from the gate insulating film 17. The interlayer insulating film 10 is disposed so as to cover the surface SBa of the semiconductor substrate SB, the first gate electrode 8, the second gate electrode 9-1, the third gate electrode 15-1, and the contact plug 13. . The interlayer insulating film 10 insulates the surface SBa of the semiconductor substrate SB from the wiring layer 14. The interlayer insulating film 12 is disposed so as to be in contact with the first gate electrode 8, the second gate electrode 9-1, the third gate electrode 15-1, and the interlayer insulating film 10. The interlayer insulating film 12 insulates the wiring layer 14 from the first gate electrode 8, the second gate electrode 9-1, and the third gate electrode 15-1. The wiring layer 14 is disposed on the interlayer insulating film 12. That is, the wiring layer 14 is an opening region with respect to the first semiconductor region 6 (photoelectric conversion unit 31) above the first gate electrode 8, the second gate electrode 9-1, and the third gate electrode 15-1. It is arranged to define OA. Here, the opening area OA may be defined by a wiring layer other than the wiring layer 14. The contact plug 13 is formed by arranging a conductor in a contact hole penetrating the interlayer insulating film 10 and the interlayer insulating film 12 so as to electrically connect the second semiconductor region 3 and the wiring layer 14. In the present specification, the first gate electrode 8 formed on the gate insulating film 7 is a gate electrode pattern, and the second and third gates are formed entirely and partially on the element isolation portion 2. The electrodes 9 and 15 are also referred to as a conductive pattern.

  Here, the height from the bottom surface to the top surface of the second gate electrode 9-1 is lower than the height from the bottom surface to the top surface of the first gate electrode 8. Of the third gate electrode 15-1, the height from the bottom surface to the top surface of the portion disposed on the element isolation portion is lower than the height from the bottom surface to the top surface of the first gate electrode 8. Thereby, the height from the surface SBa of the semiconductor substrate SB of the wiring layer 14 that defines the opening region OA with respect to the first semiconductor region 6 (the photoelectric conversion unit 31) can be suppressed. As a result, the light collection efficiency to the semiconductor region functioning as the photoelectric conversion unit can be improved. For comparison between Example 1 and the prior art, FIG. 2B shows a cross-sectional view corresponding to FIG. 2A of the solid-state imaging device 100 ′ manufactured according to the prior art. In FIG. 2B, since the film thicknesses of the first gate electrode 8, the second gate electrode 9, and the third gate electrode 15 remain the same, the second gate electrode 9 and the third gate electrode are the same. The upper surface of the upper portion of the element isolation portion 2 of the electrode 15 becomes the lower surface of the interlayer insulating film 12 having a lower limit film thickness. Therefore, there is a limit to suppressing the height from the surface SBa of the semiconductor substrate SB of the wiring layer 14 that defines the opening region OA with respect to the first semiconductor region 6 (photoelectric conversion unit 31).

<Example of Manufacturing Process of Solid-State Image Sensor of Example 1> (a1) to (d1) of FIG. 3 are diagrams for explaining a method of manufacturing the solid-state image sensor 100 of FIG. 2 (a). In the illustrated process, first, a P well 1 and an N well (not shown) and an element isolation portion 2 are formed in a semiconductor substrate SB such as silicon. The element isolation portion 2 is formed by STI, selective oxidation, or the like. Next, gate insulating films 7 and 17 are formed on the semiconductor substrate SB by a thermal oxidation method or a CVD method. By forming and patterning a polysilicon layer to be a gate electrode on the gate insulating films 7 and 17 on the semiconductor substrate SB, the first gate electrode 8, the second gate electrode 9, and the third gate electrode are formed. A gate electrode 15 is formed. By injecting an n-type impurity into the semiconductor substrate SB, the first semiconductor region 6 that functions as the photoelectric conversion unit 31 is formed in the semiconductor substrate SB (in the semiconductor substrate) with a high concentration. In addition, by implanting p-type impurities into the semiconductor substrate SB, the third semiconductor region 5 for protecting the first semiconductor region 6 is formed in the vicinity of the surface SBa of the semiconductor substrate SB at a high concentration. The order of forming the gate electrode and the semiconductor region can be selected as appropriate. Then, by implanting an n-type impurity into the semiconductor substrate SB using the resist pattern and the gate electrode as a mask, the source and drain regions of the transistor such as the semiconductor region to be the semiconductor region 3 are highly concentrated in the vicinity of the surface SBa of the semiconductor substrate SB. Form with. The source and drain regions are regions that are self-aligned with the first gate electrode 8, the second gate electrode 9, the third gate electrode 15, and the like.

  In the step shown in FIG. 3B1, the insulating film 10i is deposited so as to cover the surface SBa of the semiconductor substrate SB and the first gate electrode 8, the second gate electrode 9, and the third gate electrode 15. . In the step shown in FIG. 3C1, planarization is performed by polishing the surface of the insulating film 10i deposited in FIG. 3B1. Thereby, a first interlayer insulating film 10 (first insulating film) is formed. At this time, polishing is performed until the upper surface of the first gate electrode 8 is exposed. For this reason, the second gate electrode 9 and a part of the third gate electrode 15 formed on the element isolation part 2 have a height corresponding to the height protruding from the semiconductor substrate SB of the element isolation part 2. It becomes thinner than the film thickness of the gate electrode 8. The thinned gate electrode after the polishing is indicated by a second gate electrode 9-1 and a third gate electrode 15-1. In the step shown in FIG. 3D1, the interlayer insulating film 10 and the exposed surfaces of the first gate electrode 8, the second gate electrode 9-1, and the third gate electrode 15-1 are covered. An insulating film 12i is deposited.

  Thereafter, as shown in FIG. 2A, the interlayer insulating film 10 and the insulating film 12i are penetrated so as to expose the upper surface of the second semiconductor region 3 and the upper surface (not shown) of the gate electrode. A contact hole is formed. Then, a conductive material is deposited in the contact hole and on the surface of the insulating film 12i, and then the insulating film 12i and the conductive material are polished. Specifically, the second interlayer insulating film 12 and the contact plug 13 are formed by polishing the surface conductive material and the surface of the underlying insulating film 12i. Next, a wiring layer 14 is formed on the second interlayer insulating film 12 so as to define an opening region OA for the first semiconductor region 3.

  As described above, the height from the bottom surface to the top surface of the portions of the second gate electrode 9-1 and the third gate electrode 15-1 that are in contact with the upper surface of the element isolation region is the gate insulating film of the first gate electrode 8. 7 Lower than the height from the bottom surface to the top surface of the portion in contact with the top surface. Accordingly, a sufficient distance can be secured between the upper surfaces of the second gate electrode 9-1 and the third gate electrode 15-1 and the wiring layer. Therefore, even when the height of the wiring layer is lowered, an increase in parasitic capacitance between the second gate electrode 9-1 and the third gate electrode 15-1 and the wiring layer 14 can be suppressed.

  <Effect of Embodiment 1> According to this embodiment, in a solid-state imaging device having a gate electrode in contact with the upper surface of the gate insulating film 7 and a gate electrode in contact with the upper surface of the element isolation portion, the light collection efficiency can be increased for the following reasons. it can. That is, the height from the bottom surface to the top surface of the portion of the second gate electrode 9-1 and the third gate electrode 15-1 that is in contact with the upper surface of the element isolation portion is the gate insulating film 7 of the first gate electrode 8. It becomes lower than the height from the bottom surface to the top surface of the portion in contact with the top surface. As a result, the height from the surface SBa of the semiconductor substrate SB to the upper surface of the gate electrode disposed on the element isolation portion can be reduced. As a result, since the height from the semiconductor substrate to the wiring layer can also be reduced, the light collection efficiency of the light passing through the opening region defined by the wiring layer to the first semiconductor region is increased.

[Example 2]
<Configuration Example of Solid-State Image Sensor of Example 2> FIG. 4 is a cross-sectional view illustrating a configuration example of a pixel of a solid-state image sensor 200 according to Example 2. Below, it demonstrates centering on a different part from Example 1. FIG. In FIG. 4, the solid-state imaging element 200 is disposed on the upper surface of the second gate electrode 9-2 located on the element isolation unit 2 and on the element isolation unit 2 of the third gate electrode 15-3. A thermal oxide film 11 in contact with the upper surface of the portion is provided. The upper surface of the second gate electrode 9-2 located on the element isolation portion 23 and the upper surface of the portion disposed on the element isolation portion 2 of the third gate electrode 15-2 and the wiring layer 14 are heated. It is insulated by the oxide film 11. On the other hand, the portion of the semiconductor substrate SB and the first gate electrode 8 that are in contact with the gate insulating film 7 and the wiring layer 14 are insulated by the interlayer insulating film 10. In FIG. 4, the height from the bottom surface to the top surface of the portion of the second gate electrode 9-2 and the third gate electrode 15-2 that contacts the upper surface of the element isolation region is the gate insulating film of the first gate electrode 8. 7 Lower than the height from the bottom surface to the top surface of the portion in contact with the top surface. As a result, the height from the surface SBa of the semiconductor substrate SB of the wiring layer 14 that defines the opening region OA to the first semiconductor region 6 (photoelectric conversion unit 31) can be kept low. It is the same.

  <Example of Manufacturing Process of Solid-State Image Sensor of Example 2> FIG. 5 is a cross-sectional view showing a characteristic process of the method of manufacturing the solid-state image sensor 200 of FIG. In the second embodiment, the steps up to FIGS. 3A1 and 3B1 in the first embodiment are the same. The subsequent steps after that are different from those of the first embodiment.

  In the step shown in FIG. 5C2, the insulating film 10i deposited in FIG. 3B1 is formed at the highest position on the upper surface of the gate electrode, that is, the second gate electrode 9 and the third gate electrode 15. Polishing is performed until the upper surface of the portion riding on the element isolation portion 2 is exposed. Note that polishing may be performed using the gate electrode as a stopper layer by utilizing the difference in polishing rate between the insulating film 10i and the gate electrode. In the step shown in FIG. 5D2, the thermal oxide film 11 is formed by oxidizing the exposed surface layer of the gate electrode. That is, the surface layer of the second gate electrode 9 and the portion of the third gate electrode 15 that rides on the element isolation portion 2 is oxidized to form the thermal oxide film 11. As a result, the portions of the second gate electrode 9 and the third gate electrode 15 that run over the element isolation portion 2 are thin. The formation of the thermal oxide film 11 by such oxidation is adjusted so that the lower surface of the thermal oxide film 11 is substantially the same as the upper surface of the first gate electrode 8. The oxidized gate electrode is represented by a second gate electrode 9-2 and a third gate electrode 15-2. In the step shown in FIG. 5E 2, the insulating film 12 i is formed so as to cover the insulating film 10 and the thermal oxide film 11. In the step shown in FIG. 5F2, the insulating film 12i and the thermal oxide film 11 are polished to expose the insulating film 10. If necessary, the interlayer insulating film 12 may be left. For example, when the thickness of the insulating film 10 on the first gate electrode 8 or the thickness of the thermal oxide film 11 is such a thickness that the parasitic capacitance between each gate electrode and the wiring layer 14 cannot be sufficiently suppressed. Is adjusted to leave the interlayer insulating film 12.

  The state of FIG. 5 (f2) in the second embodiment corresponds to the state of FIG. 3 (d1) of the first embodiment. Therefore, the subsequent steps are the same as those in the first embodiment. That is, a contact hole is formed in the insulating film 10 so as to expose the upper surface of the second semiconductor region 3 and the upper surface (not shown) of the gate electrode disposed on the element isolation portion 2. A conductive material is deposited in the contact hole and on the surface of the insulating film 10. The conductive material and the insulating film 10 are polished. A wiring layer 14 is formed on the interlayer insulating film 10 so as to define an opening region OA for the first semiconductor region 3.

  <Modification of Manufacturing Process of Example 2> In the step shown in FIG. 5D2, the exposed surface layer of the gate electrode may be removed before oxidizing the exposed surface layer of the gate electrode. For removing the surface layer of the gate electrode, wet etching may be used or dry etching may be used by utilizing the difference in etch rate between the interlayer insulating film 10 and the gate electrode. In that case, by adjusting the removal amount of the gate electrode surface layer and the subsequent oxidation amount of the gate electrode surface layer, the upper surface of the thermal oxide film 11 and the upper surface of the insulating film 10 are formed on a continuous surface, Subsequent planarization of the interlayer insulating layer can be omitted.

[Example 3]
<Example of Cross-Sectional Configuration of Pixel of First Embodiment> FIG. 6 is a cross-sectional view illustrating an example of a pixel configuration of a solid-state imaging device 300 according to the third embodiment. Below, it demonstrates centering on a different part from Example 2. FIG. The solid-state imaging device 300 in FIG. 6 includes a top surface of the second gate electrode 9-3 positioned on the element isolation unit 2 and a portion of the third gate electrode 15-3 disposed on the element isolation unit 2. The second embodiment is different from the second embodiment in that the film in contact with the upper surface is the insulating film 16 formed by the CVD method or the like.

  <Example of Manufacturing Process of Solid-State Image Sensor of Example 3> FIG. 7 is a cross-sectional view showing a characteristic process of the method of manufacturing the solid-state image sensor 300 of FIG. In Example 3, the processes up to FIGS. 3A1 and 3B1 in Example 1 and FIG. 5C2 in Example 2 are the same. The next process after that is different from the second embodiment.

  In the step shown in FIG. 7D3, the exposed surface layers of the second and third gate electrodes 9 and 15 are removed. For removing the surface layer of the gate electrode, wet etching may be used or dry etching may be used by utilizing a difference in etching rate between the insulating film 10 and the gate electrode. This result is represented by the second gate electrode 9-3 and the third gate electrode 15-3 in FIG. 7 (d3). In the step shown in FIG. 7E3, the insulating film 16i is formed by CVD or the like so as to cover the interlayer insulating film 10 and the exposed gate electrode surface. At this time, the insulating film 16i is formed so as to bury a groove generated by removing the gate electrode surface layer on the second gate electrode 9-3 and the third gate electrode 15-3. In the step shown in FIG. 8F3, the insulating film 16i is polished so that the insulating film 10 is exposed. The insulating film 16 is left on the second gate electrode 9-3 and the third gate electrode 15-3. If necessary, the interlayer insulating film 12 may be left. For example, when the thickness of the insulating film 10 on the first gate electrode 8 or the thickness of the insulating film 16 is such a thickness that the parasitic capacitance between each gate electrode and the wiring layer 14 cannot be sufficiently suppressed. The interlayer insulating film 12 is adjusted.

  [Other Embodiments] In the above description, an example using an nMOS transistor has been described. However, when a solid-state imaging device is manufactured by a CMOS process, a pMOS transistor can be similarly manufactured by changing the conductivity type. it can.

  DESCRIPTION OF SYMBOLS 1 P well, 2 Element isolation part, 3 2nd semiconductor region, 5 3rd semiconductor region, 6 1st semiconductor region, 7 Gate insulating film, 8 1st gate electrode, 9, 9 '2nd gate Electrode 10, 11 Interlayer insulating film, 12, 16 Insulating film, 13 Contact plug, 14 Wiring layer, 15, 15 'Third gate electrode, 17 Gate insulating film, 31 Photoelectric converter, 32 Transfer transistor, 33 Floating diffusion (FD), 34 reset transistor, 35 selection transistor, 36 amplification transistor, 37 vertical signal line, 38 constant current source, 39 readout circuit 39, 100, 200, 300 solid-state imaging device

Claims (7)

A plurality of photoelectric conversion units formed on a semiconductor substrate, a plurality of gate insulating films formed on each of the plurality of photoelectric conversion units, and a plurality of element isolation films respectively surrounding the plurality of photoelectric conversion units And a part of the conductive pattern disposed on the same layer as the gate electrode pattern is disposed on the element isolation film. In solid-state image sensor,
A solid-state imaging device, wherein a thickness of a portion of the conductive pattern disposed on the element isolation film is thinner than a thickness of the gate electrode pattern disposed on the gate insulating film.   A continuous surface is formed by the upper surface of the conductive pattern disposed on the element isolation film and the upper surface of the gate electrode pattern disposed on the gate insulating film. The solid-state imaging device according to claim 1. A wiring layer formed on the gate electrode pattern and the conductive pattern via an interlayer insulating film;
The insulating film different from the thermal oxide film or the interlayer insulating film is formed between the upper surface of the conductive pattern disposed on the element isolation film and the wiring layer. 2. A solid-state imaging device according to 2. A solid-state imaging device according to any one of claims 1 to 3,
An optical system that forms an image on the imaging surface of the solid-state imaging device;
An image pickup apparatus comprising: a signal processing unit that processes a signal obtained by the solid-state image pickup device. Forming an element isolation film on a semiconductor substrate;
Forming a gate insulating film on the semiconductor substrate;
Forming a conductive pattern in contact with the gate insulating film and the element isolation film;
Forming an interlayer insulating film between the conductive pattern and the wiring layer;
In a method for manufacturing a solid-state imaging device having:
The step of forming the interlayer insulating film includes:
Forming a first interlayer insulating film on a semiconductor substrate including the conductive pattern;
Polishing the first interlayer insulating film and an upper portion of the conductive pattern in contact with the element isolation film until the conductive pattern in contact with the gate insulating film is exposed;
And a step of forming a second interlayer insulating film on the polished conductive pattern in contact with the first interlayer insulating film and the element isolation film. Forming an element isolation film on a semiconductor substrate;
Forming a gate insulating film on the semiconductor substrate;
Forming a conductive pattern in contact with the gate insulating film and the element isolation film;
Forming an interlayer insulating film between the conductive pattern and the wiring layer;
In a method for manufacturing a solid-state imaging device having:
The step of forming the interlayer insulating film includes:
Forming a first interlayer insulating film on a semiconductor substrate including the conductive pattern;
Polishing the first interlayer insulating film until a conductive pattern in contact with the element isolation film is exposed;
Changing the surface layer of the conductive pattern in contact with the element isolation film to an insulating film;
And a step of forming a second interlayer insulating film on the polished insulating film on the surface layer of the conductive pattern in contact with the first interlayer insulating film and the element isolation film. Production method.   The step of changing to the insulating film on the surface of the conductive pattern in contact with the element isolation film includes a step of oxidizing the surface layer of the conductive pattern in contact with the element isolation film, or etching the surface layer of the conductive pattern in contact with the element isolation film. 7. The method of forming a groove on the conductive pattern in contact with the element isolation film and filling the groove formed on the conductive pattern in contact with the element isolation film with an insulating film. The manufacturing method of the solid-state image sensor as described in 1 ..

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