JP2011075929A - Display panel and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress degradation of image quality of an image, when the image is displayed by using a plurality of regions. <P>SOLUTION: A boundary display region BR.1 is arranged between a display region DR.1 where a plurality of light-emitting pixels PX are arranged and a display region DR.2 where the plurality of light-emitting pixels PX are arranged. In the boundary display region BR.1, the plurality of light-emitting pixels PX arranged on one and the same row include: the light-emitting pixel PX to which a power supply voltage is applied by a power supply drive part P10.1; and the light-emitting pixel PX to which the power supply voltage is applied by a power supply drive part P10.2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display panel and a display device in which light emitting elements are arranged in a matrix.

  As a display device using a current-driven light emitting element, a display device using an organic EL (Electro Luminescence) element (hereinafter referred to as an organic EL display device) is known. The organic EL display device using the self-emitting organic EL element does not require a backlight used in the liquid crystal display device, and is optimal for thinning the device. Moreover, since there is no restriction | limiting in a viewing angle, the organic EL display apparatus is anticipated for practical use as a next-generation display apparatus.

Therefore, various techniques in the organic EL display device are disclosed.
For example, Patent Document 1 discloses a technique for forming one organic EL display panel by joining a plurality of unit panels (hereinafter referred to as Conventional Art A).

JP 2002-108253 A

  The display area of the organic EL display panel (hereinafter referred to as an integral display area) in the prior art A is formed by joining the display areas of the plurality of unit panels (hereinafter referred to as unit display areas). In the integrated display area, the boundary line indicating the boundary of each unit display area is a straight line. In this case, the organic EL display panel having an integral display area has the following problems.

  Here, in order to simplify the explanation, as an example, it is assumed that the integrated display area includes a first display area and a second display area. In this case, the boundary line indicating the boundary between the first display area and the second display area is a straight line. Hereinafter, the boundary line indicating the boundary between the first display area and the second display area is referred to as a display area boundary line.

  Further, it is assumed that the operating voltage is supplied from the first power source and the second power source to the first display area and the second display area, respectively. That is, it is assumed that the power supplies that supply the operating voltage to each of the first display area and the second display area are independent and different power supplies.

  Further, it is assumed that the electrical characteristics of the first power source and the electrical characteristics of the second power source are slightly different due to manufacturing variations and the like. Further, it is assumed that an image composed of a plurality of pixels having the same luminance value needs to be displayed on the entire integrated display area.

  In this case, if the electrical characteristics of the first power source and the electrical characteristics of the second power source are slightly different, the level of the operating voltage supplied by the first power source to the first display area and the second power source to the second display area There is a slight difference between the level of operating voltage supplied. Thereby, for example, there is a slight difference in luminance between two adjacent light emitting pixels across the display area boundary line.

  In this case, when the display area boundary line indicating the boundary between the first display area and the second display area is a straight line as in the conventional technique A, in the image displayed in the integrated display area, in the vicinity of the display area boundary line. The presence of a line along the display area boundary line due to the difference in luminance is easily recognized by the user. That is, the image quality of the image displayed in the integrated display area is deteriorated.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a display that can suppress image quality deterioration when an image is displayed using a plurality of areas. It is to provide panels.

  In order to solve the above-described problem, a display panel according to an aspect of the present invention includes a first display region in which a plurality of light emitting pixels to which a power supply voltage is applied by a first power supply driving unit are arranged in a matrix, A plurality of light emitting pixels to which a power supply voltage is applied by a two power source driving unit are positioned between a second display area arranged in a matrix, the first display area, and the second display area, and a plurality of light emitting elements A plurality of light emitting pixels arranged in the same column in the boundary display area, the pixels including at least a boundary display area arranged to form one or more columns. Both the light emitting pixel to which the power supply voltage is applied and the light emitting pixel to which the power supply voltage is applied by the second power supply driver are included.

  According to the present invention, it is possible to suppress image quality deterioration when an image is displayed using a plurality of regions.

It is a block diagram which shows the structure of the display apparatus in 1st Embodiment. It is a figure for demonstrating a display area. It is sectional drawing which shows an example of a structure of the light emitting pixel which concerns on this Embodiment. As an example, it is a figure which expands and shows a part of boundary display area. It is a top view which shows a lower electrode layer. It is a figure which shows an upper electrode layer. As an example, it is a figure which shows an example of a structure of the light emission pixel corresponding to u line 1st column in a light emission pixel matrix. It is a figure for demonstrating the boundary line in the modification 1 of 1st Embodiment. It is a block diagram which shows the structure of the display apparatus in 2nd Embodiment. It is a figure for demonstrating a display area. As an example, it is a figure which expands and shows a part of boundary display area in a 2nd embodiment. As an example, it is a figure which expands and shows a part of boundary display area in a 2nd embodiment. As an example, it is a figure which shows an example of a structure of the light emission pixel corresponding to the 1st row | line | column t in a light emission pixel matrix. It is a figure which expands and shows a part in boundary display area in 3rd Embodiment. It is a figure which expands and shows a part in boundary display area in the modification 1 of 3rd Embodiment. It is an external view of a display apparatus.

  A display panel according to an aspect of the present invention includes a first display region in which a plurality of light emitting pixels to which a power supply voltage is applied by a first power supply drive unit are arranged in a matrix, and a power supply voltage applied by a second power supply drive unit. The plurality of light emitting pixels are located between the second display region arranged in a matrix and the first display region and the second display region, and the plurality of light emitting pixels are at least in one or more columns. A plurality of light emitting pixels arranged in the same column in the boundary display region, and a power supply voltage is applied to the plurality of light emitting pixels by the first power supply driving unit. And a light emitting pixel to which a power supply voltage is applied by the second power supply driver.

  In other words, the boundary display area is arranged between the first display area in which the plurality of light emitting pixels are arranged and the second display area in which the plurality of light emitting pixels are arranged. In the boundary display region, a plurality of light emitting pixels arranged in the same column include a light emitting pixel to which a power supply voltage is applied by a first power supply driving unit, and a light emitting pixel to which a power supply voltage is applied by a second power supply driving unit. Both are included.

  That is, a boundary line indicating a boundary between a region including a plurality of light emitting pixels to which a power supply voltage is applied by the first power supply driving unit and a region including a plurality of light emitting pixels to which the power supply voltage is applied by the second power supply driving unit is Non-linear.

  Therefore, in the case where an image is displayed by causing all of the light emitting pixels in the first display area, the second display area, and the boundary display area to emit light, the electrical characteristics of the first power supply drive section and the second power supply drive section are assumed. Even if the electrical characteristics are slightly different from each other, it is difficult to visually recognize the luminance difference in the vicinity of the boundary line in the displayed image, and image quality deterioration of the image can be suppressed. That is, the display image quality of the entire panel can be improved.

  In addition, even when a plurality of small display panels each having a power supply drive unit are combined and divided drive is performed, the image quality around the connection unit of the panels does not deteriorate, so that the display panel can be easily enlarged. it can.

  In a display panel according to another aspect of the present invention, a plurality of light-emitting pixels to which a power supply voltage is applied by a first power supply driving unit are arranged in a matrix, and a power supply voltage is supplied by a second power supply driving unit. The plurality of light emitting pixels to be applied are positioned between the second display region arranged in a matrix and the first display region and the second display region, and the plurality of light emitting pixels is at least one or more. A plurality of light emitting pixels arranged in the same row within the boundary display region, the power supply voltage being applied by the first power supply driving unit. Both a pixel and a light emitting pixel to which a power supply voltage is applied by the second power supply driver are included.

  In other words, the boundary display area is arranged between the first display area in which the plurality of light emitting pixels are arranged and the second display area in which the plurality of light emitting pixels are arranged. In the boundary display region, a plurality of light emitting pixels arranged in the same row include a light emitting pixel to which a power supply voltage is applied by a first power supply driving unit, and a light emitting pixel to which a power supply voltage is applied by a second power supply driving unit. Both are included.

  That is, a boundary line indicating a boundary between a region including a plurality of light emitting pixels to which a power supply voltage is applied by the first power supply driving unit and a region including a plurality of light emitting pixels to which the power supply voltage is applied by the second power supply driving unit is It is non-linear.

  Therefore, in the case where an image is displayed by causing all of the light emitting pixels in the first display area, the second display area, and the boundary display area to emit light, the electrical characteristics of the first power supply drive section and the second power supply drive section are assumed. Even if the electrical characteristics are slightly different from each other, it is difficult to visually recognize the luminance difference in the vicinity of the boundary line in the displayed image, and image quality deterioration of the image can be suppressed. That is, the display image quality of the entire panel can be improved.

  In addition, even when a plurality of small display panels each having a power supply drive unit are combined and divided drive is performed, the image quality around the connection unit of the panels does not deteriorate, so that the display panel can be easily enlarged. it can.

  Each light emitting pixel to which a power supply voltage is applied by the first power supply driving unit includes a first lower electrode and a first upper electrode, and the first power supply driving unit is configured to emit the light emitting pixel at least during light emission. Each light emitting pixel electrically connected to the first lower electrode or the first upper electrode and to which a power supply voltage is applied by the second power driver includes a second lower electrode and a second upper electrode, It is preferable that the power supply driving unit is electrically connected to the second lower electrode or the second upper electrode at least when the light emitting pixel to be lit emits light.

  The first power supply driving unit is electrically connected to the first lower electrode at least when the light emitting pixel to be emitted emits light, and the second power supply driving unit is configured to emit the first power at least when the light emitting pixel to be emitted emits light. 2 is electrically connected to the lower electrode, and each of the first lower electrode and the second lower electrode constitutes an independent pixel electrode for each light emitting pixel, and the first upper electrode and the second upper electrode are It is preferable that a common electrode provided in common for the plurality of light emitting pixels is configured.

  In addition, each of the first lower electrode, the first upper electrode, the second lower electrode, and the second upper electrode is provided in common to a plurality of light emitting pixels arranged in the same column or the same row, and the first power supply driving And the second power source drive unit is electrically connected to the second lower electrode, or the first power source drive unit is electrically connected to the first upper electrode. The second power supply driving unit is electrically connected to the second upper electrode, and the first lower electrode and the second lower electrode are connected in the same row or the same column in the boundary display region. It is preferable that the electrode is electrically disconnected, or the first upper electrode and the second upper electrode are electrically disconnected.

  The plurality of light emitting pixels arranged in the same row or the same column in the boundary display region are provided with first and second power supply lines associated with each other, and the first power supply line is connected to the boundary display area. A power line used to apply a power supply voltage to the first light-emitting pixel to which a power supply voltage is applied by the first power supply driver, and the second power supply line, A power line used to apply a power supply voltage to the second light emitting pixel disposed in the boundary display area and applied with a power supply voltage by the second power supply driver; The line is electrically connected to the plurality of first light emitting pixels arranged in the same row or the same column in the boundary display region, and the second power line is connected to the same row or in the boundary display region. A plurality of said first arranged in the same row; The first power supply driving unit applies a power supply voltage to the plurality of first light emitting pixels in the boundary display region via the first power supply line, and Preferably, the second power supply driving unit applies a power supply voltage to the plurality of second light emitting pixels in the boundary display region via the second power supply line.

The first and second power lines are preferably arranged in parallel.
Moreover, it is preferable that the shape of each of the first and second power supply lines is a non-linear shape.

  Further, in the same row or the same column in the boundary display region, the light emitting pixels to which the power supply voltage is applied by the first power supply driving unit and the light emitting pixels to which the power supply voltage is applied by the second power supply driving unit have a period Is preferably arranged.

  Further, in the same row or the same column in the boundary display region, the light emitting pixels to which the power supply voltage is applied by the first power supply driving unit and the light emitting pixels to which the power supply voltage is applied by the second power supply driving unit are not It is preferable to arrange periodically.

  Further, in the same row or the same column in the boundary display area, the light emitting pixels to which the power supply voltage is applied by the first power supply driving unit and the light emitting pixels to which the power supply voltage is applied by the second power supply driving unit alternate. It is preferable to arrange | position.

  The light emitting pixels arranged in the same row or the same column in the boundary display region are light emitting pixels to which a power supply voltage is applied by the first power supply driving unit based on an arrangement determined based on a dither matrix. It is preferable that both of the light emitting pixels to which a power supply voltage is applied by the second power supply driver are included.

  Each of the plurality of light emitting pixels preferably includes an organic EL (Electro Luminescence) element, and the organic EL element emits light by a current supplied by an applied power supply voltage.

  According to this aspect, it is possible to easily enlarge the screen even in the case of a display panel using an organic EL that is difficult to enlarge.

  A display device according to still another aspect of the present invention includes the display panel and a control circuit that controls the first power supply drive unit and the second power supply drive unit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
(Configuration of display device)
FIG. 1 is a block diagram illustrating a configuration of a display device 1000 according to the first embodiment. As shown in FIG. 1, the display device 1000 includes a control circuit 100, a data line driving circuit 200, a scanning line driving circuit 300, a display panel 400, and power supply driving units P10.1, P10.2, P10. 3, P10.4.

  The control circuit 100 controls the data line driving circuit 200, the scanning line driving circuit 300, and the power supply driving units P10.1, P10.2, P10.3, and P10.4. Each of power supply drive units P10.1, P10.2, P10.3, and P10.4 is an IC (Integrated Circuit) manufactured to have the same electrical characteristics.

  The power supply driving units P10.1, P10.2, P10.3, and P10.4 are power supplies for supplying a power supply voltage, details of which will be described later. Hereinafter, each of the power supply drive units P10.1, P10.2, P10.3, and P10.4 is also referred to as a power supply drive unit P10.

  The display panel 400 is an active matrix type or passive matrix type display panel. The display panel 400 is an organic EL panel using an organic EL (Electro Luminescence) element.

  The display panel 400 is not limited to an organic EL panel, and may be a display panel of another type such as a liquid crystal panel.

  Display panel 400 includes a display area 410 for displaying an image. The display area 410 includes a plurality of light emitting pixels PX. The plurality of light emitting pixels PX are arranged in a matrix. That is, the plurality of light emitting pixels PX form a matrix (hereinafter referred to as a light emitting pixel matrix) of m (an integer of 2 or more) rows n (an integer of 2 or more) columns. Each of the plurality of light emitting pixels PX emits light according to a signal supplied from the outside.

  In the following, the light emitting pixel PX in the u (natural number) row t (natural number) column in the light emitting pixel matrix is also referred to as the light emitting pixel PX [t, u].

  The display panel 400 is electrically connected to the scanning line driving circuit 300 by m scanning lines CL. Each of the m scanning lines CL is electrically connected to n light emitting pixels PX arranged in each of m rows in the light emitting pixel matrix. Each of the m scanning lines CL is an electric wire for supplying a control signal to the light emitting pixel PX to be processed under the control of the scanning line driving circuit 300.

  The display panel 400 is electrically connected to the data line driving circuit 200 by n data lines DL. Each of the n data lines DL is electrically connected to m light emitting pixels PX arranged in each of n columns in the light emitting pixel matrix. Each of the n data lines DL is a data line for supplying a signal for causing the light emitting pixel to emit light to the light emitting pixel PX to be processed.

  FIG. 2 is a diagram for explaining the display area 410. In FIG. 2, for the sake of explanation, power supply driving units P10.1, P10.2, P10.3, and P10.4 are shown.

  The display area 410 includes a display area DR. 1, DR. 2, DR. 3, DR. 4 and the boundary display area BR. 1, BR. 2, BR. 3, BR. 4 is included.

  That is, the display area 410 includes the boundary display area BR. 1, BR. 2, BR. 3, BR. 4, the display area DR. 1, DR. 2, DR. 3, DR. Divided into four. The display area 410 is not limited to four display areas, and may be divided into five or more display areas.

  Boundary display area BR. 1 is a display area DR. 1 and display area DR. Between the two. Boundary display area BR. 2 is a display area DR. 1 and display area DR. 3 is arranged. Boundary display area BR. 3 is a display area DR. 2 and display area DR. 4 is arranged. Boundary display area BR. 4 is a display area DR. 3 and display area DR. 4 is arranged.

  Display area DR. 1, DR. 2, DR. 3, DR. 4 and the boundary display area BR. 1, BR. 2, BR. 3, BR. 4 are on the same plane.

  Display area DR. 1, DR. 2, DR. 3, DR. Each of 4 includes a plurality of light emitting pixels PX arranged in a matrix.

  Boundary display area BR. 1, BR. Each of 4 includes a plurality of light emitting pixels PX arranged in the vertical direction. In this specification, the vertical direction is a direction in which the rows in the light emitting pixel matrix are juxtaposed (arranged). That is, the boundary display area BR. 1, BR. Each of 4 is a region in which a plurality of light emitting pixels PX are arranged to form one or more columns.

  Boundary display area BR. 2, BR. Each of 3 includes a plurality of light emitting pixels PX arranged in the horizontal direction. In this specification, the horizontal direction is a direction in which the columns in the light emitting pixel matrix are juxtaposed (arranged). That is, the boundary display area BR. 2, BR. Each of 3 is an area in which a plurality of light emitting pixels PX are arranged to form one or more rows.

  Boundary display area BR. 1, BR. Each of 4 is provided along the vertical direction. Boundary display area BR. 2, BR. Each of 3 is provided along the horizontal direction.

  In the following, the display area DR. 1, DR. 2, DR. 3, DR. Each of 4 is also referred to as a display area DR. In the following, the boundary display area BR. 1, BR. 2, BR. 3, BR. Each of 4 is also referred to as a boundary display area BR.

  Hereinafter, one row in the light emitting pixel matrix is also referred to as a light emitting pixel row. The light emitting pixel row is a row in which one or more light emitting pixels PX are arranged in the horizontal direction. Hereinafter, one column in the light emitting pixel matrix is also referred to as a light emitting pixel column. The light emitting pixel column is a column in which one or more light emitting pixels PX are arranged in the vertical direction.

FIG. 3 is a cross-sectional view showing an example of the configuration of the light-emitting pixel PX according to the present embodiment.
Referring to FIG. 3, the luminescent pixel PX includes a substrate 401, an anode 402, a hole injection layer 403, a hole transport layer 404, an organic light emitting layer 405, an electron transport layer 406, a cathode 407, A sealing layer 408.

  The anode 402 is an electrode having light reflectivity and is formed on the substrate 401. As the anode 402, a metal such as aluminum, a metal such as Al or Pd, an alloy containing these metals as a main component, or a laminate of these can be used.

  The hole injection layer 403 is a layer mainly composed of a hole injecting material and is formed on the anode 402. As the hole injection layer 403, for example, tungsten oxide (WOx), PEDOT (polyethylenedioxythiophene), or the like can be used.

  The hole transport layer 404 is a layer mainly composed of a hole transport material and is formed on the hole injection layer 103. For the hole transport layer 404, for example, a triphenylamine-based material is used.

  The organic light emitting layer 405 is a layer mainly composed of an organic light emitting material that emits light by recombination of holes and electrons, and is formed between the anode 402 and the cathode 407. Specifically, the organic light emitting layer 405 is formed on the hole transport layer 404 as shown in FIG.

  The electron transport layer 406 is a layer containing an electron transporting material as a main component and is formed on the organic light emitting layer 405.

  The cathode 407 is a light transmissive electrode and is formed on the electron transport layer 406. The cathode 407 is made of, for example, indium tin oxide (ITO).

The anode 402 and the cathode 407 are a lower electrode and an upper electrode, respectively.
The sealing layer 408 is a resin layer that covers the surface of the light emitting pixel PX according to this embodiment, and is formed on the cathode 407 as shown in FIG.

  The anode 402 as the lower electrode, the hole injection layer 403, the hole transport layer 404, the organic light emitting layer 405, the electron transport layer 406, and the cathode 407 as the upper electrode constitute the light emitting element EL1. . That is, the light emitting element EL1 includes a cathode 407 as an upper electrode and an anode 402 as a lower electrode. The light emitting element EL1 is an organic EL element.

  The lower electrode in the light emitting element EL1 is not limited to the anode, and may be a cathode. Further, the upper electrode in the light emitting element EL1 is not limited to the cathode, but may be an anode.

  Further, the light-emitting element EL1 that is an organic EL element is not limited to the configuration shown in FIG. 3, and for example, an anode, a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer And a cathode.

(Configuration of active matrix method)
The display panel 400 in this embodiment is an active matrix panel. A configuration of the display panel 400 in this case will be described.

  Again referring to FIG. 1, DR. 2, DR. 3, DR. Each of 4 is provided with a plurality of power supply lines PL (not shown). Each of the plurality of power supply lines PL is linearly arranged in the vertical direction in association with each light emitting pixel column in the corresponding display region DR.

  The power supply drive units P10.1, P10.2, P10.3, and P10.4 are respectively connected to the display area DR. 1, DR. 2, DR. 3, DR. 4 is a power supply for supplying a power supply voltage to 4. That is, the display area DR. 1, DR. 2, DR. 3, DR. Each light emitting pixel PX in each of 4 is supplied with a power supply voltage from an independent different power supply driving unit P10.

  In the following, the power supply drive unit P10. The power supply line PL electrically connected to y (natural number), and the power line PL in the x (natural number) column in the light emitting pixel matrix is also referred to as power supply line PL [y, x].

  FIG. 4 shows an example of the boundary display area BR. It is a figure which expands and shows a part of 2. FIG. FIG. 4 also shows some of the plurality of light emitting pixels PX.

  4, the boundary display area BR. 2 above each display pixel DR. 1 is a pixel. Boundary display area BR. 2, each light emitting pixel PX below the display area DR. 3 is a pixel.

  Referring to FIGS. 2 and 4, for example, power supply line PL [1, x (natural number)] is electrically connected to power supply drive unit P10.1. That is, the power supply line PL [1, x] is a power supply line to which a power supply voltage is supplied from the power supply driving unit P10.1. Further, for example, the power supply line PL [1,2] is electrically connected to the power supply drive unit P10.1 and is the power supply line in the second column in the light emitting pixel matrix.

  Further, for example, the power supply line PL [3, x (natural number)] is electrically connected to the power supply drive unit P10.3. Further, for example, the power supply line PL [3, 2] is electrically connected to the power supply drive unit P10.3 and is the power supply line in the second column in the light emitting pixel matrix.

  2 and 4, the boundary display area BR. 1, BR. 2, BR. 3, BR. 4 are boundary lines BL. 1, BL. 2, BL. 3, BL. 4 is included. Boundary line BL. 1, BL. 2, BL. 3, BL. Each of 4 is a boundary line for specifying a region including a plurality of light emitting pixels PX to which a power supply voltage is supplied from the same power supply driving unit P10. Boundary line BL. 1, BL. 2, BL. 3, BL. Each of 4 is non-linear.

  Boundary line BL. 1, BL. 2, BL. 3, BL. Each shape of 4 is the same. Note that the boundary line BL. 1, BL. 2, BL. 3, BL. Each shape of 4 may be different.

  In the following, the boundary line BL. 1, BL. 2, BL. 3, BL. Each of 4 is also expressed as a boundary line BL.

  Note that the shape of the boundary line BL is not limited to a shape in which convex portions for one light emitting pixel PX are repeated, as shown in FIG. The shape of the boundary line BL may be a shape in which convex portions for two or more light emitting pixels PX are repeated.

  Boundary line BL. 1 and the boundary line BL. 2 and an upper left area in the display area 410 is an area to which a power supply voltage is supplied from the power supply driving unit P10.1 (hereinafter referred to as a first power supply area). That is, the power supply voltage is supplied from the power supply drive unit P10.1 to each light emitting pixel PX in the first power supply region.

  In this case, the first power supply area is the display area DR. 1 and the boundary display area BR. 1 and the boundary display area BR. 2 is a region including a part of 2.

  Hereinafter, the light emitting pixel PX in the first power supply region to which the power supply voltage is supplied (applied) from the power supply driving unit P10.1 is also referred to as the first light emitting pixel PX. The first light emitting pixel PX is electrically connected to the power supply line PL [1, x], and a power supply voltage is supplied (applied) from the power supply driving unit P10.1 via the power supply line PL [1, x].

  Boundary line BL. 1 and the boundary line BL. 3 and an upper right region in the display region 410 is a region to which a power supply voltage is supplied from the power supply driving unit P10.2 (hereinafter referred to as a second power supply region). That is, the power supply voltage is supplied from the power supply drive unit P10.2 to each light emitting pixel PX in the second power supply region.

  In this case, the second power supply area is the display area DR. 2 and the boundary display area BR. 1 and the boundary display area BR. 3 is a region including a part of 3.

  Hereinafter, the light emitting pixel PX in the second power supply region to which the power supply voltage is supplied (applied) from the power supply driving unit P10.2 is also referred to as a second light emitting pixel PX. The second light emitting pixel PX is electrically connected to the power supply line PL [2, x], and a power supply voltage is supplied (applied) from the power supply driving unit P10.2 via the power supply line PL [2, x].

  Boundary line BL. 2 and the boundary line BL. 4 and the lower left region in the display region 410 is a region to which a power supply voltage is supplied from the power supply driving unit P10.3 (hereinafter referred to as a third power supply region). That is, the power supply voltage is supplied from the power supply drive unit P10.3 to each light emitting pixel PX in the third power supply region.

  In this case, the third power supply area is the display area DR. 3 and the boundary display area BR. 2 and the boundary display area BR. 4 is a region including a part of 4.

  Hereinafter, the light emitting pixel PX in the third power supply region to which the power supply voltage is supplied (applied) from the power supply driving unit P10.3 is also referred to as the third light emitting pixel PX. The third light emitting pixel PX is electrically connected to the power supply line PL [3, x], and a power supply voltage is supplied (applied) from the power supply driving unit P10.3 via the power supply line PL [3, x].

  Boundary line BL. 3 and the boundary line BL. 4 and the lower right region in the display region 410 is a region to which a power supply voltage is supplied from the power supply driver P10.4 (hereinafter referred to as a fourth power supply region). That is, the power supply voltage is supplied from the power supply drive unit P10.4 to each light emitting pixel PX in the fourth power supply region.

  In this case, the fourth power supply area is the display area DR. 4 and the boundary display area BR. 3 and the boundary display area BR. 4 is a region including a part of 4.

  Hereinafter, the light emitting pixel PX in the fourth power supply region to which the power supply voltage is supplied (applied) from the power supply driving unit P10.4 is also referred to as a fourth light emitting pixel PX. The fourth light emitting pixel PX is electrically connected to the power supply line PL [4, x], and the power supply voltage is supplied (applied) from the power supply driving unit P10.4 through the power supply line PL [4, x].

Each of the first, second, third and fourth power supply areas is an area for displaying an image.
Boundary display area BR. 1 includes the boundary display area BR. A power supply line PL [1, x] and a power supply line PL [2, x] are arranged for each light emitting pixel column in one. Boundary display area BR. 1 is connected to the boundary display area BR. It is shaped so as to be electrically connected to only the plurality of first light emitting pixels PX arranged in the light emitting pixel column within 1, and is arranged in the vertical direction. Boundary display area BR. 1 is connected to the boundary display area BR. It is shaped so as to be electrically connected only to the plurality of second light emitting pixels PX arranged in the light emitting pixel column in 1, and is arranged in the vertical direction.

  Boundary display area BR. 2 includes the boundary display area BR. A power supply line PL [1, x] or a power supply line PL [3, x] is arranged for each light emitting pixel column in 2. Boundary display area BR. 2 is connected to the boundary display area BR. 2 are electrically connected to one or more first light-emitting pixels PX arranged in the light-emitting pixel column in 2 and arranged in the vertical direction. Boundary display area BR. 2 is connected to the boundary display area BR. 2 are electrically connected to one or more third light emitting pixels PX arranged in the light emitting pixel column in 2 and arranged in the vertical direction.

  Boundary display area BR. 3 includes the boundary display area BR. A power supply line PL [2, x] or a power supply line PL [4, x] is arranged for each light emitting pixel column in FIG. Boundary display area BR. 3 is connected to the boundary display area BR. 3 is electrically connected to one or more second light-emitting pixels PX arranged in the light-emitting pixel column in the line 3, and is arranged in the vertical direction. Boundary display area BR. 3 is connected to the boundary display area BR. 3 are electrically connected to one or more fourth light-emitting pixels PX arranged in the light-emitting pixel column, and are arranged in the vertical direction.

  Boundary display area BR. 4 includes the boundary display area BR. A power supply line PL [3, x] and a power supply line PL [4, x] are arranged for each light emitting pixel column in 4. Boundary display area BR. 4 is connected to the boundary display area BR. 4 is shaped so as to be electrically connected to only the plurality of third light emitting pixels PX arranged in the light emitting pixel row in 4 and is arranged in the vertical direction. Boundary display area BR. 4 is connected to the boundary display area BR. 4 has a shape that is electrically connected to only the plurality of fourth light emitting pixels PX arranged in the light emitting pixel row within 4, and is arranged in the vertical direction.

  The first power supply region includes v (natural number less than n) power supply lines PL [1, x]. The second power supply region includes v power supply lines PL [2, x]. The third power supply region includes v power supply lines PL [3, x]. The fourth power supply region includes v power supply lines PL [4, x].

  The number of power supply lines PL included in each of the first, second, third, and fourth power supply regions is not the same and may be different.

  Each of power supply lines PL [1, x], PL [2, x], PL [3, x], PL [4, x] is electrically disconnected from each other.

  Hereinafter, each of the first, second, third, and fourth power supply regions is also referred to as an independent power supply region. As described above, each of the first, second, third, and fourth power supply areas is an area for displaying an image. Therefore, the independent power supply area is an area for displaying an image.

  Boundary line BL. 1, BL. 2, BL. 3, BL. Each of 4 is also a line for specifying each of the first, second, third and fourth power supply regions. Further, the power supply drive units P10.1, P10.2, P10.3, and P10.4 are power supplies for supplying a power supply voltage to the first, second, third, and fourth power supply regions, respectively. In other words, power supply drive units P10.1, P10.2, P10.3, and P10.4 are power supplies associated with the first, second, third, and fourth power supply regions, respectively. In other words, each light emitting pixel PX in each of the first, second, third, and fourth power supply regions is supplied with a power supply voltage from an independent different power supply driving unit P10.

  In FIG. 4, for example, the light emitting pixel PX [1, u] is the first light emitting pixel PX. A power supply voltage is supplied (applied) to the light emitting pixel PX [1, u] from the power supply driving unit P10.1 via the power supply line PL [1, 1].

  The light emitting pixel PX [1, u + 1] is the third light emitting pixel PX. A power supply voltage is supplied (applied) to the light emitting pixel PX [1, u + 1] from the power supply driver P10.3 via the power supply line PL [3, 1].

The power supply line PL [1,1] and the power supply line PL [3,1] are electrically disconnected.
For example, the boundary display area BR. 2 includes, as an example, a plurality of light emitting pixels PX arranged in the same row. Boundary display area BR. The plurality of light emitting pixels PX arranged in the same row in 2 includes both one or more first light emitting pixels PX and one or more third light emitting pixels PX.

  Specifically, the boundary display area BR. In the same row in 2, the first light emitting pixels PX and the third light emitting pixels PX are alternately arranged. That is, the boundary display area BR. 2, the first light emitting pixel PX and the third light emitting pixel PX are periodically arranged.

  The boundary display area BR. 3 is a boundary display area BR. 2 includes a plurality of light emitting pixels PX arranged in the same row. Further, the boundary display area BR. 2, the boundary display area BR. The plurality of light emitting pixels PX arranged in the same row in 3 includes both one or more second light emitting pixels PX and one or more fourth light emitting pixels PX.

  The boundary display area BR. 1 is a boundary display area BR. 2 includes a plurality of light emitting pixels PX arranged in the same column instead of the same row. Further, the boundary display area BR. 2, the boundary display area BR. The plurality of light emitting pixels PX arranged in the same column in 1 includes both one or more first light emitting pixels PX and one or more second light emitting pixels PX.

  Boundary display area BR. In the same column in 1, the first light emitting pixels PX and the second light emitting pixels PX are alternately arranged. That is, the boundary display area BR. 1, the first light emitting pixel PX and the second light emitting pixel PX are periodically arranged.

  The boundary display area BR. 4 is a boundary display area BR. 1 includes a plurality of light emitting pixels PX arranged in the same column. Further, the boundary display area BR. 1, the boundary display area BR. The plurality of light emitting pixels PX arranged in the same column in 4 includes both one or more third light emitting pixels PX and one or more fourth light emitting pixels PX.

  1, 2, and 4, control circuit 100 includes power supply driving units P <b> 10.1, P <b> 10.2, P <b> 10.3, and P <b> 10.4 according to the characteristics of the image displayed in display area 410. Control the voltage supplied. Hereinafter, an image displayed in the display area 410 is referred to as a display image.

  Specifically, for example, the control circuit 100 performs control such that the darker the portion corresponding to each independent power supply region in the display image, the lower the voltage level supplied by the power supply driving unit P10 corresponding to the independent power supply region. . For example, when only the upper left portion is dark in the display image, the power supply drive unit P10.1 is controlled so as to reduce only the voltage level supplied by the power supply drive unit P10.1 corresponding to the first power supply region. Thereby, for example, when the brightness of the display image is low as a whole, the power consumption of the display device 1000 can be reduced.

  FIG. 5 is a plan view showing the lower electrode layer 402BT. Lower electrode layer 402BT is included in display area 410. The lower electrode layer 402BT is a layer in which the anode 402 of FIG. 3 included in each light emitting pixel PX included in the display area 410 of FIG. 1 is formed.

  The lower electrode layer 402BT is a layer to which a power supply voltage is supplied (applied) from each of the power supply driving units P10.1, P10.2, P10.3, and P10.4. The size of the lower electrode layer 402BT is the same as the size of the display area 410 in FIG.

  Lower electrode layer 402BT is formed in electrode layer region PR. 1, PR. 2, PR. 3, PR. 4 and the boundary region PBR. 1, PBR. 2, PBR. 3, PBR. 4 is included.

  That is, the lower electrode layer 402BT has a boundary region PBR. 1, PBR. 2, PBR. 3, PBR. 4, the electrode layer region PR. 1, PR. 2, PR. 3, PR. Divided into four. Note that the lower electrode layer 402BT is not limited to four electrode layer regions, and may be divided into five or more electrode layer regions.

  Boundary region PBR. 1 represents the electrode layer region PR. 1 and electrode layer region PR. Between the two. Boundary region PBR. 2 represents the electrode layer region PR. 1 and electrode layer region PR. 3 is arranged. Boundary region PBR. 3 represents the electrode layer region PR. 2 and electrode layer region PR. 4 is arranged. Boundary region PBR. 4 is an electrode layer region PR. 3 and the electrode layer region PR. 4 is arranged.

  Boundary region PBR. 1, PBR. 2, PBR. 3, PBR. 4 are respectively the boundary display area BR. 1, BR. 2, BR. 3, BR. This is the same as position 4.

  Boundary region PBR. 1, PBR. 2, PBR. 3, PBR. 4 is a boundary line PL. 1, PL. 2, PL. 3, PL. 4 is included. Boundary line PL. 1, PL. 2, PL. 3, PL. Each of 4 is a boundary line for specifying a region including a plurality of anodes 402 to which a power supply voltage is supplied from the same power supply driving unit P10.

  Boundary line PL. 1, PL. 2, PL. 3, PL. 4 are respectively aligned with the boundary line BL. 1, BL. 2, BL. 3, BL. This is the same as position 4. Boundary line PL. 1, PL. 2, PL. 3, PL. 4 are respectively the boundary lines BL. 1, BL. 2, BL. 3, BL. It is the same as the shape of 4. That is, the boundary line PL. 1, PL. 2, PL. 3, PL. Each of 4 is non-linear.

  Electrode layer region PR. 1, PR. 2, PR. 3, PR. 4 has a display area DR. 1, DR. 2, DR. 3, DR. It is the same as the size of 4. The electrode layer region PR. 1, PR. 2, PR. 3, PR. 4 are respectively displayed in the display area DR. 1, DR. 2, DR. 3, DR. This is the same as position 4.

  Electrode layer region PR. 1, PR. 2, PR. 3, PR. Each of 4 includes a plurality of anodes 402 arranged in a matrix. In the lower electrode layer 402BT of FIG. 5, the position where the anode 402 included in each light emitting pixel PX is formed is the same as the position where each light emitting pixel PX shown in FIG. 2 is formed.

  Boundary region PBR. 1, PBR. Each of 4 includes a plurality of anodes 402 arranged in a vertical direction. Boundary region PBR. 2, PBR. Each of 3 includes a plurality of anodes 402 arranged in a horizontal direction.

  Boundary line PL. 1 and the boundary line PL. 2 and an upper left region in the lower electrode layer 402BT is a region to which a power supply voltage is supplied from the power supply drive unit P10.1 (hereinafter referred to as a first power supply drive region). That is, a power supply voltage is supplied from the power supply drive unit P10.1 to each anode 402 in the first power supply drive region.

  In this case, the first power supply drive region is the electrode layer region PR. 1 and the boundary region PBR. 1 and the boundary region PBR. 2 is a region including a part of 2.

  In the first power supply driving region, the anode 402 (lower electrode) included in each of the first light emitting pixels PX described above is formed. The v power supply lines PL [1, x] described above are formed on the first power supply driving region. Power supply drive unit P10.1 is electrically connected to v power supply lines PL [1, x] formed in the first power supply drive region. Each anode 402 in the first power supply drive region is electrically connected to the power supply line PL [1, x], and the power supply voltage is supplied from the power supply drive unit P10.1 via the power supply line PL [1, x] ( Applied).

  Boundary line PL. 1 and the boundary line PL. 3 and the upper right region in the lower electrode layer 402BT is a region to which a power supply voltage is supplied from the power supply drive unit P10.2 (hereinafter referred to as a second power supply drive region). That is, the power supply voltage is supplied from the power supply drive unit P10.2 to each anode 402 in the second power supply drive region.

  In this case, the second power supply drive region is the electrode layer region PR. 1 and the boundary region PBR. 1 and the boundary region PBR. 3 is a region including a part of 3.

  In the second power supply driving region, the anode 402 (lower electrode) included in each of the second light emitting pixels PX described above is formed. The above-described v power supply lines PL [2, x] are formed on the second power supply drive region. Power supply drive unit P10.2 is electrically connected to v power supply lines PL [2, x] formed in the second power supply drive region. Each anode 402 in the second power supply drive region is electrically connected to the power supply line PL [2, x], and the power supply voltage is supplied from the power supply drive unit P10.2 via the power supply line PL [2, x] ( Applied).

  Boundary line PL. 2 and the boundary line PL. 4 and the lower left region in the lower electrode layer 402BT is a region to which a power supply voltage is supplied from the power supply driver P10.3 (hereinafter referred to as a third power supply drive region). That is, the power supply voltage is supplied from the power supply drive unit P10.3 to each anode 402 in the third power supply drive region.

  In this case, the third power supply drive region is the electrode layer region PR. 3 and the boundary region PBR. 2 and the boundary region PBR. 4 is a region including a part of 4.

  In the third power supply driving region, the anode 402 (lower electrode) included in each third light emitting pixel PX is formed. On the third power supply drive region, the above-described v power supply lines PL [3, x] are formed. The power supply drive unit P10.3 is electrically connected to v power supply lines PL [3, x] formed in the third power supply drive region. Each anode 402 in the third power supply drive region is electrically connected to the power supply line PL [3, x], and a power supply voltage is supplied from the power supply drive unit P10.3 via the power supply line PL [3, x] ( Applied).

  Boundary line PL. 3 and the boundary line PL. 4 and a lower right region in the lower electrode layer 402BT is a region to which a power supply voltage is supplied from the power supply driver P10.4 (hereinafter referred to as a fourth power supply drive region). That is, a power supply voltage is supplied from the power supply drive unit P10.4 to each anode 402 in the fourth power supply drive region.

  In this case, the fourth power supply drive region is the electrode layer region PR. 4 and the boundary region PBR. 3 and the boundary region PBR. 4 is a region including a part of 4.

  In the fourth power supply driving region, the anode 402 (lower electrode) included in each of the fourth light emitting pixels PX described above is formed. The above-described v power supply lines PL [4, x] are formed on the fourth power supply drive region. Power supply drive unit P10.4 is electrically connected to v power supply lines PL [4, x] formed in the fourth power supply drive region. Each anode 402 in the fourth power supply drive region is electrically connected to the power supply line PL [4, x], and a power supply voltage is supplied from the power supply drive unit P10.4 via the power supply line PL [4, x] ( Applied).

  The positions of the first, second, third, and fourth power supply drive regions are the same as the positions of the first, second, third, and fourth power supply regions described in FIG. The sizes of the first, second, third, and fourth power supply drive regions are the same as the sizes of the first, second, third, and fourth power supply regions, respectively. The shapes of the first, second, third, and fourth power source drive regions are the same as the shapes of the first, second, third, and fourth power source regions, respectively.

  That is, each of the four anodes 402 (lower electrodes) included in each of the first, second, third, and fourth light emitting pixels PX constitutes an independent pixel electrode for each light emitting pixel PX.

  FIG. 6 is a diagram showing the upper electrode layer 407UD. FIG. 6 also shows the lower electrode layer 402BT and the power supply drive units P10.1, P10.2, P10.3, and P10.4 for the sake of explanation.

  The upper electrode layer 407UD is included in the display area 410. The upper electrode layer 407UD is a ground layer. The upper electrode layer 407UD is a layer in which the cathode 407 of FIG. 3 included in each light emitting pixel PX included in the display area 410 of FIG. 1 is formed.

  The size of the upper electrode layer 407UD is the same as the size of the display area 410 in FIG. That is, the size of the upper electrode layer 407UD is the same as the size of the lower electrode layer 402BT.

  Referring to FIG. 6, the upper electrode layer 407UD is a common electrode including a cathode 407 (upper electrode) included in each of the plurality of light emitting pixels PX included in the display region 410. That is, the upper electrode layer 407UD is a common electrode including the cathode 407 (upper electrode) included in each of the plurality of first, second, third, and fourth light emitting pixels PX.

  That is, the cathode 407 (upper electrode) included in each of the plurality of first, second, third, and fourth light emitting pixels PX constitutes a common electrode provided in common to the plurality of light emitting pixels PX. .

  In the following, when the state in which the object A is electrically connected to the object B is described, it is simply described that the object A is connected to the object B.

(Configuration of light-emitting pixels)
Next, an example of the configuration of the light emitting pixel PX in the present embodiment is shown.

  FIG. 7 is a diagram illustrating an example of the configuration of the light-emitting pixel PX corresponding to the u-th row and the first column in the light-emitting pixel matrix. That is, FIG. 7 is a diagram illustrating an example of a configuration of the light emitting pixel PX [1, u].

  Referring to FIG. 7, the light emitting pixel PX includes a switching element SW1, a capacitive element C1, a driver element DR1, and a light emitting element EL1.

  The switching element SW1 is an N-channel field effect transistor (FET). Note that the switching element SW1 is not limited to an N-channel FET, and may be a P-channel FET.

  Switching element SW1 is not limited to a transistor, and may be another element as long as it is an element that can be in a conductive state and a non-conductive state between two terminals. The conduction state is a state in which a current can flow. The non-conducting state is a state in which current cannot flow.

  The switching element and the driver element used in this embodiment are elements that are in a conductive state or a non-conductive state in accordance with an external signal. In addition, the driver element in this embodiment is an element for supplying current to the light emitting element.

  The capacitive element C1 is a capacitor. The driver element DR1 is an N-channel field effect transistor (FET). The driver element DR1 is not limited to an N-channel FET, and may be a P-channel FET.

  The light emitting element EL1 is an organic EL element. An organic EL element is an element in which the degree of light emission increases as the current supplied to the organic EL element itself increases. That is, the light emitting element EL1 emits light according to a signal supplied from the outside.

  In the following description, the binary high voltage state (voltage Vdd) and low voltage state of the signal and the signal line are also referred to as “H level” and “L level”, respectively. Hereinafter, the gate electrode, the drain electrode, and the source electrode of each element are also referred to as a gate, a drain, and a source, respectively.

  As shown in FIG. 7, the gate of the switching element SW1 is connected to the scanning line CL. One of the drain and the source of the switching element SW1 is connected to the data line DL. The other of the drain and the source of switching element SW1 is connected to the gate of driver element DR1.

  The drain of driver element DR1 is connected to power supply line PL [1,1]. The source of the driver element DR1 is connected to the anode of the light emitting element EL1.

  As described with reference to FIG. 3, the light emitting element EL <b> 1 includes the cathode 407 and the anode 402. The anode of the light emitting element EL1 is an anode 402 (lower electrode). Therefore, the source of the driver element DR1 is connected to the anode 402 of the light emitting element EL1.

  The light emitting pixel PX [1, u] is a light emitting pixel in the first power supply region. Therefore, when the light emitting element EL1 is caused to emit light, the state of the driver element DR1 becomes conductive, and the anode (anode 402 (lower electrode)) of the light emitting element EL1 is driven by power supply via the power supply line PL [1,1]. Part P10.1 is electrically connected.

  That is, the power supply drive unit P10.1 is electrically connected to the anode 402 (lower electrode) when the light emitting pixel PX that is a light emission target emits light.

  The cathode of the light emitting element EL1 is connected to the negative power supply line NPL. The negative power supply line NPL is ground. In the present embodiment, the cathode of the light emitting element EL1 is the cathode 407 (upper electrode). That is, the cathode (cathode 407) of the light emitting element EL1 is formed on the upper electrode layer 407UD.

The negative power supply line NPL may be a power supply line that supplies a voltage of 0 V or less, for example.
One of the two electrodes of the capacitive element C1 is connected to the gate of the driver element DR1. The other of the two electrodes of the capacitor C1 is connected to the anode of the light emitting element EL1.

  The light emitting pixel PX [1, u + 1] corresponding to the (u + 1) row 1st column shown in FIG. 7 is similar to the light emitting pixel PX [1, u], the data line DL and the power supply line PL [3, 1] and the scanning line CL. Since the configuration of the luminescent pixel PX [1, u + 1] is similar to the configuration of the luminescent pixel PX [1, u], detailed description will not be repeated.

  In the present embodiment, each of the plurality of light emitting pixels PX included in the display region 410 includes a light emitting element EL1 that is an organic EL element. The light emitting element EL1 includes a cathode 407 (upper electrode) and an anode 402 (lower electrode). That is, each of the plurality of light emitting pixels PX included in the display area 410 includes a cathode 407 (upper electrode) and an anode 402 (lower electrode).

  That is, each of the cathode 407 (upper electrode) and the anode 402 (lower electrode) constitutes an independent pixel electrode for each light emitting pixel PX.

(Image display processing)
Next, a process for displaying an image in the display area 410 will be described.

  Here, as an example, it is assumed that the display image displayed in the display area 410 has the same luminance value (pixel value) of a plurality of pixels constituting the display image. In the following, an image in which the luminance values of a plurality of pixels constituting the image are the same is referred to as an entire luminance identical image. That is, the display image is an image having the same overall luminance.

  For the sake of simplicity, the control for causing only the light-emitting pixel PX [1, u] and the light-emitting pixel PX [1, u + 1] to emit light will be described except for the processing for supplying the power supply voltage. The luminescent pixel PX [1, u] and the luminescent pixel PX [1, u + 1] are pixels included in the first and second power supply regions, respectively.

  1, 2, and 4, first, control circuit 100 supplies an instruction for supplying an H level power supply voltage (hereinafter referred to as a voltage supply instruction) to power supply driving units P <b> 10.1, P <b> 10. 2, P10.3 and P10.4.

  In response to receiving the voltage supply instruction, the power supply drive units P10.1, P10.2, P10.3, and P10.4 are respectively connected to the power supply drive units P10.1, P10.2, P10.3, and P10.4. The H level power supply voltage is supplied to the first, second, third and fourth power supply regions. It is assumed that the power supply voltage levels supplied by the power supply drive units P10.1, P10.2, P10.3, and P10.4 are the same.

  Thus, the same level of power supply voltage is supplied (applied) to each power supply line PL included in each of the first, second, third and fourth power supply regions. That is, the display area DR. 1, DR. 2, DR. 3, DR. 4, boundary display area BR. 1, BR. 2, BR. 3, BR. 4 is supplied (applied) to the light emitting pixels PX included in each of the four through the corresponding power supply line PL.

  First, a process for causing each light emitting pixel PX in the u-th row including the light emitting pixel PX [1, u] included in the first power supply region to emit light will be described.

  The control circuit 100 transmits the u-th row light emission signal to the data line driving circuit 200. Here, the u-th light emission signal is a signal for causing each light-emitting pixel PX (for example, the light-emitting pixel PX [1, u]) corresponding to the u-th row to emit light.

  The control circuit 100 transmits an instruction for driving the scanning line CL corresponding to the u-th row to the scanning line driving circuit 300 simultaneously with the transmission of the u-th row emission signal.

  In response to the instruction, the scanning line driving circuit 300 drives the u-th scanning line CL in the light emitting pixel matrix. As a result, the state of the switching element SW1 corresponding to the u-th row becomes a conductive state.

  In addition, when the data line driving circuit 200 receives the u-th row light emission signal, the data line driving circuit 200 performs control for causing each light-emitting pixel PX in the u-th row in the light-emitting pixel matrix to emit light using the n data lines DL. Since the control is a well-known control in which a voltage for causing the light emitting element EL1 to emit light (hereinafter referred to as a light emitting voltage) is applied to the gate of the driver element DR1 in each light emitting pixel PX, detailed description thereof will not be repeated. .

  Thereby, the state of the driver element DR1 of the light emitting pixel PX [1, u] becomes a conductive state, and the anode (anode 402 (lower electrode)) of the light emitting element EL1 is connected via the power supply line PL [1, 1]. It is electrically connected to power supply drive unit P10.1. That is, an H level power supply voltage is applied from the power supply drive unit P10.1 to the anode (anode 402 (lower electrode)) of the light emitting element EL1 of the light emitting pixel PX [1, u] in the first power supply region. . Thereby, a current flows through the light emitting element EL1.

  In addition, due to the control, a charge corresponding to the light emission voltage is held in the capacitor C1. That is, the light emission voltage is written into the light emitting pixel PX. Then, the light emitting pixels PX corresponding to the u-th row emit light simultaneously.

  Next, a process for causing each light-emitting pixel PX in the u + 1-th row including the light-emitting pixel PX [1, u + 1] included in the second power supply region to emit light will be described.

  The control circuit 100 transmits the u + 1-th row light emission signal to the data line driving circuit 200. Here, the light emission signal in the u + 1-th row is a signal for causing each light-emitting pixel PX (for example, the light-emitting pixel PX [1, u + 1]) corresponding to the u + 1-th row to emit light. The process for causing each light emitting pixel PX corresponding to the u + 1th row to emit light is the same as the process for causing each light emitting pixel PX corresponding to the uth row to emit light, and thus detailed description thereof will not be repeated.

  By this processing, the state of the driver element DR1 of the light emitting pixel PX [1, u + 1] becomes conductive, and the anode (anode 402 (lower electrode)) of the light emitting element EL1 is connected via the power line PL [3, 1]. And electrically connected to the power supply drive unit P10.3. That is, an H level power supply voltage is applied to the anode (anode 402 (lower electrode)) of the light emitting element EL1 of the light emitting pixel PX [1, u + 1] in the second power supply region from the power supply driving unit P10.3. . Thereby, a current flows through the light emitting element EL1.

In addition, the light emitting pixels PX corresponding to the (u + 1) th row emit light simultaneously.
The above processing is performed on each light emitting pixel corresponding to each of the 1st to m-th rows in the light emitting pixel matrix, so that the display area 410 displays an image of one frame (an image having the same overall luminance).

  Here, it is assumed that the electrical characteristics of the power supply drive units P10.1, P10.2, P10.3, and P10.4 are slightly different due to manufacturing variations and the like.

  In addition, it is assumed that each boundary line BL indicating the boundary of each independent power supply region to which a voltage is supplied from the same independent power supply is a straight line. Also, it is assumed that an image with the same overall luminance needs to be displayed in the display area 410. That is, as an example, the boundary line BL. It is assumed that two adjacent light emitting pixels (light emitting pixels PX [1, u], PX [1, u + 1]) sandwiching 2 need to emit light with the same luminance (brightness).

  However, for example, if the electrical characteristics of the power supply drive unit P10.1 and the electrical characteristics of the power supply drive unit P10.3 are slightly different, the level of the power supply voltage supplied by the power supply drive unit P10.1 and the power supply drive unit P10 There is a slight difference from the level of the power supply voltage supplied by .3. Thereby, for example, the boundary line BL. There is a slight difference in luminance between adjacent light emitting pixels PX [1, u] and PX [1, u + 1] with 2 interposed therebetween.

  In this case, if the boundary line BL is a straight line, in the image displayed in the display area 410, there is a line along each boundary line BL due to a difference in luminance near each boundary line BL. It becomes easy for a user to visually recognize. That is, the image quality of the image displayed in the display area 410 is deteriorated.

  However, in the present embodiment, each boundary line BL is non-linear. Therefore, in the image displayed in the display area 410, it is difficult for the user to visually recognize the presence of a line along each boundary line BL due to a difference in luminance near each boundary line BL.

  That is, according to the present embodiment, it is possible to suppress image quality deterioration of an image displayed in display area 410 including a plurality of independent power supply areas for displaying an image. That is, it is possible to suppress image quality degradation when displaying an image using a plurality of regions. As a result, the display image quality of the entire panel can be improved.

  In addition, according to the present embodiment, even when a plurality of small display panels each having a power supply driving unit are combined and divided driving is performed, the image quality around the connecting unit of the panels is not deteriorated. Screening can be performed easily.

  In the present embodiment, each power supply driving unit P10 is configured to supply the power supply voltage to the corresponding independent power supply region (for example, the first power supply region) in the lower electrode layer 402BT of FIG. 5, but is not limited thereto. Never happen.

  For example, the configuration of the upper electrode layer 407UD in FIG. 6 may be the same as the configuration of the lower electrode layer 402BT, and the lower electrode layer 402BT may be a ground layer. That is, the upper electrode and the lower electrode in the light emitting element EL1 may be an anode and a cathode, respectively. In this case, a plurality of anodes are formed in the upper electrode layer 407UD.

  In this case, each power supply driving unit P10 supplies a power supply voltage to the corresponding independent power supply region in the upper electrode layer 407UD. In other words, power supply drive units P10.1, P10.2, P10.3, and P10.4 supply power supply voltages to the first, second, third, and fourth power supply regions in upper electrode layer 407UD, respectively.

  Further, in this case, when all the light emitting pixels PX included in the display area 410 are caused to emit light by the above-described processing for displaying the same image with the entire luminance in the display area 410, the power supply driving units P10.1, P10.2, P10.3. , P10.4 are electrically connected to the upper electrode of each light emitting pixel PX included in each of the first, second, third and fourth power supply regions.

  In this case, for example, the power supply driving unit P10.1 is electrically connected to the upper electrode of each light emitting pixel PX in the first power supply region. That is, the power supply drive unit P10.1 is electrically connected to the upper electrode of the light emitting pixel PX when the light emitting pixel PX to emit light is emitted.

  For example, the power supply drive unit P10.2 is electrically connected to the upper electrode of each light emitting pixel PX in the second power supply region. That is, the power supply drive unit P10.2 is electrically connected to the upper electrode of the light emitting pixel PX when the light emitting pixel PX that is the light emission target emits light.

<Variation 1 of the first embodiment>
In the first modification of the present embodiment, an example for dividing the display area 410 into first, second, third, and fourth power supply areas by a boundary line BL that is different from the first embodiment. Show.

  The display device according to the first modification of the present embodiment is the same as the display device 1000 of the first embodiment, and therefore detailed description will not be repeated.

  In the first modification of the present embodiment, the aspect of the boundary line BL is different from that in the first embodiment. Other than that, since it is the same as that of the first embodiment, detailed description will not be repeated.

FIG. 8 is a diagram for explaining the boundary line BL in the first modification of the first embodiment.
FIG. 8A shows a halftone dither matrix DMX as an example. The halftone dot dither matrix is a matrix for making it difficult for a user to see a pseudo contour generated in an image subjected to image processing. FIG. 8A shows a 4 × 4 halftone dot dither matrix DMX as an example.

  Each numerical value (hereinafter also referred to as a dither value) shown in the halftone dot dither matrix DMX is a value added to the pixel value of the corresponding pixel. In the halftone dot dither matrix DMX in FIG. 8A, dither values of “0” to “15” are shown as an example.

  Note that an average value (for example, 7 or 8) of a plurality of dither values indicated in the halftone dither matrix DMX is subtracted from the pixel value of the pixel to which the dither value is added.

  In the first modification of the present embodiment, in the halftone dither matrix DMX, as an example, each of four positions corresponding to four dither values having small values is used for the shape of the boundary line BL.

  FIG. 8B shows an example of the boundary display area BR. It is a figure which expands and shows a part of 2. FIG. FIG. 8B also shows some of the plurality of light emitting pixels PX.

  As shown in FIG. 8B, the boundary line BL. The shape of 2 corresponds to the positions of “3”, “0”, “2”, and “1” shown in the halftone dot dither matrix DMX in FIG.

  For every four columns in the luminescent pixel matrix, the boundary line BL. The shape of 2 is repeated.

  In FIG. 8B, the boundary line BL. Each light emitting pixel PX above 2 is a pixel in the first power supply region described above. Boundary line BL. Each light emitting pixel PX below 2 is a pixel in the third power supply region described above. The first power supply region and the third power supply region include a first light emitting pixel PX and a third light emitting pixel PX, respectively. The first light-emitting pixel PX and the third light-emitting pixel PX are supplied (applied) with a power supply voltage from the power supply drive unit P10.1 and the power supply drive unit P10.3, respectively.

  In other words, the boundary line BL. The shape 2 is a shape determined based on the halftone dither matrix DMX. That is, the boundary display area BR. 2, the plurality of light-emitting pixels PX arranged in the same row of the light-emitting pixel matrix have both the first light-emitting pixel PX and the third light-emitting pixel PX based on the arrangement determined based on the dither matrix. Including.

  Therefore, the boundary display area BR. In the same row in 2, the first light emitting pixel PX and the third light emitting pixel PX are aperiodically arranged.

  Note that the boundary line BL. 1, BL. 3, BL. 4 also has the boundary line BL. Suppose that it is the same as the shape of 2.

  In this case, the boundary display area BR. 3 is a boundary display area BR. 2 includes a plurality of light emitting pixels PX arranged in the same row of the light emitting pixel matrix. Further, the boundary display area BR. 2, the boundary display area BR. The plurality of light emitting pixels PX arranged in the same row in 3 includes both the second light emitting pixels PX and the fourth light emitting pixels PX based on the arrangement determined based on the dither matrix.

  Therefore, the boundary display area BR. 3, the second light-emitting pixels PX and the fourth light-emitting pixels PX are arranged aperiodically.

  In this case, the boundary display area BR. 1 is a boundary display area BR. 2 includes a plurality of light emitting pixels PX arranged in the same column instead of the same row. Further, the boundary display area BR. 2, the boundary display area BR. The plurality of light emitting pixels PX arranged in the same column in 1 includes both the first light emitting pixels PX and the second light emitting pixels PX based on the arrangement determined based on the dither matrix. Therefore, the boundary display area BR. In the same column within 1, the first light-emitting pixels PX and the second light-emitting pixels PX are arranged aperiodically.

  The boundary display area BR. 4 represents the boundary display area BR. 1 includes a plurality of light emitting pixels PX arranged in the same column. In addition, the boundary display area BR. 1, the boundary display area BR. The plurality of light emitting pixels PX arranged in the same column in 4 includes both the third light emitting pixels PX and the fourth light emitting pixels PX based on the arrangement determined based on the dither matrix. Therefore, the boundary display area BR. In the same column in 4, the third light emitting pixel PX and the fourth light emitting pixel PX are arranged aperiodically.

  Note that the process for displaying an image in display area 410 is the same as that in the first embodiment, and thus detailed description will not be repeated.

  As described above, also in the first modification of the present embodiment, the same effect as in the first embodiment can be obtained.

  In the first modification of the present embodiment, the shape of each boundary line BL is determined using a halftone dot dither matrix DMX for making it difficult to see the pseudo contour in the image. Therefore, in the first modification of the present embodiment, in each image displayed in the display area 410, the boundary line BL is caused by a difference in luminance near each boundary line BL in the image displayed in the first embodiment. The presence of the warped line is difficult for the user to visually recognize.

  That is, according to the first modification of the present embodiment, it is possible to further suppress the image quality degradation of the image when the image is displayed using a plurality of regions, as compared with the first embodiment.

  In the first modification of the present embodiment, the shape of each boundary line BL is determined using a 4 × 4 halftone dot dither matrix, but is not limited to this. The shape of each boundary line BL may be determined using a large halftone dot dither matrix.

  Further, the shape of each boundary line BL may be determined using a dither matrix of another method.

<Second Embodiment>
In the first embodiment, the configuration of the display panel in the case where the display panel is an active matrix panel has been described. In this embodiment, a structure of a display panel in the case where the display panel is a passive matrix panel will be described.

  FIG. 9 is a block diagram illustrating a configuration of a display device 1000A according to the second embodiment. As shown in FIG. 9, the display device 1000A includes a control circuit 100, data line driving circuits 210 and 220, scanning line driving circuits 310A and 320A, and a display panel 400A.

  The control circuit 100 controls the data line driving circuits 210 and 220 and the scanning line driving circuits 310A and 320A.

  The scanning line driving circuit 310A includes power supply driving units P11.1 and P11.3. The scanning line drive circuit 320A includes power supply drive units P11.2 and P11.4. Each of the power supply drive units P11.1, P11.2, P11.3, and P11.4 is an IC (Integrated Circuit) manufactured to have the same electrical characteristics.

  The control circuit 100 controls the power supply drive units P11.1, P11.2, P11.3, and P11.4.

  The power supply drive units P11.1, P11.2, P11.3, and P11.4 are for supplying a power supply voltage in the same manner as the power supply drive units P10.1, P10.2, P10.3, and P10.4 in FIG. Is the power source. Hereinafter, each of the power supply drive units P11.1, P11.2, P11.3, and P11.4 is also referred to as a power supply drive unit P11.

  The display panel 400A is a passive matrix display panel. The display panel 400A is an organic EL panel using an organic EL (Electro Luminescence) element.

  The display panel 400A is not limited to the organic EL panel, and may be a display panel of another type such as a liquid crystal panel.

  Display panel 400A includes a display area 410A for displaying an image. The display area 410A includes a plurality of light emitting pixels PX. The plurality of light emitting pixels PX are arranged in a matrix. That is, the plurality of light emitting pixels PX form a matrix (hereinafter referred to as a light emitting pixel matrix) of m (an integer of 2 or more) rows n (an integer of 2 or more) columns. Each of the plurality of light emitting pixels PX emits light according to a signal supplied from the outside.

  In the following, the light emitting pixel PX in the u (natural number) row t (natural number) column in the light emitting pixel matrix is also referred to as the light emitting pixel PX [t, u].

  The display panel 400A is electrically connected to the scanning line driving circuit 310A by m scanning lines CL. Each of the m scanning lines CL is electrically connected to a plurality of light emitting pixels PX arranged in each of m rows in the light emitting pixel matrix. The power supply driving unit P11.1 is electrically connected to a part of the m scanning lines CL. The power supply driving unit P11.3 is electrically connected to a part of the m scanning lines CL.

  The display panel 400A is electrically connected to the scanning line driving circuit 320A by m scanning lines CL. Each of the m scanning lines CL is electrically connected to a plurality of light emitting pixels PX arranged in each of m rows in the light emitting pixel matrix. The power supply driver P11.2 is electrically connected to a part of the m scanning lines CL. The power supply driving unit P11.4 is electrically connected to a part of the m scanning lines CL.

  The display panel 400A is electrically connected to the data line driving circuit 210 by n data lines DL. Each of the n data lines DL is electrically connected to a plurality of light emitting pixels PX arranged in each of n columns in the light emitting pixel matrix.

  The display panel 400A is electrically connected to the data line driving circuit 220 by n data lines DL. Each of the n data lines DL is electrically connected to a plurality of light emitting pixels PX arranged in each of n columns in the light emitting pixel matrix.

  FIG. 10 is a diagram for explaining the display area 410A. In FIG. 10, for the sake of explanation, the power supply drive units P11.1, P11.2, P11.3, and P11.4 are shown.

  Display area 410A includes display area DRA. 1, DRA. 2, DRA. 3, DRA. 4 and the boundary display area BRA. 1, BRA. 2, BRA. 3, BRA. 4 is included.

  That is, the display area 410A includes the boundary display area BRA. 1, BRA. 2, BRA. 3, BRA. 4, the display area DRA. 1, DRA. 2, DRA. 3, DRA. Divided into four. The display area 410A is not limited to four display areas, and may be divided into five or more display areas.

  Border display area BRA. 1 is a display area DRA. 1 and the display area DRA. Between the two. Border display area BRA. 2 is a display area DRA. 1 and the display area DRA. 3 is arranged. Border display area BRA. 3 is a display area DRA. 2 and display area DRA. 4 is arranged. Border display area BRA. 4 is a display area DRA. 3 and the display area DRA. 4 is arranged.

  Display area DRA. 1, DRA. 2, DRA. 3, DRA. 4 and the boundary display area BRA. 1, BRA. 2, BRA. 3, BRA. 4 are on the same plane.

  Display area DRA. 1, DRA. 2, DRA. 3, DRA. Each of 4 includes a plurality of light emitting pixels PX arranged in a matrix.

  Border display area BRA. 1, BRA. Each of 4 includes a plurality of light emitting pixels PX arranged in the vertical direction. That is, the boundary display area BRA. 1, BRA. Each of 4 is a region in which a plurality of light emitting pixels PX are arranged to form one or more columns.

  Border display area BRA. 2, BRA. Each of 3 includes a plurality of light emitting pixels PX arranged in the horizontal direction. That is, the boundary display area BRA. 2, BRA. Each of 3 is an area in which a plurality of light emitting pixels PX are arranged to form one or more rows.

  Border display area BRA. 1, BRA. Each of 4 is provided along the vertical direction. Border display area BRA. 2, BRA. Each of 3 is provided along the horizontal direction.

  In the following, the display area DRA. 1, DRA. 2, DRA. 3, DRA. Each of 4 is also referred to as a display area DRA. In the following, the boundary display area BRA. 1, BRA. 2, BRA. 3, BRA. Each of 4 is also referred to as a boundary display area BRA.

  Note that the light-emitting pixel PX in the present embodiment has the same configuration as the light-emitting pixel PX shown in FIG.

  Display area DRA. 1, DRA. 2, DRA. 3, DRA. Each of 4 is provided with a plurality of scanning lines CL. Each of the plurality of scanning lines CL is linearly arranged in the horizontal direction in association with each light emitting pixel row in the light emitting pixel matrix in the corresponding display area DRA.

  In addition, the display area DRA. 1, DRA. 2, DRA. 3, DRA. Each of 4 is provided with a plurality of data lines DL. Each of the plurality of data lines DL is linearly arranged in the vertical direction in association with each light emitting pixel column in the light emitting pixel matrix in the corresponding display area DRA.

  The power supply drive units P11.1, P11.2, P11.3, and P11.4 are displayed on the display area DRA. 1, DRA. 2, DRA. 3, DRA. 4 is a power supply for supplying a power supply voltage to 4. That is, the display area DRA. 1, DRA. 2, DRA. 3, DRA. Each light emitting pixel PX in each of 4 is supplied with a power supply voltage from an independent different power supply driving unit P11.

  In the following, the power supply drive unit P11. The scanning line CL that is electrically connected to y (natural number) and is in the x (natural number) row in the light-emitting pixel matrix is also referred to as scanning line CL [y, x]. Hereinafter, the data line DL electrically connected to the data line driver circuit 210 is also referred to as a data line DL [1]. Hereinafter, the data line DL electrically connected to the data line driving circuit 220 is also referred to as a data line DL [2].

  FIG. 11 shows, as an example, a boundary display area BRA. In the second embodiment. It is a figure which expands and shows a part of 1. FIG. FIG. 11 also shows some of the plurality of light emitting pixels PX.

  Referring to FIGS. 10 and 11, for example, scanning line CL [1, x (natural number)] is electrically connected to power supply drive unit P11.1. That is, the scanning line CL [1, x (natural number)] is a power supply line to which a power supply voltage is supplied from the power supply driving unit P11.1. Further, for example, the scanning line CL [1,2] is electrically connected to the power supply driving unit P11.1 and is the second scanning line in the light emitting pixel matrix.

  Further, for example, the scanning line CL [2, x (natural number)] is electrically connected to the power supply driving unit P11.2. Further, for example, the scanning line CL [2, 2] is electrically connected to the power supply driving unit P11.2 and is the second scanning line in the light emitting pixel matrix.

  FIG. 12 shows, as an example, the boundary display area BRA. It is a figure which expands and shows a part of 2. FIG. FIG. 12 also shows some of the plurality of light emitting pixels PX.

  Referring to FIGS. 9, 10, and 12, for example, data line DL [1] is electrically connected to data line driving circuit 210. The data line DL [2] is electrically connected to the data line driving circuit 220.

  Referring to FIGS. 10, 11 and 12, boundary display area BRA. 1, BRA. 2, BRA. 3, BRA. 4 are boundary lines BLA. 1, BLA. 2, BLA. 3, BLA. 4 is included. Boundary line BLA. 1, BLA. 2, BLA. 3, BLA. Each of 4 is a boundary line for specifying a region including a plurality of light emitting pixels PX to which a power supply voltage is supplied from the same power supply driving unit P11. Boundary line BLA. 1, BLA. 2, BLA. 3, BLA. Each of 4 is non-linear.

  Boundary line BLA. 1, BLA. 2, BLA. 3, BLA. Each shape of 4 is the same. Note that the boundary line BLA. 1, BLA. 2, BLA. 3, BLA. Each shape of 4 may be different.

  In the following, the boundary line BLA. 1, BLA. 2, BLA. 3, BLA. Each of 4 is also expressed as a boundary line BLA.

  Note that the shape of the boundary line BLA is not limited to a shape in which convex portions for one light emitting pixel PX are repeated, as shown in FIGS. 11 and 12. The shape of the boundary line BLA may be a shape in which convex portions for two or more light emitting pixels PX are repeated.

  Boundary line BLA. 1 and the boundary line BLA. 2 and the upper left area of the display area 410A is an area to which a power supply voltage is supplied from the power supply driver P11.1 via the scanning line CL (hereinafter referred to as a first power supply area A). ). That is, the power supply voltage is supplied from the power supply drive unit P11.1 to each light emitting pixel PX in the first power supply region A.

  In this case, the first power supply area A includes the display area DRA. 1 and the boundary display area BRA. 1 and the boundary display area BRA. 2 is a region including a part of 2.

  Hereinafter, the light emitting pixel PX in the first power supply region A to which the power supply voltage is supplied (applied) from the power supply driving unit P11.1 is also referred to as the first light emitting pixel PXA. The first light emitting pixel PXA is electrically connected to the scanning line CL [1, x] and the data line DL [1], and the power supply voltage is supplied from the power supply driving unit P11.1 via the scanning line CL [1, x]. Supplied (applied). That is, the first light emitting pixel PXA is electrically connected to the power supply driving unit P11.1.

  Boundary line BLA. 1 and the boundary line BLA. 3 and the upper right region in the display region 410A is a region to which a power supply voltage is supplied from the power supply driver P11.2 (hereinafter referred to as a second power supply region A). That is, the power supply voltage is supplied from the power supply drive unit P11.2 to each light emitting pixel PX in the second power supply region A.

  In this case, the second power supply area A includes the display area DRA. 2 and the boundary display area BRA. 1 and the boundary display area BRA. 3 is a region including a part of 3.

  Hereinafter, the light emitting pixels PX in the second power supply region A to which the power supply voltage is supplied (applied) from the power supply driving unit P11.2 are also referred to as second light emitting pixels PXA. The second light emitting pixel PXA is electrically connected to the scanning line CL [2, x] and the data line DL [1], and the power supply voltage is supplied from the power supply driving unit P11.2 through the scanning line CL [2, x]. Supplied (applied). That is, the second light emitting pixel PXA is electrically connected to the power supply driver P11.2.

  Boundary line BLA. 2 and the boundary line BLA. 4 and the lower left region in the display region 410A is a region to which a power supply voltage is supplied from the power supply drive unit P11.3 (hereinafter referred to as a third power supply region A). That is, the power supply voltage is supplied from the power supply driving unit P11.3 to each light emitting pixel PX in the third power supply region A.

  In this case, the third power supply area A is the display area DRA. 3 and the boundary display area BRA. 2 and the boundary display area BRA. 4 is a region including a part of 4.

  Hereinafter, the light emitting pixel PX in the third power supply region A to which the power supply voltage is supplied (applied) from the power supply driving unit P11.3 is also referred to as a third light emitting pixel PXA. The third light emitting pixel PXA is electrically connected to the scanning line CL [3, x] and the data line DL [2], and the power supply voltage is supplied from the power supply driving unit P11.3 via the scanning line CL [3, x]. Supplied (applied). That is, the third light emitting pixel PXA is electrically connected to the power supply driving unit P11.3.

  Boundary line BLA. 3 and the boundary line BLA. 4 and the lower right region in the display region 410A is a region to which a power supply voltage is supplied from the power supply drive unit P11.4 (hereinafter referred to as a fourth power supply region A). That is, each light emitting pixel PX in the fourth power supply region A is supplied with the power supply voltage from the power supply drive unit P11.4.

  In this case, the fourth power supply area A includes the display area DRA. 4 and the boundary display area BRA. 3 and the boundary display area BRA. 4 is a region including a part of 4.

  Hereinafter, the light emitting pixel PX in the fourth power supply region A to which the power supply voltage is supplied (applied) from the power supply driving unit P11.4 is also referred to as a fourth light emitting pixel PXA. The fourth light emitting pixel PXA is electrically connected to the scanning line CL [4, x] and the data line DL [2], and the power supply voltage is supplied from the power supply driving unit P11.4 through the scanning line CL [4, x]. Supplied (applied). That is, the fourth light emitting pixel PXA is electrically connected to the power supply driving unit P11.4.

Each of the first, second, third and fourth power supply areas A is an area for displaying an image.
Border display area BRA. 1 includes the boundary display area BRA. Two data lines DL [1] are arranged for each light emitting pixel column in one. In the following, the boundary display area BRA. One of the two data lines DL [1] for each column in 1 is referred to as a first data line DL [1]. In the following, the boundary display area BRA. The other of the two data lines DL [1] for each column in 1 is referred to as a second data line DL [1].

  Border display area BRA. 1 is connected to the boundary display area BRA. It is shaped so as to be electrically connected only to the plurality of first light emitting pixels PXA arranged in the light emitting pixel column within 1, and is arranged in the vertical direction. Border display area BRA. 1 is connected to the boundary display area BRA. It is shaped so as to be electrically connected only to the plurality of second light emitting pixels PXA arranged in the light emitting pixel column in 1, and is arranged in the vertical direction.

  In addition, the boundary display area BRA. 1 includes the boundary display area BRA. A scanning line CL [1, x] or a scanning line CL [2, x] is arranged for each light emitting pixel row in one. Border display area BRA. 1 in the boundary display area BRA. It is electrically connected to one or more first light emitting pixels PXA arranged in the light emitting pixel row within 1, and is arranged in the horizontal direction. Border display area BRA. 1 in the boundary display area BRA. It is electrically connected to one or more second light emitting pixels PXA arranged in the light emitting pixel row within 1, and is arranged in the horizontal direction.

  Border display area BRA. 2 includes the boundary display area BRA. The data line DL [1] or the data line DL [2] is arranged for each light emitting pixel column in 2. Border display area BRA. 2 is connected to the boundary display area BRA. 2 is electrically connected to one or more first light-emitting pixels PXA arranged in the light-emitting pixel column in 2 and arranged in the vertical direction. Border display area BRA. 2 is connected to the boundary display area BRA. 2 is electrically connected to one or more third light emitting pixels PXA arranged in the light emitting pixel column in 2 and arranged in the vertical direction.

  In addition, the boundary display area BRA. 2 includes the boundary display area BRA. A scanning line CL [1, x] and a scanning line CL [3, x] are arranged for each light emitting pixel row in 2. Border display area BRA. 2 in the boundary display area BRA. 2 is shaped so as to be electrically connected to only the plurality of first light emitting pixels PXA arranged in the light emitting pixel row in 2 and is arranged in the horizontal direction. Border display area BRA. 2 in the boundary display region BRA. 2 is shaped so as to be electrically connected only to the plurality of third light emitting pixels PXA arranged in the light emitting pixel row in 2, and is arranged in the horizontal direction.

  Border display area BRA. 3 includes the boundary display area BRA. The data line DL [1] or the data line DL [2] is arranged for each light emitting pixel column in the line 3. Border display area BRA. 3 is connected to the boundary display area BRA. 3 is electrically connected to one or more second light-emitting pixels PXA arranged in the light-emitting pixel column in the line 3, and is arranged in the vertical direction. Border display area BRA. 3 is connected to the boundary display area BRA. 3 are electrically connected to one or more fourth light-emitting pixels PXA arranged in the light-emitting pixel column in the line 3, and are arranged in the vertical direction.

  In addition, the boundary display area BRA. 3 includes the boundary display area BRA. The scanning line CL [2, x] and the scanning line CL [4, x] are arranged for each light emitting pixel row in the line 3. Border display area BRA. 3 in the boundary display area BRA. 3 is configured to be electrically connected to only the plurality of second light emitting pixels PXA arranged in the light emitting pixel rows in the line 3, and is arranged in the horizontal direction. Border display area BRA. 3 in the boundary display area BRA. 3 is configured to be electrically connected to only the plurality of fourth light emitting pixels PXA arranged in the light emitting pixel rows in 3, and is arranged in the horizontal direction.

  Border display area BRA. 4 includes the boundary display area BRA. Two data lines DL [2] are arranged for each light emitting pixel column in 4. In the following, the boundary display area BRA. One of the two data lines DL [2] for each column in 4 is referred to as a first data line DL [2]. In the following, the boundary display area BRA. The other of the two data lines DL [2] for each column in 4 is referred to as a second data line DL [2].

  Border display area BRA. 4 is connected to the boundary display area BRA. 4 is shaped so as to be electrically connected to only the plurality of third light emitting pixels PXA arranged in the light emitting pixel row in 4 and is arranged in the vertical direction. Border display area BRA. 4 is connected to the boundary display area BRA. 4 is shaped so as to be electrically connected to only the plurality of third light emitting pixels PXA arranged in the light emitting pixel row in 4 and is arranged in the vertical direction.

  In addition, the boundary display area BRA. 4 includes the boundary display area BRA. The scanning line CL [3, x] or the scanning line CL [4, x] is arranged for each light emitting pixel row in the line 4. Border display area BRA. 4 in the boundary display area BRA. 4 are electrically connected to one or more third light emitting pixels PXA arranged in the light emitting pixel row in 4 and arranged in the horizontal direction. Border display area BRA. 4 in the boundary display region BRA. 4 are electrically connected to one or more fourth light emitting pixels PXA arranged in the light emitting pixel row in 4 and arranged in the horizontal direction.

  In the first power supply region A, w (natural number less than m) scan lines CL [1, x] and v (natural number less than n) data lines DL [1] are arranged. In the second power supply region A, w scanning lines CL [2, x] and v data lines DL [1] are arranged.

  In the third power supply region A, w scanning lines CL [3, x] and v data lines DL [2] are arranged. In the fourth power supply region, w scanning lines CL [4, x] and v data lines DL [2] are arranged.

  The numbers of data lines DL and scanning lines CL arranged in each of the first, second, third, and fourth power supply regions A are not the same and may be different.

  Each of the scanning lines CL [1, x], CL [2, x], CL [3, x], CL [4, x] is electrically disconnected from each other. The data lines DL [1] and DL [2] are not electrically connected to each other.

  Hereinafter, each of the first, second, third, and fourth power supply regions A is also referred to as an independent power supply region A. As described above, each of the first, second, third, and fourth power supply areas A is an area for displaying an image. Therefore, the independent power supply area A is an area for displaying an image.

  Boundary line BLA. 1, BLA. 2, BLA. 3, BLA. Each of 4 is also a line for specifying each of the first, second, third, and fourth power supply regions A. Further, the power drive units P11.1, P11.2, P11.3, and P11.4 are power supplies for supplying a power supply voltage to the first, second, third, and fourth power supply regions A, respectively. That is, the power supply drive units P11.1, P11.2, P11.3, and P11.4 are power supplies associated with the first, second, third, and fourth power supply regions A, respectively. That is, each light emitting pixel PX in each of the first, second, third, and fourth power supply regions A is supplied with a power supply voltage from an independent power supply driving unit P11.

  In FIG. 11, for example, the light emitting pixel PX [t, 1] is the first light emitting pixel PXA. The light-emitting pixel PX [t, 1] is supplied (applied) with a power supply voltage from the power supply driving unit P11.1. The light emitting pixel PX [t + 1, 1] is the second light emitting pixel PXA. The light-emitting pixel PX [t + 1, 1] is supplied (applied) with a power supply voltage from the power supply driving unit P11.2.

The scanning line CL [1,1] and the scanning line CL [2,1] are not electrically connected.
For example, the boundary display area BRA. 1 includes a plurality of light emitting pixels PX arranged in the same column as an example. Border display area BRA. The plurality of light emitting pixels PX arranged in the same column in 1 includes both one or more first light emitting pixels PXA and one or more second light emitting pixels PXA.

  Specifically, the boundary display area BRA. In the same column in 1, the first light emitting pixels PXA and the second light emitting pixels PXA are alternately arranged. That is, the boundary display area BRA. 1, the first light emitting pixel PXA and the second light emitting pixel PXA are periodically arranged.

  In FIG. 12, for example, the luminescent pixel PX [1, u] is the first luminescent pixel PXA. The light-emitting pixel PX [1, u] is supplied (applied) with a power supply voltage from the power supply drive unit P11.1. The light emitting pixel PX [1, u + 1] is the third light emitting pixel PXA. The light-emitting pixel PX [1, u + 1] is supplied (applied) with the power supply voltage from the power supply driving unit P11.3.

The data line DL [1] and the data line DL [2] are electrically disconnected.
For example, the boundary display area BRA. 2 includes, as an example, a plurality of light emitting pixels PX arranged in the same row. Border display area BRA. The plurality of light emitting pixels PX arranged in the same row in 2 includes both one or more first light emitting pixels PXA and one or more third light emitting pixels PXA.

  Specifically, the boundary display area BRA. 2, the first light emitting pixels PXA and the third light emitting pixels PXA are alternately arranged. That is, the boundary display area BRA. 2, the first light emitting pixel PXA and the third light emitting pixel PXA are periodically arranged.

  The boundary display area BRA. 3 is a boundary display area BRA. 2 includes a plurality of light emitting pixels PX arranged in the same row. Further, the boundary display area BRA. 2, the boundary display area BRA. The plurality of light emitting pixels PX arranged in the same row in 3 includes both one or more second light emitting pixels PXA and one or more fourth light emitting pixels PXA.

  The boundary display area BRA. 4 is a boundary display area BRA. 1 includes a plurality of light emitting pixels PX arranged in the same column. Further, the boundary display area BRA. 1, the boundary display area BRA. The plurality of light emitting pixels PX arranged in the same column in 4 includes both one or more third light emitting pixels PXA and one or more fourth light emitting pixels PXA.

  Referring to FIGS. 9, 10, 11, and 12, control circuit 100 has power supply driving units P11.1, P11.2, P11.3, and P11 according to the characteristics of the image displayed on display area 410A. .4 controls the voltage supplied. Hereinafter, an image displayed in the display area 410A is referred to as a display image.

  Specifically, for example, the control circuit 100 decreases the voltage level supplied by the power supply drive unit P11 corresponding to the independent power supply region A as the portion corresponding to each independent power supply region A in the display image is darker. Control. For example, in the display image, when only the upper left portion is dark, the power supply drive unit P11.1 is controlled so as to reduce only the voltage level supplied by the power supply drive unit P11.1 corresponding to the first power supply region A. Thereby, for example, when the brightness of the display image is low as a whole, the power consumption of the display device 1000A can be reduced.

  In the following, when the state in which the object A is electrically connected to the object B is described, it is simply described that the object A is connected to the object B.

(Configuration of light-emitting pixels)
Next, an example of the configuration of the light emitting pixel PX in the present embodiment is shown.

  FIG. 13 is a diagram illustrating an example of the configuration of the light-emitting pixel PX corresponding to the first row and the t-th column in the light-emitting pixel matrix as an example. That is, FIG. 13 is a diagram illustrating an example of a configuration of the light emitting pixel PX [t, 1].

  Referring to FIG. 13, the light emitting pixel PX is configured by a light emitting element EL1. Since light emitting element EL1 in FIG. 13 is the same as light emitting element EL1 in FIG. 7, detailed description thereof will not be repeated. That is, the light emitting element EL1 is an organic EL element.

  The anode of the light emitting element EL1 can be constituted by the scanning line CL [1,1] itself. The cathode of the light emitting element EL1 can be constituted by the data line DL [1] itself.

  As described above, the anode and the cathode of the light emitting element EL1 are the anode 402 (lower electrode) and the cathode 407 (upper electrode), respectively.

  Here, the light emitting pixel PX [t, 1] is a light emitting pixel in the first power supply region A. Therefore, the anode (anode 402 (lower electrode)) of the light-emitting element EL1 is electrically connected to the power supply driving unit P11.1 via the scanning line CL [1,1].

  Note that the luminescent pixel PX [t + 1, 1] corresponding to the first row t + 1 column shown in FIG. 13 is similar to the luminescent pixel PX [t, 1] in the scanning line CL [2, 1] and the data line DL [ 2]. Since the configuration of the luminescent pixel PX [t + 1, 1] is similar to the configuration of the luminescent pixel PX [t, 1], detailed description will not be repeated.

  Referring to FIG. 10 again, display panel 400A in the present embodiment is a passive matrix display panel, and thus display panel 400A has the following configuration.

  Each of the plurality of light emitting pixels PX included in the display area 410A includes a light emitting element EL1 that is an organic EL element. The light emitting element EL1 includes a cathode 407 (upper electrode) and an anode 402 (lower electrode). That is, each of the plurality of light emitting pixels PX included in the display area 410A includes the cathode 407 (upper electrode) and the anode 402 (lower electrode).

  The first power supply area A includes a plurality of first light emitting pixels PXA. That is, the first power supply region A includes a plurality of cathodes 407 (upper electrodes) and anodes 402 (lower electrodes).

  Therefore, in the first power supply region A, the plurality of anodes 402 (lower electrodes) arranged in the same row of the light emitting pixel matrix are electrically connected to each other to form the scanning line CL [1, x]. To do. That is, each of the plurality of anodes 402 (lower electrodes) configuring the scanning line CL [1, x] is provided in common to the plurality of first light emitting pixels PXA arranged in the same row. In this case, the power supply driving unit P11.1 is electrically connected to a plurality of anodes 402 (lower electrodes) constituting the scanning line CL [1, x].

  The second power supply area A includes a plurality of second light emitting pixels PXA. That is, the second power supply region A includes a plurality of cathodes 407 (upper electrodes) and anodes 402 (lower electrodes).

  Accordingly, in the second power supply region A, the plurality of anodes 402 (lower electrodes) arranged in the same row of the light emitting pixel matrix are electrically connected to each other to form the scanning line CL [2, x]. To do. That is, each of the plurality of anodes 402 (lower electrodes) constituting the scanning line CL [2, x] is provided in common to the plurality of second light emitting pixels PXA arranged in the same row. In this case, the power supply drive unit P11.2 is electrically connected to a plurality of anodes 402 (lower electrodes) constituting the scanning line CL [2, x].

  Note that the upper electrode and the lower electrode in the light emitting element EL1 may be an anode and a cathode, respectively.

  In this case, in the first power supply region A, the plurality of upper electrodes arranged in the same row of the light emitting pixel matrix are electrically connected to each other, thereby forming the scanning line CL [1, x]. That is, each of the plurality of upper electrodes constituting the scanning line CL [1, x] is provided in common to the plurality of first light emitting pixels PXA arranged in the same row. In this case, the power supply drive unit P11.1 is electrically connected to a plurality of upper electrodes constituting the scanning line CL [1, x].

  In this case, in the second power supply region A, the plurality of upper electrodes arranged in the same row of the light emitting pixel matrix are electrically connected to each other, thereby forming the scanning line CL [2, x]. . In other words, each of the plurality of upper electrodes constituting the scanning line CL [2, x] is provided in common to the plurality of second light emitting pixels PXA arranged in the same row. In this case, the power supply driving unit P11.2 is electrically connected to a plurality of upper electrodes that configure the scanning line CL [2, x].

  In the first power supply region A, the plurality of cathodes 407 (upper electrodes) arranged in the same column of the light emitting pixel matrix are electrically connected to each other to form the data line DL [1]. That is, each of the plurality of cathodes 407 (upper electrodes) constituting the data line DL [1] is provided in common to the plurality of first light emitting pixels PXA arranged in the same column.

  In the second power supply region A, the plurality of cathodes 407 (upper electrodes) arranged in the same column of the light emitting pixel matrix are electrically connected to each other to form the data line DL [1]. That is, each of the plurality of cathodes 407 (upper electrodes) constituting the data line DL [1] is provided in common to the plurality of second light emitting pixels PXA arranged in the same column.

  Note that the upper electrode and the lower electrode in the light emitting element EL1 may be an anode and a cathode, respectively.

  In this case, in the first power supply region A, the plurality of lower electrodes arranged in the same column of the light emitting pixel matrix are electrically connected to each other, thereby configuring the data line DL [1]. That is, each of the plurality of lower electrodes constituting the data line DL [1] is provided in common to the plurality of first light emitting pixels PXA arranged in the same column.

  In this case, in the second power supply region A, the plurality of lower electrodes arranged in the same column of the light emitting pixel matrix are electrically connected to each other, thereby forming the data line DL [2]. That is, each of the plurality of lower electrodes constituting the data line DL [2] is provided in common to the plurality of second light emitting pixels PXA arranged in the same column.

  In addition, the boundary display area BRA. 1 includes a plurality of first light-emitting pixels PXA and second light-emitting pixels PXA in the same column. That is, the boundary display area BRA. In the same column in 1, the anode 402 (lower electrode) of the first light emitting pixel PXA and the anode 402 (lower electrode) of the second light emitting pixel PXA are not connected. In addition, the boundary display area BRA. In the same column in 1, the cathode 407 (upper electrode) of the first light emitting pixel PXA and the cathode 407 (upper electrode) of the second light emitting pixel PXA are not connected.

The boundary display area BRA. 4 is also the boundary display area BRA. 1 has the same configuration.
In addition, the boundary display area BRA. 2 includes a plurality of first light-emitting pixels PXA and third light-emitting pixels PXA in the same row. That is, the boundary display area BRA. 2, the anode 402 (lower electrode) of the first light emitting pixel PXA and the anode 402 (lower electrode) of the third light emitting pixel PXA are not connected. In addition, the boundary display area BRA. 2, the cathode 407 (upper electrode) of the first light emitting pixel PXA and the cathode 407 (upper electrode) of the third light emitting pixel PXA are not connected.

  The boundary display area BRA. 3 is also the boundary display area BRA. 2 has the same configuration.

(Image display processing)
Next, a process for displaying an image in the display area 410A will be described. It is assumed that the display image displayed in the display area 410A is the above-described image having the same overall luminance.

  In order to display an image in the display area 410A, each of the first power supply area A, the second power supply area A, the third power supply area A, and the fourth power supply area A included in the display area 410A is independently and simultaneously performed. Display control is performed.

  For example, in the first power supply area A, the control circuit 100 controls the power supply drive unit P11.1 and the data line drive circuit 210 to display an image in the first power supply area A. Since the control is a well-known display control by the passive matrix method, detailed description will not be repeated. In this case, the first power supply region A controls a plurality of corresponding scanning lines CL.

  In the second power supply region A, the control circuit 100 controls the power supply drive unit P11.2 and the data line drive circuit 210 to display an image in the second power supply region A. In the third power supply area A, the control circuit 100 controls the power supply drive unit P11.3 and the data line drive circuit 220 to display an image in the third power supply area A. In the fourth power supply region A, the control circuit 100 controls the power supply drive unit P11.4 and the data line drive circuit 220 to display an image in the fourth power supply region A.

  In each of the second power supply region A, the third power supply region A, and the fourth power supply region A, the same control as the control performed on the first power supply region A is performed, and thus detailed description will not be repeated.

  By performing well-known display control for each of the first power supply area A, the second power supply area A, the third power supply area A, and the fourth power supply area A, the display area 410A has an image of one frame (with the same overall luminance). Image).

  In this case, since each boundary line BL in the display area 410A is non-straight, the same effect as in the first embodiment can be obtained in this embodiment. That is, it is possible to suppress image quality degradation when displaying an image using a plurality of regions.

  Note that the shape of the boundary line BLA in the present embodiment may be a shape determined based on the halftone dither matrix DMX, as in the first modification of the first embodiment.

<Third Embodiment>
The present embodiment is characterized by the connection configuration of the light emitting pixels PX.

  Since the display device in the present embodiment is similar to display device 1000 in FIG. 1, detailed description will not be repeated.

  In addition, the configuration of the display area included in the display panel in the present embodiment is the same as the configuration of display area 410 in FIG. 2, and thus detailed description will not be repeated. That is, the display area 410 includes the display area DR. 1, DR. 2, DR. 3, DR. 4 and the boundary display area BR. 1, BR. 2, BR. 3, BR. 4 is included.

  The display area 410 includes the first power supply area, the second power supply area, the third power supply area, and the fourth power supply area described above. Since the first power supply region, the second power supply region, the third power supply region, and the fourth power supply region have been described in the first embodiment, detailed description thereof will not be repeated.

  The display area 410 includes a plurality of light emitting pixels PX, as in the first embodiment. The plurality of light emitting pixels PX are arranged in a matrix. That is, the plurality of light emitting pixels PX form a matrix (hereinafter referred to as a light emitting pixel matrix) of m (an integer of 2 or more) rows n (an integer of 2 or more) columns.

  Note that the light-emitting pixel PX in the present embodiment has the same configuration as the light-emitting pixel PX shown in FIG.

  Further, the present embodiment is characterized in the connection configuration of the light emitting pixels PX in the boundary display region BR.

  In the following, the power supply drive unit P10. The power supply line PL electrically connected to y (natural number), and the power line PL in the x (natural number) column in the light emitting pixel matrix is also referred to as power supply line PL [y, x].

  As in the first embodiment, the boundary display area BR. 1 includes the boundary display area BR. A power supply line PL [1, x] and a power supply line PL [2, x] are arranged for each light emitting pixel column in one. That is, the boundary display area BR. 1, a plurality of light emitting pixels arranged in the same column are provided with a power supply line PL [1, x] and a power supply line PL [2, x] in association with each other. Boundary display area BR. The power supply line PL [1, x] and the power supply line PL [2, x] in 1 are arranged in parallel. In addition, the boundary display area BR. The shape of the power supply line PL [1, x] and the power supply line PL [2, x] in 1 is a linear shape.

  FIG. 14 shows the boundary display area BR. In the third embodiment. It is a figure which expands and shows a part in 1. FIG. 14 shows the boundary display area BR. A part of the plurality of light emitting pixels PX in 1 is also shown.

  The figure showing the light emitting pixels PX [t, u] and PX [t, u + 1] shown in FIG. 14 is a figure that shows the connection relationship of the light emitting element EL1 included in the light emitting pixel PX. Each configuration of the luminescent pixels PX [t, u] and PX [t, u + 1] is, for example, the configuration of the luminescent pixels PX [1, u] in FIG.

  The luminescent pixel PX [t, u] and the luminescent pixel PX [t, u + 1] are the first luminescent pixel PX and the second luminescent pixel PX, respectively. The light emitting pixels PX [t, u] and PX [t, u + 1] are arranged in the same column.

  Referring to FIG. 14, boundary display area BR. 1 includes a power line PL [1, x] and a power line PL [2, x + 1]. The power supply line PL [2, x + 1] is connected to the boundary display area BR. 1 is a power supply line PL [2, x].

  Boundary display area BR. 1, a plurality of light emitting pixels arranged in the same column are provided with a power supply line PL [1, x] and a power supply line PL [2, x + 1] in association with each other.

  The power supply line PL [1, x] is connected to the boundary display area BR. 1 is electrically connected to a plurality of first light-emitting pixels PX arranged in the same column. Specifically, the power supply line PL [1, x] is electrically connected to the drain of the driver element DR1 of FIG. 7 included in each of the plurality of first light emitting pixels PX.

  For example, the power supply line PL [1, x] is electrically connected to the light emitting pixel PX [t, u] which is the first light emitting pixel PX. Further, the power supply line PL [1, x] is electrically connected to the drain of the driver element DR1 of FIG. 7 included in the light emitting pixel PX [t, u] which is the first light emitting pixel PX. The cathode of the light emitting element EL1 included in the light emitting pixel PX [t, u] is electrically connected to the negative power supply line NPL described above.

  The power supply drive unit P10.1 is connected to the boundary display area BR. A power supply voltage is applied to a plurality of first light-emitting pixels PX arranged in the same column in 1.

  The power supply line PL [2, x + 1] is connected to the boundary display area BR. It is electrically connected to a plurality of second light emitting pixels PX arranged in the same column in 1. Specifically, the power supply line PL [2, x + 1] is electrically connected to the drain of the driver element DR1 included in each of the plurality of second light emitting pixels PX.

  For example, the power supply line PL [2, x + 1] is electrically connected to the light emitting pixel PX [t, u + 1] which is the second light emitting pixel PX. Further, the power supply line PL [2, x + 1] is electrically connected to the drain of the driver element DR1 of FIG. 7 included in the light emitting pixel PX [t, u + 1] which is the second light emitting pixel PX. The cathode of the light emitting element EL1 included in the light emitting pixel PX [t, u + 1] is electrically connected to the negative power supply line NPL described above.

  The power supply drive unit P10.2 is connected to the boundary display region BR.2 via the power supply line PL [2, x + 1]. A power supply voltage is applied to a plurality of second light emitting pixels PX arranged in the same column in 1.

  As described above, the boundary display area BR. 1 is connected to the plurality of light emitting pixels PX arranged in the same column as shown in FIG. 1 is similar to the first embodiment in that the boundary line BL. 1 is included.

  Note that the boundary display area BR. 2, BR. 3, BR. 4 includes a boundary display area BR. The configuration is the same as in FIG.

  Therefore, for example, the boundary display area BR. 2, a power supply line PL [1, x] and a power supply line PL [3, x] are provided in association with a plurality of light emitting pixels arranged in the same row. Boundary display area BR. Power line PL [1, x] and power line PL [3, x] in 2 are arranged in parallel. In addition, the boundary display area BR. The shape of the power supply line PL [1, x] and the power supply line PL [3, x] in 2 is a linear shape.

  In this case, the power supply line PL [1, x] is connected to the boundary display area BR. 2 is electrically connected to a plurality of first light emitting pixels PX arranged in the same row. The power supply drive unit P10.1 is connected to the boundary display area BR. A power supply voltage is applied to the plurality of first light emitting pixels PX arranged in the same row in FIG.

  In this case, the power supply line PL [3, x] is connected to the boundary display area BR. 2 is electrically connected to a plurality of third light emitting pixels PX arranged in the same row. The power supply drive unit P10.3 is connected to the boundary display area BR. A power supply voltage is applied to a plurality of third light emitting pixels PX arranged in the same row in 2.

  Therefore, also in this embodiment, since each boundary line BL in the display area 410 is non-linear, as in the first embodiment, the same effect as in the first embodiment can be obtained. That is, it is possible to suppress image quality degradation when displaying an image using a plurality of regions.

<Variation 1 of the third embodiment>
In the first modification of the present embodiment, the shape of the power supply line PL is different from that in the third embodiment. Other than that, it is the same as that of the third embodiment, and the detailed description will not be repeated.

  In the first modification of the present embodiment, the boundary display area BR. 1, a plurality of light emitting pixels arranged in the same column are provided with a power supply line PL [1, x] and a power supply line PL [2, x] in association with each other. Boundary display area BR. The shapes of the power supply line PL [1, x] and the power supply line PL [2, x] in 1 are non-linear.

  15 shows a boundary display area BR. In the first modification of the third embodiment. It is a figure which expands and shows a part in 1. FIG. In FIG. 15, the boundary display area BR. A part of the plurality of light emitting pixels PX in 1 is also shown.

  In FIG. 15, except for the power supply line PL [1, x] and the power supply line PL [2, x + 1] are the same as those described with reference to FIG. 14, detailed description will not be repeated.

  The figure showing the light emitting pixels PX [t, u], PX [t, u + 1] shown in FIG. 15 is a figure that shows the connection relationship of the light emitting element EL1 included in the light emitting pixel PX. Each configuration of the luminescent pixels PX [t, u] and PX [t, u + 1] is, for example, the configuration of the luminescent pixels PX [1, u] in FIG.

  The luminescent pixel PX [t, u] and the luminescent pixel PX [t, u + 1] are the first luminescent pixel PX and the second luminescent pixel PX, respectively.

  Referring to FIG. 15, boundary display area BR. 1 includes a power line PL [1, x] and a power line PL [2, x + 1]. The power supply line PL [2, x + 1] is connected to the boundary display area BR. 1 is a power supply line PL [2, x].

  Boundary display area BR. 1, a plurality of light emitting pixels arranged in the same column are provided with a power supply line PL [1, x] and a power supply line PL [2, x + 1] in association with each other.

  Each shape of the power supply line PL [1, x] and the power supply line PL [2, x + 1] is a shape in which convex portions for one light emitting pixel PX are repeated. That is, each shape of power supply line PL [1, x] and power supply line PL [2, x + 1] is a non-linear shape.

  Each shape of the power supply line PL [1, x] and the power supply line PL [2, x + 1] may be a shape in which convex portions for two or more light emitting pixels PX are repeated.

  The power supply line PL [1, x] is connected to the boundary display area BR. 1 is electrically connected to a plurality of first light-emitting pixels PX arranged in the same column. Specifically, the power supply line PL [1, x] is electrically connected to the drain of the driver element DR1 of FIG. 7 included in each of the plurality of first light emitting pixels PX.

  For example, the power supply line PL [1, x] is electrically connected to the light emitting pixel PX [t, u] which is the first light emitting pixel PX. Further, the power supply line PL [1, x] is electrically connected to the drain of the driver element DR1 of FIG. 7 included in the light emitting pixel PX [t, u] which is the first light emitting pixel PX. The cathode of the light emitting element EL1 included in the light emitting pixel PX [t, u] is electrically connected to the negative power supply line NPL described above.

  The power supply drive unit P10.1 is connected to the boundary display area BR. A power supply voltage is applied to a plurality of first light-emitting pixels PX arranged in the same column in 1.

  The power supply line PL [2, x + 1] is connected to the boundary display area BR. It is electrically connected to a plurality of second light emitting pixels PX arranged in the same column in 1. Specifically, the power supply line PL [2, x + 1] is electrically connected to the drain of the driver element DR1 included in each of the plurality of second light emitting pixels PX.

  For example, the power supply line PL [2, x + 1] is electrically connected to the light emitting pixel PX [t, u + 1] which is the second light emitting pixel PX. Further, the power supply line PL [2, x + 1] is electrically connected to the drain of the driver element DR1 of FIG. 7 included in the light emitting pixel PX [t, u + 1] which is the second light emitting pixel PX. The cathode of the light emitting element EL1 included in the light emitting pixel PX [t, u + 1] is electrically connected to the negative power supply line NPL described above.

  The power supply drive unit P10.2 is connected to the boundary display region BR. A power supply voltage is applied to a plurality of second light emitting pixels PX arranged in the same column in 1.

  As described above, the boundary display area BR. 1 is connected to a plurality of light emitting pixels PX arranged in the same column as shown in FIG. 1 is similar to the first embodiment in that the boundary line BL. 1 is included.

  In the present embodiment, the shapes of the power supply line PL [1, x] and the power supply line PL [2, x + 1] are as shown in FIG. 15 and the connection configuration of the light emitting pixels PX is as described above. Boundary line BL. The shape of 1 can be a shape in which convex portions for two or more light emitting pixels PX are repeated.

  Note that the boundary display area BR. 2, BR. 3, BR. 4 includes a boundary display area BR. The configuration is the same as in FIG.

  Therefore, for example, the boundary display area BR. 2, a power supply line PL [1, x] and a power supply line PL [3, x] are provided in association with a plurality of light emitting pixels arranged in the same row. In addition, the boundary display area BR. The shape of the power line PL [1, x] and the power line PL [3, x] in 2 is a non-linear shape like the power line PL [1, x].

  In this case, the power supply line PL [1, x] is connected to the boundary display area BR. 2 is electrically connected to a plurality of first light emitting pixels PX arranged in the same row. The power supply drive unit P10.1 is connected to the boundary display area BR. A power supply voltage is applied to the plurality of first light emitting pixels PX arranged in the same row in FIG.

  In this case, the power supply line PL [3, x] is connected to the boundary display area BR. 2 is electrically connected to a plurality of third light emitting pixels PX arranged in the same row. The power supply drive unit P10.3 is connected to the boundary display area BR. A power supply voltage is applied to a plurality of third light emitting pixels PX arranged in the same row in 2.

  Therefore, also in the first modification of the present embodiment, the same effect as that of the third embodiment can be obtained.

  In addition, the external view of the display apparatus 1000 and the display apparatus 1000A is a figure shown by FIG.

  As described above, the display device according to the present invention has been described based on the embodiments, but the present invention is not limited to these embodiments. Unless it deviates from the meaning of this invention, the form which carried out various deformation | transformation which those skilled in the art can think to this embodiment, or the structure constructed | assembled combining the component in different embodiment is also contained in the scope of the present invention. .

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  INDUSTRIAL APPLICABILITY The present invention can be used as a display panel that can suppress deterioration in image quality when an image is displayed using a plurality of areas.

BL. 1, BL. 2, BL. 3, BL. 4, BLA. 1, BLA. 2, BLA. 3, BLA. 4 Boundary line BR. 1, BR. 2, BR. 3, BR. 4, BRA. 1, BRA. 2, BRA. 3, BRA. 4 Border display area DR. 1, DR. 2, DR. 3, DR. 4, DRA. 1, DRA. 2, DRA. 3, DRA. 4 display area EL1 light emitting element PBR. 1, PBR. 2, PBR. 3, PBR. 4 Boundary region PL Power line PR. 1, PR. 2, PR. 3, PR. 4 Electrode layer region PX Light-emitting pixels P10.1, P10.2, P10.3, P10.4, P11.1, P11.2, P11.3, P11.4 Power supply drive unit 100 Control circuit 200, 210, 220 Data Line drive circuit 300, 310A, 320A Scan line drive circuit 400, 400A Display panel 402 Anode 402BT Lower electrode layer 407 Cathode 407UD Upper electrode layer 410, 410A Display area 1000, 1000A Display device

Claims (14)

A first display region in which a plurality of light emitting pixels to which a power supply voltage is applied by a first power supply driving unit are arranged in a matrix;
A second display region in which a plurality of light emitting pixels to which a power supply voltage is applied by a second power supply driving unit are arranged in a matrix;
A boundary display region located between the first display region and the second display region, wherein a plurality of light emitting pixels are arranged to form at least one column;
Including
In the boundary display area, a plurality of light emitting pixels arranged in the same column are applied with a power supply voltage by the first power supply driving unit and a power supply voltage by the second power supply driving unit. Including both luminescent pixels,
Display panel. A first display region in which a plurality of light emitting pixels to which a power supply voltage is applied by a first power supply driving unit are arranged in a matrix;
A second display region in which a plurality of light emitting pixels to which a power supply voltage is applied by a second power supply driving unit are arranged in a matrix;
A boundary display region located between the first display region and the second display region, wherein a plurality of light emitting pixels are arranged to form at least one or more rows;
Including
In the boundary display area, a plurality of light emitting pixels arranged in the same row are applied with a power supply voltage by the first power supply driving unit and a power supply voltage by the second power supply driving unit. Including both luminescent pixels,
Display panel. Each light emitting pixel to which a power supply voltage is applied by the first power driver includes a first lower electrode and a first upper electrode,
The first power supply driving unit is electrically connected to the first lower electrode or the first upper electrode at least when the light emitting pixel to be lit emits light,
Each light emitting pixel to which a power supply voltage is applied by the second power driver includes a second lower electrode and a second upper electrode.
The second power supply driving unit is electrically connected to the second lower electrode or the second upper electrode at least when the light emitting pixel to be lit emits light.
The display panel according to claim 1. The first power supply driving unit is electrically connected to the first lower electrode at least when the light emitting pixel to be emitted emits light, and the second power supply driving unit is configured to emit the second lower part at least when the light emitting pixel to be emitted emits light. Electrically connected to the electrode,
Each of the first lower electrode and the second lower electrode constitutes an independent pixel electrode for each light emitting pixel,
The first upper electrode and the second upper electrode constitute a common electrode provided in common to a plurality of light emitting pixels.
The display panel according to claim 3. Each of the first lower electrode, the first upper electrode, the second lower electrode, and the second upper electrode is provided in common to a plurality of light emitting pixels arranged in the same column or the same row,
The first power driver is electrically connected to the first lower electrode, the second power driver is electrically connected to the second lower electrode, or the first power driver is The second power supply driving unit is electrically connected to the second upper electrode and electrically connected to the first upper electrode.
In the same row or the same column in the boundary display region, the first lower electrode and the second lower electrode are electrically disconnected, or the first upper electrode and the second upper electrode Is electrically disconnected,
The display panel according to claim 3. A plurality of light emitting pixels arranged in the same row or the same column in the boundary display region are provided with first and second power supply lines in association with each other,
The first power line is a power line used for applying a power supply voltage to the first light emitting pixel to which a power supply voltage is applied by the first power supply driver, which is disposed in the boundary display region. And
The second power line is a power line used for applying a power supply voltage to the second light emitting pixel, which is disposed in the boundary display area and to which a power supply voltage is applied by the second power supply driver. And
The first power supply line is electrically connected to the plurality of first light emitting pixels arranged in the same row or the same column in the boundary display region,
The second power supply line is electrically connected to the plurality of second light emitting pixels arranged in the same row or the same column in the boundary display region,
The first power supply driving unit applies a power supply voltage to the plurality of first light emitting pixels in the boundary display region via the first power supply line,
The second power supply driving unit applies a power supply voltage to the plurality of second light emitting pixels in the boundary display region via the second power supply line.
The display panel according to claim 1. The first and second power supply lines are arranged in parallel.
The display panel according to claim 6. Each of the first and second power supply lines has a non-linear shape.
The display panel according to claim 6. A light emitting pixel to which a power supply voltage is applied by the first power supply driving unit and a light emitting pixel to which a power supply voltage is applied by the second power supply driving unit in the same row or the same column in the boundary display region are periodically Arranged,
The display panel according to claim 1. A light emitting pixel to which a power supply voltage is applied by the first power supply driving unit and a light emitting pixel to which a power supply voltage is applied by the second power supply driving unit in the same row or the same column in the boundary display region are aperiodic. Placed in the
The display panel according to claim 1. In the same row or the same column in the boundary display area, the light emitting pixels to which the power supply voltage is applied by the first power supply driving unit and the light emitting pixels to which the power supply voltage is applied by the second power supply driving unit are alternately arranged. To be
The display panel according to claim 9. The light emitting pixels arranged in the same row or the same column in the boundary display region are, based on an arrangement determined based on a dither matrix, light emitting pixels to which a power supply voltage is applied by the first power supply driving unit, Including both the light emitting pixel to which the power supply voltage is applied by the second power supply driving unit,
The display panel according to claim 1. Each of the plurality of light emitting pixels includes an organic EL (Electro Luminescence) element,
The organic EL element emits light by a current supplied by an applied power supply voltage.
The display panel according to claim 1. A display panel according to any one of claims 1 to 13,
A control circuit for controlling the first power supply driving unit and the second power supply driving unit,
Display device.

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