JP2011071224A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its manufacturing method which includes a silicide layer having a higher heat resistance. <P>SOLUTION: The manufacturing method of a semiconductor device 100 includes a step of forming a gate electrode 5 on a semiconductor substrate 2 through a gate insulating film 4; a step of forming a Ge-contained region 8 on both sides of the gate electrode 5 on the semiconductor substrate 2; a step of forming a source/drain region 9, in the regions on both sides of the gate electrode 5 in the Ge-containing region 8 and the semiconductor substrate 2; and a step of forming a silicide layer 11 containing a metal silicide containing Pd whose concentration is 5 atom% or higher on the Ge-containing region 8, and a step, in which after the silicide layer 11 is formed, the semiconductor substrate 2 is subjected to thermal treatment at 650-750°C. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, with miniaturization of semiconductor devices, reduction of sheet resistance of silicide layers on source / drain regions and gate electrodes has been demanded. In addition, in a device such as FeRAM that requires high-temperature heat treatment in the back-end process during the manufacturing process, the silicide layer is required to have heat resistance.

  As a technique for improving the heat resistance of the silicide layer, a technique of adding Pt to Ni silicide is known (see, for example, Patent Document 1). By adding Pt to Ni silicide, an increase in the sheet resistance of the silicide layer can be suppressed even when heat treatment at a relatively high temperature is performed.

JP 2009-99947 A

  An object of the present invention is to provide a semiconductor device including a silicide layer having higher heat resistance and a method for manufacturing the same.

  One embodiment of the present invention includes a step of forming a gate electrode on a substrate through a gate insulating film, and a step of forming a base layer made of Si-based crystals containing Ge on both sides of the gate electrode on the substrate. A step of forming source / drain regions in regions of the substrate and the underlayer on both sides of the gate electrode, and a silicide layer made of metal silicide containing Pd at a concentration of 5 atomic% or more on the underlayer. There is provided a method for manufacturing a semiconductor device, comprising: a step of forming; and a step of heat-treating the substrate at 650 to 750 ° C. after forming the silicide layer.

  In another aspect of the present invention, a gate electrode formed on a substrate via a gate insulating film, a base layer made of Si-based crystals containing Ge, formed on both sides of the gate electrode on the substrate, Source / drain regions formed in regions of the substrate and the underlayer on both sides of the gate electrode, and a silicide layer made of a metal silicide containing Pd at a concentration of 5 atomic% or more formed on the underlayer. A semiconductor device is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device provided with the silicide layer which has higher heat resistance, and its manufacturing method can be provided.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. The graph showing the heat treatment temperature dependence of the sheet resistance of Ni silicide containing Pd. (A), (b) is a graph showing the Pd density | concentration dependence of the sheet resistance of Ni silicide containing Pd. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. The graph showing the formation temperature dependence of the sheet resistance of Ni silicide containing Pt or Pt. Sectional drawing of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing of the modification of the semiconductor device which concerns on the 3rd Embodiment of this invention.

[First Embodiment]
(Configuration of semiconductor device)
FIG. 1 is a cross-sectional view of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 includes a MOSFET 1 that is isolated from other elements by an element isolation region 3 on a semiconductor substrate 2.

  MOSFET 1 includes a gate electrode 5 formed on a semiconductor substrate 2 via a gate insulating film 4, an offset spacer 6 formed on a side surface of the gate electrode 5, and a gate sidewall formed on a side surface of the offset spacer 6. 7, Ge-containing regions 8 formed on both sides of the gate electrode 5 in the semiconductor substrate 2, source / drain regions 9 formed on both sides of the gate electrode 5 in the semiconductor substrate 2 and the Ge-containing region 8, A silicide layer 10 on the electrode 5 and a silicide layer 11 on the Ge-containing region 8 are included. Although not shown, a well may be formed in a region under the MOSFET 1 in the semiconductor substrate 2.

  The semiconductor substrate 2 is made of a Si-based substrate and includes a Ge-containing region 8 in the vicinity of the surface thereof. The Si-based substrate is made of, for example, a Si-based single crystal such as Si, SiGe, SiC, or SiSn, or a Si-based polycrystal. Note that when a SiGe substrate is used as the Si-based substrate, the Ge-containing region 8 does not have to be formed because it originally contains Ge.

  The Ge-containing region 8 is a region containing 0.001 to 50 atomic%, more preferably 0.001 to 30 atomic% of Ge in the semiconductor substrate 2. Ge has a property of improving the heat resistance of the silicide 11 that is a metal silicide containing Pd formed on the Ge-containing region 8. When the Ge concentration is lower than 0.001 atomic%, it is difficult to sufficiently improve the heat resistance of the silicide 11. Further, when the Ge concentration is higher than 30 atomic%, there is a possibility that crystal defects may occur on the surface of the semiconductor substrate 2. The Ge-containing region 8 is formed by implanting Ge into the semiconductor substrate 2 using an ion implantation method or the like.

The element isolation region 3 is made of an insulating material such as SiO ₂ and has an STI (Shallow Trench Isolation) structure.

The gate insulating film 4 is made of, for example, an insulating material such as SiO ₂ , SiN, or SiON, or a high dielectric constant material such as HfSiON.

  The gate electrode 5 is made of, for example, Si-based polycrystal such as polycrystal Si or polycrystal SiGe containing conductive impurities. The gate electrode 5 may be a metal gate electrode made of metal, and may have a two-layer structure made of a metal layer and a Si-based polycrystalline layer on the metal layer. When the gate electrode 5 is a metal gate electrode, the silicide layer 10 on the gate electrode 5 is not formed.

The offset spacer 6 and the gate sidewall 7 are made of an insulating material such as SiO ₂ or SiN. Further, the gate side wall 7 may have a two-layer structure made of a plurality of types of insulating materials such as SiN, SiO ₂ , TEOS (Tetraethoxysilane), or a structure having three or more layers.

The source / drain regions 9 are formed by injecting conductive impurities into the semiconductor substrate 2. When the n-type source / drain region 9 is formed, n-type impurities such as As and P are used. Further, when the p-type source / drain region 9 is formed, an n-type impurity such as B or BF ₂ is used.

  The silicide layers 10 and 11 are made of a metal silicide containing Pd. Pd has the property of improving the heat resistance of the metal silicide. In order to improve the heat resistance of the metal silicide more effectively, the concentration of Pd contained in the metal silicide is preferably 5 atomic% or more. There is no particular upper limit of the concentration because there is no major problem that occurs when the concentration of Pd increases.

  As the metal silicide, a compound of Ni, V, Ti, Co, Rh, or Ir (hereinafter referred to as a base metal) and Si can be used. The metal silicide may include a plurality of types of base metals. Moreover, it is preferable that the metal silicide has a crystal structure of MnP structure or a point group symmetry of the crystal structure is close to that of NiSi.

  Further, since Pd tends to segregate at the interface between the metal silicide and silicon, the interface resistance between the metal silicide and silicon can be reduced and the direct current value can be increased. In addition, since Pd segregates at the interface between the metal silicide and silicon, the height of the Schottky barrier (SBH) against holes can be reduced. Therefore, when MOSFET 1 is p-type, Operation performance can be improved.

  FIG. 2 is a graph showing the heat treatment temperature dependence of the sheet resistance of Ni silicide containing Pd. The horizontal axis of FIG. 2 represents the temperature [° C.] of the heat treatment applied to the silicide, and the vertical axis represents the sheet resistance [ohm / sq.] Per square millimeter of the silicide after the heat treatment.

  FIG. 2 shows a profile of Ni silicide containing 4 atomic% Pd and Ni silicide containing 8 atomic% Pd formed on the Si substrate, and in the vicinity of the surface in the same manner as the semiconductor substrate 2 including the Ge-containing region 8. The profile of Ni silicide containing 8 atomic% Pd formed on a Si substrate containing Ge is shown.

  According to FIG. 2, in the profile of Ni silicide formed on the Si substrate, the sheet resistance increases rapidly when the heat treatment temperature exceeds 650 ° C. On the other hand, in the profile of Ni silicide formed on the Si substrate containing Ge near the surface, the rapid increase in sheet resistance is suppressed until the heat treatment temperature reaches 750 ° C. From this result, when Ni silicide containing Pd is formed on a Si substrate containing Ge near the surface, the heat resistance of Ni silicide containing Pd is higher than when it is formed on a Si substrate not containing Ge. I understand.

  In the above experiment, it is considered that the same result can be obtained even when another metal silicide used as the material of the silicide layer 11 is used instead of the Ni silicide. From this result, it can be seen that the Ge-containing region 8 enhances the heat resistance of the silicide layer 11.

  3A and 3B are graphs showing the Pd concentration dependence of the sheet resistance of Ni silicide containing Pd. 3A and 3B, the horizontal axis represents the concentration [at%] of Pd contained in Ni silicide, and the vertical axis represents the sheet resistance per square millimeter of Ni silicide after heat treatment [ohm / sq.]. Represents. 3A and 3B include a profile of Ni silicide containing Pt as a comparative example.

  FIG. 3A shows a profile of Ni silicide containing Pd or Pt that has been heat-treated at 700 ° C. FIG. According to FIG. 3A, in the profile of Ni silicide containing Pd, the sheet resistance is the lowest when the concentration of Pd is 8 atomic%, and the sheet resistance increases as the concentration of Pd increases from 8 atomic%. Increases moderately.

  Further, by comparing the profile of Ni silicide containing Pd with the profile of Ni silicide containing Pt, it can be seen that Ni silicide containing Pd is superior in heat resistance to Ni silicide containing Pt.

  FIG. 3B shows a profile of Ni silicide containing Pd or Pt that has been heat-treated at 750 ° C. According to FIG. 3B, as in FIG. 3A, in the profile of Ni silicide containing Pd, the sheet resistance is the lowest when the concentration of Pd is 8 atomic%, and the concentration of Pd is 8 atoms. As the value increases from%, the sheet resistance increases gradually. In this case, when the concentration of Pd is 5 atomic% or more, the effect of improving the heat resistance of the metal silicide by Pd appears.

  Further, by comparing the profile of Ni silicide containing Pd with the profile of Ni silicide containing Pt, it can be seen that Ni silicide containing Pd is superior in heat resistance to Ni silicide containing Pt.

  In the above experiment, it is considered that the same result can be obtained even when another metal silicide used as the material of the silicide layer 11 is used instead of the Ni silicide.

  Below, an example of the manufacturing method of the semiconductor device 100 which concerns on this Embodiment is shown.

(Manufacture of semiconductor devices)
4A to 4D are cross-sectional views illustrating the manufacturing steps of the semiconductor device 100 according to the first embodiment of the present invention.

  First, as shown in FIG. 4A, an element isolation region 3 is formed on a semiconductor substrate 2 to partition an element region for forming the MOSFET 1, and then a gate insulating film 4 and a gate electrode are formed in the element region. 5 is formed.

  Next, as shown in FIG. 4B, an offset spacer 6 is formed on the side surface of the gate electrode 5, and then a shallow region of the source / drain region 9 is formed. The shallow region of the source / drain region 9 is formed by implanting conductive impurities into the semiconductor substrate 2 by ion implantation using the gate electrode 5 and the offset spacer 6 as a mask.

  Next, as shown in FIG. 4C, the gate sidewall 7 is formed on the side surface of the offset spacer 6, and then the deep region of the Ge-containing region 8 and the source / drain region 9 is formed. The deep regions of the Ge-containing region 8 and the source / drain regions 9 are formed by implanting conductive impurities into the semiconductor substrate 2 by ion implantation using the gate electrode 5, the offset spacer 6 and the gate sidewall 7 as a mask. The

  Next, as shown in FIG. 4D, a silicide layer 10 and a silicide layer 11 are formed on the gate electrode 5 and the source / drain regions 8, respectively.

  The step of forming the silicide layers 10 and 11 includes a step of forming a metal film so as to cover the gate electrode 5 and the Ge-containing region 8, and a reaction between the gate electrode 5 and the metal film and the Ge-containing region 8 and the metal film by heat treatment. Including the step of

  As a specific method for forming the silicide layers 10 and 11, for example, there is the following method. (1) A method of performing heat treatment after simultaneously sputtering a base metal such as Ni and Pd to form a metal film containing the base metal and Pd. (2) A method of performing a heat treatment after laminating a metal film containing Pd on a metal film containing a base metal. (3) A method in which a heat treatment is performed after a metal film containing a base metal is stacked on a metal film containing Pd. (4) A method in which a metal film containing a base metal is formed, a silicide containing a base metal is formed by heat treatment, Pd is then implanted into the silicide by an ion implantation method, and a heat treatment is performed. (5) A method of forming a metal film containing a base metal, forming a silicide containing a base metal by heat treatment, forming a metal film containing Pd on the silicide, and performing a heat treatment. (6) A method of forming a metal film containing Pd, forming a silicide containing Pd by heat treatment, forming a metal film containing a base metal on the silicide, and performing a heat treatment. In each of the above methods, the metal film is formed by a PVD method, a CVD method, or the like.

  Note that the Ge-containing region 8 may be formed at any timing before the silicide layer 11 is formed. For example, when the Ge-containing region 8 is formed after the offset spacer 6 is formed and before the gate sidewall 7 is formed, the Ge-containing region 8 is also formed under the gate sidewall 7. When the Ge-containing region 8 is formed before forming the gate insulating film 4, the Ge-containing region 8 is also formed under the gate insulating film 4.

  After the MOSFET 1 is formed, an interlayer insulating film (not shown) is formed on the MOSFET 1 and a memory element is formed above the MOSFET 1. When forming this memory element, a high-temperature heat treatment is performed. Here, the high temperature means a temperature of 650 ° C. or higher. When the memory element is formed, a high-temperature heat treatment at 650 to 750 ° C. may be performed.

  In the high-temperature heat treatment step after the MOSFET 1 is formed, the sheet resistance of the silicide layer 11 hardly increases even if the MOSFET 1 is placed at a high temperature.

(Effects of the first embodiment)
According to the first embodiment of the present invention, by using the silicide layer 11 made of metal silicide containing Pd having high heat resistance as the silicide layer on the source / drain regions, the comparison is performed in the process after the formation of the silicide layer. Even when the substrate is subjected to a heat treatment at a relatively high temperature, an increase in the electrical resistance of the silicide layer and abnormal growth in the vicinity of the edge portion of the element isolation region 3 of the silicide layer can be suppressed.

  Therefore, this embodiment exhibits a higher effect when applied to the manufacture of a transistor that requires high-temperature processing in a back-end process. Transistors that require high-temperature processing in subsequent processes include, for example, cell transistors of memory elements such as CMOS (Complementary Metal-Oxide Semiconductor), FeRAM, DRAM, MRAM, PCRAM, FeRAM, DRAM, MRAM, PCRAM, ReRAM, etc. There are peripheral circuit transistors of a mixed memory device.

[Second Embodiment]
The second embodiment of the present invention is different from the first embodiment in that the silicide layer 11 includes Pt in addition to Pd. Note that the description of the same points as in the first embodiment will be omitted or simplified.

(Configuration of semiconductor device)
The silicide layer 11 is made of a metal silicide such as Ni silicide containing Pd and Pt. Pd has the property of improving the heat resistance of the metal silicide, and Pt has the property of reducing the lower limit of the metal silicide formation temperature.

  In order to further reduce the lower limit of the metal silicide formation temperature, the concentration of Pt contained in the metal silicide is preferably 8 to 15 atomic%. Further, similarly to the first embodiment, in order to more effectively improve the heat resistance of the metal silicide, the concentration of Pd contained in the metal silicide is preferably 5 atomic% or more.

  FIG. 5 is a graph showing the temperature dependence of sheet resistance of Ni silicide containing Pt or Pt. The horizontal axis in FIG. 5 represents the Ni silicide formation temperature [° C.], and the vertical axis represents the sheet resistance [ohm / sq.] Per square millimeter of Ni silicide. Here, the formation temperature refers to the temperature of heat treatment for causing a silicide reaction between the metal film and the Si crystal.

  FIG. 5 shows that 8 atomic% Pt, 15 atomic% Pt, 8 atomic% Pd, 15 atomic% Pd, or 15 atomic% Pd formed on a Si substrate containing Ge in the vicinity of the surface as in the semiconductor substrate 2. The profile of Ni silicide containing 30 atomic% Pd is shown.

  As can be seen from FIG. 5, Ni silicide containing Pt can obtain a lower sheet resistance at a lower forming temperature than Ni silicide containing Pd. For example, when Ni silicide containing Pd is formed at 350 ° C., any sheet resistance is larger than 45 [ohm / sq.]. On the other hand, when Ni silicide containing Pt is formed at 350 ° C., any sheet resistance is smaller than 30 [ohm / sq.].

  FIG. 5 also shows that Ni silicide containing 8% Pt can obtain a lower sheet resistance at a lower forming temperature than Ni silicide containing 15% Pt. A low sheet resistance can be obtained at the lowest formation temperature when the Pt concentration is 8 atomic%, and the formation temperature necessary to obtain a lower sheet resistance as the Pt concentration increases from 8 atomic%. Increases moderately.

  In the above experiment, it is considered that the same result can be obtained even when another metal silicide used as the material of the silicide layer 11 is used instead of the Ni silicide.

  From these results, in order to reduce the lower limit of the formation temperature of the silicide layer 11 necessary for obtaining a sufficiently low sheet resistance, it is preferable that the metal silicide of the silicide layer 11 contains 8 atomic% or more of Pt. Recognize. On the other hand, when the Pt concentration increases, the sheet resistance of the metal silicide tends to increase. In order to keep the sheet resistance low, the concentration of Pt in the metal silicide of the silicide layer 11 is preferably 15 atomic% or less.

  The step of forming the silicide layers 10 and 11 includes a step of forming a metal film so as to cover the gate electrode 5 and the Ge-containing region 8, and a reaction between the gate electrode 5 and the metal film and the Ge-containing region 8 and the metal film by heat treatment. Including the step of

  As a specific method for forming the silicide layers 10 and 11, for example, there is the following method. (1) A method in which a base metal such as Ni, Pd and Pt are simultaneously sputtered to form a metal film containing the base metal, Pd and Pt, and then heat treatment is performed. (2) A method of performing a heat treatment after laminating a metal film containing Pd and Pt on a metal film containing a base metal. (3) A method of performing a heat treatment after laminating a metal film containing a base metal on a metal film containing Pd and Pt. (4) A method in which a metal film containing a base metal is formed, a silicide containing a base metal is formed by heat treatment, Pd and Pt are implanted into the silicide by an ion implantation method, and a heat treatment is further performed. (5) A method of forming a metal film containing a base metal, forming a silicide containing a base metal by heat treatment, forming a metal film containing Pd and Pt on the silicide, and performing a heat treatment. (6) A method of forming a metal film containing Pd, forming a silicide containing Pd and Pt by heat treatment, forming a metal film containing a base metal on the silicide, and further performing a heat treatment.

(Effect of the second embodiment)
According to the second embodiment of the present invention, the silicide layer 11 made of a metal silicide containing Pd and Pt is used as the silicide layer on the source / drain regions, thereby having a low sheet resistance at a relatively low temperature. A silicide layer can be formed, and even if a relatively high temperature heat treatment is applied to the substrate in the process after the formation of the silicide layer, the increase in the electrical resistance of the silicide layer or the element isolation region 3 of the silicide layer. It is possible to suppress abnormal growth in the vicinity of the edge portion.

[Third Embodiment]
The third embodiment of the present invention is different from the first embodiment in that a silicide layer is formed on a SiGe crystal epitaxially grown on a semiconductor substrate. Note that the description of the same points as in the first embodiment will be omitted or simplified.

(Configuration of semiconductor device)
FIG. 6 is a cross-sectional view of a semiconductor device 200 according to the third embodiment of the present invention. The semiconductor device 200 includes a MOSFET 20 that is isolated from other elements by the element isolation region 3 on the semiconductor substrate 2.

  The MOSFET 20 includes a gate electrode 5 formed on the semiconductor substrate 2 via the gate insulating film 4, an offset spacer 6 formed on the side surface of the gate electrode 5, and a gate side wall formed on the side surface of the offset spacer 6. 7, SiGe epitaxial layers 21 formed on both sides of the gate electrode 5 on the semiconductor substrate 2, source / drain regions 9 formed on both sides of the gate electrode 5 in the semiconductor substrate 2 and in the SiGe epitaxial layer 21, A silicide layer 10 on the gate electrode 5 and a silicide layer 11 on the SiGe epitaxial layer 21 are included. Although not shown, a well may be formed in a region under the MOSFET 20 in the semiconductor substrate 2.

  The SiGe epitaxial layer 21 is made of SiGe crystal that is epitaxially grown with the surface of the semiconductor substrate 2 on both sides of the gate sidewall 7 as a base. Similar to the Ge concentration in the Ge-containing region 8 of the first embodiment, the Ge concentration in the SiGe epitaxial layer 21 is 0.001 to 50 atomic%, more preferably 0.001 to 30 atomic%. Ge has a property of improving the heat resistance of the silicide 11 which is a metal silicide containing Pd formed on the SiGe epitaxial layer 21.

  Below, an example of the manufacturing method of the semiconductor device 200 concerning this Embodiment is shown.

(Manufacture of semiconductor devices)
7A to 7D are cross-sectional views illustrating the manufacturing steps of the semiconductor device 200 according to the third embodiment of the present invention.

  First, as shown in FIG. 7A, the steps until the formation of the shallow regions of the source / drain regions 9 shown in FIGS. 4A and 4B are performed in the same manner as in the first embodiment.

  Next, as shown in FIG. 7B, the gate sidewall 7 is formed on the side surface of the offset spacer 6, and then the SiGe epitaxial layer 21 is formed on both sides of the gate sidewall 7.

  The SiGe epitaxial layer 21 is formed by epitaxially growing SiGe crystals using the surface of the semiconductor substrate 2 on both sides of the gate sidewall 7 as a base. The SiGe epitaxial layer 21 may be formed by implanting Ge into the Si crystal by ion implantation or the like after the Si crystal is epitaxially grown.

  Next, as shown in FIG. 7C, deep regions of the source / drain regions 9 are formed. The deep region of the source / drain region 9 is formed by implanting conductive impurities into the SiGe epitaxial layer 21 and the semiconductor substrate 2 by ion implantation using the gate electrode 5, the offset spacer 6 and the gate sidewall 7 as a mask. The

  Next, as shown in FIG. 7D, a silicide layer 10 and a silicide layer 11 are formed on the gate electrode 5 and the SiGe epitaxial layer 21, respectively.

  The step of forming the silicide layers 10 and 11 includes a step of forming a metal film so as to cover the gate electrode 5 and the SiGe epitaxial layer 21, and a reaction between the gate electrode 5 and the metal film and the SiGe epitaxial layer 21 and the metal film by heat treatment. Including the step of

(Effect of the third embodiment)
According to the third embodiment of the present invention, the same effect as that of the first embodiment can be obtained by forming the silicide layer 10 on the SiGe epitaxial layer 21 made of the epitaxially grown SiGe crystal.

  As shown in FIG. 8, the SiGe epitaxial layer 21 may be formed in grooves formed on both sides of the gate sidewall 7 in the semiconductor substrate 2. In this case, when the Ge concentration in the SiGe crystal of the SiGe epitaxial layer 21 is 10 to 50 atomic%, a strain is generated in the channel region under the gate insulating film 4 in the semiconductor substrate 2 so that holes in the channel region are generated. The mobility of can be improved. For this reason, when the MOSFET 20 is p-type, its operation performance can be improved.

[Fourth Embodiment]
The fourth embodiment of the present invention is different from the third embodiment in that the silicide layer 11 includes Pt in addition to Pd. Note that the description of the same points as in the third embodiment will be omitted or simplified.

(Configuration of semiconductor device)
The silicide layer 11 is made of a metal silicide such as Ni silicide containing Pd and Pt. Pd has the property of improving the heat resistance of the metal silicide, and Pt has the property of reducing the lower limit of the metal silicide formation temperature.

  In order to further reduce the lower limit of the metal silicide formation temperature, the concentration of Pt contained in the metal silicide is preferably 8 to 15 atomic%. Further, similarly to the first embodiment, in order to more effectively improve the heat resistance of the metal silicide, the concentration of Pd contained in the metal silicide is preferably 5 atomic% or more.

(Effect of the fourth embodiment)
According to the fourth embodiment of the present invention, the silicide layer 11 made of a metal silicide containing Pd and Pt is used as the silicide layer on the source / drain region, thereby having a low sheet resistance at a relatively low temperature. A silicide layer can be formed, and even if a relatively high temperature heat treatment is applied to the substrate in the process after the formation of the silicide layer, an increase in the electrical resistance of the silicide layer and the element isolation region 3 of the silicide layer It is possible to suppress abnormal growth in the vicinity of the edge portion.

[Other Embodiments]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention.

  In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

  100, 200 Semiconductor device, 2 Semiconductor substrate, 4 Gate insulating film, 5 Gate electrode, 8 Ge-containing region, 9 Source / drain region, 11 Silicide layer, 21 SiGe epitaxial layer

Claims (5)

Forming a gate electrode on the substrate via a gate insulating film;
Forming a base layer made of Si-based crystal containing Ge on both sides of the gate electrode on the substrate;
Forming source / drain regions in regions on both sides of the gate electrode of the substrate and the base layer;
Forming a silicide layer made of a metal silicide containing Pd at a concentration of 5 atomic% or more on the underlayer;
After forming the silicide layer, subjecting the substrate to a heat treatment at 650 to 750 ° C .;
A method of manufacturing a semiconductor device including: The metal silicide of the silicide layer further includes Pt at a concentration of 8 to 15 atomic%, and is formed by a silicide reaction generated by a heat treatment at 350 ° C. or lower.
A method for manufacturing a semiconductor device according to claim 1. A gate electrode formed on the substrate via a gate insulating film;
An underlayer made of Si-based crystals containing Ge, formed on both sides of the gate electrode on the substrate;
Source / drain regions formed in regions on both sides of the gate electrode of the substrate and the base layer;
A silicide layer made of a metal silicide containing Pd having a concentration of 5 atomic% or more formed on the underlayer;
A semiconductor device. The metal silicide of the silicide layer further includes 8 to 15 atomic% of Pt.
The semiconductor device according to claim 3. The underlayer is made of a Ge-containing region in the substrate or a SiGe epitaxial crystal.
The semiconductor device according to claim 3 or 4.

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