JP2011065169A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device, in an active matrix-type liquid crystal display device, which solves the problem that, though the number of masks used for the simplification of a production process is reduced, in the conventional process, the structure in which a gate signal line comes directly in contact with a liquid crystal part (including an alignment layer) must be taken, and that the liquid crystal part by the influence of the gate signal voltage is deteriorated; and to suppress the influence of the gate signal voltage on the liquid crystal part. <P>SOLUTION: In the display device, a gate signal line is covered with an insulating film, and a liquid crystal part is not directly contacted. The constitution of the pixel part thereof is shown in the Fig.1. The display device having the insulating film can be produced by simultaneously pattern-forming the gate signal line and the insulating film thereon without increasing the number of the masks to be used. Further, the periphery of the gate signal line can be covered with a BM layer instead of producing the BM layer on a counter substrate, and the BM is used as the insulating layer. At this time, there is no increase in the number of the masks to be used. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device including a thin film transistor (TFT) formed over an insulating substrate and a manufacturing method thereof.

  Active matrix liquid crystal display devices using thin film transistors (TFTs) are used as direct-view display devices for video cameras, image playback devices, head mounted displays, mobile phones, personal digital assistants, and lenses such as front and rear projects. Development as a projection type display device aiming at enlarged display by an optical system is being actively carried out.

  FIG. 3 shows an example of the configuration of an active matrix liquid crystal display device. A source signal line 301, a gate signal line 302, a pixel TFT 303, and a storage capacitor 304 are included. The gate electrode of the pixel TFT 303 is connected to the gate signal line 302, one of the drain region or the source region of the pixel TFT 303 is connected to the source signal line 301, and the other is connected to the storage capacitor 304 and the pixel electrode 305. ing.

  This pixel driving method will be described below. When a signal voltage is input to the gate signal line 302 and the pixel TFT 303 is turned on, the signal voltage is input from the source signal line 301 and charges are accumulated in the storage capacitor 304. Due to this accumulated charge, a voltage is applied to the pixel electrode 305, and a voltage is applied between the electrodes sandwiching the liquid crystal. Corresponding to this applied voltage, the orientation of liquid crystal molecules changes, and the amount of transmitted light is controlled.

FIG. 4 shows the relationship between the applied voltage and the amount of transmitted light. The amount of transmitted light can be changed by changing the applied voltage in the range of −V _{m to} V _m . When the applied voltage is 0, the maximum transmitted light amount T _max is assumed. Here, the liquid crystal has a problem that, when an electric field in a certain direction is continuously applied, ions accumulate on one side and deteriorate immediately. Therefore, it is common to perform driving with the polarity of the applied voltage reversed every time a signal is written to the pixel.

  FIG. 5 shows the relationship between the gate signal voltage, the source signal voltage, and the voltage applied to the liquid crystal when this display device is driven. In this figure, attention is paid to a certain gate signal line Gn and a certain source signal line Sm, and the applied voltage to the liquid crystal in a certain pixel is shown.

When the gate signal line is selected and a voltage is applied to the liquid crystal, the orientation of the liquid crystal molecules changes according to the applied voltage. As a result, the amount of transmitted light changes, and an image is displayed. Here, the voltage applied to the liquid crystal changes in the range of −V to V, and the polarity is reversed every time a signal is written to the pixel. Note that | V | is a value equal to or smaller than | V _m | in FIG.

  In the production of this active matrix type liquid crystal display device, the manufacturing cost has been reduced and the yield has been improved by reducing the number of steps.

  FIG. 6A shows an example of a cross-sectional view of a pixel portion of a conventional active matrix liquid crystal display device.

  A pixel TFT 102 and a storage capacitor 103 are formed in the pixel portion 101. Here, 104 is an insulating substrate of the TFT substrate, 105 is a source region or drain region of the pixel TFT 102, 106 is a channel region of the pixel TFT 102, 108 is a gate insulating film, 107 and 112 are electrodes of the storage capacitor 103, and are insulated The layer 109 is sandwiched. Note that the electrode 107 is formed of a semiconductor layer and is doped with an impurity element. The electrode 107 is connected to the drain region of the pixel TFT 102. 215 is a gate signal line, 210 is a source signal line, 116 is a drain wiring, 113 is an interlayer insulating film, 118 is a pixel electrode, 119 and 126 are alignment films, 120 is a liquid crystal, 121 is an insulating substrate of a counter substrate, 122 Is a black matrix (BM), 123 is a color filter, 124 is a planarizing film, and 125 is a counter electrode.

Here, in order to reduce the number of masks to be used, the pixel electrode 118 connected to the drain wiring 116 is brought into conduction by directly contacting the drain wiring 116.

  Here, the source wiring 210 is patterned in the same layer as the drain wiring 116 and the pixel electrode 118. For this reason, in order to prevent a short circuit between the source wiring and the pixel electrode, there must be a sufficient space between the source signal line and the pixel electrode. Further, in order to prevent light leakage from the space portion, it is necessary to cover the space portion with BM.

A top view of the pixel at this time is shown in FIG. For the sake of clarity, a part of the region where the pixel electrode and the BM are removed is shown. Here, FIG. 6A corresponds to a cross-sectional view taken along lines A to A ′ in FIG. Note that the same reference numerals as those in FIG. 6A denote the same parts. Reference numeral 210 denotes a source signal line, 116 denotes a drain wiring, 215 denotes a gate signal line, 118 denotes a pixel electrode, and 220 denotes a semiconductor layer, which correspond to 105 to 107 in FIG.

Here, a space portion 230 is provided between the source signal line 210 and the pixel electrode 118 to prevent the source signal line 210 and the pixel electrode 118 from being short-circuited. For this reason, the area of the pixel electrode 118 cannot be increased. Therefore, the aperture ratio cannot be increased. In order to prevent light leakage from the space portion 230, the space portion 230 is covered with a BM 122 provided on the counter substrate. Here, it is necessary to allow the BM to overlap with the end portion of the pixel electrode in consideration of the influence of the shift in bonding the TFT substrate and the counter substrate, the influence of light wraparound, and the like. As a result, there is a problem that the aperture ratio further decreases.

  Accordingly, a display device having a structure as shown in FIG. 7A has been proposed. Note that the same reference numerals as those in FIGS. 6A and 6B denote the same parts.

  In FIG. 7A, 111 is a gate electrode, 114 is a source wiring, 110 is a source signal line, and 115 is a gate signal line.

  In the cross-sectional view display device shown in FIG. 7A, the source signal line 114 is formed simultaneously with the gate electrode 111, and the gate signal line 115 is formed simultaneously with the source wiring 114 and the drain wiring 116. Here, the source signal line 110 is connected to the source region of the pixel TFT 102 by the source wiring 114. With this configuration, the layers in which the source signal line and the gate signal line are formed can be interchanged without increasing the number of masks. Such an arrangement of the source signal line and the gate signal line is called an inverted cross structure. With this structure, since the source signal line 110 is arranged in a layer below the drain wiring 116, the pixel electrode 118 can be formed also on the source signal line 110, and the aperture ratio can be increased.

  FIG. 7B is a top view of FIG. For the sake of clarity, a part of the region where the pixel electrode and the BM are removed is shown. Here, FIG. 7A corresponds to cross-sectional views of A to A ′ and B to B ′ in FIG. Since the pixel electrode 118 is formed over the source signal line 110 to prevent light leakage, the portion of the BM 122 provided on the counter substrate is reduced as compared with FIG. 6B. Thus, the aperture ratio increases as compared with FIG.

  In the display device using the reverse cross structure, the gate signal line is formed in the same layer as the drain wiring and the pixel electrode, and the alignment film and the liquid crystal are formed thereon.

  Here, in FIG. 5, the gate signal line selection signal voltage is Vo, and the non-selection signal voltage is -Vo. If the number of gate signal lines is y, the period during which the gate signal lines are selected is 1 / y of one frame period. Therefore, as y increases, the selection period becomes shorter and a non-selected signal voltage is applied. The ratio of the period is increased. Therefore, while the pixel is not selected, the voltage of −Vo is continuously input.

  When the standard of the display device is VGA, −Vo is input in a period of 479/480 or more.

  As shown in FIG. 5, the voltage applied to the source signal line has a little influence on the liquid crystal part because the polarity is periodically inverted. On the other hand, the voltage input to the gate signal line tends to have a certain polarity as described above. Such a signal voltage input to the gate signal line affects the liquid crystal portion disposed immediately above the gate signal line. This is the cause of the deterioration of the liquid crystal.

Therefore, an object is to manufacture a display device in which the influence of a signal voltage applied to a gate signal line on peripheral liquid crystals is suppressed without increasing the number of masks used in the process.

  After forming a metal layer to be a gate signal line, a source wiring, and a drain wiring, an insulating layer is formed, and the insulating layer and the metal layer are patterned by one photolithography process. That is, an insulating film is formed between the gate signal line and the alignment film without increasing the number of masks. Thereby, the influence of the signal voltage flowing through the gate signal line on the liquid crystal can be suppressed.

The configuration of the present invention is shown below.

According to the present invention, a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are provided on an insulating substrate, and the plurality of pixels include a pixel TFT, a pixel electrode, a counter electrode, and the pixel electrode. And a liquid crystal portion disposed between the counter electrode and the liquid crystal portion, the liquid crystal portion including a first alignment film, a second alignment film, the first alignment film, and the second alignment film. And a gate electrode of the pixel TFT is connected to one of the plurality of gate signal lines, and one of the drain region and the source region of the pixel TFT is the plurality of source signal lines. The other is connected to the pixel electrode, the first alignment film is disposed between the pixel electrode and the liquid crystal, and the second alignment film is connected to the counter electrode. The plurality of gate signal lines are arranged between the liquid crystals and the pixel T In a display device formed of a conductive material constituting a source electrode and a drain electrode of T, an insulating layer is provided between the gate signal line and the first alignment film, and the insulating layer is the gate A display device is provided that is formed by patterning a layer made of an insulating material in a process of patterning a signal line.

  According to the present invention, an insulating layer obtained by etching the layer made of the insulating material by dry etching and the layer made of the conductive material by etching only by wet etching or by both wet etching and dry etching are formed. A display device comprising the gate signal line is provided.

  According to the present invention, the end face of the gate signal line is located 0.1 μm to 0.5 μm inside from the end face of the insulating layer, and the end of the gate signal line is recessed inward with respect to the end of the insulating layer. However, a display device characterized by having a recessed portion is provided.

  According to the present invention, there is provided a display device characterized in that the hollow portion is blocked by the first alignment film.

According to the present invention, a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are provided on an insulating substrate, and the plurality of pixels include a pixel TFT, a pixel electrode, a counter electrode, and the pixel electrode. And a liquid crystal portion disposed between the counter electrode and the liquid crystal portion, the liquid crystal portion including a first alignment film, a second alignment film, the first alignment film, and the second alignment film. And a gate electrode of the pixel TFT is connected to one of the plurality of gate signal lines, and one of the drain region and the source region of the pixel TFT is the plurality of source signal lines. And the other is connected to the pixel electrode, the first alignment film is disposed between the pixel electrode and the liquid crystal, and the second alignment film is connected to the counter electrode and the liquid crystal. The plurality of gate signal lines are disposed between the liquid crystals and the pixel TF A display device formed of a conductive material constituting the source electrode and the drain electrode of the display device, further comprising: a light-shielding insulating material between the gate signal line and the first alignment film. Provided.

According to the present invention, a source signal line driving circuit for processing signals input to a plurality of source signal lines and a gate signal line driving circuit for processing signals input to a plurality of gate signal lines are externally provided by a flexible printed circuit board. In the display device for inputting the signal, the wiring portion of the external input terminal to which the flexible printed circuit board is connected is placed on the same layer as the gate electrode of the TFT constituting the source signal line driving circuit and the gate signal line driving circuit. A display device characterized by being formed of the same material is provided.

According to the present invention, the display device includes a plurality of pixels on an insulating substrate and an external input terminal for connecting a flexible printed circuit board, and the plurality of pixels include a TFT and a transparent electrode. There is provided a display device comprising a laminated structure of a material constituting the gate electrode of the TFT and a material constituting the transparent electrode.

  According to the present invention, there is provided a display device wherein the external input terminal is formed by removing an interlayer film between the gate electrode of the TFT and the source electrode and drain electrode of the TFT. .

  The present invention may be a video camera, an image reproducing device, a head mounted display, a mobile phone, or a portable information terminal using the display device.

  In the conventional liquid crystal display device having a reverse cross structure, since the gate signal line is in direct contact with the alignment film, there is a problem that the liquid crystal is deteriorated by a signal voltage flowing therethrough.

  With the above structure, the present invention can form an insulating film over the gate signal line without increasing the number of masks used in the manufacturing process. Thereby, the influence of the signal voltage flowing through the gate signal line on the liquid crystal can be suppressed, and the deterioration of the liquid crystal can be prevented.

FIG. 3 is a cross-sectional view of a pixel portion of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a pixel portion of a liquid crystal display device of the present invention. FIG. 6 illustrates a structure of a pixel of a liquid crystal display device. The figure which shows the relationship between the applied voltage of a liquid crystal, and the transmitted light amount. FIG. 10 is a diagram illustrating a timing chart of driving voltages of a liquid crystal display device. Sectional drawing and top view of the pixel part of the conventional liquid crystal display device. Sectional drawing and top view of the pixel part of the conventional liquid crystal display device. FIG. 3 is a cross-sectional view of a pixel portion of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a pixel portion of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 2A and 2B are a top view and a cross-sectional view of a liquid crystal display device of the present invention. 1 is a top view of a liquid crystal display device of the present invention. The SEM observation image around the gate signal line of TFT of the liquid crystal display device of this invention. FIG. 3 is an enlarged view around a gate signal line of a TFT of the liquid crystal display device of the present invention. FIG. 11 is a diagram of an electronic device using the liquid crystal display device of the present invention.

FIG. 1 is a cross-sectional view of a pixel portion of a display device of the present invention. 7 that are the same as those in FIG. 7 are denoted by the same reference numerals and description thereof is omitted.

  In FIG. 1, the insulating film 10 is disposed on the gate signal line 115, the source wiring 114, the drain wiring 116, and the wiring 117. With this insulating film 10, the influence of the signal voltage flowing through the gate signal line 115 on the alignment film 119 and the liquid crystal 120 can be suppressed.

A method for manufacturing the display device having the structure of FIG. 1 will be described with reference to FIGS.
7 that are the same as those in FIG. 7 are denoted by the same reference numerals and description thereof is omitted.

FIG. 2A shows a state in which an interlayer insulating film 113 is formed after the pixel TFT 102 and the storage capacitor 103 are manufactured. A known method may be used for the process so far. Thereafter, as shown in FIG. 2B, the pixel electrode 118 is first formed by patterning. Thereafter, contact holes 16 to 19 reaching the source signal line, the source and drain regions of the pixel TFT, and the semiconductor layer of the storage capacitor are formed. Although not shown, a contact hole reaching the gate electrode of the pixel TFT is also formed at this time. Then, the metal layer 20 is formed in order to form a gate signal line, a source wiring, a drain wiring, and a wiring for connecting the storage capacitor and the pixel electrode. In this specification, for convenience, the metal layer 20 is referred to as an S / D metal layer.
An insulating layer 21 is further formed on the S / D metal layer 20. The S / D metal layer 20 and the insulating layer 21 are patterned at the same time to form a source wiring 114, a gate signal line 115, a drain wiring 116, and a wiring 117, and a structure as shown in FIG. 2C is obtained.

  In the above description, the contact holes 16 to 19 are formed after the pixel electrode 118 is formed. However, this order may be reversed.

  After that, if an alignment film is attached and bonded to the counter substrate and liquid crystal is sealed in between, a liquid crystal display device having the structure of FIG. 1 can be obtained.

  Thus, by patterning the S / D metal layer 20 and the insulating layer 21 at once, a display device having a structure in which the gate signal line is covered with the insulating film 10 can be manufactured without increasing the number of masks. .

  Examples of the present invention will be described below.

  In this example, a method for manufacturing a display device in which a gate signal line is covered with an insulating film without increasing the number of masks will be described by a method different from the method described in Embodiment Mode.

  In the conventional display device as shown in FIG. 7 and the display device shown in FIG. 1, the BM layer is formed on the counter substrate side. Here, in this embodiment, as shown in FIG. 8, the BM 222 is used as an insulating film covering the gate signal line. For this reason, it is not necessary to form a BM layer on the counter substrate. 7 that are the same as those in FIG. 7 are denoted by the same reference numerals and description thereof is omitted.

  FIG. 9 shows a manufacturing process of the display device of FIG.

  As shown in FIG. 9A, after the pixel TFT 102 and the storage capacitor 103 are manufactured, an interlayer insulating film 113 is formed, and a pixel electrode 118 is first formed by patterning. Thereafter, contact holes 16 to 19 reaching the source signal line, the source and drain regions of the pixel TFT, and the semiconductor layer of the storage capacitor are formed. Although not shown, a contact hole reaching the gate electrode of the pixel TFT is also formed at this time. Then, the S / D metal layer 20 is formed in order to form a gate signal line, a source wiring, a drain wiring, and a wiring for connecting the storage capacitor and the pixel electrode.

  In the above description, the contact holes 16 to 19 are formed after the pixel electrode 118 is formed, but this order may be reversed.

  The process so far is the same as the process described in the embodiment of the invention.

Next, as shown in FIG. 9B, the S / D metal layer 20 is patterned to form a source wiring 114, a gate signal line 115, a drain wiring 116, and a wiring 117. Thereafter, the BM layer 22 is formed. The BM layer 22 is formed of a black or brown resin and performs light shielding.

  As shown in FIG. 9C, the BM layer 22 is patterned so that the periphery of the gate signal line, the source wiring, and the drain wiring is covered with the BM 222. The BM layer 22 may be dry-etched after patterning a resist mask, or may be a photosensitive resin.

  After that, an alignment film is attached, and the liquid crystal is sealed between the opposite substrates and the display device as shown in FIG. 8 is completed.

  In this embodiment, when patterning the BM 222 around the gate signal line, one mask is used. Instead, it is not necessary to form a BM layer on the counter substrate, and the mask used at this time is necessary. Therefore, there is no increase in the number of masks when the display device is manufactured as a whole.

  In this embodiment, an example of an FPC (Flexible Printed Circuit) terminal portion of the display device of the present invention will be described.

  In the conventional display device, the input part of each circuit is connected to the external input terminal using a wiring formed of S / D metal, and an external signal is input. Here, in the structure of this embodiment, an insulating film is formed on the S / D metal layer, and the wiring formed on the S / D metal layer cannot be connected to the FPC.

  Therefore, a wiring for connecting the input portion of each circuit and the external input terminal is formed in the same layer as the gate electrode using a metal forming the gate electrode. In this specification, the metal forming the gate electrode is referred to as a gate metal.

  FIG. 14 shows a top view and a cross-sectional view of the display device of the present invention.

  FIG. 14A is a top view of a display device of the present invention. A source signal line driver circuit 1401, a gate signal line driver circuit 1402, a pixel portion 1403, and an external input terminal 1404 are formed over the pixel substrate 1400. Reference numeral 1430 denotes a sealing material. In this figure, for the sake of clarity, the counter substrate side and the liquid crystal portion are not shown.

  An FPC terminal 1406 is connected to the external input terminal 1404, and a signal input from the FPC terminal 1406 is input to each circuit through wirings 1407a and 1407b.

  In the drawing, a cross-sectional view taken along line AA ′ is shown in FIG. The same portions as those in FIG. 14A are denoted by the same reference numerals. Note that as a structure of the source signal line driver circuit 1401, a CMOS circuit 1408 in which an N-channel TFT and a P-channel TFT are combined is illustrated. In the pixel portion 1403, only the pixel TFT 1414 is shown. Here, 1422 is a base film, 1421 is a gate insulating film, and 1405 is a liquid crystal. The alignment film and the like are not shown. Further, the counter electrode and the color filter on the counter substrate side 1420 are omitted here.

  In the external input terminal 1404, the FPC terminal 1406 is pasted with an anisotropic conductive resin 1417, and the connection wiring 1410 and the FPC terminal 1406 are connected. Note that the connection wiring 1410 corresponds to 1407a and 1407b in FIG. A signal or the like is input from the outside via the FPC terminal 1406.

  Here, the connection wiring 1410 is formed at the same time as the gate electrode is formed. In order to connect the FPC terminal 1406 to the connection wiring 1410, it is necessary to form a contact hole in the interlayer insulating film 1411. This may be formed at the same time when contact holes are formed for the source wiring 1412, the drain wiring 1413, and the like.

  In addition, after forming the contact hole, when forming the pixel electrode 1415, the ITO film 1416 is simultaneously formed by patterning. By providing the ITO film 1416, adhesion when the FPC terminal 1406 is attached by the anisotropic conductive resin 1417 can be improved, and oxidation of the gate metal forming the connection wiring 1410 can be prevented. it can.

  Note that the anisotropic conductive resin 1417 includes conductive particles 1418 and an adhesive material 1419. Since the outer diameter of the conductive particles 1418 is smaller than the pitch of the wirings 1410, if the amount dispersed in the adhesive 1419 is set appropriately, the corresponding FPC-side wirings and electrical circuits can be electrically connected without short-circuiting with adjacent wirings. Connections can be made.

  In this embodiment, in the display device having the structure of the pixel portion shown in FIG. 1, TFTs and holdings of the pixel portion and the drive circuit portion (source signal line side drive circuit, gate signal line side drive circuit) provided in the periphery of the pixel portion. A method for simultaneously manufacturing the capacitor will be described in detail with reference to FIGS. However, in order to simplify the description, a CMOS circuit which is a basic unit is illustrated in the drive circuit portion.

First, as shown in FIG. 10A, a silicon oxide film is formed on a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass. A base film 5002 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, a silicon oxynitride film 5002a made of SiH ₄ , NH ₃ , and N ₂ O is formed by plasma CVD method to 10 to 200 [nm] (preferably 50 to 100 [nm]), and similarly, SiH ₄ and N _A silicon oxynitride silicon film 5002b formed from ₂ O is stacked to a thickness of 50 to 200 [nm] (preferably 100 to 150 [nm]).
Although the base film 5002 is shown as a two-layer structure in this embodiment, it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

  The island-shaped semiconductor layers 5003 to 5006 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. The island-like semiconductor layers 5003 to 5006 are formed with a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to manufacture a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser is used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 [Hz] and the laser energy density is 100 to 400 [mJ / cm ² ] (typically 200 to 300 [mJ / cm ² ]). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 10 [kHz], and the laser energy density is 300 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ]. / cm ² ]). Then, a laser beam condensed in a linear shape with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80 Perform as ~ 98 [%].

Next, a gate insulating film 5007 is formed to cover the island-shaped semiconductor layers 5003 to 5006. The gate insulating film 5007 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to obtain a reaction pressure of 40 [Pa], a substrate temperature of 300 to 400 [° C.], and a high frequency (13.56). [MHz]), and can be formed by discharging at a power density of 0.5 to 0.8 [W / cm ² ]. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

  Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed with Ta to a thickness of 50 to 100 [nm], and the second conductive film 5009 is formed with W to a thickness of 100 to 300 [nm].

  The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 [μΩcm] and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 [μΩcm] and is used as the gate electrode. It is unsuitable. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm. It can be easily obtained.

When forming a W film, it is formed by sputtering using W as a target. In addition, it can also be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 [μΩcm] or less. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. From this, in the case of the sputtering method, by using a W target having a purity of 99.9999 [%] and further forming a W film with sufficient consideration so that impurities are not mixed in from the gas phase during film formation, A resistivity of 9 to 20 [μΩcm] can be realized.

  Note that in this embodiment, the first conductive film 5008 is Ta and the second conductive film 5009 is W, but there is no particular limitation, and any of them is selected from Ta, W, Ti, Mo, Al, Cu, and the like. Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As another example of a combination other than the present embodiment, a combination in which the first conductive film 5008 is formed of tantalum nitride (TaN) and the second conductive film 5009 is W is used. Is made of tantalum nitride (TaN), the second conductive film 5009 is made of Al, the first conductive film 5008 is made of tantalum nitride (TaN), and the second conductive film 5009 is made of Cu. Can be mentioned.

Next, a resist mask 5010 is formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ and Cl ₂ are mixed in an etching gas, and a coil type electrode of 500 [W] is applied at a pressure of 1 [Pa]. RF (13.56 [MHz]) power is applied to generate plasma. 100 [W] RF (13.56 [MHz]) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °.
In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 [nm] by the overetching process. become. Thus, the first shape conductive layers 5011 to 5016 (the first conductive layers 5011a to 5016a and the second conductive layers 5011b to 5016b) formed of the first conductive layer and the second conductive layer by the first etching treatment. Form. At this time, in the gate insulating film 5007, a region which is not covered with the first shape conductive layers 5011 to 5016 is etched and thinned by about 20 to 50 [nm].
(Fig. 10 (B))

Then, an impurity element imparting N-type is added by performing a first doping process.
As a doping method, an ion doping method or an ion implantation method may be used. The conditions of the ion doping method are a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and an acceleration voltage of 60 to 100 [keV]. As an impurity element imparting N-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 5011 to 5015 serve as a mask for the impurity element imparting N-type, and the first impurity regions 5017 to 5025 are formed in a self-aligning manner. An impurity element imparting N-type conductivity is added to the first impurity regions 5017 to 5025 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ [atoms / cm ³ ]. (Fig. 10 (B))

Next, as shown in FIG. 10C, a second etching process is performed without removing the resist mask. The W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as an} etching gas. At this time, second shape conductive layers 5026 to 5031 (first conductive layers 5026a to 5031a and second conductive layers 5026b to 5031b) are formed by the second etching process. At this time, in the gate insulating film 5007, a region that is not covered with the second shape conductive layers 5026 to 5031 is further etched and thinned by about 20 to 50 [nm].

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, WF ₆ which is a fluoride of W is extremely high, and other WCl ₅ , TaF ₅ and TaCl ₅ are similar. Therefore, both the W film and the Ta film are etched with a mixed gas of CF ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ . Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, the impurity amount imparting N-type is doped as a condition of a high acceleration voltage by lowering the dose than the first doping treatment. For example, the acceleration voltage is set to 70 to 120 [keV] and the dose is 1 × 10 ¹³ [atoms / cm ² ], and the inside of the first impurity region formed in the island-shaped semiconductor layer in FIG. Then, a new impurity region is formed. Doping is performed using the second shape conductive layers 5026 to 5030 as masks against the impurity elements so that the impurity elements are also added to the lower regions of the first conductive layers 5026a to 5030a. Thus, third impurity regions 5032 to 5036 are formed. The concentration of phosphorus (P) added to the third impurity regions 5032 to 5036 has a gradual concentration gradient according to the film thickness of the tapered portions of the first conductive layers 5026a to 5030a. Note that, in the semiconductor layer overlapping the tapered portions of the first conductive layers 5026a to 5030a, although the impurity concentration slightly decreases inward from the end portions of the tapered portions of the first conductive layers 5026a to 5030a, The concentration is similar.

A third etching process is performed as shown in FIG. CHF ₆ is used as an etching gas and a reactive ion etching method (RIE method) is used. By the third etching treatment, the tapered portions of the first conductive layers 5026a to 5031a are partially etched, and a region where the first conductive layer overlaps with the semiconductor layer is reduced. Through the third etching treatment, third-shaped conductive layers 5037 to 5042 (first conductive layers 5037a to 5042a and second conductive layers 5037b to 5042b) are formed. At this time, in the gate insulating film 5007, regions that are not covered with the third shape conductive layers 5037 to 5042 are further etched by about 20 to 50 [nm] to form thin regions.

  By the third etching process, in the third impurity regions 5032 to 5036, the third impurity regions 5032a to 5036a overlapping with the first conductive layers 5037a to 5041a, the first impurity region, the third impurity region, Second impurity regions 5032b to 5036b are formed.

Then, as shown in FIG. 11C, fourth impurity regions 5043 to 5054 having a conductivity type opposite to the first conductivity type are formed in the island-like semiconductor layers 5004 and 5006 forming the P-channel TFT. . Using the third shape conductive layers 5038b and 5041b as masks against the impurity element, impurity regions are formed in a self-aligning manner. At this time, the island-shaped semiconductor layers 5003 and 5005 and the conductive layer 5042 forming the N-channel TFT are covered with a resist mask 5200 in advance. Although phosphorus is added to the impurity regions 5043 to 5054 at different concentrations, the impurity regions 5043 to 5054 are formed by ion doping using diborane (B ₂ H ₆ ), and the impurity concentration is 2 × 10 ²⁰ to 2 × 10 ²¹ [atoms / cm ³ ].

  Through the above steps, impurity regions are formed in each island-like semiconductor layer. The third shape conductive layers 5037 to 5041 overlapping with the island-shaped semiconductor layers function as gate electrodes. Reference numeral 5042 functions as an island-shaped source signal line.

After removing the resist mask 5200, a process of activating the impurity element added to each island-like semiconductor layer is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
In the thermal annealing method, oxygen concentration is 1 [ppm] or less, preferably 0.1 [ppm] or less in a nitrogen atmosphere at 400 to 700 [° C.], typically 500 to 600 [° C.], In this embodiment, heat treatment is performed at 500 [° C.] for 4 hours. However, when the wiring material used for the third shape conductive layers 5037 to 5042 is weak against heat, activation is performed after an interlayer insulating film (mainly composed of silicon) is formed to protect the wiring and the like. Preferably it is done.

  Further, a heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours in an atmosphere containing 3 to 100 [%] hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  Next, as shown in FIG. 12A, a first interlayer insulating film 5055 made of a silicon oxynitride film is formed to a thickness of 100 to 200 [nm]. A second interlayer insulating film 5056 made of an organic insulating material is formed thereon.

  As the second interlayer insulating film 5056, a film made of an organic resin is used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 5056 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. Preferably it may be 1-5 [μm] (more preferably 2-4 [μm]).

  Next, contact holes were formed in the first interlayer insulating film 5055, the second interlayer insulating film 5056, and the gate insulating film 5007.

  The contact holes are formed by dry etching or wet etching. Contact holes reaching the N-type impurity regions 5017, 5018, 5021, and 5023, contact holes reaching the P-type impurity regions 5043, 5048, 5049, and 5054, and source signals A contact hole reaching the line 5042 and a contact hole (not shown) reaching the gate electrode are formed.

  Thereafter, an ITO film having a thickness of 110 [nm] was formed as the pixel electrode 5063 and patterned. Alternatively, a transparent conductive film in which 2 to 20% zinc oxide (ZnO) is mixed with indium oxide may be used. (Fig. 12 (A))

  Thereafter, an S / D metal layer 5100 was formed. In the present embodiment, a laminated film having a three-layer structure in which a titanium film, a titanium nitride film, and an aluminum film are continuously formed by sputtering is used as the S / D metal layer 5100. Of course, other conductive films may be used.

  An insulating layer 5101 is formed on the S / D metal layer 5100. Note that a film made of an organic resin is used as the insulating layer 5101, and polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used as the organic resin. The insulating layer 5101 is formed to a thickness of 5000 mm to 1 μm using these resins. In this embodiment, acrylic is formed to a thickness of 0.6 μm as the insulating layer 5101.

  Next, as shown in FIG. 12B, the insulating layer 5101 and the S / D metal layer 5100 are patterned at the same time, and each wiring (including connection wiring and signal lines) 5057 to 5062, 5099 and the insulating film thereon 5111 was formed.

  Here, FIG. 17A is an enlarged view near the gate signal line 5099 formed by patterning. Etching of the insulating layer 5101 and the S / D metal layer 5100 will be described with reference to FIG. Note that in FIG. 17A, the same reference numerals as those in FIG. 12 denote the same parts.

  Etching is performed by dry etching the acrylic 1704 formed as the insulating layer 5101, wet etching the aluminum layer 1703 of the S / D metal layer 5100, and dry etching the titanium nitride layer 1702 and the titanium layer 1701. Thereby, the shape which made the aluminum layer hollow 0.1 micrometer-0.5 micrometer inside can be produced.

  In FIG. 12B, the drain wiring 5061 and the connection wiring 5062 are arranged so as to be in contact with and overlap with the pixel electrode 5063 to make contact.

  Thus, the TFT of the driving circuit portion, the TFT of the pixel portion, and the storage capacitor are completed on the same substrate. In this specification, for convenience, such a substrate is referred to as an active matrix substrate.

  Note that in this embodiment, a method for manufacturing an active matrix substrate of a transmissive active matrix liquid crystal display device has been described. However, an active matrix substrate of a reflective active matrix liquid crystal display device can also be manufactured by a similar method. .

  FIG. 16A shows a cross-sectional SEM (scanning electron microscope) photograph of the gate signal line and the insulating layer formed on the gate signal line of the active matrix substrate thus obtained. FIG. 16A is an observation image before forming the alignment film.

  In this embodiment, a process of manufacturing an active matrix liquid crystal display device from an active matrix substrate manufactured by the method of Embodiment 3 will be described. FIG. 13 is used for the description.

  After obtaining the active matrix substrate in the state of FIG. 12B, an alignment film 167 is formed over the active matrix substrate of FIG. The alignment film 167 is preferably formed with a thickness of 500 to 1500 mm. In this embodiment, the film thickness is 700 mm.

  Here, as shown in FIG. 17B, the alignment film 167 is placed in the recessed portion of the aluminum layer shown in FIG. Thereby, the influence of the electric field generated around the gate signal line due to the signal voltage of the gate signal line on the liquid crystal part can be further reduced. Note that in FIG. 17B, the same reference numerals as those in FIG. 13 denote the same parts.

  FIG. 16B shows an observation image obtained by covering the gate signal line and the insulating layer formed thereon with an alignment film. In addition, after attaching the alignment film, post-baking is performed at 200 ° C. for 90 minutes.

  In this embodiment, before the alignment film 167 is formed, a columnar spacer (not shown) for maintaining a gap between the substrates is formed at a desired position by patterning an organic resin film such as an acrylic resin film. . Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.

  Next, a counter substrate 168 is prepared. In this counter substrate, a colored layer 174 and a light shielding layer 175 are provided in a color filter arranged corresponding to each pixel. Further, a light shielding layer 177 is also provided in the drive circuit portion. A planarizing film 176 that covers the color filter and the light shielding layer 177 is provided. Next, a counter electrode 169 made of a transparent conductive film was formed over the planarizing film 176 in the pixel portion, an alignment film 170 was formed over the entire surface of the counter substrate, and a rubbing process was performed. The alignment film 170 is preferably formed with a thickness of 500 to 1500 mm. In this embodiment, the film thickness is 700 mm.

  Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are attached to each other with a sealant 171. A filler is mixed in the sealing material 171, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 173 is injected between both the substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 173. In this way, the active matrix liquid crystal display device shown in FIG. 13 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Furthermore, a polarizing plate or the like was appropriately provided using a known technique. And FPC was affixed by the method described in Example 2.

The structure of the liquid crystal display panel thus obtained will be described with reference to the top view of FIG.
In addition, the same code | symbol was used for the part corresponding to FIG.

  The top view shown in FIG. 15 connects the pixel portion 1403, the source signal line driver circuit 1401, the gate signal line driver circuit 1402, the external input terminal 1404 to which the FPC terminal 1406 is pasted, and the external input terminal to the input portion of each circuit. An active matrix substrate on which wirings 1407a and 1407b and the like are formed and an opposite substrate 1420 provided with a color filter and the like are attached to each other with a sealant 1430 interposed therebetween.

  A light shielding layer 477a is provided on the counter substrate side so as to overlap with the source signal line driver circuit 1401, and a light shielding layer 477b is formed on the counter substrate side so as to overlap with the gate signal line driver circuit 1402. In addition, the color filter 409 provided on the counter substrate side over the pixel portion 1403 is provided with a light-shielding layer and colored layers of red (R), green (G), and blue (B) corresponding to each pixel. It has been. When actually displaying, a color display is formed with three colors of a red (R) colored layer, a green (G) colored layer, and a blue (B) colored layer. It shall be arbitrary.

  Here, the color filter 409 is provided on the counter substrate for colorization; however, there is no particular limitation, and the color filter may be formed on the active matrix substrate when the active matrix substrate is manufactured.

  In addition, a light-shielding layer is provided between adjacent pixels in the color filter to shield light other than the display area. Here, the light shielding layers 477a and 477b are also provided in the region covering the driver circuit. However, the region covering the driver circuit is covered with a cover when the liquid crystal display device is incorporated later as a display portion of an electronic device. It is good also as a structure which does not provide a light shielding layer. Further, when the active matrix substrate is manufactured, a light shielding layer may be formed on the active matrix substrate.

  Further, without providing the light-shielding layer, the light-shielding layer is appropriately disposed between the counter substrate and the counter electrode so as to be shielded from light by stacking a plurality of colored layers constituting the color filter. Or the drive circuit may be shielded from light.

  In this way, the liquid crystal display device is completed.

  Note that although a manufacturing method of a transmissive active matrix liquid crystal display device is described in this embodiment, a reflective active matrix liquid crystal display device can be manufactured by a similar method.

  The liquid crystal display device manufactured as in Example 3 and Example 4 can constitute a liquid crystal module, and the liquid crystal display device can be used as a display unit of various electronic devices. Hereinafter, an electronic apparatus in which a liquid crystal display device formed using the present invention is incorporated as a display medium will be described.

  As such an electronic device, a video camera, a digital camera, a head mounted display (goggles type display), a game machine, a car navigation system, a personal computer, a personal digital assistant (mobile computer, mobile phone, electronic book, etc.), and the like can be given. . An example of these is shown in FIG.

  FIG. 18A illustrates a personal computer, which includes a main body 2001, a housing 2002, a display portion 2003, a keyboard 2004, and the like. The liquid crystal display device of the present invention can be used for the display portion 2003 of a personal computer.

  FIG. 18B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The liquid crystal display device of the present invention can be used for a display portion 2102 of a video camera.

  FIG. 18C shows a part of the head-mounted liquid crystal display device (on the right side), which includes a main body 2301, a signal cable 2302, a head fixing band 2303, a display monitor 2304, an optical system 2305, a display portion 2306, and the like. Including. The liquid crystal display device of the present invention can be used for the display portion 2306 of a head-mounted liquid crystal display device.

FIG. 18D shows an image playback device (specifically a DVD playback device) provided with a recording medium.
A main body 2401, a recording medium (CD, LD, DVD, etc.) 2402, an operation switch 2403, a display unit (a) 2404, a display unit (b) 2405, and the like. The display unit (a) mainly displays image information, and the display unit (b) mainly displays character information. However, the liquid crystal display device of the present invention is a display unit (a), ( It can be used for b). Note that the present invention can be used for a CD playback device, a game machine, or the like as an image playback device provided with a recording medium.

  FIG. 18E illustrates a portable (mobile) computer, which includes a main body 2501, a camera portion 2502, an image receiving portion 2503, operation switches 2504, a display portion 2505, and the like. The liquid crystal display device 2505 of the present invention can be used for a display portion of a portable computer.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic device of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-4.

Claims (3)

A transistor and a first wiring on an insulating surface;
A first insulating layer on the first wiring;
A second wiring and a third wiring on the first insulating layer;
A second insulating layer on the second wiring and the third wiring;
A portion of the second insulating layer has a removed region;
The transistor and the first wiring are electrically connected by the third wiring,
The second wiring has a portion recessed inward from the end of the second insulating layer,
An alignment film is formed so as to cover the second insulating layer. In claim 1,
The second wiring has a laminated structure of conductive layers,
The display device is characterized in that one of the laminated structures is recessed in the indented portion. In claim 1 or claim 2,
The display device characterized in that the indented portion is made of an aluminum layer.

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