JP2011060946A - Semiconductor device having position displacement inspection pattern and pattern position displacement inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means which has a position displacement inspection pattern to improve the accuracy of pattern position displacement inspection. <P>SOLUTION: A semiconductor device is provided with a plurality of FETs, a plurality of pairs of reference inspection patterns 19 which are formed simultaneously with drain electrodes and source electrodes of the FETs in a region around an element formation region and provided at regular intervals, respectively, a plurality of inspection target inspection patterns 20 which are formed simultaneously with gate electrodes of the FETs and provided at intervals different from the intervals of the reference inspection patterns 19 between a plurality of pairs of the reference inspection patterns 19, a metal resistive layer 18 which is formed so as to be in contact with the plurality of inspection target inspection patterns 20 and the plurality of pairs of reference inspection patterns 19, a means which measures first resistance between the inspection target inspection patterns 20 and the reference inspection pattern 19 which are adjacent to one-end sides of the patterns 20, and second resistance between the inspection target inspection patterns 20 and the reference inspection patterns 19 which are adjacent to other sides of the patterns 20. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a misalignment inspection pattern for inspecting misalignment of a pattern of a semiconductor device and a pattern misalignment inspection method using the misalignment inspection pattern.

  A conventional semiconductor device is manufactured by sequentially superposing a plurality of different patterns on a wafer. For example, a field effect transistor is manufactured by forming a source electrode and a drain electrode on a wafer, and then forming a gate electrode at a desired position between the source electrode and the drain electrode.

  In such a semiconductor device, pattern misalignment may occur in the manufacturing process. In the above-described example, when the pattern misalignment occurs, for example, the distance between the gate electrode and the drain electrode is deviated from a desired distance, which causes the performance of the apparatus to deteriorate. In addition, when a displacement occurs in the position of the contact hole connecting each electrode and the wiring pattern, the electrode and the wiring are not connected, which also causes the performance of the apparatus to deteriorate.

  For this reason, conventionally, when patterning each layer, a semiconductor device is formed by simultaneously forming inspection patterns called verniers. And the position shift of the pattern each formed in each layer was inspected using the vernier pattern (refer patent documents 1 grade).

  Hereinafter, a method for inspecting misalignment using a vernier pattern will be described using the above-described field effect transistor as an example.

  First, a drain electrode and a source electrode are formed by patterning at desired locations on the wafer. At this time, a plurality of strip-shaped first inspection patterns are simultaneously formed at desired positions. Here, the plurality of first inspection patterns are formed such that the interval between the adjacent inspection patterns is a constant interval L.

  Next, a gate electrode is formed by patterning between the drain electrode and the source electrode. At this time, a plurality of strip-shaped inspection patterns are simultaneously formed at desired positions. Here, the plurality of second inspection patterns are formed such that the interval between adjacent inspection patterns is a constant interval La. One of the plurality of second inspection patterns (hereinafter referred to as the second reference pattern) overlaps with any one of the plurality of first inspection patterns (hereinafter referred to as the first reference pattern). Formed.

  Thereafter, the positions of the first reference pattern and the second reference pattern are confirmed. If these positions overlap, the gate electrode is formed at a desired position between the drain electrode and the source electrode. Can be confirmed.

  Conversely, the positions of the first reference pattern and the second reference pattern are confirmed, and if there is a deviation between them, the positions of the other first inspection pattern and the second inspection pattern are confirmed, Search for overlapping points. Here, for example, when the first inspection pattern shifted from the first reference pattern and the second reference pattern and the second inspection pattern overlap, the gate electrode is connected to the drain electrode or the source electrode. It can be confirmed that the position is shifted by a.

  As described above, the pattern displacement has been inspected. However, this inspection method is an inspection method that is visually confirmed by a human using an optical microscope, and since the amount of misalignment cannot be measured quantitatively, there is a limit to the inspection accuracy of pattern misalignment. Therefore, there is a problem that it is difficult to improve the inspection accuracy of the pattern displacement.

JP-A-2-121324

  An object of the present invention is to provide a semiconductor device having a misalignment inspection pattern capable of improving the inspection accuracy of pattern misalignment and a pattern misalignment inspection method capable of improving the inspection accuracy of pattern misalignment. There is to do.

  The position of the semiconductor device according to the present invention is formed at the same time as a plurality of semiconductor elements formed in an element formation region on a wafer and a test pattern formation region around the element formation region at the same time as the reference pattern of the semiconductor element. A plurality of pairs of reference inspection patterns provided at intervals of the semiconductor element and a pattern to be inspected of the semiconductor element, and a constant interval different from the interval of the reference inspection patterns between the plurality of pairs of reference inspection patterns. A plurality of inspection target inspection patterns provided in the above, a plurality of inspection target inspection patterns and a metal resistance layer provided in contact with the plurality of pairs of reference inspection patterns, and the plurality of inspection target inspections A first resistance between the plurality of reference inspection patterns adjacent to each other in the pattern and one of these patterns, and the plurality of the plurality of reference inspection patterns It is characterized in that it comprises a means for measuring a second resistor, a between the plurality of reference test pattern adjacent the inspected test pattern and the other of each of these patterns.

  Further, the position of the semiconductor device according to the present invention is formed on a wafer on which a plurality of semiconductor elements are formed, and a first wiring layer having a first wiring pattern and an insulating layer on the first wiring layer are interposed. A second wiring layer having a second wiring pattern, a plurality of pairs of reference inspection patterns formed simultaneously with the first wiring pattern and provided at regular intervals, and the second wiring A plurality of inspection target inspection patterns formed at the same time as the pattern and provided between the plurality of pairs of reference inspection patterns at a fixed interval different from the interval of the reference inspection patterns, and the plurality of inspection target inspections A metal resistance layer provided in contact with the pattern and the plurality of pairs of reference inspection patterns, and adjacent to one of the plurality of inspection target inspection patterns and each of these patterns A first resistance between the plurality of reference inspection patterns, a plurality of inspection target inspection patterns, and a second resistance between the plurality of reference inspection patterns adjacent in the other of the patterns, And means for measuring.

  Further, the pattern misalignment inspection method according to the present invention includes a step of forming a plurality of pairs of reference inspection patterns in contact with the metal resistance layer at a predetermined interval simultaneously with the reference pattern, and simultaneously with the pattern to be inspected, Forming a plurality of inspection target inspection patterns in contact with the metal resistance layer at a constant interval different from the interval of the reference inspection patterns between a plurality of pairs of the reference inspection patterns; and the plurality of inspection targets A first resistance between the target inspection pattern and the plurality of reference inspection patterns adjacent in one of each of the patterns; the plurality of inspection target inspection patterns; and the plurality of adjacent ones in the other of these patterns Measuring a second resistance between the reference inspection patterns, and a plurality of the first resistances measured by this process A step of calculating a resistance difference with the second resistor, and a positional deviation of the pattern to be inspected with respect to the reference pattern based on a plurality of resistance differences calculated in this step. It is a method to do.

  According to the present invention, there is provided a semiconductor device having a misregistration inspection pattern capable of improving a pattern misregistration inspection accuracy, and a pattern misregistration inspection method capable of improving a pattern misregistration inspection accuracy. Can be provided.

It is a top view which shows the whole semiconductor device of this embodiment. FIG. 2 is an enlarged top view of a part of FIG. 1. FIG. 3 is an enlarged top view of a part of FIG. 2 and shows a misalignment inspection pattern formed in the semiconductor device of the present embodiment. It is a top view which shows the mask used in the manufacturing process of the misalignment inspection pattern shown by FIG. FIG. 5 is a top view showing a state of alignment of the mask shown in FIG. 4. It is a top view which shows the mask used in the manufacturing process of the misalignment inspection pattern shown by FIG. It is a top view which shows the position shift inspection pattern formed when position shift arises in a to-be-inspected pattern. It is a graph which shows the relationship between the amount of positional deviation and the resistance difference calculated by the positional deviation test pattern.

  Hereinafter, the semiconductor device of this embodiment will be described in detail. In the following description, a field effect transistor (hereinafter referred to as FET) will be described as an example of a semiconductor device.

  FIG. 1 is a top view showing the entire semiconductor device of the present embodiment, specifically, a top view showing a wafer 11 on which a plurality of FETs are formed. As shown in FIG. 1, the wafer 11 is divided into a plurality of cells along the vertical direction (hereinafter referred to as the y-axis direction) and the horizontal direction (hereinafter referred to as the x-axis direction).

  This grid corresponds to, for example, a shot area of an exposure apparatus used when forming an FET. That is, the area exposed by one shot is within the above-mentioned one square.

  2 is an enlarged top view showing one of the cells in FIG. 1 (for example, the cell M in FIG. 1). As shown in FIG. 2, the inside of one square M is constituted by an element formation region 13 in which a plurality of FETs 12 are formed and an inspection pattern formation region 14 around the element formation region 13.

  In the element formation region 13, for example, a plurality of FETs 12 are formed in a lattice shape.

The inspection pattern formation region 14 includes an x-direction misalignment test pattern 15 for inspecting an x-direction pattern misalignment used when forming the FET 12 formed in the element formation region 13, and a y-direction misalignment test pattern 15. A y-direction misalignment inspection pattern 16 for inspecting misalignment is formed.

  3 is an enlarged top view showing the x-direction misalignment inspection pattern 15 of FIG. As shown in FIG. 3, the x-direction misalignment inspection pattern 15 includes a plurality of sets of misalignment inspection patterns 17 and a metal resistance layer 18 provided so as to be in contact with each of the misalignment inspection patterns 17.

  The metal resistance layer 18 is a metal formed on the wafer 11 so as to extend in a strip shape along the x direction. A plurality of sets of misregistration inspection patterns 17 are provided on the metal resistance layer 18 so as to be in contact with the resistance layer 18. Each set of misalignment inspection patterns 17 includes a pair of reference inspection patterns 19 that serve as a reference for misalignment, and an inspection target inspection pattern 20 provided between the reference inspection patterns 19.

  A plurality of pairs of reference inspection patterns 19 provided in the plurality of sets of misregistration inspection patterns 17 are provided at regular intervals (for example, a μm intervals). Further, the central interval between the respective reference patterns 19 is provided, for example, at an interval of b μm.

  On the other hand, the inspection target inspection pattern 20 is provided at a constant interval (for example, an interval of a + b−1 μm) different from the interval of the reference inspection pattern 19. At this time, if the misalignment inspection pattern 17 located at the center of the plurality of sets of misalignment inspection patterns 17 is a first inspection pattern 17-1, an object to be inspected provided in the first inspection pattern 17-1. The inspection pattern 20 is ideally formed so as to be arranged at the center position of the reference inspection pattern 19.

  As a result, the second inspection pattern 17-2 adjacent to the first inspection pattern 17-1 in the + x direction is inspected at a position shifted by −1 μm from the center position of the reference inspection pattern 19. A pattern 20 is formed.

  Similarly, the third inspection pattern 17-3 adjacent to the second inspection pattern 17-2 in the + x direction is inspected at a position shifted by −2 μm from the center position of the reference inspection pattern 19. A pattern 20 is formed.

  Further, the fourth inspection pattern 17-4 adjacent in the −x direction of the first inspection pattern 17-1 described above is a test pattern to be inspected at a position shifted by +1 μm from the center position of the reference inspection pattern 19. 20 is formed.

  Similarly, the fifth inspection pattern 17-5 adjacent in the −x direction of the above-described fourth inspection pattern 17-4 has the inspection target inspection at a position shifted by +2 μm from the center position of the reference inspection pattern 19. A pattern 20 is formed.

  The y-direction misalignment test pattern 16 is obtained by rotating the same configuration as the x-direction misalignment test pattern 17 shown in FIG. 3 by 90 degrees.

  The above-described misregistration inspection pattern 17 may be formed by forming the reference inspection pattern 19 at the same time as the reference pattern serving as a reference for misregistration and the inspection target inspection pattern 20 at the same time as the pattern to be inspected. When it is desired to inspect the positional deviation of the gate electrode 23 with respect to the drain electrode 21 and the source electrode 22 in the FET 12 shown in FIG. 2, the reference inspection pattern 19 is formed together with the drain electrode 20 and the source electrode 21, and the inspection target inspection pattern 20 is gated. It is formed together with the electrode 23.

  Specifically, it is as follows. First, an impurity layer such as a drain region, a source region, and a channel layer of the FET 12 and a metal resistance layer 18 are formed on the surface of the wafer 11, and then a resist layer is formed on the wafer 11, and as shown in FIG. The resist layer is exposed using a mask 27 having an opening 24 for forming the drain electrode 21, an opening 25 for forming the source electrode 22, and an opening 26 for forming the reference inspection pattern 19.

  Here, each of the openings 24, 25, and 26 of the mask 27 is formed at a predetermined position from a predetermined reference point on the mask 27.

  As shown in FIG. 5, for example, the mask 27 is aligned with a mask alignment mark 31-1 formed on the wafer 11 and an alignment mark 31-2 formed on the mask 27 (FIG. 5). 4 is not shown).

  Next, the exposed resist layer is developed, and a conductor such as a desired metal is vapor-deposited on the developed resist layer. Thereby, the drain electrode 21, the source electrode 22, and the reference inspection pattern 19 are formed.

  Next, after removing the resist layer, a resist layer is formed again on the wafer 11, and an opening 28 for forming the gate electrode 23 and an inspection target inspection pattern 20 as shown in FIG. 6 are formed. The resist layer is exposed using a mask 30 having openings 29.

  Here, the openings 28 and 29 of the mask 30 define the reference point of the mask 30 corresponding to the reference point of the mask 27, and are formed at predetermined positions from this position. In particular, the opening 29-1 for providing the inspection target inspection pattern 20 of the first inspection pattern 17-1 corresponds to the center position of the pair of openings 26-1 for providing the reference inspection pattern 19. Formed in position.

  Further, the alignment of the mask 30 is performed, for example, as shown in FIG. 5, for example, the mask alignment mark 31-1 formed on the wafer 11 and the alignment mark 31-3 formed on the mask 30. (Not shown in FIG. 6).

  Next, the exposed resist layer is developed, and a conductor such as a desired metal is vapor-deposited on the developed resist layer. Thereby, the gate electrode 23 and the inspection target inspection pattern 20 are formed.

  In the ideal case where the above-described forming method does not cause the displacement of the gate electrode 23 with respect to the drain electrode 21 and the source electrode 22, the x-direction displacement inspection pattern 15 shown in FIG. A shift inspection pattern 16 is formed.

  However, when the position of the gate electrode 23 is shifted by c μm in the x direction, for example, as shown in FIG. And the position indicated by the dotted line in FIG. 7 are shifted by c μm in the x direction.

  Next, a pattern misalignment inspection method using the above-described misalignment inspection pattern 17 will be described.

  First, a direct current voltage is applied to each of the reference inspection patterns 19 included in the plurality of sets of misalignment inspection patterns 17 and the inspection target inspection pattern 20 between them, and a direct current is passed between them. By flowing a direct current in this way, the resistance R1 between the inspection target inspection pattern 20 of each misregistration inspection pattern 17 and the reference inspection pattern 19 on the right side thereof, the inspection target inspection pattern 20 and this The resistance R2 between the left reference inspection pattern 19 and the resistance difference ΔR = R1−R2 is calculated.

  Note that a method of measuring the resistances R1 and R2 by applying a DC voltage to the reference inspection pattern 19 and the inspection target inspection pattern 20 between them may be automatically performed using, for example, a semiconductor test apparatus. . That is, the semiconductor test apparatus has a plurality of probers that are in contact with a plurality of sets of misalignment inspection patterns 17, and a desired voltage is applied by these probers. Furthermore, each resistance R1, R2 is measured by detecting the voltage value applied and the current value flowing through each. Also, the resistance difference ΔR = R1−R2 may be calculated in the above-described semiconductor test apparatus.

  Next, as shown in FIG. 8, the calculated ΔR = R1− where the horizontal axis represents the amount of deviation of the pattern to be inspected (for example, the gate electrode 23) from the reference pattern (for example, the drain electrode 21 and the source electrode 22). The above calculation results are plotted on a graph with R2 as the vertical axis.

  Specifically, this plot is performed as follows. ΔR calculated by the first inspection pattern 17-1 is plotted on the vertical axis. Further, ΔR calculated by the second inspection pattern 17-2 is plotted at a position where the shift amount (horizontal axis) is 1 μm. Similarly, R1-R2 calculated by the third, fourth, and fifth inspection patterns 17-3, 17-4, and 17-5 have deviation amounts (horizontal axes) of 2 μm, −1 μm, and −2 μm, respectively. Plot each at the position.

  Each of the above-described misregistration inspection patterns 17 is formed by shifting the position of the inspection target inspection pattern 20 with respect to the center position of the reference inspection pattern 19 by 1 μm. The plot of may be performed as follows. ΔR calculated by the first inspection pattern 17-1 is plotted on the vertical axis in the same manner as described above. On the other hand, ΔR calculated by the second inspection pattern 17-2 is plotted at a position where the deviation amount (horizontal axis) is d μm. Similarly, ΔR calculated by the third, fourth, and fifth inspection patterns 17-3, 17-4, and 17-5 are positions where the deviation amounts (horizontal axes) are 2d μm, −d μm, and −2 d μm, respectively. Plot each.

  Here, as shown in FIG. 7, when the calculated ΔR is plotted and the straight line A drawn by connecting these passes through the origin, the position of the non-inspection target pattern is not shifted from the position of the reference pattern. Indicates. This is because the first inspection pattern 17-1 is formed so that ΔR calculated thereby is 0 in an ideal case where there is no positional deviation.

  On the other hand, when the calculated ΔR is plotted and the straight line B drawn by connecting them is shifted in the negative direction of the vertical axis with respect to the straight line A, the position of the non-inspection target pattern with respect to the reference pattern position is in the + x direction. Indicates that there is a shift. This is because when the position of the inspection target pattern with respect to the position of the reference pattern is shifted in the x direction, the position of the inspection target inspection pattern 20 is shifted in the + x direction accordingly. This is because the value of R1 decreases and the value of R2 increases.

  Therefore, contrary to the above, when the straight line drawn by connecting the plots is shifted in the positive direction of the vertical axis with respect to the straight line A, the position of the pattern to be inspected is shifted in the −x direction with respect to the position of the reference pattern. It shows that. This is for the same reason. That is, when the position of the inspection target pattern with respect to the position of the reference pattern is shifted in the −x direction, the position of the inspection target inspection pattern 20 is shifted in the −x direction accordingly, and as a result, the R1 of each inspection pattern is changed. This is because the value increases and the value of R2 decreases.

  Furthermore, by calculating the intersection coordinates between the straight line drawn by connecting the plots and the horizontal axis in FIG. 4, the amount of deviation of the position of the pattern to be inspected from the position of the reference pattern can be quantitatively calculated. That is, by calculating the shift amount when ΔR becomes 0, the shift amount of the position of the non-inspection target pattern with respect to the position of the reference pattern can be calculated quantitatively.

  By such a method, it is possible to quantitatively calculate the shift amount of the position of the pattern to be inspected with respect to the position of the reference pattern.

  Note that the above-described plot of the resistance difference ΔR and the calculation of the shift amount when ΔR becomes 0 may be performed in the above-described semiconductor test.

  As described above, according to the semiconductor device according to the present embodiment, the plurality of sets of misregistration inspection patterns 17 as described above are provided for each shot, and the resistance difference ΔR of each misregistration inspection pattern 17 is calculated. Then, by showing this result on the graph, it is possible to quantitatively calculate the shift amount of the position of the pattern to be inspected with respect to the position of the reference pattern. Therefore, it is possible to improve the inspection accuracy of the pattern displacement.

  Further, since the pattern positional deviation amount can be calculated quantitatively for each shot, the deviation direction and the deviation amount distribution in the wafer 11 surface can also be known.

  In such a pattern positional deviation inspection method, in the above description, the case of inspecting the positional deviation of the gate electrode 23 with respect to the drain electrode 21 and the source electrode 22 in the FET 12 has been described. However, for example, a plurality of wiring layers including a wiring layer in which wiring patterns for supplying signals to the drain electrode 21, the source electrode 22, and the gate electrode 23 are formed on the FET 12 via an insulating film.

At this time, when a position shift occurs in the second wiring pattern of the upper wiring layer formed via the insulating film with respect to the first wiring pattern formed in the lower wiring layer, these first wiring patterns are formed. The second wiring pattern is not connected through the contact hole formed in the insulating film. Therefore, the above-described pattern misalignment inspection method can be similarly applied to the case of inspecting such misalignment of the wiring pattern.

  That is, the reference inspection pattern 19 is formed in, for example, the lower wiring layer simultaneously with the first wiring pattern that is the reference pattern, and the inspection target inspection pattern 20 is simultaneously formed with the second wiring pattern that is the inspection target pattern. And formed in the lower wiring layer. At this time, the metal resistance layer 18 may be formed at a position in contact with all the misregistration inspection patterns 17, for example, in the lower wiring layer.

  The inspection target inspection pattern 20 may be formed on an upper wiring layer. In this case, the metal resistance layer 18 needs to be formed on the insulating film in order to make contact with all the misalignment inspection patterns 17.

  By configuring as described above and applying the pattern misalignment inspection method described above, it is possible to quantitatively calculate the amount of misalignment of the second wiring pattern with respect to the first wiring pattern. It becomes possible to improve the inspection accuracy of deviation.

  The pattern displacement inspection method described above can be similarly applied to the inspection of the displacement of the first wiring pattern or the second wiring pattern with respect to the positions of the electrodes 21, 22, and 23.

  Further, the above-described pattern misalignment inspection method can be similarly applied to other semiconductor devices that require pattern superposition in manufacturing and semiconductor devices such as IC and LSI.

  In addition to semiconductor devices, the present invention can be similarly applied to all devices as long as they require pattern alignment during manufacturing.

  For example, a liquid crystal display has a structure in which a liquid crystal layer is formed between two glass substrates arranged opposite to each other via an alignment film. A plurality of transistors are formed in a matrix on a glass substrate. Further, a signal line for supplying a desired signal to the transistor and a scanning line for supplying a control signal for controlling the transistor operation are formed on the glass substrate.

  The transistor supplies a desired signal to an electrode formed in a matrix on a glass substrate, and the signal is supplied to the electrode to control transmission and non-transmission of light through the liquid crystal layer.

  The signal line is composed of a plurality of wirings parallel to each other. Similarly, the scanning line includes a plurality of wirings parallel to each other. For example, the signal line is formed in the lower wiring layer, and the scanning line is formed in the upper wiring layer so as to be orthogonal to the signal line. Note that each transistor is connected to a signal line or a scanning line through a contact hole formed in an insulating layer formed between the layers.

  As described above, when forming a transistor, a scanning line, or a signal line on a glass substrate used for a liquid crystal display, the x-direction misalignment inspection pattern 15 or the y-direction misalignment inspection pattern 16 is simultaneously formed. Thus, it is possible to quantitatively calculate the positional deviation amount of each electrode constituting the transistor, the positional deviation amount of the pattern between the transistor and the scanning line or the signal line, and the positional deviation amount of the pattern between the scanning line and the signal line. Can do.

  For example, when forming a transistor, as in the case of the above-described FET 12, for example, a plurality of sets of reference inspection patterns 19 are formed together with the drain electrode and the source electrode of the transistor which is the reference pattern, and the pattern to be inspected is formed. A plurality of inspection target inspection patterns 20 may be formed together with a gate electrode of a certain transistor. At this time, a plurality of misalignment inspection patterns 17 including a plurality of sets of reference inspection patterns 19 and a plurality of inspection target inspection patterns 20 are formed, for example, in a peripheral portion (non-display region) of the glass substrate. Note that the metal resistance layer 18 may be formed at any location as long as it is in contact with all the misalignment inspection patterns 17, for example, at the peripheral portion of the glass substrate.

  Further, when forming the scanning line and the signal line, for example, a plurality of sets of signal lines that are reference patterns are used together with the signal line that is the reference pattern, as in the above-described inspection of the positional deviation between the first wiring pattern and the second wiring pattern. The reference inspection pattern 19 may be formed, and a plurality of inspection target inspection patterns 20 may be formed along with the scanning lines that are inspection target patterns. At this time, a plurality of misalignment inspection patterns 17 including a plurality of sets of reference inspection patterns 19 and a plurality of inspection target inspection patterns 20 are formed, for example, in a peripheral portion (non-display region) of the glass substrate. Note that the metal resistance layer 18 may be formed at any location as long as it is in contact with all the misalignment inspection patterns 17, for example, in the lower wiring layer.

  Note that the present invention can be similarly applied to the inspection of the positional deviation of the signal line or the scanning line with respect to the position of each electrode of the transistor.

  Although the application example of the present invention has been described above, the misregistration inspection pattern 17 itself is not limited to the above-described form. For example, the number of sets in which the misalignment inspection pattern 17 is formed is not limited. However, the number of sets of misalignment inspection patterns 17 is increased, and the amount of misalignment of the inspection target inspection pattern 20 with respect to the center position of the reference inspection pattern 19 of each misalignment inspection pattern 17 (in the above example, ± By shortening (1 μm, ± 2 μm), more accurate inspection is possible.

  Further, the shape or the like of the above-described misregistration inspection pattern 17 is not limited as long as R1-R2 can be calculated.

  In the present invention, the pattern misalignment detection method using the misalignment test pattern 17 described above is automatically performed using a semiconductor test apparatus, but may be performed manually by a human. Even in this case, the positional deviation amount can be calculated quantitatively.

11 ... Wafer 12 ... FET
13 ... Element formation region 14 ... Inspection pattern formation region 15 ... x-direction displacement inspection pattern 16 ... y-direction displacement inspection pattern 17 ... Position displacement inspection pattern 17-1 ... No. 1 inspection pattern 17-2 ... 2nd inspection pattern 17-3 ... 3rd inspection pattern 17-4 ... 4th inspection pattern 17-5 ... 5th inspection pattern 18. .. Metal resistance layer 19... Reference inspection pattern 20... Inspection target inspection pattern 21... Drain electrode 22... Source electrode 23. .. Source electrode forming opening 26... Reference pattern forming opening 27... Mask 28... Gate electrode forming opening 29. ... Mark for the alignment of the alignment marks 31-2, 31-3 ... mask on Fine

Claims (9)

A plurality of semiconductor elements formed in an element formation region on the wafer;
A plurality of pairs of reference inspection patterns formed at the same time as the reference pattern of the semiconductor element, in the inspection pattern formation region around the element formation region,
A plurality of inspection target inspection patterns that are formed at the same time as the inspection target pattern of the semiconductor element, and are provided between the plurality of pairs of reference inspection patterns at fixed intervals different from the intervals of the reference inspection patterns,
A metal resistance layer provided in contact with the plurality of inspection target inspection patterns and the plurality of pairs of reference inspection patterns;
A first resistance between the plurality of inspection target inspection patterns and the plurality of reference inspection patterns adjacent in one of these patterns, and a plurality of inspection target inspection patterns and the other of these patterns adjacent to each other Means for measuring a second resistance between the plurality of reference inspection patterns;
A semiconductor device comprising: The semiconductor element is a semiconductor element having a drain electrode, a source electrode and a gate electrode,
2. The semiconductor device according to claim 1, wherein the reference pattern is the drain electrode and the source electrode, and the pattern to be inspected is the gate electrode.   The semiconductor device according to claim 2, wherein the metal resistance layer is formed on the wafer. A first wiring layer formed on a wafer on which a plurality of semiconductor elements are formed and having a first wiring pattern;
A second wiring layer formed on the first wiring layer via an insulating layer and having a second wiring pattern;
A plurality of pairs of reference inspection patterns formed at the same time as the first wiring pattern and provided at regular intervals;
A plurality of inspection target inspection patterns formed simultaneously with the second wiring pattern, and provided between the plurality of pairs of reference inspection patterns at fixed intervals different from the intervals of the reference inspection patterns;
A metal resistance layer provided in contact with the plurality of inspection target inspection patterns and the plurality of pairs of reference inspection patterns;
The plurality of inspection target inspection patterns, a first resistance between the plurality of reference inspection patterns adjacent in one of these patterns, the plurality of inspection target inspection patterns, and the other of these patterns Means for measuring a second resistance between the plurality of adjacent reference test patterns at
A semiconductor device comprising:   5. The semiconductor device according to claim 4, wherein the plurality of pairs of reference inspection patterns, the plurality of inspection target inspection patterns, and the metal resistance layer are formed in the first wiring layer. Simultaneously with the reference pattern, forming a plurality of pairs of reference inspection patterns in contact with the metal resistance layer at regular intervals, and
Simultaneously with the inspection target pattern, a plurality of inspection target inspection patterns are formed between the plurality of pairs of reference inspection patterns so as to contact the metal resistance layer at a constant interval different from the interval of the reference inspection patterns. Process,
The plurality of inspection target inspection patterns, a first resistance between the plurality of reference inspection patterns adjacent in one of these patterns, the plurality of inspection target inspection patterns, and the other of these patterns Measuring a second resistance between the plurality of adjacent reference test patterns in FIG.
Calculating a resistance difference between each of the plurality of first resistors and the second resistors measured by this step;
A pattern misalignment inspection method, comprising: calculating a misalignment of the pattern to be inspected with respect to the reference pattern based on a plurality of resistance differences calculated in this step. The step of calculating the positional deviation includes plotting the plurality of resistance differences on a graph in which the horizontal axis is the positional deviation and the vertical axis is the resistance difference;
Calculating intersection coordinates of a straight line passing through the plurality of plots and the horizontal axis;
The pattern misalignment inspection method according to claim 6, further comprising:   8. The reference pattern according to claim 6, wherein the reference pattern is a drain electrode and a source electrode of a transistor formed on a wafer or a glass substrate, and the pattern to be inspected is a gate electrode of the transistor. Pattern misalignment inspection method.   The reference pattern is a first wiring pattern formed on a first wiring layer on a wafer or a glass substrate, and the pattern to be inspected is formed on a second wiring layer on the first wiring layer. The pattern misalignment inspection method according to claim 6, wherein the second pattern is a second wiring pattern.

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