JP2011060897A - Annealing apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an annealing apparatus and method that obtain a desired temperature distribution of a semiconductor substrate in annealing. <P>SOLUTION: The annealing apparatus 1 includes: a top lamp 22 that is arranged on a first area 201 above a wafer 4 and corresponding to the wafer 4; a first and second lateral lamps 24, 26 that are arranged in a second area 202 located around the first area 201; and control unit 8 for controlling the top lamp 22, and the first and second lateral lamps 24, 26 to emit light at different timings. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an annealing apparatus and an annealing method.

  As a conventional technique, a heat treatment apparatus is known in which, among a plurality of arranged flash lamps, an end side flash lamp is arranged close to the wafer surface (see, for example, Patent Document 1).

  According to this heat treatment apparatus, since the flash lamp on the end side is disposed close to the wafer surface, the illuminance of the flash lamp on the end side is relatively higher than the illuminance from the other flash lamp side during the annealing process. It is said that the temperature difference between the central portion and the outer peripheral portion of the wafer is reduced.

  Further, as a conventional technique, there is known a hot plate that reduces the temperature difference between the central portion and the outer peripheral portion during annealing by providing a temperature difference between the central portion and the outer peripheral portion of the wafer and heating (for example, , See Patent Document 2).

  However, in the heat treatment apparatus described in Patent Document 1, since the flash lamps are turned on simultaneously, it is difficult to obtain a desired temperature distribution on the wafer. Further, in the hot plate described in Patent Document 2, heating with a temperature difference between the central portion and the outer peripheral portion of the wafer promotes solid phase growth in the layer implanted with the amorphized impurities. The reflectance of the light emitted from the flash lamp is increased, and the high temperature at the outer peripheral portion is hindered.

JP 2006-278754 A JP-A-11-297806

  An object of the present invention is to provide an annealing apparatus and an annealing method capable of obtaining a desired temperature distribution of a semiconductor substrate in an annealing process.

  One embodiment of the present invention is arranged in a first flash lamp portion disposed in a first region corresponding to the semiconductor substrate above the semiconductor substrate, and in a second region located around the first region. There is provided an annealing apparatus comprising: the second flash lamp unit that is configured; and a control unit that controls the first flash lamp unit and the second flash lamp unit to emit light at different timings.

  According to another aspect of the present invention, a first flash lamp unit disposed in a first region corresponding to the semiconductor substrate above the semiconductor substrate and a second region positioned around the first region are provided. Provided is an annealing method for emitting light at a different timing from the arranged second flash lamp section.

  According to the present invention, a desired temperature distribution of the semiconductor substrate can be obtained in the annealing process.

FIG. 1A is a schematic diagram of an annealing apparatus according to the first embodiment of the present invention, and FIG. 1B is a side view of the annealing apparatus. FIG. 2 is a block diagram showing the configuration of the annealing apparatus according to the first embodiment of the present invention. FIG. 3A is a graph of lamp intensity and time when the lamp intensity of the upper lamp unit and the first and second side lamp units according to the first embodiment of the present invention are the same, (b ) Is a graph of the central wafer surface temperature and time, and (c) is a graph of the outer peripheral wafer surface temperature and time. FIG. 4A is a graph of lamp intensity and time when the lamp intensity of the upper lamp unit and the first and second side lamp units according to the first embodiment of the present invention are the same, (b ) Is a graph of the central wafer surface temperature and time, and (c) is a graph of the outer peripheral wafer surface temperature and time. FIG. 5A is a graph of lamp intensity and time when the lamp intensity of the upper lamp unit according to the first embodiment of the present invention is different from that of the first and second side lamp units. ) Is a graph of the central wafer surface temperature and time, and (c) is a graph of the outer peripheral wafer surface temperature and time. FIG. 6A is a graph of lamp intensity and time when the lamp intensity of the upper lamp unit according to the first embodiment of the present invention is different from that of the first and second side lamp units. ) Is a graph of the central wafer surface temperature and time, and (c) is a graph of the outer peripheral wafer surface temperature and time. FIG. 7A is a graph of lamp intensity and time when the light emission timing is Δt5 according to the first embodiment of the present invention, and FIG. 7B is the outer peripheral wafer surface when the light emission timing is Δt5. It is a graph of temperature and time. FIG. 8A is a schematic diagram of an annealing apparatus according to the second embodiment of the present invention, and FIG. 8B is a side view of the annealing apparatus. FIG. 9A is a schematic view of an annealing apparatus according to the third embodiment of the present invention, and FIG. 9B is a side view of the annealing apparatus. FIG. 10 is a schematic diagram of an annealing apparatus according to the fourth embodiment of the present invention. FIG. 11A is a side view of an annealing apparatus according to the fourth embodiment of the present invention, and FIG. 11B is a top view of the annealing apparatus. 12A to 12C are schematic diagrams relating to the arrangement of the upper lamp part and the side lamp part according to the fourth embodiment of the present invention. FIG. 13 is a schematic view showing a modification of the annealing apparatus of the present invention.

[First embodiment]
(Configuration of annealing equipment)
FIG. 1A is a schematic diagram of an annealing apparatus according to the first embodiment of the present invention, and FIG. 1B is a side view of the annealing apparatus. As shown in FIGS. 1A and 1B, the annealing apparatus 1 includes a lamp unit 2 including a plurality of flash lamps 20 and a hot plate 3 that heats a wafer 4 as a semiconductor substrate from below. It is roughly structured.

  The lamp unit 2 is provided outside a chamber to be described later. For example, a plurality of flash lamps 20 are arranged above the hot plate 3 so that their longitudinal directions are adjacent to each other at a constant interval. The lamp unit 2 is positioned above the wafer 4 and in the vicinity of the upper region 22 as the first flash lamp unit disposed in the first region 200 corresponding to the wafer 4 and the first region 200. The first and second side lamp parts 24 and 26 as the second flash lamp part arranged in the second region 202 are configured.

  The flash lamp 20 is, for example, a Xe lamp that has a cylindrical elongated shape and heats the surface of the wafer 4 by emitting light in pulses. The Xe lamp has an insulating Xe gas sealed inside a glass tube, and a positive electrode and a negative electrode connected to a capacitor are disposed at both ends thereof. The Xe lamp has a trigger electrode connected to the first power supply unit 6 outside the glass tube.

  In the Xe lamp, when a high voltage is applied from the first power supply unit 6 to the trigger electrode, Xe gas inside the glass tube along the trigger electrode is ionized. When the Xe gas is ionized, the electric resistance value between the positive electrode and the negative electrode is lowered to be in a conductive state, and the energy charged in the capacitor is discharged through the Xe lamp. The Xe lamp emits light when this discharge current flows through the Xe gas. The surface temperature of the wafer 4 reaches approximately 1200 to 1300 ° C. by heating by the lamp unit 2 in which a plurality of flash lamps 20 are arranged.

  Note that the flash lamp 20 is not limited to the Xe lamp. For example, a flash lamp using other rare gas, mercury and hydrogen, an excimer laser, a YAG (Yttrium Aluminum Garnet) laser, a carbon monoxide gas laser, and a carbon dioxide gas laser. Or a light source capable of high-luminance emission such as a Xe arc discharge lamp.

  In the first region 200, for example, as shown in FIG. 1B, the wafer 4 placed on the hot plate 3 is projected in the direction perpendicular to the surface of the hot plate 3, and the projected wafer is projected. This is an area formed by a plurality of flash lamps 20. The second area 202 is an area formed by the flash lamp 20 other than the first area 200.

  For example, when the wafer 4 is viewed from a direction perpendicular to the surface of the wafer 4, the upper lamp unit 22 has the flash lamp 20 in a square area centered on the wafer 4 and including the entire wafer 4. They are formed side by side.

  The first side lamp portion 24 is constituted by, for example, at least one flash lamp 20 arranged on the left side of the upper lamp portion 22 shown in FIG. Similarly, the 2nd side lamp part 26 is comprised from the some flash lamp 20 arrange | positioned at the right side of the upper lamp part 22 shown, for example in FIG.1 (b).

  The hot plate 3 is disposed in a chamber to be described later. For example, a heating wire such as a nichrome wire or an infrared lamp such as a halogen lamp is disposed therein. The hot plate 3 raises the surface temperature of the wafer 4 to about 500 ° C., for example.

  For example, the hot plate 3 in the present embodiment is configured to heat the wafer 4 so that the central portion 40 and the outer peripheral portion 42 of the wafer 4 have the same temperature. Note that the hot plate 3 is heated with a temperature difference between the central portion 40 and the outer peripheral portion 42 of the wafer 4 within a range in which solid phase growth is not promoted in a layer implanted with an amorphized impurity, for example. It may be configured.

  FIG. 2 is a block diagram showing the configuration of the annealing apparatus according to the first embodiment of the present invention. As shown in FIG. 2, the annealing apparatus 1 further includes a lamp control unit 5, a first power supply unit 6, a second power supply unit 7, a control unit 8, and a chamber 10.

  The lamp control unit 5 switches the connection between the upper lamp unit 22, the first and second lamp units 24 and 26, and the first power supply unit 6 based on control by the control unit 8, for example.

  The first power supply unit 6 drives the lamp unit 2 via the lamp control unit 5 with a pulse width of approximately 0.5 to 2.0 milliseconds, for example.

  The second power supply unit 7 supplies power to the hot plate 3 based on the control of the control unit 8.

  The control unit 8 includes process data 80 and timing data 81, for example. The process data 80 is data related to annealing such as the amount of power supplied to the hot plate 3 via the second power supply unit 7, for example. The timing data 81 is data relating to, for example, the pulse width of the power supplied to the upper lamp unit 22, the first and second side lamp units 24, 26, lamp intensity, and light emission timing.

For example, the control unit controls the first power supply unit 6 to control the pulse width and the lamp intensity for driving the lamp unit 2. The lamp intensity density of the lamp unit 2 is, for example, 15 to 30 J / cm ² . The control unit 8 adjusts the temperature of the hot plate 3 by controlling the power supplied to the hot plate 3 by controlling the second power supply unit 7 based on the process data 80, for example.

  For example, the control unit 8 controls the lamp control unit 5 based on the process data 80 and the timing data 81 to switch which flash lamp 20 is supplied with the electric power supplied from the first power supply unit 6.

  The chamber 10 includes, for example, a window 12 that transmits light from the lamp unit 2. The lamp unit 2 raises the surface temperature of the wafer 4 on the hot plate 3 through the window 12.

  Below, an example of operation | movement of the annealing apparatus 1 of this Embodiment is demonstrated.

(Operation of annealing equipment)
First, the lamp intensity of the upper lamp part 22 is the same as that of the first and second side lamp parts 24, 26, and the light emission timings of the first and second side lamp parts 24, 26 are set higher than those of the upper lamp part 22. A case where the annealing process is performed with a delay of Δt 1 msec will be described.

  FIG. 3A is a graph of lamp intensity and time when the lamp intensity of the upper lamp unit and the first and second side lamp units according to the first embodiment of the present invention are the same, (b ) Is a graph of the central wafer surface temperature and time, and (c) is a graph of the outer peripheral wafer surface temperature and time. 3A, the horizontal axis represents time and the vertical axis represents lamp intensity. In FIGS. 3B and 3C, the horizontal axis represents time (msec) and the vertical axis represents room temperature (for example, 27 ° C.). The wafer surface temperature. In each of the following embodiments, the lamp intensity indicates, for example, the lamp intensity of one flash lamp 20, the central wafer surface temperature indicates the average surface temperature of the central part 40 of the wafer 4, The outer peripheral wafer surface temperature indicates the average surface temperature of the outer peripheral portion 42 of the wafer 4.

  Here, in each of the following embodiments, the pulse width of the power supplied from the first power supply unit 6 of the upper lamp unit 22 and the first and second side lamp units 24 and 26 is the same tm seconds ( For example, 0.5 to 2.0 milliseconds). Further, in each of the following embodiments, the lamp intensity of the upper lamp portion 22, the first and second side lamp portions 24, 26 is aJ (for example, 24J) for the stronger one and fJ (for example, for the weaker one). 22J.). This difference in lamp intensity (= af) is preferably within 10%, for example, and more preferably 5% or less.

  First, the control unit 8 of the annealing apparatus 1 controls the second power supply unit 7 after the wafer 4 is placed on the hot plate 3 based on the process data 80, and moves the wafer 4 through the hot plate 3. Heat to 500 ° C.

  Next, the control unit 8 drives the upper lamp unit 22 with the lamp intensity aJ for tm seconds, for example, via the lamp control unit 5 and the first power supply unit 6 based on the process data 80 and the timing data 81, and Δt1m After a second, the first and second side lamp portions 24 and 26 are driven at a lamp intensity aJ for tm seconds, and the annealing process of the wafer 4 is finished.

  The lamp intensity of the flash lamp 20 constituting the upper lamp portion 22 is, for example, a curve 100 as shown in FIG. 3A, and the flash lamp 20 constituting the first and second side lamp portions 24 and 26. The lamp intensity is, for example, a curve 102.

  The central wafer surface temperature that changes due to the light emitted from the upper lamp section 22 is, for example, a curve 104 as shown in FIG. Further, the central wafer surface temperature that changes due to the light emission of the first and second side lamp portions 24 and 26 becomes, for example, a curve 106 as shown in FIG.

  The surface temperature at the central portion 40 of the wafer 4 becomes the maximum temperature b by the light emission of the upper lamp portion 22 and the light emission of the first and second side lamp portions 24 and 26 after Δt1 msec from the upper lamp portion 22. A convex curve 108 having a vertex is obtained.

  Further, the outer peripheral wafer surface temperature that changes due to the light emission of the upper lamp portion 22 is, for example, a curve 110 as shown in FIG. Further, the outer peripheral wafer surface temperature that changes due to the light emission of the first and second side lamp portions 24 and 26 becomes, for example, a curve 112 as shown in FIG.

  The surface temperature of the outer peripheral portion 42 of the wafer 4 becomes the maximum temperature c by the light emission of the upper lamp portion 22 and the light emission of the first and second side lamp portions 24 and 26 after Δt1 msec from the upper lamp portion 22. A convex curve 108 having a vertex is obtained.

  For example, the maximum temperatures b and c are preferably 1200 to 1300 ° C, and more preferably 1220 to 1270 ° C. Furthermore, the absolute value of the difference between the maximum temperatures b and c is preferably, for example, 0 to 50 ° C, and more preferably 0 to 25 ° C.

  The maximum temperature b of the central wafer surface temperature is based on a curve 104 that is a temperature profile of the upper lamp portion 22 in the central portion 40 and a curve 106 that is a temperature profile of the first and second side lamp portions 24 and 26. Is set. The maximum temperature c of the outer peripheral wafer surface temperature is based on the curve 110 that is the temperature profile of the upper ramp portion 22 in the outer peripheral portion 42 and the curve 112 that is the temperature profile of the first and second side ramp portions 24 and 26. Is set.

  Next, a case where the annealing process is performed by delaying the light emission timing of the upper lamp unit 22 by Δt 2 m seconds from the first and second side lamp units 24 and 26 will be described.

  FIG. 4A is a graph of lamp intensity and time when the lamp intensity of the upper lamp unit and the first and second side lamp units according to the first embodiment of the present invention are the same, (b ) Is a graph of the central wafer surface temperature and time, and (c) is a graph of the outer peripheral wafer surface temperature and time. In FIG. 4A, the horizontal axis represents time, the vertical axis represents lamp intensity, and (b) and (c) represent the wafer surface temperature with the horizontal axis representing time (msec) and the vertical axis representing room temperature as the origin. is there.

  First, the control unit 8 of the annealing apparatus 1 heats the wafer 4 to about 500 ° C. via the hot plate 3.

  Next, based on the process data 80 and the timing data 81, the control unit 8 causes the first and second side lamp units 24 and 26 to pass through the lamp control unit 5 and the first power supply unit 6 for tm seconds, for example. Then, the lamp is driven with the lamp intensity aJ, and after Δt 2 msec, the upper lamp section 22 is driven with the lamp intensity aJ for tm sec, and the annealing process of the wafer 4 is finished.

  The lamp intensity of the flash lamp 20 constituting the first and second side lamp portions 24 and 26 is, for example, a curve 116 as shown in FIG. 4A, and the flash lamp 20 constituting the upper lamp portion 22. The lamp intensity becomes a curve 118, for example.

  The central wafer surface temperature that is changed by the light emission of the first and second side lamp portions 24 and 26 becomes, for example, a curve 120 as shown in FIG. Further, the central wafer surface temperature that changes due to the light emission of the upper lamp portion 22 is, for example, a curve 122 as shown in FIG.

  Further, the light emission of the first and second side lamp parts 24 and 26 and the light emission of the upper lamp part 22 after Δt 2 msec from the first and second side lamp parts 24 and 26 cause the center of the wafer 4 to be centered. The surface temperature in the portion 40 is a convex curve 124 having the maximum temperature d as a vertex.

  Further, the outer peripheral wafer surface temperature that changes due to the light emission of the first and second side lamp portions 24 and 26 becomes, for example, a curve 126 as shown in FIG. The outer peripheral wafer surface temperature that changes due to the light emission of the upper lamp portion 22 is, for example, a curve 128 as shown in FIG.

  The outer peripheral portion 42 of the wafer 4 is emitted by the light emission of the first and second side lamp portions 24, 26 and the light emission of the upper lamp portion 22 after Δt 2 msec from the first and second side lamp portions 24, 26. The surface temperature at is a convex curve 130 having the maximum temperature e as a vertex.

  The maximum temperatures d and e are preferably in the same temperature range as the maximum temperatures b and c.

  The maximum temperature d of the central wafer surface temperature is a curve 120 which is a temperature profile of the first and second side lamp portions 24 and 26 in the central portion 40 and a curve 122 which is a temperature profile of the upper lamp portion 22. Is set based on The maximum temperature e of the outer peripheral wafer surface temperature is based on a curve 126 that is the temperature profile of the first and second side lamp portions 24 and 26 in the outer peripheral portion 42 and a curve 128 that is the temperature profile of the upper lamp portion 22. Is set.

  Next, the case where the annealing process is performed by changing the light emission timing and the lamp intensity will be described. The light emission timing is slower in the first and second side lamp parts 24 and 26 than in the upper lamp part 22, and the lamp intensity is higher in the upper lamp part 22 than in the first and second side lamps. It is stronger than the parts 24 and 26.

  FIG. 5A is a graph of lamp intensity and time when the lamp intensity of the upper lamp unit according to the first embodiment of the present invention is different from that of the first and second side lamp units. ) Is a graph of the central wafer surface temperature and time, and (c) is a graph of the outer peripheral wafer surface temperature and time. 5A, the horizontal axis represents time, the vertical axis represents lamp intensity, and (b) and (c) represent the wafer surface temperature with the horizontal axis representing time (msec) and the vertical axis representing room temperature as the origin. is there.

  First, the control unit 8 of the annealing apparatus 1 heats the wafer 4 to about 500 ° C. via the hot plate 3.

  Next, the control unit 8 drives the upper lamp unit 22 with the lamp intensity aJ for tm seconds, for example, via the lamp control unit 5 and the first power supply unit 6 based on the process data 80 and the timing data 81, and Δt3m After a second, the first and second side lamp portions 24 and 26 are driven with a lamp intensity fJ for tm seconds, and the annealing process of the wafer 4 is finished. In this annealing process, the lamp intensity is set stronger in the upper lamp part 22 than in the first and second side lamp parts 24 and 26.

  The lamp intensity of the flash lamp 20 constituting the upper lamp portion 22 is, for example, as shown in FIG. 5A, a curve 132, and the flash lamp 20 constituting the first and second side lamp portions 24 and 26. The lamp intensity becomes a curve 134, for example.

  The central wafer surface temperature that changes due to the light emitted from the upper lamp portion 22 is, for example, a curve 136 as shown in FIG. Further, the central wafer surface temperature that changes due to the light emission of the first and second side lamp portions 24 and 26 becomes, for example, a curve 138 as shown in FIG.

  The surface temperature at the central portion 40 of the wafer 4 is set to the maximum temperature g by the light emission of the upper lamp portion 22 and the light emission of the first and second side lamp portions 24 and 26 after Δt 3 msec from the upper lamp portion 22. A convex curve 140 having a vertex is obtained.

  Further, the outer peripheral wafer surface temperature that changes due to the light emission of the upper lamp portion 22 is, for example, a curve 142 as shown in FIG. Further, the outer peripheral wafer surface temperature that changes due to the light emission of the first and second side lamp portions 24 and 26 becomes, for example, a curve 144 as shown in FIG.

  The surface temperature at the outer peripheral portion 42 of the wafer 4 becomes the maximum temperature h by the light emission of the upper lamp portion 22 and the light emission of the first and second side lamp portions 24 and 26 after Δt 3 msec from the upper lamp portion 22. A convex curve 146 having a vertex is obtained.

  The maximum temperatures g and h are preferably in the same temperature range as the maximum temperatures b and c.

  The maximum temperature g of the central wafer surface temperature is a curve 136 that is the temperature profile of the upper lamp portion 22 in the central portion 40 and a curve 138 that is the temperature profile of the first and second side lamp portions 24 and 26. Is set based on The maximum temperature h of the outer peripheral wafer surface temperature is based on a curve 142 that is a temperature profile of the upper lamp portion 22 in the outer peripheral portion 42 and a curve 144 that is a temperature profile of the first and second side lamp portions 24 and 26. Is set.

  Subsequently, the case where the lamp intensity is the same as described above and the light emission timing is slower in the upper lamp unit 22 than in the first and second side lamp units 24 and 26 will be described.

  FIG. 6A is a graph of lamp intensity and time when the lamp intensity of the upper lamp unit according to the first embodiment of the present invention is different from that of the first and second side lamp units. ) Is a graph of the central wafer surface temperature and time, and (c) is a graph of the outer peripheral wafer surface temperature and time. 6A, the horizontal axis represents time, the vertical axis represents lamp intensity, and (b) and (c) represent the wafer surface temperature with the horizontal axis representing time (msec) and the vertical axis representing room temperature as the origin. is there.

  First, the control unit 8 of the annealing apparatus 1 heats the wafer 4 to about 500 ° C. via the hot plate 3.

  Next, based on the process data 80 and the timing data 81, the control unit 8 causes the first and second side lamp units 24 and 26 to pass through the lamp control unit 5 and the first power supply unit 6 for tm seconds, for example. Then, the lamp is driven with the lamp intensity fJ, and after Δt 4 msec, the upper lamp section 22 is driven with the lamp intensity aJ for tm sec, and the annealing process of the wafer 4 is finished.

  The lamp intensity of the flash lamp 20 constituting the first and second side lamp portions 24 and 26 is, for example, a curve 148 as shown in FIG. 6A, and the flash lamp 20 constituting the upper lamp portion 22. The lamp intensity becomes a curve 150, for example.

  The central wafer surface temperature that changes due to the light emission of the first and second side lamp portions 24 and 26 becomes, for example, a curve 152 as shown in FIG. Further, the central wafer surface temperature that changes due to the light emission of the upper lamp portion 22 is, for example, a curve 154 as shown in FIG.

  Further, the light emission of the first and second side lamp parts 24 and 26 and the light emission of the upper lamp part 22 after Δt 4 msec from the first and second side lamp parts 24 and 26 cause the center of the wafer 4 to be centered. The surface temperature in the portion 40 is a convex curve 156 having the maximum temperature i as a vertex.

  Further, the outer peripheral wafer surface temperature that changes due to the light emission of the first and second side lamp portions 24 and 26 becomes, for example, a curve 158 as shown in FIG. The outer peripheral wafer surface temperature that changes due to light emission from the upper lamp portion 22 is, for example, a curve 160 as shown in FIG.

  The outer peripheral portion 42 of the wafer 4 is emitted by the light emission of the first and second side lamp portions 24 and 26 and the light emission of the upper lamp portion 22 after Δt 4 msec from the first and second side lamp portions 24 and 26. The surface temperature at is a convex curve 162 having the maximum temperature j as a vertex.

  The maximum temperatures i and j are preferably in the same temperature range as the maximum temperatures b and c.

  The maximum temperature i is set based on a curve 152 that is a temperature profile of the first and second side lamp portions 24 and 26 in the central portion 40 and a curve 154 that is a temperature profile of the upper lamp portion 22. . The maximum temperature j of the outer peripheral wafer surface temperature is based on a curve 158 that is the temperature profile of the first and second side lamp portions 24 and 26 in the central portion 40 and a curve 160 that is the temperature profile of the upper lamp portion 22. Is set.

  Next, the range of the light emission timing will be described.

  FIG. 7A is a graph of lamp intensity and time when the light emission timing is Δt5 according to the first embodiment of the present invention, and FIG. 7B is the outer peripheral wafer surface when the light emission timing is Δt5. It is a graph of temperature and time. FIGS. 7A and 7B show a case where the first and second lamp portions 24 and 26 emit light after the upper lamp portion 22.

  As shown in FIG. 7A, the upper lamp unit 22 and the first and second side lamp units 24 and 26 are driven at a light emission timing at which the lamp intensity curve 164 and the curve 166 do not intersect. Since the light emission timings are separated, there is no overlapping portion between the peripheral wafer temperature curve 168 based on the lamp intensity curve 164 and the peripheral wafer temperature curve 170 based on the lamp intensity curve 166.

  At this time, the temperature profile of the outer peripheral portion 42 is, for example, a curve 172 having two convex shapes. When the annealing process is performed so that the apexes of the two convex portions have the target surface temperature, the thermal stress at the central portion 40 and the outer peripheral portion 42 becomes remarkable, and the wafer 4 remains damaged. Therefore, the light emission of the upper lamp portion 22 and the light emission of the first and second side lamp portions 24 and 26 are the lamp intensity curve due to the light emission of the upper lamp portion 22, the first and second side lamp portions 24, It is preferable that the curve of the lamp intensity by the 26 light emission is performed at least at the overlapping light emission timing.

(Effects of the first embodiment)
According to the first embodiment of the present invention, the following effects can be obtained.
(1) Since the upper lamp part 22 and the first and second side lamp parts 24, 26 have different light emission timings, the upper lamp part 22, the first and second side lamp parts 24, The temperature distribution of the wafer 4 can be easily set to a desired temperature distribution as compared with the case where the light is emitted simultaneously.
(2) Since the upper lamp portion 22 and the first and second side lamp portions 24 and 26 have different light emission timings, the upper lamp portion 22, the first and second side lamp portions 24, The first power supply unit 6 having a smaller maximum output can be used as compared with the case where the light is emitted at the same time, and the manufacturing cost of the annealing apparatus 1 can be suppressed.
(3) In addition to the light emission timing, by providing a difference in lamp intensity between the upper lamp part 22 and the first and second side lamp parts 24 and 26, the upper lamp part 22 and the first and second side lamps The temperature distribution of the wafer 4 can be easily set to a desired temperature distribution as compared with the case where there is no difference between the light emission timing of the portions 24 and 26 and the lamp intensity.
(4) Since the number and arrangement of the flash lamps 20 are not changed, it is possible to use an existing annealing device, improve the performance of the semiconductor device manufactured by the existing annealing device, and reduce the manufacturing cost of the semiconductor device. Can be suppressed.

[Second Embodiment]
The second embodiment is the first embodiment in that it includes third and fourth side lamp portions 28 and 30 in addition to the upper lamp portion 22 and the first and second side lamp portions 24 and 26. The form is different. In the following, portions having the same functions and configurations as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

(Configuration of annealing equipment)
FIG. 8A is a schematic diagram of an annealing apparatus according to the second embodiment of the present invention, and FIG. 8B is a side view of the annealing apparatus.

  As shown in FIG. 8A, the annealing apparatus 1 of the present embodiment includes a lamp unit 2 having an upper lamp unit 22 and first to fourth side lamp units 24, 26, 28, 30.

  The third side lamp unit 28 includes, for example, at least one flash lamp 20, and as shown in FIGS. 8A and 8B, the upper lamp unit 22, the first and second side lamp units. 24 and 26 are provided below one end of the flash lamp 20 in the longitudinal direction.

  The fourth side lamp unit 30 includes, for example, at least one flash lamp 20, and as shown in FIGS. 8A and 8B, the upper lamp unit 22, the first and second side lamps. It is provided below the other end of the flash lamp 20 constituting the portions 24 and 26 in the longitudinal direction. The third side lamp portion 28 is provided to face the fourth side lamp portion 30.

  As shown in FIG. 8A, the third and fourth side lamp portions 28 and 30 are mainly end portions of the upper lamp portion 22 and the first and second side lamp portions 24 and 26. It is installed to increase the surface temperature of the regions 400 and 401 of the wafer 4 corresponding to the lower side.

  Since the regions 400 and 401 are located below the end portions of the upper lamp portion 22 and the first and second side lamp portions 24 and 26, in the arrangement of the flash lamp 20 in the first embodiment, This is a region where the surface temperature may not rise sufficiently.

(Operation of Second Embodiment)
First, the control unit 8 of the annealing apparatus 1 controls the second power supply unit 7 after the wafer 4 is placed on the hot plate 3 based on the process data 80, and moves the wafer 4 through the hot plate 3. Heat to 500 ° C.

  In the operation of delaying the driving of the first and second side lamp units 24 and 26 and the third and fourth side lamp units 28 and 30, first, the control unit 8 includes the process data 80 and the timing data 81. Based on the above, the upper lamp unit 22 is driven via the lamp control unit 5 and the first power supply unit 6. Subsequently, the first and second side lamp portions 24 and 26 and the third and fourth side lamp portions 28 and 30 are driven, and the annealing process of the wafer 4 is finished.

  The operation in the case of delaying the driving of the upper lamp unit 22 is as follows. First, the control unit 8 performs the first and second operations via the lamp control unit 5 and the first power supply unit 6 based on the process data 80 and the timing data 81. The side lamp parts 24 and 26 and the third and fourth side lamp parts 28 and 30 are driven. Subsequently, the control unit 8 drives the upper lamp unit 22 and ends the annealing process of the wafer 4.

  Here, the first to fourth side lamp parts 24, 26, 28, 30 may have a lamp intensity different from that of the upper lamp part 22.

(Effect of the second embodiment)
According to the second embodiment of the present invention, the third and fourth side lamp portions 28 and 30 are provided in addition to the upper lamp portion 22 and the first and second side lamp portions 24 and 26. Compared with the case where the third and fourth side lamp portions 28 and 30 are not provided, the flash lamp 20 constituting the upper lamp portion 22 and the first and second side lamp portions 24 and 26 in the short direction. The surface temperature of the regions 400 and 401 of the wafer 4 corresponding to the end can be set to a desired surface temperature, and the temperature distribution of the wafer 4 can be set to a desired temperature distribution.

[Third Embodiment]
The third embodiment is different from the above-described embodiments in that the first and second side lamps 24 and 26 are provided below the end of the upper lamp section 22.

  FIG. 9A is a schematic view of an annealing apparatus according to the third embodiment of the present invention, and FIG. 9B is a side view of the annealing apparatus.

  As shown in FIGS. 9A and 9B, the annealing apparatus 1 according to the present embodiment is provided below the upper lamp portion 22 and one end portion in the short direction of the flash lamp 20 constituting the upper lamp portion 22. The lamp unit 2 includes a first side lamp unit 24 provided and a second side lamp unit 26 provided below the other end.

  The annealing apparatus 1 is different in light emission timing or lamp intensity from the upper lamp portion 22 and the first and second side lamp portions 24 and 26.

(Operation of the third embodiment)
First, the control unit 8 of the annealing apparatus 1 controls the second power supply unit 7 after the wafer 4 is placed on the hot plate 3 based on the process data 80, and moves the wafer 4 through the hot plate 3. Heat to 500 ° C.

  In the operation of delaying the driving of the first and second side lamp units 24 and 26, the control unit 8 first determines the lamp control unit 5 and the first power supply unit 6 based on the process data 80 and the timing data 81. The upper lamp part 22 is driven via Subsequently, the first and second side lamp portions 24 and 26 are driven, and the annealing process of the wafer 4 is finished.

  The operation in the case of delaying the driving of the upper lamp unit 22 is as follows. First, the control unit 8 performs the first and second operations via the lamp control unit 5 and the first power supply unit 6 based on the process data 80 and the timing data 81. The side lamp parts 24 and 26 are driven. Subsequently, the control unit 8 drives the upper lamp unit 22 and ends the annealing process of the wafer 4.

  Here, the first and second side lamp portions 24 and 26 may have a lamp intensity different from that of the upper lamp portion 22.

(Effect of the third embodiment)
According to the third embodiment of the present invention, since the first and second side lamp portions 24 and 26 are provided on the lower side of the upper lamp portion 22, Compared to the case where the first and second side lamp portions 24 and 26 are not provided, the surface temperature of the outer peripheral portion 42 of the wafer 4 is easily set to a desired surface temperature, and the temperature distribution of the wafer 4 is set to a desired temperature distribution. be able to.

[Fourth Embodiment]
The fourth embodiment differs from the above-described embodiments in that the first to fourth side lamps 24, 26, 28, 30 are provided on the lower side of each side surface of the upper lamp section 22. ing.

  FIG. 10 is a schematic view of an annealing apparatus according to the fourth embodiment of the present invention, and FIG. 11A is a side view of the annealing apparatus according to the fourth embodiment of the present invention. b) is a top view of the annealing apparatus.

  The annealing apparatus 1 according to the present embodiment includes an upper lamp part 22 and first to fourth side lamp parts 24, 26, 28, 30 arranged below each side surface of the upper lamp part 22. The lamp portion 2 is provided.

  As shown in FIGS. 10, 11 (a) and 11 (b), each of the first to fourth side lamp portions 24, 26, 28, 30 is composed of at least one flash lamp 20, for example. The Further, the first side lamp portion 24 faces the second side lamp portion 26, and the third side lamp portion 28 faces the fourth side lamp portion 30.

  In the annealing apparatus 1, for example, the light emission timing of the upper lamp portion 22 and the first to fourth side lamp portions 24, 26, 28, and 30, or the light emission timing and lamp intensity are different.

  As shown in FIG. 11B, the first to fourth side lamp portions 24, 26, 28, 30 are centered on the wafer 4 when viewed from the direction perpendicular to the surface of the wafer 4. And is arranged in a square shape so that the entire wafer 4 is included. Since the first to fourth side lamp portions 24, 26, 28, 30 are arranged so as to surround the wafer 4, for example, without generating the regions 400, 401 shown in FIG. Annealing treatment can be performed.

  Further, since the first to fourth side lamp portions 24, 26, 28, 30 are arranged so as to surround the wafer 4, unevenness in the surface temperature of the outer peripheral portion 42 is less likely to occur, and the surface temperature of the outer peripheral portion 42 is reduced. Therefore, the light emission timing may be the same as that of the upper lamp unit 22, the light emission timing may be the same, and the lamp intensity may be different.

  12A to 12C are schematic diagrams relating to the arrangement of the upper lamp part and the side lamp part according to the fourth embodiment of the present invention. Below, the 1st-4th side lamp part 24, 26, 28, 30 is made into the side lamp part 2A on behalf, and arrangement | positioning with respect to the upper lamp part 22 is demonstrated.

  As shown in FIG. 12 (a), the horizontal distance W between the flash lamp 20 at the end of the upper lamp portion 22 and the uppermost flash lamp 20 of the side lamp portion 2A is increased, for example, The temperature rise width of the outer peripheral portion 42 due to the light emission of the side lamp portion 2A becomes smaller, and as the distance W becomes smaller, the temperature rise width of the outer peripheral portion 42 due to the light emission of the side lamp portion 2A becomes larger.

  As shown in FIG. 12B, the angle θ of the side lamp portion 2A with respect to the vertical direction is, for example, the outer peripheral portion 42 of the outer peripheral portion 42 due to light emission of the side lamp portion 2A as the angle θ increases. As the temperature rise width becomes smaller and the angle θ approaches 0 °, the temperature rise width of the outer peripheral portion 42 due to light emission of the side lamp portion 2A becomes larger. Here, when the side lamp portion 2A is disposed at an angle θ immediately below the upper lamp portion 22, light emission of the flash lamp 20 located at the end of the upper lamp portion 22 is blocked by the side lamp portion 2A. Therefore, the surface temperature of the outer peripheral portion 42 is hardly increased, which is not preferable.

  As shown in FIG. 12C, the vertical distance H between the flash lamp 20 at the end of the upper lamp portion 22 and the uppermost flash lamp 20 of the side lamp portion 2A is increased, for example. As the distance H decreases as the temperature increase width of the outer peripheral portion 42 due to light emission from the side lamp portion 2A increases, the temperature increase width of the outer peripheral portion 42 due to light emission from the side lamp portion 2A decreases.

  In each of the above embodiments, in addition to the light emission timing and the lamp intensity, by changing the distances W and H and the angle θ of the first to fourth side lamp portions 24, 26, 28, and 30, for example, The surface temperature of the outer peripheral portion 42 of the wafer 4 is adjusted.

(Operation of the fourth embodiment)
First, the control unit 8 of the annealing apparatus 1 controls the second power supply unit 7 after the wafer 4 is placed on the hot plate 3 based on the process data 80, and moves the wafer 4 through the hot plate 3. Heat to 500 ° C.

  In the operation of delaying the driving of the first and second side lamp units 24 and 26 and the third and fourth side lamp units 28 and 30, first, the control unit 8 includes the process data 80 and the timing data 81. Based on the above, the upper lamp unit 22 is driven via the lamp control unit 5 and the first power supply unit 6. Subsequently, the first and second side lamp portions 24 and 26 and the third and fourth side lamp portions 28 and 30 are driven, and the annealing process of the wafer 4 is finished.

  The operation in the case of delaying the driving of the upper lamp unit 22 is as follows. First, the control unit 8 performs the first and second operations via the lamp control unit 5 and the first power supply unit 6 based on the process data 80 and the timing data 81. The side lamp parts 24 and 26 and the third and fourth side lamp parts 28 and 30 are driven. Subsequently, the control unit 8 drives the upper lamp unit 22 and ends the annealing process of the wafer 4.

  Here, the first to fourth side lamp parts 24, 26, 28, 30 may have a lamp intensity different from that of the upper lamp part 22.

(Effect of the fourth embodiment)
According to the fourth embodiment of the present invention, the following effects can be obtained.
(1) Since the first to fourth side lamp portions 24, 26, 28, and 30 are arranged below the respective side surfaces of the upper lamp portion 22, the temperature of the wafer 4 is compared with the case where this configuration is not adopted. The distribution can be a desired temperature distribution.
(2) Since the temperature distribution of the wafer 4 can be set to a desired temperature distribution, the activation of impurities by the annealing process is performed in the central portion 40 of the wafer 4 as compared with the case where the desired temperature distribution of the wafer 4 cannot be obtained. And the outer peripheral portion 42 are performed without deviation, so that the performance of the semiconductor device can be improved and the yield of the semiconductor device can be improved.
(3) Since the distances W, H, and the angle θ between the upper lamp portion 22 and the first to fourth side lamp portions 24, 26, 28, 30 can be changed, the distances W, H, and the angle θ can be set. Compared to the case where it cannot be changed, the temperature distribution of the wafer 4 can be a desired temperature distribution.
(4) Since the upper lamp portion 22 and the first to fourth side lamp portions 24, 26, 28, 30 can simultaneously emit light, the lamp can be compared with a case where the light emission timing is different. Control of part 2 becomes easy.

(Modification)
FIG. 13 is a schematic view showing a modification of the annealing apparatus of the present invention. The first to sixth side lamp portions 24, 26, 28, 30, 32, and 34 in this modification are arranged side by side along the sides in the six directions.

  The first to sixth side lamp portions 24, 26, 28, 30, 32, 34 are located below the upper lamp portion 22. By providing this configuration, the surface temperature of the outer peripheral portion 42 of the wafer 4 can be easily set to a desired surface temperature as compared with the case where the number of side lamp portions is small, and the temperature distribution of the wafer 4 is desired. Temperature distribution. In addition, since the flash lamps 20 are arranged along each side of a symmetrical figure having at least three sides, a temperature distribution with no bias can be obtained as compared with the case where the flash lamps 20 are not arranged symmetrically. The arrangement is not limited to a hexagon and may be another polygon.

  The present invention is not limited to the above-described embodiments, and various modifications and combinations can be made without departing from or changing the technical idea of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Annealing apparatus, 4 ... Wafer, 8 ... Control part, 20 ... Flash lamp, 22 ... Upper lamp part, 24 ... 1st side lamp part, 26 ... 2nd side lamp part, 28 ... 3rd Side lamp section, 30 ... fourth side lamp section, 201 ... first area, 202 ... second area

Claims (6)

A first flash lamp unit disposed in a first region corresponding to the semiconductor substrate above the semiconductor substrate;
A second flash lamp unit disposed in a second region located around the first region;
A control unit that controls the first flash lamp unit and the second flash lamp unit to emit light at different timings;
Annealing equipment equipped with.   The annealing apparatus according to claim 1, wherein the second flash lamp unit is disposed at a position closer to the semiconductor substrate than the first flash lamp unit.   3. The annealing apparatus according to claim 2, wherein the second flash lamp units are arranged side by side in the vertical direction so that the longitudinal directions of the plurality of bar-shaped flash lamps are adjacent to each other.   The annealing apparatus according to claim 3, wherein the control unit controls the first flash lamp unit and the second flash lamp unit to emit light with different emission intensities.   The annealing apparatus according to any one of claims 1 to 4, wherein the second flash lamp unit is disposed along each side in at least three directions.   A first flash lamp unit disposed in a first region corresponding to the semiconductor substrate above the semiconductor substrate, and a second flash lamp unit disposed in a second region located around the first region Annealing method that emits light at different timings.

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