JP2011060896A - Method for manufacturing nonvolatile memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a nonvolatile memory device suppressing generation of pattern collapse or pattern short-circuit between adjacent memory cells in a lower part of the memory cells when a laminated film containing a resistance change layer and a rectifying layer is processed to form a columnar memory cell. <P>SOLUTION: The method for manufacturing a nonvolatile memory device comprises the steps of: forming a laminate containing a rectifying layer 21 and a resistance change layer 22 and an insulating film 24 on a first interlayer dielectric 10 in which a first wiring 11 is formed; forming a resist pattern where a pattern with a memory cell-forming position opened is two-dimensionally disposed on a position where the first wiring 11 is formed; etching the insulating film 24 using the resist pattern to form an opening; embedding a conductive material film in the opening to form a mask film 23; etching the insulating film 24, the rectifying layer 21 and the resistance change layer 22 by dry etching using the mask film 23 as a mask to form memory cells; and embedding a second interlayer dielectric between the memory cells and forming a second wiring such that the second wiring is in contact with the upper surface of each memory cell. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile memory device.

  In recent years, attention has been paid to ReRAM (Resistive Random Access Memory) that stores resistance value information of an electrically rewritable variable resistance element, for example, a high resistance state and a low resistance state in a nonvolatile manner as a nonvolatile memory device. Such a ReRAM includes, for example, a plurality of bits in which a resistance change memory cell in which a resistance change element as a memory element and a rectifier element such as a diode are connected in series are extended in parallel in a first direction. An array is formed at the intersection of a line and a plurality of word lines extending in parallel in a second direction perpendicular to the first direction (see, for example, Non-Patent Document 1). Examples of the resistance change element include a metal oxide such as NiO that can be switched between a high resistance state and a low resistance state by controlling the voltage value and the application time.

Such a ReRAM is an intersection of a plurality of first wirings extending in parallel in a first direction and a second wiring extending in parallel in a second direction perpendicular to the first direction. It can be formed in the same manner as a conventional Field-Programmable ROM having a columnar structure in which a rectifying layer and an insulating layer serving as an antifuse are connected in series (for example, see Non-Patent Document 2). In Non-Patent Document 2, a silicon film is deposited on an insulating film on which a first wiring is formed, and a rectifying layer having a PIN junction is formed. Next, the resist applied on the rectifying layer is exposed to light and developed by photolithography to form a desired pattern, and then a mask is formed. Then, a reactive ion etching (hereinafter referred to as RIE) method is used. The rectifying layer is etched into a perfect circular column by isotropic etching. At this time, the rectifying layer is etched so as to be positioned on the first wiring. Next, after an interlayer insulating film is formed so as to fill the columnar rectifying layer, an insulating layer made of a SiO ₂ film of several nm is formed on the rectifying layer. Thereafter, the second wiring is formed on the stacked structure of the columnar rectifying layer and the insulating layer, and the field-programmable ROM is formed.

  ReRAM can also be manufactured in the same manner as the manufacturing method of Non-Patent Document 2. That is, a resistance change layer to be a resistance change element, a rectification layer to be a rectification element, a cap film made of a conductive material, and a TEOS (Tetraethyl orthosilicate) to be a mask layer for later processing into a perfect circular columnar memory cell ) After the film is laminated on the insulating film on which the first wiring is formed, a resist pattern in which a dot pattern is formed at the memory cell formation position is formed. Next, the resist pattern is transferred to the mask layer, and the resistance change layer, the rectifying layer, and the cap film are processed into a perfect circular columnar memory cell using the mask layer. Then, the ReRAM can be manufactured by filling the space between the memory cells with an interlayer insulating film and forming the second wiring above the memory cell.

  However, the formation of a minute dot pattern in the lithography process is more likely to cause a shape abnormality such as a resist collapse or a short circuit, and the process margin is smaller than the formation of a pattern such as line and space. Also, in the etching in the RIE process after the formation of the resist pattern, it is necessary to process a laminated film having a considerably high aspect ratio in consideration of the necessary mask layer thickness. Therefore, there has been a problem that pattern collapse and pattern short-circuit between adjacent memory cells below the memory cell are likely to occur.

Myoung-Jae Lee; Youngsoo Park; Bo-Soo Kang; Seung-Eon Ahn; Changbum Lee; Kihwan Kim; Wenxu Xianyu; Stefanovich, G .; Jung-Hyun Lee; Seok-Jae Chung; Yeon-Hee Kim; Chang-Soo Lee; Jong-Bong Park; In-Kyeong Yoo, "2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications," IEEE, pp.771-774, 2007 SB Herner, A. Bandyopadhyay, SV Dunton, V. Eckert, J. Gu, KJ Hsia, S. Hu, C. Jahn, D. Kidwell, M. Konevecki, M. Mahajani, K. Park, C. Petti, SR Radigan, U. Raghuram, J. Vienna, MA Vyvoda, "Vertical pin polysilicon diode with antifuse for stackable field-programmable ROM", Electron Device Letters, IEEE, vol.25, no.5, pp. 271-273, May 2004

  In the present invention, when a columnar memory cell is processed using a mask patterned into a predetermined shape from a laminated film including a nonvolatile memory layer such as a resistance change layer and a rectifying layer, the pattern collapses and the lower part of the memory cell. An object of the present invention is to provide a method for manufacturing a nonvolatile memory device that can suppress the occurrence of pattern shorts between adjacent memory cells.

  According to one embodiment of the present invention, a stacked body including a rectifying layer and a nonvolatile memory layer over a first interlayer insulating film in which a first wiring extending in a first direction is formed, an insulating film, And forming a mask pattern in which a pattern in which a memory cell formation position is opened is two-dimensionally arranged on the formation position of the first wiring. A mask pattern forming step, an opening forming step for etching the insulating film to form an opening using the mask pattern, and a mask film forming for forming a mask film by embedding a conductive material film in the opening A memory cell forming step of etching the insulating film, the rectifying layer, and the nonvolatile memory layer by a dry etching method using the mask film as a mask to form a memory cell; and the memory cell And a second wiring forming step of forming a second wiring extending in a second direction so as to be embedded in the second interlayer insulating film and to be in contact with the upper surface of the memory cell. A non-volatile memory device manufacturing method is provided.

  According to the present invention, when a columnar memory cell is processed using a mask that is patterned into a predetermined shape from a laminated film including a nonvolatile memory layer such as a resistance change layer and a rectifying layer, pattern collapse or memory cell may occur. There is an effect that it is possible to suppress the occurrence of pattern shorts between adjacent memory cells in the lower part.

FIG. 1 is a diagram showing an example of a memory cell array configuration of a nonvolatile memory device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing an example of the structure of the memory cell. FIGS. 3-1 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by 1st Embodiment (the 1). FIGS. 3-2 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by 1st Embodiment (the 2). FIG. 3-3 is a sectional view schematically showing an example of a procedure of the method for manufacturing the nonvolatile memory device according to the first embodiment (No. 3). 3-4 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by 1st Embodiment (the 4). 3-5 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by 1st Embodiment (the 5). 3-6 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by 1st Embodiment (the 6). 3-7 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by 1st Embodiment (the 7). 3-8 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by 1st Embodiment (the 8). FIG. 4 is a top view of the nonvolatile memory device having a resist pattern formed thereon. FIG. 5 is a cross-sectional view schematically showing an example of the procedure of the method for manufacturing the nonvolatile memory device according to the second embodiment.

  A method for manufacturing a nonvolatile memory device according to an embodiment of the present invention will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. In addition, the cross-sectional views of the nonvolatile memory device used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones. Furthermore, the film thickness shown below is an example and is not limited thereto.

(First embodiment)
FIG. 1 is a diagram showing an example of a memory cell array configuration of a nonvolatile memory device according to an embodiment of the present invention. In this figure, the left-right direction of the paper surface is the X direction, and the direction perpendicular to the X direction in the paper surface is the Y direction. A plurality of word lines WL extending in parallel in the X direction (row direction) and a plurality of bit lines BL extending in parallel in the Y direction (column direction) to a height different from the word line WL, A resistance change type memory cell (hereinafter also simply referred to as a memory cell) MC in which a resistance change element VR and a rectifier element D are connected in series is arranged at each of these intersections. In this example, one end of the resistance change element VR is connected to the bit line BL, and the other end is connected to the word line WL via the rectifying element D.

  FIG. 2 is a cross-sectional view schematically showing an example of the structure of the memory cell. This figure shows a state of a part of a cross section on a certain word line WL along the X direction of FIG. 1, for example. In the following description, it is assumed that the bit line BL corresponds to the first wiring 11 and the word line WL corresponds to the second wiring 31. A plurality of first wirings 11 (bit lines BL) extending in the Y direction are formed in parallel at a predetermined interval in the first interlayer insulating film 10, and a second interlayer is formed on the first interlayer insulating film 10. In a third interlayer insulating film (not shown) formed through the insulating film 20, a second wiring 31 (word line WL) extending in the X direction orthogonal to the first wiring 11 is formed. . And in the area | region where each 1st wiring 11 and 2nd wiring 31 in the 2nd interlayer insulation film 20 cross | intersect, the rectification layer 21 which is the rectification element D, and the resistance change layer 22 as the resistance change element VR. And the memory cell MC in which the mask film 23 is sequentially laminated is formed.

  The rectifying layer 21 is made of a material having a rectifying action such as a Schottky diode, a PN junction diode, or a PIN diode, and is formed on the first wiring 11. Here, the rectifying layer 21 has a PIN structure in which a P-type polysilicon film 21P, an I-type polysilicon film 21I, and an N-type polysilicon film 21N are sequentially stacked from the first wiring 11 side, and has a thickness of about 150 nm. The case where it comprises by the silicon layer of this is illustrated.

  The resistance change layer 22 is made of a metal oxide that can be switched between a high resistance state and a low resistance state by controlling the voltage value and the application time. For example, a metal oxide film having a thickness of about 20 nm containing at least one element such as Si, Ti, Ta, Nb, Hf, Zr, W, Al, Ni, Co, Mn, Fe, Cu, and Mo is exemplified. can do.

  A mask film 23 made of a conductive material and having a thickness of about 80 to 100 nm is formed on the resistance change layer 22, and further, a second wiring 31 extending in the X direction is formed thereon. As will be described later, the mask film 23 is used in the process when connecting the memory cell MC and the second wiring 31 and is used when processing the memory cell MC. The mask film 23 and the resistance change layer 22 of each memory cell MC are in ohmic contact.

  Next, a method for manufacturing the nonvolatile memory device having such a structure will be described. 3A to 3E are cross-sectional views schematically showing an example of the procedure of the method for manufacturing the nonvolatile memory device according to the first embodiment. In these drawings, FIG. 2B is a cross-sectional view in a direction along the word line (a direction perpendicular to the X direction), and FIG. 4B is a cross-sectional view in a direction along the word line (a direction perpendicular to the Y direction).

  First, a first interlayer insulating film 10 is formed on a substrate such as a Si substrate (not shown), and a first wiring 11 extending in the Y direction in the upper surface of the first interlayer insulating film 10 is formed by a damascene method or the like. (Fig. 3-1). An element such as a CMOS (Complementary Metal-Oxide Semiconductor) transistor is formed on the substrate under the first interlayer insulating film 10.

  Next, a rectifying layer 21, a resistance change layer 22 made of a resistance change material film, and an insulating film 24 are sequentially formed on the first interlayer insulating film 10 on which the first wiring 11 is formed (FIG. 3). -2).

  As the rectifying layer 21, for example, as shown in FIG. 2, a silicon layer having a PIN structure made of a laminated film of a P-type polysilicon film 21P, an I-type polysilicon film 21I and an N-type polysilicon film 21N is about 150 nm thick. Further, it can be formed by a film forming method such as a CVD (Chemical Vapor Deposition) method. In this case, the P-type polysilicon film 21P is obtained by depositing a silicon film while introducing a P-type impurity such as B (boron), and the I-type polysilicon film 21I is a silicon film in an environment where no impurity is introduced. The N-type polysilicon film 21N is obtained by depositing a silicon film while introducing an N-type impurity such as P (phosphorus).

  Further, as the resistance change layer 22, for example, a metal oxide film containing at least one element such as Si, Ti, Ta, Nb, Hf, Zr, W, Al, Ni, Co, Mn, Fe, Cu, and Mo, or the like. Can be formed by a film forming method such as an ALD (Atomic Layer Deposition) method or a CVD method. Here, NiO having a thickness of 20 nm is used as the resistance change layer 22. Further, as the insulating film 24, for example, a TEOS film or the like can be formed with a thickness of 300 nm by a film forming method such as a plasma CVD method.

  Next, a resist is applied on the insulating film 24, and patterning is performed by a lithography technique so that the formation position of the memory cell MC becomes the opening 52 (FIG. 3-3). FIG. 4 is a top view of the nonvolatile memory device having a resist pattern formed thereon. As shown in this figure, in the resist pattern 51, dot-like (perfectly circular) openings 52 are formed in a matrix on the position where the first wiring 11 is formed. As will be described below, the insulating film 24 is processed with the resist pattern 51, a mask film is formed in the insulating film 24, and etching is performed using this mask film. However, this mask film is used. The etching depth is only the thickness of the rectifying layer 21 and the resistance change layer 22. Therefore, the processing margin at the time of lithography is compared with the processing margin at the time of pattern formation used when etching a laminated film composed of a cap film and a mask layer in addition to the rectifying layer 21 and the resistance change layer 22 as in the prior art. And improve.

  Thereafter, the resist pattern 51 is used as a mask to etch the insulating film 24 using an anisotropic etching method such as RIE, and the pattern formed on the resist pattern 51 is transferred to the insulating film 24 (FIG. 3-4). As a result, a pattern in which the cylindrical openings 24a are two-dimensionally arranged in the insulating film 24 is formed.

  Next, a metal film such as tungsten or copper is buried on the insulating film 24 in which the opening 24a is formed, so that a sufficient selection ratio with the base film can be obtained in the RIE process for forming the memory cell MC later. Further, the surface of the metal film is planarized by a CMP (Chemical Mechanical Polishing) method or the like until the insulating film 24 is exposed (FIG. 3-5). Thereby, the mask film 23 is formed.

  Thereafter, using the mask film 23 as a mask, the insulating film 24, the resistance change layer 22 and the rectifying layer 21 around the mask film 23 are etched by the RIE method to form the memory cell MC (FIGS. 3-6). At this time, etching is performed under the condition that the insulating film 24, the resistance change layer 22, and the rectifying layer 21 are more easily etched than the mask film 23. As a result, the memory cell MC having a columnar structure in which the direction parallel to the substrate surface has a substantially circular shape is formed.

  Next, an interlayer such as an HDP-USG (High Density Plasma-Undoped Silicate Glasses) film formed by, for example, a plasma CVD method so as to fill the space between the rectifying layers 21 processed into columnar shapes and to be higher than the upper surface of the rectifying layer 21. An insulating film is formed. Here, the interlayer insulating film filling the space between the memory cells MC is referred to as a second interlayer insulating film 20, and the interlayer insulating film formed at a position higher than the upper surface of the memory cell MC is referred to as the third interlayer insulating film 30. Shall be called. Then, the upper surface of the third interlayer insulating film 30 is planarized by a method such as a CMP method (FIGS. 3-7).

  Then, using a normal damascene method, a wiring forming groove for forming the second wiring 31 extending in the X direction is formed in the third interlayer insulating film 30, and copper or the like is embedded in the groove. Thus, the second wiring 31 is formed (FIGS. 3-8). Note that etching is performed until the mask film 23 constituting the upper layer of the memory cell MC is exposed at the time of forming the wiring forming groove. That is, the mask film 23 also functions as an etching stopper film. Thus, a nonvolatile memory device can be obtained.

  In the above description, the case where the rectifying layer 21 and the resistance change layer 22 are stacked in this order on the first wiring 11 has been described. However, the resistance change layer 22 and the rectification layer 21 are formed on the first wiring 11. You may make it laminate | stack in this order. Moreover, although the case where the semiconductor layer of PIN junction structure was used as the rectification | straightening layer 21 was shown, the semiconductor layer of PN junction structure may be used and a Schottky junction may be used. In the above description, the case where the planar shape of the memory cell MC has a perfect circle has been described as an example. However, the present invention is not limited to this, and the memory cell MC may have a rectangular shape or an oval shape.

  In the first embodiment, after the stacked body of the rectifying layer 21 and the resistance change layer 22 and the insulating film 24 are stacked on the first wiring 11, the insulating film 24 corresponds to the formation position of the memory cell MC. The opening 24a is provided, and a metal film having a sufficient selection ratio with respect to the laminated film is embedded in the opening 24a to form the mask film 23, and the laminated body is formed into a columnar structure using the mask film 23 as a mask. Processed by etching. Thus, for example, after forming a laminate of a rectifying layer and a resistance change layer, a cap film having a function of connecting the second wiring and the memory cell MC, and an insulating film having a function of a hard mask, a resist is formed. The etching depth can be reduced as compared with the case where these stacked films are etched using a mask. In other words, the cap film and the insulating film are formed in the same layer, and the cap film has a function as a mask layer. Therefore, the aspect ratio during processing is increased by the thickness of the conventional cap film or insulating film. Can be reduced. As a result, pattern collapse during processing of the memory cells MC and occurrence of pattern shorts between adjacent memory cells MC below the memory cells MC can be suppressed, and the process margin can be improved.

(Second Embodiment)
FIG. 5 is a cross-sectional view schematically showing an example of the procedure of the method for manufacturing the nonvolatile memory device according to the second embodiment. In the first embodiment, in FIG. 3-5, using the mask film 23 embedded in the insulating film 24 as a mask as it is, the insulating film 24 formed on the resistance change layer 22, the resistance change layer 22, and the rectification. Although the layer 21 was etched, after FIG. 3-5, as shown in FIG. 5, the insulating film 24 is removed by wet etching to leave only the mask film 23, and this mask film 23 is used as a mask. As shown in FIG. 3-6, the resistance change layer 22 and the rectifying layer 21 may be etched by the RIE method to form the memory cell MC.

  When the insulating film 24 is removed by wet etching, the insulating film 24 is made of a material having a selection ratio with respect to the rectifying layer 21 or the resistance change layer 22 immediately below the insulating film 24 at the time of wet etching. Is desirable. Further, as in the above-described example, when the memory cell MC is laminated in the order of the rectifying layer 21 and the resistance change layer 22, and the insulating film 24 cannot take a selection ratio with the resistance change layer 22. Etching may be performed under the condition that the rectification layer 21 and the resistance change layer 22 are stacked in a different order and the rectification layer 21 has a selection ratio.

  In the second embodiment, after the mask film 23 is formed at a position corresponding to the memory cell MC formation position of the insulating film 24, the insulating film 24 is removed by wet etching, and then the rectifying layer 21 using the mask film 23 as a mask. The resistance change layer 22 is etched by the RIE method to form the memory cell MC. This eliminates the need to remove the insulating film 24 by the RIE method, so that the RIE processing conditions can be simplified as compared with the first embodiment.

  In the above description, the resistance change type memory has been described as an example. However, the present invention is not limited to this, and the nonvolatile memory such as a phase change type memory having a phase change element or a field-programmable ROM using an anti-fuse is used. The present invention can be applied to a device manufacturing method. In addition, the present invention can be applied to a method for manufacturing a nonvolatile memory device in which a plurality of nonvolatile memory cells are stacked.

  DESCRIPTION OF SYMBOLS 10 ... 1st interlayer insulation film, 11 ... 1st wiring, 20 ... 2nd interlayer insulation film, 21 ... Rectification layer, 21P ... P type polysilicon layer, 21I ... I type polysilicon layer, 21N ... N type Polysilicon layer, 22 ... variable resistance layer, 23 ... mask film, 24 ... insulating film, 24a ... opening, 30 ... third interlayer insulating film, 51 ... resist pattern.

Claims (5)

A laminated film forming step of forming a laminated body including a rectifying layer and a nonvolatile memory layer and an insulating film on the first interlayer insulating film in which the first wiring extending in the first direction is formed; ,
A mask pattern forming step of applying a resist on the insulating film and forming a mask pattern in which a pattern in which a memory cell formation position is opened is two-dimensionally arranged on the formation position of the first wiring;
An opening forming step of etching the insulating film to form an opening using the mask pattern;
A mask film forming step of burying a conductive material film in the opening and forming a mask film;
A memory cell forming step of forming a memory cell by etching the insulating film, the rectifying layer, and the nonvolatile memory layer by a dry etching method using the mask film as a mask;
A second wiring formation step of burying a second interlayer insulating film between the memory cells and forming a second wiring extending in a second direction so as to be in contact with the upper surface of the memory cell;
A method for manufacturing a nonvolatile memory device, comprising:   The said mask film | membrane formation process WHEREIN: The said mask film | membrane is comprised by the material which can take a selection ratio between the said insulating film, the said rectification | straightening layer, and the said non-volatile memory layer at the time of dry etching. The manufacturing method of the non-volatile memory device of description.   3. The method for manufacturing a nonvolatile memory device according to claim 1, further comprising an insulating film removing step of removing the insulating film by wet etching after the mask film forming step.   In the stacked film forming step, the insulating film is made of a material having a selection ratio with respect to the rectifying layer or the nonvolatile memory layer immediately below the insulating film during wet etching in the mask film forming step. The method for manufacturing a nonvolatile memory device according to claim 3.   In the laminated film forming step, any one of the rectifying layer and the nonvolatile memory layer that can take a selection ratio with the insulating film during wet etching in the mask film forming step is insulated from the insulating film. The method for manufacturing a nonvolatile memory device according to claim 3, wherein the method is formed immediately below the film.

Images