JP2011029462A - Nonvolatile storage device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile storage device, capable of preventing a memory cell processed into a columnar shape from being twisted and collapsed in the direction perpendicular to the extending direction of an upper layer wiring. <P>SOLUTION: The device includes a first wiring extending in a first direction, a second wiring formed above the first wiring and extending in a second direction, a third wiring formed above the second wiring and extending in the first direction, a first memory cell MC of a columnar structure arranged on a position where the first wiring and the second wiring intersect with each other and containing a resistance change element 13 and a rectifier element 12, and a second memory cell MC of the columnar structure arranged on a position where the second wiring and the third wiring intersect with each other and containing the resistance change element 13 and the rectifier element 12. In the first and second memory cells MC, the size within a plane made in the first and second directions is different from direction to direction. A major axis direction having a longest size is so arranged as to correspond to the extending direction of a lower layer wiring connected to the memory cell MC. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device and a method for manufacturing the same.

  In recent years, attention has been paid to ReRAM (Resistive Random Access Memory) that stores resistance value information of an electrically rewritable variable resistance element, for example, a high resistance state and a low resistance state in a nonvolatile manner as a nonvolatile memory device. Such a ReRAM includes, for example, a plurality of bits in which a resistance change memory cell in which a resistance change element as a memory element and a rectifier element such as a diode are connected in series are extended in parallel in a first direction. An array is formed at the intersection of a line and a plurality of word lines extending in parallel in a second direction perpendicular to the first direction (see, for example, Non-Patent Document 1). Examples of the resistance change element include a metal oxide such as NiO that can be switched between a high resistance state and a low resistance state by controlling the voltage value and the application time.

Such a ReRAM is an intersection of a plurality of first wirings extending in parallel in a first direction and a second wiring extending in parallel in a second direction perpendicular to the first direction. It can be formed in the same manner as a conventional Field-Programmable ROM having a columnar structure in which a diode layer and an insulating layer serving as an antifuse are connected in series (see, for example, Non-Patent Document 2). In Non-Patent Document 2, a silicon film is deposited on an insulating film on which a first wiring is formed, and a diode layer having a PIN junction is formed. Next, the resist applied on the diode layer is exposed and developed by photolithography to form a desired pattern, and then a mask is formed. Then, a reactive ion etching (hereinafter referred to as RIE) method is used. The diode layer is etched into a perfect circular column by isotropic etching. At this time, the diode layer is etched so as to be located on the first wiring. Next, after an interlayer insulating film is formed so as to fill the columnar diode layers, an insulating layer made of a SiO ₂ film having a thickness of several nm is formed above the diode layer. Thereafter, the second wiring is formed on the stacked structure of the columnar diode layer and the insulating layer, and the field-programmable ROM is formed.

  As for the ReRAM, similarly to the manufacturing method of Non-Patent Document 2, a resistance change layer to be a resistance change element and a rectification layer to be a rectification element are stacked on an insulating film on which a first wiring is formed. Thereafter, it can be manufactured by processing into a perfect circular columnar memory cell, filling the space between the memory cells with an interlayer insulating film, and forming a second wiring above the memory cell.

  However, in the above method, since the memory cell has a perfect columnar shape, the memory cell is randomly inserted in all directions in processing steps such as RIE processing, post-processing, and interlayer insulating film formation. There was a problem of falling or falling. If the memory cell falls or falls in a direction orthogonal to the extending direction of the second wiring formed in the upper layer, there is a concern about poor contact between the memory cell and the second wiring. Is done.

Myoung-Jae Lee; Youngsoo Park; Bo-Soo Kang; Seung-Eon Ahn; Changbum Lee; Kihwan Kim; Wenxu Xianyu; Stefanovich, G .; Jung-Hyun Lee; Seok-Jae Chung; Yeon-Hee Kim; Chang-Soo Lee; Jong-Bong Park; In-Kyeong Yoo, "2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications," IEEE, pp.771-774, 2007 SB Herner, A. Bandyopadhyay, SV Dunton, V. Eckert, J. Gu, KJ Hsia, S. Hu, C. Jahn, D. Kidwell, M. Konevecki, M. Mahajani, K. Park, C. Petti, SR Radigan, U. Raghuram, J. Vienna, MA Vyvoda, "Vertical pin polysilicon diode with antifuse for stackable field-programmable ROM", Electron Device Letters, IEEE, vol.25, no.5, pp. 271-273, May 2004

  An object of the present invention is to provide a non-volatile memory device and a method for manufacturing the same that can prevent the memory cell processed in a columnar shape from being twisted or tilted in a direction orthogonal to the extending direction of the upper layer wiring. .

  According to one aspect of the present invention, a first wiring extending in a first direction, a second wiring formed above the first wiring and extending in a second direction, A third wiring formed above the second wiring and extending in the first direction; and the first wiring and the second wiring at a position where the first wiring and the second wiring intersect each other. A first nonvolatile memory cell having a columnar structure including a nonvolatile memory element and a rectifying element, disposed so as to be sandwiched between second wirings; the second wiring; and the third wiring; A second non-volatile memory cell having a columnar structure including a non-volatile memory element and a rectifying element, disposed so as to be sandwiched between the second wiring and the third wiring at a position where The first and second nonvolatile memory cells are sized in a plane formed in the first and second directions. Depends direction, size longest major axis nonvolatile memory device characterized in that it is arranged a direction to correspond to the extending direction of the wiring of the lower layer to be connected to the nonvolatile memory cell is provided.

  According to one embodiment of the present invention, the first rectifying layer and the first nonvolatile memory are formed on the first interlayer insulating film in which the plurality of first wirings extending in the first direction are formed. A first step of forming a first laminated film including a layer, and the first direction is longer on the first laminated film than in a second direction intersecting the first direction. A second step of forming a first mask pattern in which a pattern having a shape to be two-dimensionally arranged on the plurality of first wirings, and using the first mask pattern, A third step of etching the stacked film to form a first memory cell having a columnar structure including a rectifying element and a nonvolatile memory element; and a second interlayer insulating film between the first memory cells having the columnar structure And a fourth step of planarizing until the surface of the first memory cell is exposed, and the first memory cell A fifth step of forming a plurality of second wirings connecting the second wirings in the second direction and a third interlayer insulating film that insulates between the plurality of second wirings; and the plurality of second wirings A sixth step of forming a second laminated film including a second rectifying layer and a second nonvolatile memory layer on the third interlayer insulating film on which the wiring is formed; and the second laminated film A second mask pattern is formed in which a pattern having a shape in which the second direction is longer than the first direction is two-dimensionally arranged on the plurality of second wirings. Etching the second laminated film using the seventh step and the second mask pattern to form a second memory cell having a columnar structure including a rectifying element and a nonvolatile memory element A step of filling a space between the second memory cells having a columnar structure with a fourth interlayer insulating film, and a surface of the second memory cells; A nonvolatile process comprising: a ninth step of flattening until exposed; and a tenth step of forming a plurality of third wirings connecting the second memory cells in the first direction. A method for manufacturing a volatile memory device is provided.

  According to the present invention, there is an effect that it is possible to suppress the twisting and falling in the direction orthogonal to the extending direction of the upper layer wiring of the memory cell processed into the columnar shape.

FIG. 1 is a diagram schematically illustrating a configuration of a nonvolatile memory device according to an embodiment. FIG. 2 is a diagram schematically showing a planar state of the memory cell array of the nonvolatile memory device of FIG. FIGS. 3-1 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 1). 3-2 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 2). FIG. 3-3 is a sectional view schematically showing an example of a procedure of the method for manufacturing the nonvolatile memory device according to this embodiment (No. 3). 3-4 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 4). 3-5 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 5). 3-6 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 6). 3-7 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 7). 3-8 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 8). 3-9 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 9). 3-10 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 10). 3-11 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile memory device by this embodiment (the 11). FIG. 4 is a plan view schematically showing the relationship between the memory cell and the upper layer wiring of this embodiment. FIG. 5 is a plan view schematically showing the relationship between the columnar memory cell and the upper layer wiring.

  Exemplary embodiments of a nonvolatile memory device and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment. In addition, the cross-sectional views of the nonvolatile memory device used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones. Furthermore, the film thickness shown below is an example and is not limited thereto.

  FIG. 1 is a diagram schematically illustrating a configuration of a nonvolatile memory device according to an embodiment, (a) is a perspective view of the nonvolatile memory device, and (b) is an A-A diagram of (a). It is sectional drawing, (c) is BB sectional drawing of (a). FIG. 2 is a diagram schematically showing a planar state of the memory cell array of the nonvolatile memory device of FIG. 1, and FIG. 2A is a plan view of the first and third memory cell arrays. FIG. 2B is a plan view of the second and fourth memory cell arrays. In these drawings, the extending direction of the word lines is the X direction, and the extending direction of the bit lines is the Y direction.

  As shown in FIG. 1, the nonvolatile memory device has a plurality of word lines WL11, WL12,... That extend in parallel in the X direction, and the word lines WL11, WL12,. In addition, a plurality of bit lines BL11, BL12,... Extending in parallel in the Y direction are arranged so as to intersect each other, and a rectifier element 12 and a nonvolatile memory element are provided at each of these intersections. A resistance change type memory cell (hereinafter also simply referred to as a memory cell) MC as an elliptical columnar nonvolatile memory cell connected in series with the resistance change element 13 is disposed. Here, the two-dimensionally arranged resistance-change memory cells MC have a configuration in which a plurality of stacked memory cells MC are stacked in the height direction while sharing the word lines WL or bit lines BL of the memory cells MC adjacent in the height direction. Have. An interlayer insulating film 20 is buried between the word line WL, the bit line BL, and the memory cell MC.

  For example, in FIG. 1, at each intersection position between the word lines WL11, WL12, WL13 extending in the X direction of the lowermost layer and the bit lines BL11, BL12, BL13 extending in the Y direction on the upper layer, As the first memory layer, a memory cell MC in which the rectifying element 12 and the resistance change element 13 are connected in series is arranged. Further, at each intersection position between the bit lines BL11, BL12, and BL13 and the word lines WL21, WL22, and WL23 extending in the X direction on the upper layer, a rectifying element 12 and a resistance change as a second memory layer are provided. A memory cell MC in which the element 13 is connected in series is arranged. Here, the positions of the word lines WL21, WL22, WL23 in the XY plane substantially coincide with the positions of the lower word lines WL11, WL12, WL13 in the XY plane. The bit lines BL11, BL12, and BL13 are shared as bit lines of the first memory layer and the second memory layer.

  Furthermore, at each crossing position between the word lines WL21, WL22, WL23 and the bit lines BL21, BL22, BL23 extending in the Y direction on the upper layer, a rectifying element 12 and a resistance change are provided as a third memory layer. A memory cell MC in which the element 13 is connected in series is arranged. Here, the positions of the bit lines BL21, BL22, BL23 in the XY plane substantially coincide with the positions of the lower bit lines BL11, BL12, BL13 in the XY plane. Further, the word lines WL21, WL22, WL23 are shared as the word lines of the second memory layer and the third memory layer.

  Similarly, a rectifying element 12 and a resistor are provided as a fourth memory layer at each intersection position between the bit lines BL21, BL22, and BL23 and the word lines WL31, WL32, and WL33 extending in the X direction on the upper layer. A memory cell MC in which the change element 13 is connected in series is arranged. Here, the positions of the word lines WL31, WL32, WL33 in the XY plane substantially coincide with the positions of the lower word lines WL21, WL22, WL23 (WL11, WL12, WL13) in the XY plane. Further, the bit lines BL21, BL22, BL23 are shared as bit lines of the third memory layer and the fourth memory layer.

  In this way, the word lines WL extending in the X direction and the bit lines BL extending in the Y direction are alternately stacked in the height direction, and the memory cell MC is formed at the intersection of these wirings. Thus, a non-volatile memory device that is three-dimensionally stacked is formed.

  Next, a detailed configuration of the memory cell will be described. In a region where the bit line BL and the word line WL intersect, the resistance change type memory cell MC in which the barrier metal film 11, the rectifying element 12, the resistance change element 13, and the cap film 14 are sequentially laminated includes the bit line BL and the word line. It is pinched by WL.

  Both the bit line BL and the word line WL are made of, for example, a tungsten film, and a plurality of bit lines BL and word lines WL are provided extending in the Y direction and the X direction, respectively, as described above. The barrier metal film 11 is a layer made of a conductive material provided to improve adhesion between the lower bit line BL or word line WL and the rectifying element 12, and is, for example, a TiN film having a thickness of 5 nm. Consists of.

  The rectifying element 12 is made of a material having a rectifying action and is formed on the barrier metal film 11. Examples of the rectifying element 12 include a silicon layer having a PIN structure. For example, a P-type polysilicon film 12P having a thickness of about 20 nm, an I-type polysilicon film 12I having a thickness of about 110 nm, and a thickness from the bit line BL side. A polysilicon film in which an N-type polysilicon film 12N having a thickness of about 20 nm is sequentially stacked, an N-type polysilicon film 12N having a thickness of about 20 nm, an I-type polysilicon film 12I having a thickness of about 110 nm, and a P-type having a thickness of about 20 nm A polysilicon film in which the polysilicon film 12P is sequentially laminated can be used. In this embodiment, since the bit line BL or the word line WL is shared between vertically adjacent memory cells, the stacking state can be changed according to the direction of current flow. That is, the P-type polysilicon film 12P is disposed on the side of the rectifying element 12 close to the bit line BL.

The resistance change element 13 is made of a resistance change material capable of switching between a high resistance state and a low resistance state by controlling the voltage value and the application time. Examples of the resistance change material include C, NbO _x , Ti-doped NiO _x , Cr-doped SrTiO _3-x , Nb-doped SrTiO _3-x , MnO _x , FeO _x , CoO _x , LaO _x , PrO _x , Pr _x Ca. _y MnO _z, at least _{ZrO x, NiO x, ZnO x} , TiO x, TiO x N y, CuO x, GdO x, CuTe x, HfO x, is selected from the group consisting of ZnMn _x O _y and ZnFe _x O _y One material can be used. Further, the Joule heat generated by a voltage applied to both ends, GST (GeSb _x Te _y) of chalcogenide whose resistance state changes, N-doped GST, O doped GST, GeSb, also be used such as Inge _x Te _y Can do. Here, a NiO film having a thickness of 5 to 20 nm is used as the resistance change element 13.

  The cap film 14 is a film made of a conductive material introduced in the process in order to connect the resistance change type memory cell MC and the upper word line WL or bit line BL. Here, a W film is used as the cap film 14. As described above, the resistance change type memory cell MC is configured by including the structure in which the rectifying element 12 and the resistance change element 13 are stacked. In this embodiment, the barrier metal film 11 to the cap film 14 are called memory cells MC.

  The memory cell MC sandwiched between the bit line BL and the word line WL is processed into an elliptic cylinder. However, the major axis direction of the elliptical columnar memory cell is set so as to correspond to the extending direction of the wiring immediately below it. In other words, the lower wiring is the bit line BL or the word line WL. It depends on what.

  Specifically, in the plane parallel to the substrate surface, the elliptical columnar memory cell MC has a minor axis that coincides with the extending direction of the upper wiring layer so that the major axis thereof coincides with the extending direction of the lower wiring layer. Are arranged as follows. For example, in the first and third memory layers in FIG. 1, the lower layer wiring is the word lines WL11, WL12, WL13, WL21, WL22, WL23 extending in the X direction, and the upper layer wiring is extending in the Y direction. The bit lines BL11, BL12, BL13, BL21, BL22, and BL23 are used. Therefore, as shown in FIG. 2A, the elliptical columnar memory cells MC are arranged so that the major axis is in the X direction. On the other hand, in the second and fourth memory layers in FIG. 1, the lower layer wirings are bit lines BL11, BL12, BL13, BL21, BL22, and BL23 extending in the Y direction, and the upper layer wirings are extended in the X direction. The existing word lines WL21, WL22, WL23, WL31, WL32, and WL33. Therefore, as shown in FIG. 2B, the elliptical columnar memory cells MC are arranged so that the major axis is in the Y direction.

  By arranging the elliptical columnar memory cells MC according to the upper and lower wiring directions in this way, the memory cells MC are less likely to fall in the major axis direction and more unlikely to fall than the minor axis direction. That is, since the memory cell does not drastically fall over or fall down in the width direction of the upper layer wiring, it is possible to improve the contact between the memory cell MC and the upper layer wiring.

  Next, a method for manufacturing the nonvolatile memory device having such a structure will be described. 3-1 to 3-11 are cross-sectional views schematically showing an example of the procedure of the method for manufacturing the nonvolatile memory device according to this embodiment. In these drawings, (a) is a sectional view in a direction perpendicular to the X direction, (b) is a sectional view in a direction parallel to the X direction, and (c) is a top view. Here, the wiring extending in the Y direction will be described as the bit line BL, and the wiring extending in the X direction will be described as the word line WL.

  First, as shown in FIG. 3A, a first interlayer insulating film 101 is formed on a substrate such as a Si substrate (not shown), and a first layer extending in the Y direction on the first interlayer insulating film 101 is formed. A wiring groove 102 for forming a wiring (bit line BL) is formed. Next, a barrier metal film 103 made of TiN and having a thickness of 10 nm is formed on the first interlayer insulating film 101 so as to cover the side and bottom surfaces of the wiring trench 102, and further, a W film is formed on the barrier metal film 103. A conductive layer is formed. Thereafter, planarization is performed by CMP (Chemical Mechanical Polishing) until the first interlayer insulating film 101 between the wiring trenches 102 is exposed, whereby the first wiring 104 is formed. An element such as a CMOS (Complementary Metal-Oxide Semiconductor) transistor is formed on the substrate under the first interlayer insulating film 101.

  Next, as shown in FIG. 3B, a barrier metal film 111, a rectifying layer 112, a resistance change layer 113, a cap film 114, and a mask are formed on the first interlayer insulating film 101 on which the first wiring 104 is formed. Layers are formed in order. Specifically, first, a barrier metal film 111 made of a 5 nm thick TiN film is formed on the first interlayer insulating film 101 on which the first wiring 104 is formed by a method such as sputtering. On the barrier metal film 111, a P-type polysilicon film 112P having a thickness of about 20 nm, an I-type polysilicon film 112I having a thickness of about 110 nm, and a thickness of about 120 nm are formed by a film forming method such as a CVD (Chemical Vapor Deposition) method. A rectifying layer 112 is formed by sequentially depositing a 20 nm N-type polysilicon film 112N. The P-type polysilicon film 112P is obtained by depositing a silicon film while introducing a P-type impurity such as B (boron), and the I-type polysilicon film 112I is deposited in an environment in which no impurity is introduced. The N-type polysilicon film 112N is obtained by depositing a silicon film while introducing an N-type impurity such as P (phosphorus).

Further, a resistance change layer 113 made of a NiO film having a thickness of 5 to 20 nm is formed on the rectifying layer 112 by a method such as a CVD method, and subsequently made of a W film by a film forming method such as a sputtering method. A cap film 114 is formed. Thereafter, a hard mask film 115 made of SiO ₂ or the like formed using TEOS or SiH ₄ as a raw material and an organic film 116 are sequentially formed on the cap film 114 by a film forming method such as a CVD method. Here, the thicknesses of the hard mask film 115 and the organic film 116 are determined such that the barrier metal film 111, the rectifying layer 112, the resistance change layer 113, and the cap film 114 can be etched in a later etching process using these as masks. Is set. In some cases, the hard mask film 115 may be omitted.

  Next, the organic film 116 is patterned by a lithography method to form a pattern in which the Y direction is long. Here, an oval resist pattern (not shown) is formed, and then the resist pattern is transferred to the organic film 116 by a dry etching method such as RIE as shown in FIG. As a result, the organic film 116 is patterned into an elliptical shape. Note that the oval pattern is formed at a position corresponding to the formation position of the first wiring 104 in the lower layer.

  After that, as shown in FIG. 3-4, the hard mask film 115, the cap film 114, the resistance change layer 113, the rectifying layer are formed by a dry etching method such as the RIE method using the organic film 116 patterned in an elliptical shape as a mask. 112 and the barrier metal film 111 are etched to form a memory cell array pattern in which elliptical columnar memory cell patterns are two-dimensionally arranged. As described above, the planar shape of the memory cell at this time is an elliptical shape having a major axis in the Y direction. In addition, the memory cell may be bent or tilted by etching, but it is unlikely to be bent or toppled in the major axis direction. Therefore, the memory cell is mainly twisted or tilted in the direction perpendicular to the major axis, that is, the minor axis direction. Occurs. In the plan view of FIG. 3-4 (c), the memory cell pattern is bent or tilted in the X direction, but there is almost no displacement in the Y direction. In the plan view of FIG. 3-4 (c), the dotted line indicates the position of the organic film 116 patterned in an elliptical shape.

  Thereafter, as shown in FIG. 3-5, a second interlayer insulating film 117 made of BPSG (Boron Phosphorus Silicate Glass) film, polysilazane, or the like is formed so as to fill the space between the memory cells by a coating method or the like. Then, the upper surface of the second interlayer insulating film 117 is removed and planarized by CMP until the cap film 114 is exposed.

  Next, as shown in FIG. 3-6, a third interlayer insulating film 121 is formed on the second interlayer insulating film 117 from which the cap film 114 is exposed by a CVD method or a coating method. Thereafter, by a known lithography technique and dry etching method, a plurality of wiring trenches 122 extending in the X direction and having a depth of 100 nm serving as a template for a second wiring having a thickness of about 100 nm are formed in the third interlayer insulating film 121. Form. The wiring trench 122 is formed in the third interlayer insulating film 121 so as to connect the memory cells adjacent in the X direction and so as to penetrate the third interlayer insulating film 121.

  Next, a barrier metal film 123 made of a titanium nitride film having a thickness of 10 nm is formed on the third interlayer insulating film 121 so as to cover the bottom and side surfaces of the wiring groove 122 by sputtering. Further, a conductive layer made of a W film is formed on the barrier metal film 123 by a CVD method or a plating method so as to fill the wiring groove 122 in which the barrier metal film 123 is formed. Thereafter, the conductive layer and the barrier metal film 123 are polished and planarized by CMP until the third interlayer insulating film 121 is exposed in the region between the wiring trenches 122. As a result, a second wiring (word line) 124 extending in the X direction is formed in the third interlayer insulating film 121. Thus, a first-layer memory cell is formed between the first wiring 104 and the second wiring 124.

Next, as shown in FIG. 3-7, a barrier metal film 131, a rectifying layer 132, a resistance change layer 133, a cap film 134, and a mask are formed on the third interlayer insulating film 121 on which the second wiring 124 is formed. Layers are formed in order. Here, a TiN film having a thickness of 5 nm is formed as the barrier metal film 131, an N-type polysilicon film 132N having a thickness of about 20 nm, an I-type polysilicon film 132I having a thickness of about 110 nm, and a thickness are formed as the rectifying layer 132. A laminated film of a P-type polysilicon film 132P having a thickness of about 20 nm is formed, a NiO film having a thickness of 5 to 20 nm is formed as the resistance change layer 133, a W film is formed as the cap film 134, and SiO ₂ is formed as the mask layer. A laminated film of a hard mask film 135 and an organic film 136 made of a film or the like is formed.

  These films are formed in the same manner as in the case of the first-layer memory cell. Here, unlike the first memory cell, the rectifying layer 132 is laminated in the order of N layer / I layer / P layer from the bottom. This is to make a current flow only in the direction from the word line to the bit line in all the memory cells. Further, the thickness of the hard mask film 135 and the organic film 136 is set to such a thickness that the barrier metal film 131, the rectifying layer 132, the resistance change layer 133, and the cap film 134 can be etched in a later etching process using these as a mask. It is set. In some cases, the hard mask film 135 may be omitted.

  Next, the organic film 136 is patterned by lithography to form a pattern in which the X direction, which is the extending direction of the lower second wiring 124, becomes long. Here, an oval resist pattern (not shown) is formed, and then the resist pattern is transferred to the organic film 136 by a dry etching method such as the RIE method, as shown in FIGS. As a result, the organic film 136 is patterned into an elliptical shape.

  Thereafter, as shown in FIG. 3-9, the hard mask film 135, the cap film 134, the resistance change layer 133, the rectifying layer are formed by a dry etching method such as the RIE method using the organic film 136 patterned in an elliptical shape as a mask. 132 and the barrier metal film 131 are etched to form a memory cell array pattern in which elliptical columnar memory cell patterns are two-dimensionally arranged. As described above, the planar shape of the memory cell at this time is an elliptical shape having a major axis in the X direction. Etching also causes memory cells to sag and fall, but it is difficult to squeeze or fall down in the major axis direction, while the memory cell mainly sags or falls in the direction perpendicular to the major axis, that is, the direction of the minor axis. Occurs. In the plan view of FIG. 3C, the memory cell pattern is bent or tilted in the Y direction, but there is almost no displacement in the X direction. In the plan view of FIG. 3-9 (c), the dotted line indicates the position of the organic film 136 patterned in an elliptical shape.

  Thereafter, as shown in FIG. 3-10, a fourth interlayer insulating film 137 made of BPSG film, polysilazane, or the like is formed so as to fill the space between the memory cells by a coating method or the like. Then, the upper surface of the fourth interlayer insulating film 137 is removed and planarized by CMP until the cap film 134 is exposed.

  Next, as shown in FIG. 3-11, for example, a fifth interlayer insulating film 141 having a thickness of 100 nm is formed on the fourth interlayer insulating film 137 from which the cap film 134 is exposed by a CVD method or a coating method. To do. Thereafter, a plurality of wiring trenches 142 extending in the Y direction and having a depth of 100 nm serving as a template for the third wiring are formed in the fifth interlayer insulating film 141 by a known lithography technique and dry etching method. The wiring trench 142 is formed in the fifth interlayer insulating film 141 so as to connect the memory cells adjacent in the Y direction and to penetrate the fifth interlayer insulating film 141.

  Next, a barrier metal film 143 made of a titanium nitride film having a thickness of 10 nm is formed on the fifth interlayer insulating film 141 so as to cover the bottom and side surfaces of the wiring trench 142 by sputtering. Further, a conductive layer made of a W film is formed on the barrier metal film 143 by a CVD method so as to fill the wiring groove 142 in which the barrier metal film 143 is formed. Thereafter, the conductive layer and the barrier metal film 143 are polished and planarized by CMP until the fifth interlayer insulating film 141 is exposed in the region between the wiring trenches 142. As a result, a third wiring (bit line) 144 extending in the Y direction is formed in the fifth interlayer insulating film 141. Thus, a second-layer memory cell is formed between the second wiring 124 and the third wiring 144.

  Through the above processing steps, a nonvolatile memory device having a structure in which two layers of memory cells are stacked in the height direction is formed. Note that in the case of forming a nonvolatile memory device having a structure with more than two layers, the above-described procedure may be repeated.

  In the above description, the rectifier element and the resistance change element are stacked in this order on the lower layer wiring. However, the resistance change element and the rectification element are stacked in this order on the lower layer wiring. It may be. Furthermore, although the case where a semiconductor layer having a PIN junction structure is used as the rectifying layer has been described, a semiconductor layer having a PN junction structure may be used, or a Schottky junction may be used.

  In the above description, the bit line or the word line is shared between the memory cells adjacent in the height direction. However, the bit line or the word line is not shared between the memory cells adjacent in the height direction. Also good. In this case, a word line and a bit line are provided for each memory cell adjacent in the height direction.

  FIG. 4 is a plan view schematically showing the relationship between the memory cell and the upper layer wiring of this embodiment, and FIG. 5 is a plan view schematically showing the relationship between the columnar memory cell and the upper layer wiring. is there. FIG. 4A is a diagram showing an arrangement relationship between the first-layer memory cell and the second wiring 124 in the above manufacturing process, and FIG. 4B similarly shows the second-layer memory cell and the second-layer memory cell. 3 is a diagram illustrating an arrangement relationship with the third wiring 144; FIG. In FIGS. 4A and 4B, the upper layer wiring is indicated by a dotted line.

  As shown in FIG. 4A, the memory cell in the first layer is formed in an elliptical column shape so that the Y direction, which is the extending direction of the first wiring 104 in the lower layer, becomes the major axis direction. Therefore, during the dry etching process, the major axis direction is less likely to sag and fall than the minor axis direction X direction. That is, the formation position in the Y direction of the upper surface (cap film 114) of the memory cell of the first layer connected by the same second wiring 124 is substantially the same position. In addition, when a second interlayer insulating film 117 such as a coating-type BPSG film or polysilazane is formed between the memory cells, the position of the upper surface (cap film 114) of the memory cell is greatly increased in the Y direction due to the stress of the coating film. There is no deviation. As a result, when the second wiring 124 is formed over the first-layer memory cell, the second wiring 124 can secure a large contact area with the memory cell.

  The same applies to the second-layer memory cell shown in FIG. The second-layer memory cell is formed in an elliptical column shape so that the X direction, which is the extending direction of the second wiring 124 in the lower layer, becomes the major axis direction. As a result, the position of the upper surface (cap film 134) of the memory cell is displaced in the Y direction during dry etching or when the fourth interlayer insulating film 137 is embedded, but is not greatly displaced in the X direction. As a result, the third wiring 144 formed over the second-layer memory cell can ensure a large contact area with the memory cell.

  On the other hand, as shown in FIG. 5, in the case of a cylindrical memory cell MC, there is a possibility that the upper surface of the memory cell MC is displaced in any direction during dry etching or when an interlayer insulating film is embedded. is there. As a result, there may be a memory cell MC that has a very small contact area with the upper layer wiring 201 and causes contact failure. Thus, in the case of a memory cell MC having a shape that does not depend on the wiring direction, such as a columnar structure having a square cross section parallel to the substrate surface as well as a columnar shape, the memory cell MC may be bent or tilted. As a result, there is a risk of poor contact with the upper layer wiring 201.

  As described above, according to the present embodiment, the shape in the direction parallel to the substrate surface of the memory cell is larger in the wiring direction in the lower layer than the size in the wiring direction in the upper layer. It is possible to prevent the memory cell from being bent or tilted during the etching of the cell or when the interlayer insulating film is embedded between the memory cells in the width direction of the upper layer wiring. As a result, the contact failure between the memory cell and the upper layer wiring can be suppressed.

  In the above description, the case where the major axis of the memory cell is made to coincide with the extending direction of the lower wiring layer in a plane parallel to the substrate surface has been described. It is difficult to accurately match the major axis direction of the cell with the extending direction of the lower wiring layer. According to the experiments by the present inventors, it has been found that the same effect as described above can be obtained even when the major axis direction of the memory cell is inclined by about ± 30 ° with respect to the extending direction of the lower wiring layer. When the direction of the major axis of the memory cell becomes larger than ± 30 ° with respect to the extending direction of the lower wiring layer, the memory cell comes into contact with the adjacent memory cell in the lateral direction due to the twisting or falling of the memory cell. The fear increases and is not desirable. Therefore, the direction of the major axis of the memory cell only needs to be within a range of ± 30 ° with respect to the extending direction of the lower wiring layer.

  In the above description, the case where the memory cell has an elliptical columnar structure is described, but the same effect as described above can be obtained even when the memory cell has a rectangular columnar (rectangular columnar) structure. Further, the shape in the plane parallel to the substrate surface of the memory cell may be a shape in which the size in the lower wiring direction is longer than the upper wiring direction. In these cases, the longest direction is the direction in which the size becomes the longest.

  Furthermore, in the above description, the resistance change type memory has been described as an example. However, the present invention is not limited to this, and a nonvolatile memory such as a phase change type memory having a phase change element or a field-programmable ROM using an anti-fuse is used. The present invention can also be applied to an apparatus and a manufacturing method thereof.

  DESCRIPTION OF SYMBOLS 11 ... Barrier metal film, 12 ... Rectifier element, 12P ... P type polysilicon film, 12I ... I type polysilicon film, 12N ... N type polysilicon film, 13 ... Resistance change element, 14 ... Cap film, 20 ... Interlayer insulation film.

Claims (5)

A first wiring extending in a first direction;
A second wiring formed above the first wiring and extending in a second direction;
A third wiring formed above the second wiring and extending in the first direction;
A non-volatile memory element and a rectifying element arranged to be sandwiched between the first wiring and the second wiring at a position where the first wiring and the second wiring cross each other A first nonvolatile memory cell having a columnar structure;
A non-volatile memory element and a rectifying element arranged to be sandwiched between the second wiring and the third wiring at a position where the second wiring and the third wiring intersect A second nonvolatile memory cell having a columnar structure;
With
The first and second nonvolatile memory cells have different sizes in a plane formed in the first and second directions, and the longest diameter direction of the size is connected to the nonvolatile memory cell. A non-volatile memory device, wherein the non-volatile memory device is arranged in correspondence with an extending direction of a lower layer wiring.   2. The nonvolatile memory device according to claim 1, wherein a direction of the major axis is in a range of ± 30 ° with respect to an extending direction of the lower layer wiring.   3. The nonvolatile memory device according to claim 1, wherein a planar shape formed in the first and second directions of the nonvolatile memory cell is an elliptical shape or a rectangular shape. 4. A first stacked film including a first rectifying layer and a first nonvolatile memory layer is formed on a first interlayer insulating film in which a plurality of first wirings extending in a first direction are formed. A first step;
A pattern having a shape in which the first direction is longer than the second direction intersecting the first direction is two-dimensionally formed on the plurality of first wirings on the first stacked film. A second step of forming a first mask pattern arranged in an automatic manner;
Etching the first stacked film using the first mask pattern to form a first memory cell having a columnar structure including a rectifying element and a nonvolatile memory element;
A fourth step of filling a space between the first memory cells having a columnar structure with a second interlayer insulating film and flattening until the surface of the first memory cell is exposed;
A fifth step of forming a plurality of second wirings that connect the first memory cells in the second direction, and a third interlayer insulating film that insulates the plurality of second wirings; ,
A sixth step of forming a second laminated film including a second rectifying layer and a second nonvolatile memory layer on the third interlayer insulating film in which the plurality of second wirings are formed;
A second pattern in which a pattern having a shape in which the second direction is longer than the first direction is two-dimensionally arranged on the plurality of second wirings on the second stacked film; A seventh step of forming the mask pattern;
Etching the second laminated film using the second mask pattern to form a second memory cell having a columnar structure including a rectifying element and a nonvolatile memory element;
A ninth step of filling a space between the second memory cells having a columnar structure with a fourth interlayer insulating film and flattening until the surface of the second memory cell is exposed;
A tenth step of forming a plurality of third wirings connecting the second memory cells in the first direction;
A method for manufacturing a nonvolatile memory device, comprising:   In the second and seventh steps, the pattern is formed such that the major axis direction of the pattern is in a range of ± 30 ° with respect to the extending direction of the wiring immediately below the laminated film etched using the pattern. The method of manufacturing a nonvolatile memory device according to claim 4, wherein the non-volatile memory device is formed.

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