JP2011060080A - Simulation apparatus, simulation method and program for simulation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that when an instruction is directly edited by a memory window or the like of a debugger in a conventional simulator (simulation apparatus), the edited contents may be made different from the contents of a decode cache and a correct instruction cannot be executed. <P>SOLUTION: A simulator (simulation apparatus 10) includes: an instruction change notification part 1211 which, when the contents of a memory are rewritten and the contents are an instruction, sets a change flag in a decode cache of the corresponding instruction; and an execution simulation part 123 for detecting whether the change flag exists in the decode cache during execution of the instruction, and when the change flag exists, performing re-fetch and decoding. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a simulation apparatus, and more particularly to a simulation apparatus that simulates and debugs the operation of a microcomputer.

  Here, a simulation device that simulates the operation of a computer or the like is called a simulator. As an example of a prior art simulator, Japanese Unexamined Patent Application Publication No. 2005-63165 (Patent Document 1) discloses a high-speed emulator for a virtual machine. In this prior art, the emulator is provided with a decode cache for storing the results of instruction fetch and decode processing. At the first execution of the instruction, the decoded result is stored in the decode cache. The saved cache contents are reused at the next execution. In the decode cache, a virtual instruction pointer is used as a key and held in correspondence with the address of the execution processing routine. In the execution processing routine, execution processing corresponding to the virtual instruction is performed. Checks the decode cache when fetching an instruction based on the virtual instruction pointer, uses the decode result if it exists, decodes the instruction based on the virtual instruction pointer if the decode result does not exist, and registers the result in the decode cache To do.

  In the simulator of the prior art, when the instruction is directly edited in the memory window of the debugger, the contents are different from the contents of the decode cache, and the correct instruction cannot be executed.

  In the prior art simulator, the simulator is provided with a decode cache for storing the results of instruction fetch and decode processing. At the first execution of the instruction, the decoded result is stored in the decode cache. At the next execution, the saved cache contents could be reused to speed up the execution.

  The problem with the prior art is that there is no consideration when the instruction is directly edited in the memory window of the debugger or the like and differs from the contents of the decode cache.

JP 2005-63165 A

  Regarding the consideration when rewriting occurs on the memory, which is a problem of the prior art, it is dealt with by adding a change flag to the decode cache. When rewriting occurs in the memory, the change flag is set, and if there is a change flag in the decoding cache of the target instruction at the time of execution, the solution is achieved by performing refetching / decoding.

  The simulator (simulation apparatus) of the present invention includes an instruction change notification unit and an execution simulation unit. When the memory is rewritten and the rewritten content is an instruction, the instruction change notification unit sets a change flag in the decode cache of the corresponding instruction. The execution simulation unit detects whether there is a change flag in the decode cache at the time of execution of the corresponding instruction, and if there is a change flag, performs refetch / decode.

  Establishing a means to notify the decoding cache of the change information in the memory. When there is a change in the memory, a change flag is set in the decode cache. If there is a change flag at the time of execution, fetch / decode from the memory again. After executing the above, the correct instruction can be executed at any time.

It is a block diagram which shows the structural example of the simulator (simulation apparatus) of this invention. It is a flowchart which shows operation | movement of the simulator of this invention. It is a flowchart which shows operation | movement of the simulator of this invention.

Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.
The simulator of the present invention is a simulation device that simulates the operation of a microcomputer, and is realized by a combination of a PC (personal computer) and an application program that runs on the PC. By using the simulator of the present invention, it is possible to simulate the operation of the microcomputer on the PC. A PC is only an example. Other examples of hardware for realizing the simulator of the present invention include an I / O (Input / Output) board, a thin client server, a workstation, a mainframe, a supercomputer, a portable terminal, a home game machine, and an information appliance. (Information home application), POS (Point of Sale) terminals, OA (Office Automation) devices, and the like are conceivable. The simulator of the present invention is not limited to a terminal or a server, and may be a relay device or a peripheral device. However, actually, it is not limited to these examples.

This will be described with reference to the block diagram of the simulator of the present invention in FIG.
A simulator (simulation apparatus) 10 according to the present invention includes a debugger unit 11 and a simulation unit 12.

  The debugger unit 11 includes a command input unit 111, an execution command processing unit 112, and a memory write processing unit 113.

  The simulation unit 12 includes a memory simulation unit 121, a decode cache 122, and an execution simulation unit 123.

  The memory simulation unit 121 is a part that simulates the memory of the microcomputer. The decode cache 122 has a change flag indicating whether or not the instruction is rewritten, in addition to the instruction start address and decode information. The execution simulation unit 123 is a part that simulates instruction execution processing of the microcomputer.

  The memory simulation unit 121 includes an instruction change notification unit 1211.

  The execution simulation unit 123 includes an execution management unit 1231, a fetch / decode unit 1232, and an execution unit 1233.

  The execution target program 110 is an object file that is language-processed by a compiler or the like that operates on a microcomputer that is simulated by the simulator 10 of the present invention. When the execution target program 110 is downloaded to the debugger unit 11, it is downloaded from the command input unit 111 to the memory simulation unit 121 via the memory write processing unit 113.

  When an execution command is input, the command input unit 111 notifies the execution management unit 1231 of the execution simulation unit 123 of the input execution command via the execution command processing unit 112.

  The execution management unit 1231 searches the decode cache 122 for an address that matches the instruction to be executed next, thereby searching whether the decode information of the instruction is cached. The fetch / decode unit 1232 performs decoding when there is no decode information of the corresponding instruction, and registers an address and decode information in the decode cache 122. Thereafter, the execution unit 1233 executes the instruction using the decode information registered in the decode cache 122. Further, when there is decode information of the corresponding instruction, the execution unit 1233 executes the instruction using the decode information.

  However, if the execution management unit 1231 finds that a change flag is set in the corresponding instruction on the decode cache 122, the fetch / decode unit 1232 performs refetch / decode, updates the decode information, Reset the change flag. The execution unit 1233 executes the instruction using the updated decode information.

  When there is a rewrite request for an instruction from the command input unit 111, the memory write processing unit 113 notifies the memory simulation unit 121 of the rewrite request. After the memory rewrite by the memory simulation unit 121, the instruction change notification unit 1211 sets a change flag at the corresponding location in the decode cache 122.

  For example, the debugger unit 11 and the simulation unit 12 are realized by hardware such as a CPU that is driven by a program, software that drives the hardware to execute a desired process, and a storage device that stores the software. . The command input unit 111 may have an interface (I / F: interface) for acquiring information from an external input device or storage device.

  Examples of hardware for realizing the debugger unit 11 and the simulation unit 12 include a CPU (Central Processing Unit), a microprocessor (microprocessor), a microcontroller, or a semiconductor integrated circuit (Integrated Circuit (IC)) having similar functions. Can be considered. However, actually, it is not limited to these examples.

  Examples of storage devices that store programs and data used in the debugger unit 11 and the simulation unit 12 include semiconductor storage devices such as a RAM (Random Access Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory), a flash memory, and the like. An auxiliary storage device such as (Hard Disk Drive) or SSD (Solid State Drive), or a storage medium (media) such as a DVD (Digital Versatile Disk) or a memory card can be considered. The storage device is not limited to a storage device built in the computer main body, and may be a storage device installed in a peripheral device (external HDD or the like), an external server (storage server or the like), or NAS (Network Attached Storage). However, actually, it is not limited to these examples.

  2A and 2B show a flowchart of the operation of the simulator of the present invention.

(1) Step S201
The simulator 10 is activated by a user operation or activation setting. Thereby, simulator 10 will be in an operation state.

(2) Step S202
The simulator 10 downloads a simulation / debug target program (execution target program 110).

(3) Step S203
Thereafter, the simulator 10 enters a command waiting state.

(4) Step S204
Command execution is performed on the simulator 10. The command input unit 111 receives an execution command input when the simulator 10 is in a command waiting state.

(5) Step S205
When an execution command is input, the command input unit 111 determines whether the input execution command is a one-instruction execution command. If the input execution command is a one-command execution command, the command input unit 111 notifies the execution management unit 1231 of the execution simulation unit 123 of the input execution command via the execution command processing unit 112.

(6) Step S206
The execution management unit 1231 searches the decode cache 122 for an address that matches the instruction (target instruction) indicated in the notified execution command.

(7) Step S207
The execution management unit 1231 confirms whether the target instruction exists by confirming whether the decode information of the target instruction is cached in the decode cache 122.

(8) Step S208
When the decode information of the target instruction is cached, the execution management unit 1231 checks whether the change flag is set for the target instruction on the decode cache 122.

(9) Step S209
When the decoding information of the target instruction is not cached or when the change flag is not set, the fetch / decode unit 1232 determines that the target instruction does not exist and performs fetch / decode.

(10) Step S210
The fetch / decode unit 1232 registers the decode information obtained as a result of the fetch / decode in the decode cache 122.

(11) Step S211
The fetch / decode unit 1232 resets the change flag when the change flag is set in the target instruction on the decode cache 122.

(12) Step S212
If the change flag is not set in the target instruction on the decode cache 122, the execution unit 1233 executes the target instruction as it is. After execution of the target instruction, the simulator 10 enters a command waiting state.

(13) Step S213
The execution unit 1233 executes the target instruction based on the decode information when the decode information of the target instruction is cached on the decode cache 122 and the change flag is not set. After execution of the target instruction, the simulator 10 enters a command waiting state.

(14) Step S214
Further, if the input execution command is not a one-instruction execution command, the command input unit 111 determines whether the input execution command is a memory rewrite command.

(15) Step S215
If the input execution command is not a memory rewrite command, the command input unit 111 determines that the command is another command, notifies the processing unit to process the other command, and performs processing for the other command. After execution of processing for other commands, the simulator 10 enters a command waiting state.

(16) Step S216
If the input execution command is a memory rewrite command, the command input unit 111 notifies the memory rewrite command to the memory simulation unit 121 via the memory write processing unit 113. The memory simulation unit 121 rewrites the contents of the memory in response to the memory rewrite command.

(17) Step S217
The memory simulation unit 121 checks whether the memory rewrite command is a rewrite request for the target instruction. If the memory rewrite command is not a rewrite request for the target instruction, the simulator 10 enters a command waiting state.

(18) Step S218
If the memory rewrite command is a rewrite request for the target instruction, the instruction change notification unit 1211 sets a change flag at the corresponding location in the decode cache 122.

The overall outline (example) of the actual operation will be described below.
The simulator 10 of the present invention is activated (step S201), and a simulation / debug target program is downloaded (step S202).

  Thereafter, the simulator 10 enters a command waiting state (step S203). However, if the command is executed (step S204) and the command is a one-instruction execution command (step S205), the decode cache 122 is searched (step S206). If the target instruction does not exist, fetch / decode is performed (step S209) and registered in the decode cache 122 (step S210). If the change flag is not set (step S211), the execution is performed as it is (step S212).

  Next, when executing this instruction, the simulator 10 searches the decode cache 122 (step S206), the decode information of the target instruction is cached (step S207), and the change flag must be set. (Step S208), it can be executed based on this decoding information (step S213).

  When an instruction rewrite request is received using the memory rewrite command (step S214), the simulator 10 of the present invention rewrites the contents of the memory (step S216) and then confirms that the rewritten area is an instruction. After confirmation (step S217), a change flag is set for the corresponding instruction in the decode cache 122 (step S218).

  Thereafter, when executing the changed instruction, the decode cache 122 is searched (step S206), and even if there is the target instruction information (step S207), there is a change flag (step S208). It is determined that fetch / decode is necessary, re-registering in the decode cache 122 (step S210), clearing the change flag (step S211), and executing (step S212).

  Thus, the instruction can be correctly executed when the instruction is rewritten.

  As described above, in the simulator of the present invention, when the memory is rewritten in the memory simulation unit, if the rewritten memory is an instruction, an instruction change notification unit for setting a change flag in the decode cache is prepared. By preparing an execution management unit that detects when the command is executed, it can be executed correctly even if the command is rewritten.

  As mentioned above, although embodiment of this invention was explained in full detail, actually, it is not restricted to said embodiment, Even if there is a change of the range which does not deviate from the summary of this invention, it is included in this invention.

10 ... Simulator (simulation device)
DESCRIPTION OF SYMBOLS 11 ... Debugger part 110 ... Execution object program 111 ... Command input part 112 ... Execution command processing part 113 ... Memory write processing part 12 ... Simulation part 121 ... Memory simulation part 1211 ... Instruction change notification part 122 ... Decode cache 123 ... Execution simulation Unit 1231 ... Execution management unit 1232 ... Fetch / decode unit 1233 ... Execution unit

Claims (15)

When the memory is rewritten, if the rewritten content is an instruction, an instruction change notification unit that sets a change flag in the decode cache of the instruction, and
A simulation apparatus comprising: an execution simulation unit that checks whether or not there is a change flag in the decode cache of the instruction at the time of execution of the instruction, and performs refetch / decode if the change flag is in the decode cache. The simulation apparatus according to claim 1,
The execution simulation unit
An execution management unit that searches the decode cache for an address that matches the instruction at the time of execution of the instruction, and searches whether the decode information of the instruction is cached;
If the instruction decode information is not cached, fetch / decode, and a fetch / decode unit that registers an address and decode information in the decode cache;
When the decode information of the instruction is not cached, the instruction is executed using the decode information registered in the decode cache by the fetch / decode unit, and when the decode information of the instruction is cached, A simulation apparatus further comprising: an execution unit that executes the instruction using cached decode information. The simulation apparatus according to claim 2,
When the execution simulation unit finds that a change flag is set in the instruction on the decode cache, the fetch / decode unit performs re-fetch / decode, updates existing decode information, Simulation device that resets the change flag. The simulation apparatus according to any one of claims 1 to 3,
A memory simulation unit for simulating a memory;
When an execution command is input, it is determined whether the input execution command is a single instruction execution command. If the input execution command is not a single instruction execution command, the input execution command is a memory rewrite command. A command input section for determining whether or not
If the input execution command is a one-instruction execution command, an execution command processing unit that notifies the execution simulation unit of the one-instruction execution command;
A simulation apparatus, further comprising: a memory write processor that notifies the memory rewrite command of the memory rewrite command if the input execution command is a memory rewrite command. The simulation apparatus according to claim 4,
The memory simulation unit rewrites the contents of the memory in response to the memory rewrite command, and checks whether the memory rewrite command is a rewrite request for the instruction,
The instruction change notification unit, when the memory rewrite command is a rewrite request for the instruction, sets a change flag at a corresponding location in the decode cache after the memory rewrite by the memory simulation unit. A computer-implemented simulation method comprising:
If the rewritten content is an instruction when the memory is rewritten, a change flag is set in the decode cache of the instruction,
A simulation method in which, when an instruction is executed, whether or not there is a change flag in the decode cache of the instruction, and if there is a change flag in the decode cache, refetch / decode is performed. The simulation method according to claim 6, comprising:
When the instruction is executed, the address that matches the instruction is searched on the decode cache, and whether the decode information of the instruction is cached is searched.
If the decode information of the instruction is not cached, fetch and decode, register an address and decode information in the decode cache, execute the instruction using the decode information registered in the decode cache,
When the decode information of the instruction is cached, the instruction is executed using the cached decode information. The simulation method according to claim 7, comprising:
A simulation method in which when it is found that a change flag is set in the instruction on the decode cache, refetch / decode is performed, existing decode information is updated, and the change flag is reset. A simulation method according to any one of claims 6 to 8,
When an execution command is input, it is determined whether the input execution command is a one-instruction execution command,
If the input execution command is a single instruction execution command, the instruction execution process is simulated based on the single instruction execution command,
If the input execution command is not a one-instruction execution command, determine whether the input execution command is a memory rewrite command;
A simulation method for rewriting memory contents based on the memory rewrite command if the input execution command is a memory rewrite command. The simulation method according to claim 9, wherein
When rewriting the contents of the memory based on the memory rewrite command, check whether the memory rewrite command is a rewrite request for the instruction,
When the memory rewrite command is a rewrite request for the instruction, a change flag is set at a corresponding location in the decode cache after the memory is rewritten. A simulation program executed by a computer,
If the rewritten content is an instruction when the memory is rewritten, a step of setting a change flag in the decode cache of the instruction;
A simulation program for causing a computer to check whether or not there is a change flag in the decode cache of the instruction at the time of executing the instruction, and to perform refetch / decode if there is a change flag in the decode cache. A simulation program according to claim 11, comprising:
Searching for an address that matches the instruction on the decode cache when the instruction is executed, and searching whether the decode information of the instruction is cached;
If the decode information of the instruction is not cached, performing fetch / decode, registering an address and decode information in the decode cache, and executing the instruction using the decode information registered in the decode cache When,
A simulation program for causing a computer to further execute a step of executing the instruction using the cached decoding information when the decoding information of the instruction is cached. A simulation program according to claim 12, comprising:
When it is found that a change flag is set in the instruction on the decode cache, the computer is further executed to perform refetch / decode, update the existing decode information, and reset the change flag. Simulation program for. A simulation program according to any one of claims 11 to 13,
When an execution command is input, determining whether the input execution command is a one-instruction execution command;
If the input execution command is a single instruction execution command, simulating instruction execution processing based on the single instruction execution command;
If the input execution command is not a one-instruction execution command, determining whether the input execution command is a memory rewrite command; and
A simulation program for causing a computer to further execute a step of rewriting the contents of a memory based on the memory rewrite command if the input execution command is a memory rewrite command. A simulation program according to claim 14,
When rewriting the contents of the memory based on the memory rewrite command, checking whether the memory rewrite command is a rewrite request for the instruction;
A simulation program for causing a computer to further execute a step of setting a change flag at a corresponding location in the decode cache after a memory rewrite when the memory rewrite command is a rewrite request for the instruction.

Images