CN117270967A - Automatic generation method and device of instruction set architecture simulator based on model driving - Google Patents
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Abstract
The invention discloses a model-driven automatic generation method and device of an instruction set architecture simulator, wherein the method comprises the following steps: step 1: constructing a simulator description model; step 2: generating a mapping table according to instruction description in the simulator description model; step 3: generating a register resource record table and a memory mapping table according to the register description and the memory description in the simulator description model; step 4: reading a simulated target program to generate an index table; step 5: constructing a program PC value index table, a program instruction address index table and a program instruction parallel execution marking index table of the target program; step 6: sequentially acquiring an instruction index value corresponding to a program PC value, further acquiring corresponding instruction information, and performing simulation execution; step 7: and finishing simulation of all instructions, and outputting a simulation result. The invention has the advantages of simple implementation method, low cost, high automation degree, high flexibility, high expandability and the like.
Description
Technical Field
The invention relates to the technical field of instruction set simulator implementation, in particular to an automatic generation method and device of an instruction set architecture simulator based on model driving.
Background
In new processor architecture research and design, simulators are an indispensable tool for simulating the execution behavior and processes of instructions to verify test programs and processor performances so as to meet different demands. There are various types of simulators in the prior art, for example, gem5 is a full system simulator, which can start Linux, solaris and Android operating systems on specific hardware supported by it; simplescaler is a widely popular architecture simulator at present, and can be configured into simulators with different architectures according to simulation requirements, such as sim-safe of a simulation instruction set architecture, sim-fast for optimizing execution performance, sim-output of a superscalar processor performance model supporting speculative and out-of-order execution; QEMU is a general purpose simulator and virtual machine that translates guest code into TCG intermediate code by extracting it and finally translates the intermediate code into host specific architecture code, such as x86 or ARM architecture, using binary instruction translation techniques.
In the design process of the new instruction set architecture, the instruction set is continuously improved and optimized in an iterative manner, and can be continuously updated and expanded according to different application requirements, and in each instruction set iterative process, a tool chain and a simulator are required to be rapidly provided for testing, verifying and evaluating the performance of the instruction set of the current version. In the prior art, in the design process of a new instruction set architecture, the instruction expansion and the instruction coding design and updating are usually realized by completely relying on manual programming, meanwhile, according to the existing instruction set architecture and instruction coding and instruction semantics of an instruction set manual, an instruction set architecture simulator is realized by adopting a manual programming mode, and the manual programming mode has low efficiency, is easy to make mistakes and has poor flexibility, and particularly, each instruction set iteration or updating expansion needs to reprogram the simulator to support the design of the new instruction set architecture, so that the simulator can be realized by consuming a great deal of cost and time in the development period of the whole instruction set architecture, and the efficiency and reliability of the design realization of the instruction set architecture are reduced.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems existing in the prior art, the invention provides an automatic generation method and device for an instruction set architecture simulator based on model driving, which can automatically generate the instruction set architecture simulator, improve the efficiency and flexibility of the implementation of the simulator, dynamically adapt to the improvement and expansion of the instruction set architecture and quickly realize the update of the instruction set architecture simulator.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
an automatic generation method of an instruction set architecture simulator based on model driving comprises the following steps:
step 1: constructing a simulator description model required by generating an instruction set architecture simulator according to instruction set architecture design requirements, wherein the simulator description model comprises a register description, an instruction description and a memory description of an instruction set architecture;
step 2: generating an instruction length mapping table, an instruction name mapping table, an instruction format coding field sequence mapping table and an instruction semantic function mapping table according to the instruction description in the simulator description model;
step 3: generating a register resource record table and a memory mapping table according to the register description and the memory description in the simulator description model, wherein the register resource record table is used for recording all register resources contained in an instruction set, and the memory mapping table is used for recording the mapping relation between the memory names of all memory resources in the instruction set and the memory resources thereof;
step 4: reading a binary code program of the simulated target program, and generating an instruction binary coding index table, an instruction feature ID index table and an instruction format coding field data type mapping index table;
step 5: constructing a program PC value index table, a program instruction address index table and a program instruction parallel execution marking index table of the target program according to the instruction binary coding index table, wherein the program PC value index table records program PC values of all instructions in the target program according to an index sequence;
step 6: according to the current program PC value and the program PC value index table, sequentially acquiring an instruction index value corresponding to the program PC value, further acquiring corresponding instruction information, and performing simulation execution on the acquired instruction;
step 7: and after the simulation of all the instructions is completed, outputting a simulation result.
Further, the register description is used to declare all register resources contained by the instruction set, the instruction description is used to declare all instruction resources contained by the instruction set, and the memory description is used to declare all memory resources accessed by the instruction set.
Further, the register description includes a plurality of tuples, each tuple containing a type, a name, a bit width, a number, and a vector width, the instruction description includes a plurality of tuples, each tuple includes a feature ID, an instruction name, a function unit name, an instruction length, and an instruction field sequence, the feature ID is used to identify to which function unit the described instruction belongs a specific instruction and a specific instruction format, the instruction field sequence is used to specify a specific field sequence composition of the described instruction, the instruction field sequence includes a field length, a field name, a field attribute, and a field mapping instance; the memory description includes a plurality of tuples, each tuple including a memory name, a starting address, a memory size, and a memory granularity.
Further, the instruction length mapping table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the instruction lengths thereof, the instruction name mapping table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the instruction names thereof, the instruction format coding field sequence mapping table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the corresponding instruction format coding field sequences, each tuple in the instruction coding field sequences comprises a field length, a field name, a field attribute and a field mapping example, and the instruction semantic function mapping table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the corresponding instruction semantic functions.
Further, the register resource record table is configured to record all register resources included in the instruction set, where each tuple in the register resource record table includes a register type, a register name, a register bit width, a register number, and a register vector width; the memory mapping table is used for recording the mapping relation between the memory names of all memory resources in the instruction set and the memory resources, each entry of the memory mapping table comprises a memory name and a memory resource, and the memory resources comprise a memory name, a memory starting address, a memory size and a memory granularity.
Further, the instruction binary coding index table is used for recording binary codes of all instructions in the target program in an index sequence, the instruction feature ID index table is used for recording feature IDs of all instructions in the target program in the index sequence, the instruction format coding field data type mapping index table is used for recording instruction format coding field data type mapping of all instructions in the target program in the index sequence, the instruction format coding field data type mapping table is used for recording mapping relation from each field mapping instance to a field data type, and the field data type comprises any one or more of a storage resource name, an offset address, a data length, a message, a register type, a register name, register content and field binary codes.
Further, the program instruction address index table is used for recording program instruction addresses of all instructions in the target program according to an index sequence, and the program instruction parallel execution flag index table is used for recording program instruction parallel execution flags of all instructions in the target program according to the index sequence.
Further, step 6 includes:
step 6.1: acquiring an instruction index value corresponding to a program PC value from the program PC value index table according to the current program PC value;
step 6.2: acquiring a feature ID value of an instruction from the instruction feature ID index table according to the acquired instruction index value;
step 6.3: acquiring the instruction format coding field data type of the instruction from the instruction format coding field data type mapping index table according to the acquired instruction index value;
step 6.4: acquiring an instruction semantic function pointer of an instruction from the instruction semantic function mapping table according to the acquired feature ID value, and executing the instruction semantic function by taking the acquired instruction format coding field data type as a parameter;
step 6.5: acquiring a program instruction parallel execution mark from the program instruction parallel execution mark index table according to the acquired instruction index value, judging according to the value of the program instruction parallel execution mark, increasing the index value if the mark is 1, and skipping to the step 6.2; if the mark is 0, jumping to the step 6.1;
step 6.6: checking an execution queue, and performing write-back operation according to the remaining beat number and the empty operand;
step 6.7: and obtaining a new program PC value, and jumping to the step 6.1 until the processing of all the program PC values is completed.
Further, step 6.6 includes:
checking an execution queue, and performing write-back operation on the instruction with the residual beat number of 0;
checking whether the operation is null or not, and performing the write-back operation for a plurality of times according to the null operation.
An automatic generation device of an instruction set architecture simulator based on model driving comprises a processor and a memory, wherein the memory is used for storing a computer program, and the processor is used for executing the computer program to execute the method.
Compared with the prior art, the invention has the advantages that:
1. according to the invention, through constructing the simulator description model description register, the instruction and the memory, the corresponding mapping table and the resource record table are generated according to each description, then the related index table is generated according to the binary code program of the simulated target program, the related index table of the program instruction is reconstructed according to the instruction binary code index table, and then the instructions are sequentially acquired according to the program PC value index table and then simulated and executed by utilizing each mapping table and each index table, the simulator can be automatically generated based on the simulator description model driving, and the realization efficiency and the reliability of the simulator are effectively improved.
2. The invention is based on the model-driven automatic generation mode, not only can flexibly meet the instruction set architecture design requirements of different numbers of functional units, registers and instruction types, but also can support the dynamic update and expansion of the instruction set architecture design simulation, and when the new instruction needs to be increased or decreased and expanded to cause the dynamic change of the instruction set, the new simulator can be automatically generated again and quickly by only modifying the demand model, thereby greatly improving the efficiency and cost of the simulator in the whole instruction set architecture design process, improving the expandability of the simulator, and obviously shortening the development period of the instruction set architecture design.
3. The invention further constructs instruction description by using the feature ID and the like, decodes according to the feature ID, so that any instruction in the program can be completely decoded once, and decoding is only needed once no matter how many times the instruction is executed.
Drawings
Fig. 1 is a schematic flow chart of an implementation of the automatic generation method of the model-driven instruction set architecture simulator in the present embodiment.
FIG. 2 is a schematic diagram of an example register description of an instruction set architecture employed in a particular application embodiment of the present invention.
FIG. 3 is a schematic diagram of an example instruction description of an instruction set architecture employed in a particular application embodiment of the invention.
FIG. 4 is a schematic diagram of an example memory description of an instruction set architecture employed in a particular application embodiment of the invention.
Fig. 5 is a schematic diagram of an implementation flow of the object simulation process in the present embodiment.
Detailed Description
The invention is further described below in connection with the drawings and the specific preferred embodiments, but the scope of protection of the invention is not limited thereby.
As shown in fig. 1, the steps of the automatic generation method of the model-driven instruction set architecture simulator in this embodiment include:
step 1: according to the instruction set architecture design requirements, a simulator description model required for generating the instruction set architecture simulator is constructed, wherein the simulator description model comprises a register description, an instruction description and a memory description of an instruction set architecture, the register description is used for declaring all register resources contained in an instruction set, the instruction description is used for declaring all instruction resources contained in the instruction set, and the memory description is used for declaring all memory resources accessed by the instruction set instructions.
In this embodiment, the register description specifically includes a list including a plurality of tuples for declaring all register resources included in the instruction set, each tuple including a type, a name, a bit width, a number, and a vector width, where the type specifies a type of register, and there are three types: single registers, one-dimensional registers (scalar registers), and two-dimensional registers (vector registers); the name is used for specifying the name of the register; the bit width is used for specifying the bit width of the register; the number is used to specify the number of groups of registers; the vector width is used to specify the vector width of the register.
In a specific application embodiment, an example of a register description of an instruction set architecture in a simulator description model is given as shown in fig. 2, in which three types of register resource descriptions are shown, the first type being a single register, and the register names being respectively:
the register bit width is 32 bits, and the VST, the VECR, the SVR, the VCR, the SMR, the VLR, the SST, the SFCR1, the SFCR2, the SCR, the SAMR, the STPR, the SECR, the IER, the IFR, the ICR, the IRRL, the ISTPL, the EER, the EFR, the ECR, the ERRL, the ESTPL, the CGCR, the CVCCR, the BRREG, the IRRH, the ISTPH, and the ERRH.
The second type is a one-dimensional register (scalar register), the register names are "R", the number of register sets is 64, and the register bit width is 32 bits, respectively.
The third type is a two-dimensional register (vector register), the register names are "VR", the number of register sets is 64, the register vector width is 16, and the register bit width is 32 bits.
In this embodiment, the instruction description is specifically composed of a list including a plurality of tuples for declaring all instruction resources included in the instruction set, each tuple including a feature ID for identifying to which functional unit the described instruction belongs a specific instruction and a specific instruction format, an instruction name for specifying the instruction name of the described instruction, a function unit name for specifying the function unit name to which the described instruction belongs, an instruction length for specifying the instruction length of the described instruction, and an instruction field sequence for specifying the specific field sequence of the described instruction. The field sequence is specifically composed of a plurality of tuples, each tuple including a field length, a field name, a field attribute, a field mapping instance, and the like.
According to the embodiment, the instruction description is built by using the feature ID and the like, and decoding is carried out according to the feature ID, so that any instruction in a program can be completely decoded once, no matter how many times the instruction is executed, only one time decoding is needed, compared with the traditional simulator which needs to interpret and execute each instruction one by one according to the program execution sequence, the simulation speed can be effectively improved, and especially for a large number of circularly executed sentences, the decoding time can be greatly shortened, and the simulation speed can be improved.
In a specific application embodiment, as shown in fig. 3, an instruction description example of an instruction set architecture in a simulator description model is given, in which an instruction description of one SLDW instruction is shown. The feature ID of the SLDW instruction is 0001, the instruction name is SLDW, the name of the functional unit to which the SLDW instruction belongs is SLDST, and the instruction length is 16; the instruction field sequence includes 6 tuple components: tuple 1 includes a field length of 2, a field name of AR 12_15, a field attribute of register_AR12_15, and a field mapping instance of AR. Tuple 2 includes a field length of 6, a field name of R, a field attribute of register_R, and a field mapping instance of DST. Tuple 3 includes field length 2, field name UCST2, field attribute IMM, field mapping instance SRC1. Tuple 4 includes field length 1, field name IMM1, field attribute IMM, field mapping instance MODE. Tuple 5 includes a field length of 4, a field name of ID, a field attribute of null, and a field map instance of null. Tuple 6 includes a field length of 1, a field name of P, a field attribute of P, and a field mapping instance of null.
In this embodiment, the memory description includes a plurality of tuples for declaring all memory resources accessed by the instruction set instructions, consisting of a list containing a plurality of tuples, each tuple including a memory name, a starting address, a memory size, and a memory granularity. Wherein the memory name specifies the memory name of the described memory; the starting address specifies the starting address of the described memory; memory size specifies the memory size of the described memory; the storage granularity specifies the storage granularity of the described memory.
In a specific application embodiment, as shown in fig. 4, a memory description example of an instruction set architecture in a simulator description model is given, in which two types of memory resource descriptions are shown. The memory names of the first type of memory resources are AM, a starting address 0x20000, a memory size of 1, and a memory granularity MB (total size of 1 MB). The memory name of the second type of memory resource is SM, starting address 0x10000, memory size 64, memory granularity KB (total size 64 KB).
Step 2: generating an instruction length mapping table, an instruction name mapping table, an instruction format coding field sequence mapping table and an instruction semantic function mapping table according to the instruction description in the simulator description model;
in this embodiment, the instruction length mapping table is used to record the mapping relationship between the feature IDs and the instruction lengths of all instructions in the instruction set, and each entry of the mapping table includes the feature IDs and the instruction lengths. The instruction name mapping table is used for recording the mapping relation between the feature IDs of all the instructions in the instruction set and the instruction names of the instructions, and each entry of the mapping table comprises the feature IDs and the instruction names. The instruction format coding field sequence mapping table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the corresponding instruction format coding field sequences, and each entry of the mapping table comprises the feature IDs and the instruction coding field sequences. Each instruction encoding field sequence is made up of a plurality of tuples, each tuple including a field length, a field name, a field attribute, a field mapping instance. The instruction semantic function mapping table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the corresponding instruction semantic functions, and each entry of the mapping table comprises the feature IDs and the instruction semantic function pointers.
Step 3: generating a register resource record table and a memory mapping table according to the register description and the memory description in the simulator description model, wherein the register resource record table is used for recording all register resources contained in an instruction set, and the memory mapping table is used for recording the mapping relation between the memory names of all memory resources in the instruction set and the memory resources;
in this embodiment, the register resource record table is formed by a list including a plurality of tuples for recording all the register resources included in the instruction set, and each tuple in the register resource record table specifically includes a register type, a register name, a register bit width, a register number, and a register vector width. The memory mapping table is used for recording the mapping relation between the memory names of all the memory resources in the instruction set and the memory resources, each entry of the memory mapping table comprises the memory names and the memory resources, and each memory resource specifically comprises the memory names, the memory starting addresses, the memory sizes, the memory granularity and the like.
Step 4: and reading the binary code program of the simulated target program, and generating an instruction binary coding index table, an instruction characteristic ID index table and an instruction format coding field data type mapping index table.
In this embodiment, the instruction binary coding index table is used to record the binary coding of all the instructions in the target program in the index order, the instruction feature ID index table is used to record the feature IDs of all the instructions in the target program in the index order, the instruction format coding field data type mapping index table is used to record the instruction format coding field data type mapping of all the instructions in the target program in the index order, the instruction format coding field data type mapping table is used to record the mapping relation from each field mapping instance to the field data type, and the field data type specifically includes a storage resource name, an offset address, a data length, a message, a register type, a register name, a register content, a field binary coding, and the like.
Step 5: and constructing a program PC value index table, a program instruction address index table and a program instruction parallel execution marking index table of the target program according to the instruction binary coding index table.
In this embodiment, the program PC value index table records the program PC values of all instructions in the target program in the index order, the program instruction address index table is used to record the program instruction addresses of all instructions in the target program in the index order, and the program instruction parallel execution flag index table is used to record the program instruction parallel execution flags of all instructions in the target program in the index order.
Step 6: and sequentially acquiring an instruction index value corresponding to the program PC value according to the current program PC value and the program PC value index table, further acquiring corresponding instruction information, and performing simulation execution on the acquired instruction.
As shown in fig. 5, the specific steps of step 6 in this embodiment include:
step 6.1: acquiring an instruction index value corresponding to the program PC value from a program PC value index table according to the current program PC value;
step 6.2: acquiring a feature ID value of the instruction from the instruction feature ID index table according to the acquired instruction index value;
step 6.3: acquiring the instruction format coding field data type of the instruction from the instruction format coding field data type mapping index table according to the acquired instruction index value;
step 6.4: acquiring an instruction semantic function pointer of an instruction from an instruction semantic function mapping table according to the acquired feature ID value, and executing the instruction semantic function by taking the acquired instruction format coding field data type as a parameter;
step 6.5: acquiring a program instruction parallel execution mark from a program instruction parallel execution mark index table according to the acquired instruction index value, judging according to the value of the program instruction parallel execution mark, increasing the index value if the mark is 1, and jumping to the step 6.2; if the mark is 0, jumping to the step 6.1;
step 6.6: checking an execution queue, and performing write-back operation according to the remaining beat number and the empty operand;
step 6.7: and obtaining a new program PC value, and jumping to the step 6.1 until the processing of all the program PC values is completed.
In this embodiment, if the flag is 1 in step 6.5, the index value is increased by 1, and then step 6.2 is skipped.
In this embodiment, step 6.6 specifically includes:
checking an execution queue, and performing write-back operation on the instruction with the residual beat number of 0;
checking whether the operation is null or not, and performing the write-back operation for a plurality of times according to the null operation.
Step 7: and after the simulation of all the instructions is completed, outputting a simulation result.
According to the method, the simulator description model description register, the instruction and the memory are constructed, the corresponding mapping table and the resource record table are generated according to the descriptions, then the related index table is generated according to the binary code program of the simulated target program, the related index table of the program instruction is reconstructed according to the instruction binary code index table, then the instructions are sequentially acquired according to the program PC value index table, and then simulation execution is carried out by utilizing the mapping tables and the index table, so that the simulator can be automatically generated based on simulator description model driving, and the realization efficiency and the reliability of the simulator are effectively improved.
Based on the model-driven automatic generation mode, the method and the device can flexibly meet the instruction set architecture design requirements of different numbers of functional units, registers and instruction types, automatically generate corresponding instruction set architecture simulators, support dynamic update and expansion of the instruction set architecture design simulation, and can automatically generate new simulators again and rapidly only by modifying a demand model when new instructions need to be increased, decreased and expanded to cause dynamic changes of the instruction set, so that the efficiency and cost of the realization of the needed simulators in the whole instruction set architecture design process can be greatly improved, and the development period of the instruction set architecture design is remarkably shortened.
The embodiment also provides an automatic generation device of the instruction set architecture simulator based on model driving, which comprises a processor and a memory, wherein the memory is used for storing a computer program, and the processor is used for executing the computer program to execute the method.
It will be understood that the method in this embodiment may be performed by a single device, for example, a computer or a server, or may be implemented by a plurality of devices in a distributed scenario, where one device of the plurality of devices may perform only one or more steps in the method in this embodiment, and the plurality of devices interact to implement the method. The processor may be implemented as a general-purpose CPU, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, etc. for executing the relevant program to implement the methods described in this embodiment. The memory may be implemented in the form of read-only memory ROM, random access memory RAM, static storage devices, dynamic storage devices, etc. The memory may store an operating system and other application programs, and when the methods of the present embodiments are implemented in software or firmware, the associated program code is stored in the memory and invoked for execution by the processor.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. While the invention has been described with reference to preferred embodiments, it is not intended to be limiting. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention shall fall within the scope of the technical solution of the present invention.
Claims (10)
1. An automatic generation method of an instruction set architecture simulator based on model driving is characterized by comprising the following steps:
step 1: constructing a simulator description model required by generating an instruction set architecture simulator according to instruction set architecture design requirements, wherein the simulator description model comprises a register description, an instruction description and a memory description of an instruction set architecture;
step 2: generating an instruction length mapping table, an instruction name mapping table, an instruction format coding field sequence mapping table and an instruction semantic function mapping table according to the instruction description in the simulator description model;
step 3: generating a register resource record table and a memory mapping table according to the register description and the memory description in the simulator description model, wherein the register resource record table is used for recording all register resources contained in an instruction set, and the memory mapping table is used for recording the mapping relation between the memory names of all memory resources in the instruction set and the memory resources thereof;
step 4: reading a binary code program of the simulated target program, and generating an instruction binary coding index table, an instruction feature ID index table and an instruction format coding field data type mapping index table;
step 5: constructing a program PC value index table, a program instruction address index table and a program instruction parallel execution marking index table of the target program according to the instruction binary coding index table, wherein the program PC value index table records program PC values of all instructions in the target program according to an index sequence;
step 6: according to the current program PC value and the program PC value index table, sequentially acquiring an instruction index value corresponding to the program PC value, further acquiring corresponding instruction information, and performing simulation execution on the acquired instruction;
step 7: and after the simulation of all the instructions is completed, outputting a simulation result.
2. The model driven based instruction set architecture simulator auto-generation method of claim 1, wherein the register descriptions are used to declare all register resources contained in an instruction set, the instruction descriptions are used to declare all instruction resources contained in an instruction set, and the memory descriptions are used to declare all memory resources accessed by an instruction set instruction.
3. The model-driven based instruction set architecture simulator auto-generation method of claim 2, wherein the register description comprises a plurality of tuples, each tuple comprising a type, a name, a bit width, a number, and a vector width, the instruction description comprises a plurality of tuples, each tuple comprising a feature ID, an instruction name, a function unit name, an instruction length, and an instruction field sequence, the feature ID being used to identify to which function unit the described instruction belongs a specific instruction and a specific instruction format, the instruction field sequence being used to specify a specific field sequence composition of the described instruction, the instruction field sequence comprising a field length, a field name, a field attribute, and a field mapping instance; the memory description includes a plurality of tuples, each tuple including a memory name, a starting address, a memory size, and a memory granularity.
4. The automatic generation method of the model-driven instruction set architecture simulator according to claim 1, wherein the instruction length mapping table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the instruction lengths thereof, the instruction name mapping table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the instruction names thereof, the instruction format coding field sequence table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the corresponding instruction format coding field sequences, and each tuple in the instruction coding field sequences comprises a field length, a field name, a field attribute and a field mapping example, and the instruction semantic function mapping table is used for recording the mapping relation between the feature IDs of all instructions in the instruction set and the corresponding instruction semantic functions.
5. The model driven based instruction set architecture simulator auto-generation method of claim 1, wherein the register resource record table is used for recording all register resources contained in an instruction set, and each tuple in the register resource record table comprises a register type, a register name, a register bit width, a register number and a register vector width; the memory mapping table is used for recording the mapping relation between the memory names of all memory resources in the instruction set and the memory resources, each entry of the memory mapping table comprises a memory name and a memory resource, and the memory resources comprise a memory name, a memory starting address, a memory size and a memory granularity.
6. The automatic generation method of a model-driven instruction set architecture simulator according to any one of claims 1 to 5, wherein the instruction binary-coded index table is used for recording binary codes of all instructions in the target program in index order, the instruction feature ID index table is used for recording feature IDs of all instructions in the target program in index order, the instruction format coded field data type mapping index table is used for recording instruction format coded field data type mapping of all instructions in the target program in index order, and the instruction format coded field data type mapping table is used for recording mapping relation of each field mapping instance to a field data type, and the field data type comprises any one or more of a storage resource name, an offset address, a data length, a message, a register type, a register name, a register content and a field binary code.
7. The automatic generation method of a model-driven instruction set architecture simulator according to any one of claims 1 to 5, wherein the program instruction address index table is used for recording program instruction addresses of all instructions in the target program in an index order, and the program instruction parallel execution flag index table is used for recording program instruction parallel execution flags of all instructions in the target program in the index order.
8. The automatic generation method of a model-driven instruction set architecture simulator according to any one of claims 1 to 5, wherein step 6 comprises:
step 6.1: acquiring an instruction index value corresponding to a program PC value from the program PC value index table according to the current program PC value;
step 6.2: acquiring a feature ID value of an instruction from the instruction feature ID index table according to the acquired instruction index value;
step 6.3: acquiring the instruction format coding field data type of the instruction from the instruction format coding field data type mapping index table according to the acquired instruction index value;
step 6.4: acquiring an instruction semantic function pointer of an instruction from the instruction semantic function mapping table according to the acquired feature ID value, and executing the instruction semantic function by taking the acquired instruction format coding field data type as a parameter;
step 6.5: acquiring a program instruction parallel execution mark from the program instruction parallel execution mark index table according to the acquired instruction index value, judging according to the value of the program instruction parallel execution mark, increasing the index value if the mark is 1, and skipping to the step 6.2; if the mark is 0, jumping to the step 6.1;
step 6.6: checking an execution queue, and performing write-back operation according to the remaining beat number and the empty operand;
step 6.7: and obtaining a new program PC value, and jumping to the step 6.1 until the processing of all the program PC values is completed.
9. The model-driven instruction set architecture simulator auto-generation method of claim 8, wherein step 6.6 comprises:
checking an execution queue, and performing write-back operation on the instruction with the residual beat number of 0;
checking whether the operation is null or not, and performing the write-back operation for a plurality of times according to the null operation.
10. An automatic generation device of an instruction set architecture simulator based on model driving, comprising a processor and a memory for storing a computer program, characterized in that the processor is adapted to execute the computer program to perform the method according to any of claims 1-9.
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