JP2011054041A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for efficiently determining the order of setting circuit information on a programmable logic circuit, with respect to an image processor for switching circuit configurations of the programmable logic circuit in order to achieve an image processing function. <P>SOLUTION: For a plurality of intermediate image processes constituting an image processing function to be executed, a route list creation process and an execution order list creation process are performed, to determine the order of executing intermediate image processing according to an order determined to be executable, and it is registered to the list of orders of execution together with buffer information (information on a data read position, a data write position, or the like) when determined. In executing the image processing function, circuit information on the intermediate image process and the buffer information are set to a programmable integrated circuit 2 in the order registered to the list of orders of execution, to repeatedly execute the intermediate image process until the execution order list becomes empty. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus.

In an image processing apparatus such as a copying machine, an image processing function is realized by a programmable logic circuit. In recent years, image processing functions have become complex and have become more complex to a scale that cannot be realized with a single programmable logic circuit.
As one solution to this problem, a technique has been proposed in which the circuit configuration of a programmable logic circuit is reconfigured during processing so that different logic circuits are realized at different times. According to this technique, even when the circuit scale of the programmable logic circuit is limited, various processes can be performed at a relatively high speed.

  As an invention relating to the reconfiguration of such a programmable logic circuit, for example, in Patent Document 1, circuit information holding means for holding circuit information and order used in advance, and reconfiguration of the programmable logic circuit from given processing data. The first circuit information to be used is specified, and the programmable logic circuit is reconfigured by the circuit information in the order stored in the circuit information holding means from the specified circuit information to configure a processing circuit. An invention of an information processing system having interface means for processing the processing data has been proposed.

JP 2001-069933 A

  In the method of switching the circuit configuration of the programmable logic circuit in accordance with a predetermined setting order, a plurality of intermediate image processes constituting the image processing function are connected in series, or the processing unit is one page or one line unit. In the case of simple image processing functions, it is easy for the operator to determine the setting order in a fixed manner. However, in recent years, the complexity of image processing functions (for example, intermediate image processing has been complicatedly connected and processed). With the unit being different for each intermediate image processing, the number of times of processing changes depending on the content of the document, the size of the document, etc.), it has become difficult to determine the setting order.

  The present invention relates to an image processing apparatus that switches a circuit configuration of a programmable logic circuit in order to realize an image processing function, and proposes a technique capable of efficiently determining a setting order of circuit information for the programmable logic circuit. It was made for the purpose.

  The first aspect of the present invention is a storage means for storing circuit information for each image processing set in the programmable logic circuit, and a plurality of image processing scheduled to be executed, in a reading unit corresponding to the image processing to be determined. Data reading position in the preceding buffer area when it is determined that the image processing can be executed when data can be read from the buffer area and data can be written in the subsequent buffer area in a writing unit corresponding to the image processing And changing the data writing position of the buffer area in the subsequent stage based on the reading unit and the writing unit to make the image processing a determination target again, while determining that the image processing cannot be executed in other cases. A determination unit that repeatedly performs a determination process for switching another image process to a determination target and determines an execution order of the image processes in an order determined to be executable; Setting means for setting the circuit information of the corresponding image processing stored in the storage means in the programmable logic circuit in accordance with the execution order of the image processing determined by the determination means in order to execute a number of image processing; An image processing apparatus comprising:

  According to a second aspect of the present invention, in the first aspect of the present invention, there is provided ordering means for ordering a plurality of image processes to be executed while maintaining the order of the image processes, and the determining means is ordered by the ordering means. The image processing to be determined is switched in the order according to the result.

According to the first aspect of the present invention, based on the prediction of the usage status of the buffer area used in image processing,
The setting order of circuit information for the programmable logic circuit can be determined.
According to the second aspect of the present invention, the order of setting circuit information can be determined efficiently.

It is a figure which illustrates the functional block of the image processing apparatus which concerns on one Embodiment of this invention. It is a figure which illustrates the image processing function performed by the image processing apparatus which concerns on one Embodiment of this invention. It is a figure which illustrates the execution order list produced | generated by the image processing apparatus which concerns on one Embodiment of this invention. It is a figure explaining operation | movement at the time of execution of the image processing function by the image processing apparatus which concerns on one Embodiment of this invention. It is a figure which illustrates the outline | summary of the processing flow by the image processing apparatus which concerns on one Embodiment of this invention. It is a figure which illustrates the image processing function performed by the image processing apparatus which concerns on one Embodiment of this invention. It is a figure explaining the production | generation of the cyclic | annular route list by the image processing apparatus which concerns on one Embodiment of this invention. It is a figure explaining the production | generation of the execution order list | wrist by the image processing apparatus which concerns on one Embodiment of this invention. It is a figure explaining the production | generation of the execution order list | wrist by the image processing apparatus which concerns on one Embodiment of this invention. It is a figure explaining the production | generation of the execution order list | wrist by the image processing apparatus which concerns on one Embodiment of this invention.

An embodiment of the present invention will be described with reference to the drawings.
FIG. 1 illustrates functional blocks of an image processing apparatus according to an embodiment of the present invention.
In the image processing apparatus of this example, other devices (for example, a display device such as a liquid crystal display used for display output of various information, an input device such as a touch panel and operation keys used for an input operation by an operator, and image data) An input / output IF1 that is an interface for performing data input / output with an image forming apparatus that forms an output image and records the output image on a recording medium such as a sheet), and a plurality of intermediate image processes constituting an image processing function Circuit information is set in order, a programmable integrated circuit (programmable logic circuit) 2 that realizes the image processing function, a memory 3 that stores various data related to the image processing function, and various processes related to setting circuit information for the programmable integrated circuit 2 The functional units such as the CPU 4 that executes are connected via the bus 5.

An outline of processing by the image processing apparatus of this example will be described with reference to FIGS.
FIG. 3 illustrates an image processing function executed by the image processing apparatus of this example.
In FIG. 3, a circle indicates each intermediate image process F (Function) constituting the image processing function, and a square mark indicates a buffer B (Buffer) in which image data D as a processing target or a process result of the intermediate image process F is stored. The arrow indicates the input / output stream S (Stream) of the image data D between the buffer B and the intermediate image processing F. That is, the flow from the start to the end of the image processing function is expressed by connecting the intermediate image processing F and the buffer B with the stream S to represent the work order and the dependency. Note that what is constituted by the intermediate image processing F, the buffer B, and the stream S is referred to as Pipeline.

  The image processing function shown in FIG. 3 has two intermediate image processes F of monochrome conversion processing and reduction processing and three buffers (page buffers in this example), and the image data D1 input as a processing target The image data D1 stored in the first buffer B1 is subjected to monochrome conversion processing by the first intermediate image processing F1 and stored in the second buffer B2, and stored in the second buffer B2. The stored image data D2 after the monochrome conversion processing is reduced by the second intermediate image processing F2, stored in the third buffer B3, and after the monochrome conversion and reduction processing stored in the third buffer B3. The image data D3 is output as a processing result.

  In the image processing apparatus of this example, before executing the image processing function, an execution order list (circuit information setting order list) representing the execution order of each intermediate image processing F constituting the image processing function as illustrated in FIG. ) And the image processing function is realized by switching the circuit configuration of the programmable integrated circuit 2 in accordance with the execution order list when the image processing function is executed.

  That is, as shown in FIG. 5, (1) monochrome conversion circuit information 31 representing a circuit configuration for realizing the monochrome conversion processing which is the first (first) intermediate image processing F in the execution order list is stored in the circuit of the memory 3. Reading from the information storage area and setting it in the programmable integrated circuit 2, (2) operating the programmable integrated circuit 2 with the set circuit configuration to execute monochrome conversion processing, and (3) the next (second) in the execution order list The reduced circuit information 32 representing the circuit configuration for realizing the reduction processing that is the intermediate image processing F is read from the circuit information storage area of the memory 3 and set in the programmable integrated circuit 2, and (4) programmable integration with the set circuit configuration. The circuit 2 is operated to execute the reduction process.

FIG. 2 illustrates an outline of a processing flow by the image processing apparatus of this example.
In the image processing apparatus according to this example, before executing the image processing function, first, a cyclic route list is created for a plurality of intermediate image processes constituting the image processing function (step S1), and each intermediate image is generated according to the cyclic route list. A process execution order list is created (step S2).
When executing the image processing function, the circuit information of each intermediate image processing stored in the memory 3 is set in the programmable integrated circuit 2 according to the execution order list (step S3), and the programmable integrated circuit 2 is operated to operate the intermediate image. The process is repeated (step S4) until all circuit information in the execution order list is executed (step S5).
In this example, each intermediate image processing of the image processing function, components such as a buffer used for the processing, and dependency thereof are determined based on information such as processing target images and processing contents, and the like. Based on the image processing configuration information indicating the determined content, the above processing (steps S1 to S5) is performed. However, the image processing configuration information is received from the user, and based on the received image processing configuration information. Thus, the above processing may be performed.

First, creation of a cyclic route list will be described.
The cyclic route list is generated by rearranging the intermediate image processes in Pipeline constituting the image processing function in the order in which the image data flows. That is, the cyclic route list is an order that maintains the order of each intermediate image process and is ordered.
In this example, with the intermediate image processing F as a base point, priority is determined for all intermediate image processing so that the intermediate image processing in the previous process is 1 or more and the intermediate image processing in the subsequent process is 1 or less. To do. Specifically, in the two steps of searching for the intermediate image processing of the previous step from the intermediate image processing serving as the base point and searching for the intermediate image processing of the subsequent step from the intermediate image processing serving as the base point, Priority of intermediate image processing ”>“ Priority of intermediate image processing of base point ”>“ Priority of intermediate image processing of subsequent process ”is obtained, and each intermediate image processing F has a high priority. It registers in the cyclic route list in order.

With reference to the image processing function illustrated in FIG. 6, a description will be given of a process for determining and ordering priority for each intermediate image process.
In FIG. 6, six intermediate image processes F (A) to F (F) indicated by circles, nine buffers B (1) to B (9) indicated by square marks, and 16 intermediate image processes indicated by arrows. Pipeline is composed of the input / output streams Sr (1) to Sr (8) and Sw (1) to Sw (8).
Each of the buffers B (1) to B (9) stores a page buffer (PageBuffer) for storing image data in units of one page (that is, stores all of the image data), and image data in units of N lines (N is a value for N). In FIG. 6, the page buffer is a simple square mark, and the band buffer is a double-line square mark. It is represented by That is, the image processing function of this example includes page buffers B (1), B (5), B (6), B (8), B (9) and band buffers B (2), B (3), B (4), B (7).

In each of the input / output streams Sr (1) to Sr (8) and Sw (1) to Sw (8), Sr (1) to Sr (8) are data flows from the buffer B to the intermediate image processing F. And Sw (1) to Sw (8) are output streams (WriteStream) indicating the flow of data from the intermediate image processing F to the buffer B.
In FIG. 6, the unit of data input / output (reading unit and writing unit) in the input / output stream is appended to each input / output stream. For example, in the input stream Sr (1), the page buffer B Image data is read in units of one line from (1) to the intermediate image processing F (A). In the output stream Sw (1), images are output in units of two lines from the intermediate image processing F (A) to the band buffer B (2). Data is written.

In this example, the process for determining and ordering the priority of each intermediate image process is as follows. First, any one of the intermediate image processes is selected as a base point, and the intermediate image process before the base point is +1 or more and after the base point. Priorities of all related intermediate image processes are calculated so that the intermediate image process of the process is −1 or less.
The priority is calculated in two steps: (1) Pre-process tour and (2) Post-process tour.

(1) Pre-process patrol For intermediate image processing at the base point, the intermediate image processing of the previous step is specified from the target, the priority is calculated, and the intermediate image processing of the previous step is switched to the next target Then, the process of specifying the intermediate image process of the previous process and calculating the priority thereof is repeated until the intermediate image process of the previous process is eliminated. At this time, if “priority of intermediate image processing in the previous step has not been determined” or “priority of intermediate image processing in the previous step ≦ priority of target intermediate image processing”, intermediate image processing in the previous step Priority = Priority of target intermediate image processing + 1.

(2) Post-process patrol For intermediate image processing at the base point, the intermediate image processing of the next post-process is specified from the target, its priority is calculated, and the intermediate image processing of the post-process is switched to the next target Then, the process of specifying the intermediate image process in the next subsequent process and calculating the priority thereof is repeated until there is no intermediate image process in the subsequent process. At this time, if “intermediate image processing priority in the post-process is not determined” or “priority of intermediate image processing in the post-process ≧ priority of target intermediate image processing”, intermediate image processing in the post-process Priority = Priority of target intermediate image processing−1.
Then, after calculating the priority of all intermediate image processing by (1) pre-process tour and (2) post-process tour, each intermediate image process is registered in the cyclic order list in descending order of priority.

FIG. 7 illustrates a process of calculating the priority for each intermediate image process of the image processing function represented by Pipeline in FIG. Note that the circles in FIG. 7 correspond to the circles in FIG. 6 (intermediate image processing F (A) to F (F)). Further, the square mark (target Buffer field) in FIG. 7 corresponds to the square mark (buffers B (1) to B (9)) in FIG. 6, and specifies the intermediate image processing in the previous process or the subsequent process. It shows the buffer used for.
In FIG. 7, after the priority of all intermediate image processing F (A) to F (F) is initialized to 0 (processing No. 1), the intermediate image processing at the base point is set to F (D), and the preceding process For all the intermediate image processes F (A) to F (C) located at the position (1), the priority is calculated by performing the process in the previous process (process Nos. 2 to 8) and located in the subsequent process. For all the intermediate image processes F (E) and F (F), the priority is calculated by performing the above-mentioned (2) post-process cyclic processing (process Nos. 9 to 12).
As a result, the priorities of the intermediate image processes F (A) to F (F) are +3, +2, +1, 0, −1, and −1, respectively, and the intermediate image processes F (A) to F (F). Are registered in the cyclic order list in descending order of priority. Note that the order of registration in the cyclic order list when the priorities have the same value may be arbitrary or may be determined according to other conditions.

Next, creation of an execution order list will be described.
For each buffer, parameters BufferSizeX (size in the X direction) and BufferSizeY (size in the Y direction) representing the size of the buffer area are set, and parameters BufferAddress and the like representing the head address of the buffer area are set. And In addition, for each input / output stream, parameters SwathSizeX (X direction size) and SwathSizeY (Y direction size) representing the size of data (hereinafter referred to as Swath) necessary for one processing unit by the corresponding intermediate image processing are set. It is assumed that parameters ReadPosition and WritePosition indicating the position where image data is read next and the position where data is written are set for each buffer.

In this example, the following (Process 1) to (Process 8) are performed to create an execution order list.
(Process 1) Initialize ReadPosition and WritePosition of each buffer. Specifically, as illustrated in FIG. 8A, the top address of the buffer area is set as the initial value of ReadPosition and WritePosition. In the case where there is no intermediate image processing F that is a page buffer and the image data writing source, such as a buffer located at the beginning of Pipeline (for example, buffer B (1) in FIG. 6), FIG. As illustrated in b), a position obtained by adding WritePosition by an amount corresponding to ImageSizeY (Y-direction size of image data to be processed) is set as an initial value.

(Process 2) The following (Process 3) to (Process 8) are repeated in accordance with the order of intermediate image processing registered in the cyclic order list.
(Process 3) The first intermediate image process in the cyclic order list is targeted.

(Process 4) Whether or not the target intermediate image process is executable is determined in consideration of Swath. If it is determined that the target intermediate image process is executable, the process proceeds to (Process 5) and executed. If it is determined that the state is not possible, the next intermediate image processing in the cyclic order list is performed again (processing 4).
Whether or not the target intermediate image processing is executable is determined based on the following [Condition 4-1] and [Condition 4-2].
[Condition 4-1] is a determination condition for the input stream, and determines whether image data can be read from the data reading source buffer. Specifically, if WritePosition <ReadPosition + ReadSwathSize (reading-side SwathSize (reading unit)), it is determined that execution is impossible. That is, as illustrated in FIG. 9A, it is determined that execution is not possible when WritePosition is positioned before the position where ReadSwatSize is added to ReadPosition (end position of the data to be read).
[Condition 4-2] is a determination condition for the output stream. Whether image data can be written to the data write destination buffer (whether unprocessed image data remains at the data write destination position). ). More specifically, it is determined that execution is not possible when WritePosition + WriteSwapSize (Writing SwahSize (Writing Unit)) − ReadPosition> BufferSizeY. That is, as illustrated in FIG. 9B, when a ring buffer in which the next writing destination returns to the top after writing at the end of the buffer area is used as a band buffer, a value obtained by subtracting ReadPosition from WritePosition (not yet) If BufferSizeY is smaller than the value obtained by adding WriteSwizeSize to the processing image data amount (the total value of the unprocessed image data amount and the write data amount), it is determined that execution is impossible.

  (Process 5) Register the target intermediate image process in the execution order list. For the intermediate image processing, the address of the data reading position in the reading source buffer is calculated by (ReadPosition% BufferSizeY) × BufferSizeX + BufferAddress, and the address of the data writing position in the writing destination buffer is (WritePosition% BufferSizeY) × It is calculated by BufferSizeX + BufferAddress, and these pieces of address information are registered in the execution order list in association with the target intermediate image processing.

  (Processing 6) The ReadPosition for the input stream for the target intermediate image process is added by SwatSizeY, and the WritePosition for the output stream is added by SwathSizeY.

(Processing 7) It is determined whether or not the target intermediate image processing has been completed for the entire processing target image data. If it is determined that the processing has been completed, the target intermediate image processing is determined to be a cyclic path list. Delete from.
The determination as to whether or not the target intermediate image processing has been completed for the entire processing target image data is made based on the following [Condition 7-1] and [Condition 7-2].
[Condition 7-1] is a determination condition for the input stream, and determines whether all of the image data has been read from the data read source buffer. That is, as illustrated in FIG. 10A, when ReadPosition exceeds ImageSizeY, it is determined that reading has been completed.
[Condition 7-2] is a determination condition for the output stream, and determines whether all of the image data has been written in the data write destination buffer. That is, as illustrated in FIG. 10A, when WritePosition exceeds ImageSizeY, it is determined that writing has been completed.

  (Processing 8) It is determined whether or not the cyclic route list is empty. If it is determined that it is empty, the execution order list creation process is terminated. If it is determined that it is not empty, the process proceeds to (Processing 3). Return.

As described above, in the image processing apparatus of the present example, before executing the image processing function, the cyclic route list creation process and the execution order list creation process for the plurality of intermediate image processes constituting the image processing function are performed. Yes.
In the cyclic route list creation process, an ordered cyclic route list is created while maintaining the context of each intermediate image process.
In the execution order list creation processing, the following processing is performed while switching the intermediate image processing to be determined in the order according to the cyclic route list. When data can be read from the preceding buffer area in the reading unit corresponding to the intermediate image processing to be determined and can be written into the subsequent buffer area in the writing unit corresponding to the intermediate image processing, the intermediate It is determined that the image processing can be executed, and the intermediate image processing is performed by changing the data reading position of the preceding buffer area and the data writing position of the subsequent buffer area based on the reading unit and the writing unit. It is determined again. On the other hand, in other cases, it is determined that the intermediate image processing cannot be executed, and the other intermediate image processing is switched to a determination target. These processes are repeated until it is determined that all the intermediate image processes have been executed, and the execution order of the intermediate image processes is determined according to the order determined to be executable, and the buffer information (data read out) at the time of the determination is determined. Address information such as position and data writing position) and the execution order list. That is, in the execution order list creation processing, whether or not intermediate image processing is possible is determined while calculating changes in buffer information accompanying the progress of intermediate image processing, and the execution order of intermediate image processing is determined.
When executing the image processing function, the execution order list is empty to set the circuit information and buffer information of the intermediate image processing in the programmable integrated circuit 2 in the order registered in the execution order list and execute the intermediate image processing. Repeat until.

  Note that in the image processing apparatus of this example, a program relating to functions such as the above-described cyclic route list creation processing and execution order list creation processing is held in the memory 3, and the cyclic route list is executed by the CPU 4 executing this program. Functions such as creation processing and execution order list creation processing are realized on the computer of the image processing apparatus. However, the present invention is not limited to such an aspect realized by the software configuration, and each function is implemented by a dedicated hardware module. It may be realized.

In addition, the image processing apparatus in the above description is realized by a single computer, but the image processing apparatus may be realized by distributing each functional unit to a plurality of computers.
In addition, the program in the above description is set in the computer of the image processing apparatus by, for example, a format read from an external storage medium such as a CD-ROM storing the program or a format received via a communication line. .
Further, the configuration, processing contents, processing procedures, and the like of the image processing apparatus described so far are merely examples, and the present invention is not limited to the above description contents.

  1: Input / output I / F, 2: Programmable integrated circuit, 3: Memory, 4: CPU, 5: Bus

Claims (2)

Storage means for storing circuit information for each image processing set in the programmable logic circuit;
For multiple image processing scheduled to be executed, data can be read from the previous buffer area in the reading unit corresponding to the image processing to be determined, and data can be written to the subsequent buffer area in the writing unit corresponding to the image processing. In this case, it is determined that the image processing can be executed, and the data reading position of the preceding buffer area and the data writing position of the succeeding buffer area are changed based on the reading unit and the writing unit. While the process is set as the determination target again, it is determined that the image processing cannot be executed in other cases, and the determination process for switching the other image processing to the determination target is repeatedly performed, and the images are determined in the order determined to be executable. A determination means for determining the execution order of the processes;
Setting to set the circuit information of the corresponding image processing stored in the storage means in the programmable logic circuit in accordance with the execution order of the image processing determined by the determination means in order to execute a plurality of image processing scheduled to be executed Means,
An image processing apparatus comprising: An ordering unit that orders a plurality of image processes scheduled to be executed while maintaining the context of each image process,
The determination unit switches the image processing to be determined in an order according to the ordering result by the ordering unit.
The image processing apparatus according to claim 1.

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