JP5016807B2 - Data processing system - Google Patents

Description

  The present invention relates to a data processing system that changes a programmable logic circuit in accordance with a use.

  With the progress of miniaturization of semiconductors, the capability of processors has increased, and it has become possible to perform processing that has been conventionally performed by hardware using software. Utilizing the performance of this processor, many processes are being made into software. Rather than creating software for each specific application, a library is created for each basic unit, and functions have been realized as combinations of libraries for each application. For example, in the image processing field, different processes are required for each application, and therefore, a method of promoting software library formation and generating necessary data by combining libraries has become mainstream.

However, a general-purpose processor can support only the least common multiple function in relation to cost, and most other processes are still at a level where a plurality of processes are combined and executed. For example, a multimedia-related command is SIMD (Single
Since Instruction / Multiple Data) processing also remains at the level of product-sum operation, image processing and data processing for executing a plurality of these operations take a form in which SIMD is executed a plurality of times by software. For MPEG2 decoding and MP3 codes, real-time performance can be ensured by this processing, but functions specialized for applications such as image edge processing and specific frequency extraction cannot be secured because they are a plurality of processes.

  Therefore, the speeding up of the specific processing has been realized by shortening the processing time by using dedicated hardware. For this hardware, G / A and CBIC were created according to the application, but on the contrary, the miniaturization of the semiconductor increased the development cost, and if there was no usage of millions of units / month or more, it was developed. It has become a situation where expenses cannot be recovered. Therefore, programmable logic circuits whose circuit scale and operating frequency have approached G / A and CBIC have come to be widely used as alternatives. Patent Document 1 discloses a technique for determining an execution module in consideration of software and hardware processing time, memory consumption, and FPGA reconfiguration time.

JP 2000-252814 A

  Many of the necessary data processing is often determined in the order of a plurality of algorithms. For example, in remote operation in an industrial system, image compression is performed because it is necessary to acquire an image on the remote operation side. However, in this image compression, the procedure for encoding is performed after discrete cosine transform (DCT). , A combination of a DCT algorithm and an encoding algorithm. Since the processing (processing procedure) performed by such a combination of algorithms varies depending on the user, the programmable logic circuit is not as flexible as software, but a programmable logic circuit should be created for each user. However, since it is not possible to cope with it, a programmable logic circuit that supports only the function of the least common multiple like the processor is created.

  In addition, the data processing part built in the apparatus may change if the target is changed, and the programmable logic circuit itself needs to be redesigned.

  An object of the present invention is to realize a system for freely changing a programmable logic circuit according to data processing and providing software for the same in a data processing apparatus equipped with a programmable logic circuit. It is.

  The present invention proposes a data processing system that generates a software module and a hardware module from information including a processing procedure of input data and executes each module.

  Examples of the effects of the present invention include the following.

  First, when the processing content of the data processing device changes on the user side, the hardware module is input according to the scale of the programmable logic circuit that the user has by inputting new processing content on the host side using a terminal. It is possible to generate and download software modules. By using this system, it is possible to realize optimum data processing for new processing contents.

  Next, in the control system as an example of the present invention, the data processing apparatus has the function of a terminal, so that the input to the host can be realized only by the data processing apparatus.

  Next, a control system as another example of the present invention has a function of generating software modules and hardware modules on the user side, and has a software library and a hardware library in a server connected to a network, for example, a host. By having it on the user side, further optimization of software modules and hardware modules can be realized.

  The control system which is still another example of the present invention can realize generation of a software module and a hardware module in conjunction with the data processing device by the data processing device having a host function.

  The control system, which is still another example of the present invention, can realize an optimal combination that satisfies the constraint conditions when generating the software module and the hardware module.

  In a data processing terminal equipped with a programmable logic circuit, the hardware library and software library and the data processing procedure, processing time constraints, and data input by the user for the purpose of changing the programmable logic circuit by the user when the processing contents are changed Easily realized from the information of the scale of the programmable logic circuit that the processor has

  Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

  As shown in FIG. 1, a data processing apparatus 101, a terminal 102, a host 103, and a network 104 connecting them are configured.

  As shown in FIG. 2, the data processing apparatus includes a processor 201, a communication interface 202, a programmable logic circuit 203, and a storage device 204.

  Next, a flow of a series of processes will be described with reference to FIG. When the user inputs a data processing procedure, processing time constraints, and the scale of a programmable logic circuit included in the data processing apparatus using the terminal 103, the data is transferred to the host (301). On the host side, a software module / hardware module 303 is generated based on the software library 501 and the hardware library 502 shown in FIG. 5 according to the processing shown in FIG. The software library 501 contains processing time data 503 and processing software 504, and the hardware library 502 contains processing time data 505, processing drivers 506 corresponding to processing, and processing hardware 507. Based on the information of the processing time data 503 and the processing time data 505, the data amount (the size of the image) is also input as information to the processing time constraint and the programmable logic circuit scale that are input, if necessary. From this, a hardware module / software module 303 is generated.

This procedure will be described with reference to FIG. 6 showing the defect extraction procedure. Defect extraction is a common technique used in inspection equipment for industrial applications. In this case, a noise removal function 601, an image alignment function 602, a comparison function 603, and a feature point extraction function 604 are input. After that, the noise removal function 601 is a smoothing process 605 and edge extraction process 606, the two-image registration function 602 is a registration process 607, the comparison function 63 is a subtraction process 608, and the feature point extraction function 604 is a binarization process. It is automatically disassembled to 609. After being decomposed into processing contents, the software library 501 and the hardware library 502 are searched, and the corresponding processing library is referred to. At this time, the processing time 505 and the processing time 506 are included in the library of the corresponding processing, and if necessary, the entire processing time is recalculated from the input data amount, and the input processing time constraint From the scale of the programmable logic circuit, software processing or hardware processing is selected for each processing. The software processing and hardware processing selected as described above are combined for each software and hardware to generate a software module / hardware module 303. When the processing time constraint is severe, for example, as shown in FIG. 7, the smoothing process 701, the subtraction process 704, the feature point extraction process 705 is a hardware process, the edge extraction process 702, and the alignment process 703 are software processes. Increase hardware processing and achieve time constraints. On the other hand, when the processing time constraint is sufficient or the hardware logical scale is small, for example, as shown in FIG. 8, the smoothing process 801 is a hardware process, and the edge extraction process 802, the alignment process 803, and the subtraction process The 804 and binarization processing 805 is software processing, and logic to be hardware is reduced. If the processing time is not in time, it is necessary to secure the necessary processing time by increasing the programmable logic circuit scale or simplifying the processing procedure.

  The software and hardware generated in this way are transferred to the data processing apparatus 101 used by the user via the network 104 in FIG.

  As described above, according to the present invention, it is possible to change the data processing contents according to each user. Once the software / hardware is created by the procedure of the present invention, the data processing apparatus can perform the necessary processing. The procedure can be executed.

  Next, a third embodiment of the present invention will be described with reference to the drawings.

  As shown in FIG. 9, a data processing device 901, a host 902, a server 903, a network 2 904 that connects the data processing device 901 and the host 902, and a network 2 905 that connects the host 902 and the server 903. The data processing device 901, the host 902, and the server 903 are separately connected to the network 1 904 and the network 2 905. This is based on the assumption that the network 2 905 between the host 902 and the server 903 is the Internet. If there is no security problem, the same network may be used.

As shown in FIG. 2, the data processing device 901 includes a processor 201, a communication interface 202, a programmable logic circuit 203, and a storage device 204.

Next, a flow of a series of processes will be described with reference to FIG. When the user uses the host 902 to input a data processing procedure, processing time constraints, and the scale of a programmable logic circuit included in the data processing apparatus, the host 902 executes processing according to the flow shown in FIG. Here, the software library 501 and the hardware library 502 required from the input data processing procedure are downloaded from the server 903 via the network 2 905, and the software module / hardware module 1004 is generated. The structures of the software library 501 and the hardware library 502 are shown in FIG. The software library 501 contains processing time data 503 and software 504 corresponding to processing, and the hardware library 502 contains processing time data 505, processing driver 506 corresponding to processing, and processing hardware 507. Based on the information of the processing time data 503 and the processing time data 505, the data amount (the size of the image) is also input as information to the processing time constraint and the programmable logic circuit scale that are input, if necessary. From this, a software module / hardware module 1004 is generated.

  This procedure will be described with reference to FIG. In this case, a noise removal function 601, an image alignment function 602, a comparison function 603, and a feature point extraction function 604 are input. After that, the noise removal function 601 is a smoothing process 605 and edge extraction process 606, the two-image registration function 602 is a registration process 607, the comparison function 63 is a subtraction process 608, and the feature point extraction function 604 is a binarization process. It is automatically disassembled to 609. After being decomposed into processing contents, the software library 501 and the hardware library 502 are inquired via the network 2 905 (1002), and the library of the corresponding processing is acquired (1003). At this time, the processing time 505 and the processing time 506 are included in the library of the corresponding processing, and if necessary, the entire processing time is recalculated from the input data amount, and the input processing time constraint From the scale of the programmable logic circuit, software processing or hardware processing is selected for each processing. The software processing and hardware processing selected as described above are combined for each software and hardware to generate a software module / hardware module 303. When the processing time constraint is severe, for example, as shown in FIG. 7, the smoothing process 701, the subtraction process 704, the feature point extraction process 705 is a hardware process, the edge extraction process 702, and the alignment process 703 are software processes. Increase hardware processing and achieve time constraints. On the other hand, when the processing time constraint is sufficient or the hardware logical scale is small, for example, as shown in FIG. 8, the smoothing process 801 is a hardware process, and the edge extraction process 802, the alignment process 803, and the subtraction process The 804 and binarization processing 805 is software processing, and logic to be hardware is reduced. If the processing time is not in time, it is necessary to secure the necessary processing time by increasing the programmable logic circuit scale or simplifying the processing procedure.

For example, when the user has the host 902, the algorithm for generating the software module / hardware module 1004 from the software library 501 and the hardware library 502 can be changed, or a certain process can be fixed. Customization will be improved.

  The software module / hardware module 1004 generated in this way is transferred to the data processing device 901 via the network 1 904.

  As described above, according to the present invention, if the software library 501 and the hardware library 502 are prepared, the data processing content can be changed according to each user. If the software module / hardware module 1004 is created, the data processing apparatus can execute a necessary processing procedure. Further, since the software library 501 and the hardware library 502 are on the user side, the load on the server can be minimized.

  For the user side to execute different data processing procedures on the terminal containing the same programmable logic circuit, when changing the processing procedure, it can be realized with the same device, and for the provider side, the same It is only necessary to provide hardware, and if a server or host for generating libraries and modules is set up, a flexible system according to the user can be provided.

1 is a block diagram showing a first embodiment of the present invention. The block diagram of the data processor of this invention. Explanatory drawing of the data flow of 1st Example of this invention. The flowchart from the library of this invention to module production | generation. The internal structure figure of the software library and hardware library of this invention. Explanatory drawing from the functional block of this invention to the processing block. FIG. 1 is an explanatory diagram 1 from library of the present invention to module conversion. FIG. 2 is an explanatory diagram from library of the present invention to module conversion. The block diagram which shows the 2nd Embodiment of this invention. Explanatory drawing of the data flow of 2nd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101,901 ... Data processing apparatus, 102 ... Terminal, 103, 902 ... Host, 104 ... Network, 201 ... Processor, 202 ... Communication interface, 203 ... Programmable logic circuit, 204 ... Storage device, 301 ... Data transfer, 302 ... Library inquiry / acquisition, 303, 1004 ... software module / hardware module generation,
304, 1005 ... Download, 501 ... Software module, 502 ... Hardware module, 503, 505 ... Process 1 hour data, ..., Process n time data, 504 ... Process 1 software data, ..., Process n software data, 506 ... Process 1 driver,..., Processing n driver, 507... Processing 1 hardware,..., Processing n hardware, 601... Noise removal function, 602... 2 image alignment function, 603. ... smoothing process, 606 ... edge extraction process, 607 ... alignment process, 608 ... subtraction process, 609 ... binarization process, 701, 801 ... smoothing process hardware and software driver, 702, 802 ... edge extraction process Software, 703, 803 ... registration processing software, 04 ... Subtraction processing hardware and software driver, 705 ... Binarization hardware and software driver, 804 ... Subtraction processing software, 805 ... Binarization software, 903 ... Server, 904 ... Network 1, 905 ... Network 2, 1001 ... Data input, 1002 ... Library inquiry, 1003 ... Library reference.

Claims (6)

A data processing system that is used for inspection for extracting defects from images based on image comparison, and that processes data processing procedures required for the defect extraction with a software module described in a programming language and a hardware module described with a programmable logic circuit Because
A data processing device having a processor for executing the software module and a programmable logic circuit for executing the hardware module;
A terminal for inputting information on an image processing function required for the defect extraction, a processing time constraint, and a scale of a programmable logic circuit included in the data processing device;
The image processing function input from the terminal is decomposed into processes that can be executed by the software module or hardware module, and the decomposed processing content, the processing time constraint, and the programmable logic circuit included in the data processing device A host system for generating the software module and the hardware module from the software library and the hardware library,
The terminal, the host system, and the data processing apparatus are connected via a network, and the data processing apparatus includes the software module and the hardware module generated by the host system based on the information input from the terminal. A data processing system which is downloaded from a network and executed. The data processing system of claim 1,
A data processing device having a processor for executing the software module and a programmable logic circuit for executing the hardware module;
A terminal for inputting information on the image processing function required for the defect extraction, the processing time constraint, and the scale of the programmable logic circuit included in the data processing device;
A data processing system characterized in that they are the same device. A data processing system that is used for inspection for extracting defects from images based on image comparison, and that processes data processing procedures required for the defect extraction with a software module described in a programming language and a hardware module described with a programmable logic circuit Because
A data processing device having a processor for executing the software module and a programmable logic circuit for executing the hardware module;
A server system having a software library and a hardware library; an image processing function required for the defect extraction; a processing time constraint; and information on the scale of a programmable logic circuit included in the data processing apparatus. The function is decomposed into a process that can be executed by the software module or the hardware module, and the information on the decomposed process content, the processing time constraint, and the scale of the programmable logic circuit that the data processing device has, A host system that refers to the software library and the hardware library from a server system and generates the software module and the hardware module;
The data processing device, the server system, and the host system are connected via a network, and the host system refers to the software library and the hardware library of the server system based on the input information, and the software A data processing system that generates a module and the hardware module, and wherein the data processing device downloads and executes the generated software module and the hardware module from the network. The data processing system of claim 3,
A data processing device having a processor for executing the software module and a programmable logic circuit for executing the hardware module;
Information on the image processing function required for the defect extraction, processing time constraints, and the scale of the programmable logic circuit included in the data processing apparatus is input, and the input image processing function is processed by the software module or the hardware module. The software library and the hardware library are separated from the server system with respect to information on the content of the decomposed processing, the processing time constraint, and the scale of the programmable logic circuit included in the data processing device. A host system for generating the software module and the hardware module;
A data processing system characterized in that they are the same device. In the data processing system of Claim 1 and Claim 3,
In the software library, the software logic of the corresponding process, and the execution time of the software logic,
The hardware library includes hardware logic of a corresponding process, software driver logic for executing the hardware logic, and execution times of the hardware logic and the software driver logic. Data processing system. In hardware module described in the software module and the programmable logic circuit described in a programming language, along with used test for extracting a defect from an image based on image comparison, data processing for performing data processing for the defect extraction In the system,
A terminal for inputting information on an image processing function required for the defect extraction, a processing time constraint, and a scale of a programmable logic circuit included in the data processing device;
Wherein the image processing function that is input from the terminal software modules, or decomposed into executable processing hardware module, and the decomposed processing content, and the processing time constraints, programmable logic with the data processing device A host system that generates software modules and hardware modules by referring to the software library and the hardware library for information on the scale of the circuit;
A data processing system comprising a data processing device that downloads and executes the software module and the hardware module from the host system.

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