JP2011048238A - Display controller and electronic equipment using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display controller that displays images excellent in visibility on two display panels. <P>SOLUTION: The display controller includes: a memory for storing image data; an image data read circuit for reading first image data from the memory in synchronization with a first vertical synchronization signal and reading second image data from the memory in synchronization with a second vertical synchronization signal; and a display panel interface for generating a first horizontal synchronization signal, a second horizontal synchronization signal, the first vertical synchronization signal, and the second vertical synchronization signal delayed by a predetermined time for the first vertical synchronization signal, supplying the first horizontal synchronization signal, the first vertical synchronization signal, and the first read image data to a first display panel, and supplying the second horizontal synchronization, the second vertical synchronization signal, and the second read image data to a second display panel. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display controller for controlling a display panel such as an LCD (Liquid Crystal Display) panel or an organic EL (Electro-Luminescence) panel in an electronic device such as a mobile phone or a portable OA device. In particular, the present invention relates to a display controller that can display images on two display panels. Furthermore, the present invention relates to an electronic device using such a display controller.

  In an electronic device such as a mobile phone or a portable OA device, it has been studied to display an image using two display panels. By using two display panels, for example, a screen obtained by receiving a television broadcast is divided into two images, and these images are displayed on the two display panels, respectively. It is possible to display the operation screen on the other display panel while displaying on one display panel. In particular, when one screen is divided into two images and these images are respectively displayed on two display panels, synchronization is established between two vertical synchronization signals respectively supplied to the two display panels. Otherwise, there is a risk of visually unnatural images when displaying moving images.

  As a related technique, in Patent Document 1, in a portable game machine equipped with two displays, the display is not individually flickered using a single three-dimensional image processing unit. It is disclosed that a three-dimensional game image is displayed simultaneously. This portable game machine includes a first display, a second display, a three-dimensional image processing unit, a capture circuit, a storage unit, a two-dimensional image processing unit, and an output destination setting circuit.

  The portable game machine captures the first game image at the same time as outputting the first game image generated by the three-dimensional image processing unit to the first display in the (n) th frame, ) A second game image based on the two-dimensional image data captured in the frame is output to the second display.

  In addition, in the (n + 1) th frame, the portable game machine captures the first game image at the same time as outputting the first game image generated by the three-dimensional image processing unit to the second display, ) A second game image based on the two-dimensional image data captured in the frame is output to the first display.

  As a result, the first game image generated by the three-dimensional image processing unit is alternately output to the first display and the second display. Therefore, three single images are displayed on two displays using a single three-dimensional image processing unit. A three-dimensional game image can be displayed. Further, since the first game image captured immediately before by the capture circuit is supplied through the two-dimensional image processing unit and displayed on the display on the side where the first game image is not supplied, the display screen flickers. Absent. However, Patent Document 1 does not particularly disclose the timing relationship between the two vertical synchronization signals supplied to the two displays.

JP 2005-287756 A (6th and 8th pages, FIG. 3)

  Accordingly, in view of the above points, some aspects of the present invention provide a display controller capable of realizing visually good image display when displaying images on two display panels, and An electronic device using a simple display controller can be provided.

In order to solve the above problems, a display controller according to one aspect of the present invention is a display controller capable of displaying an image on two display panels, and includes first image data and second image data. A memory for storing, an image data read circuit for reading first image data from the memory in synchronization with the first vertical synchronization signal, and reading second image data from the memory in synchronization with the second vertical synchronization signal; The first horizontal synchronization signal, the second horizontal synchronization signal, the first vertical synchronization signal, and the first vertical synchronization signal are delayed by a predetermined time based on an externally supplied clock signal. The first vertical synchronization signal is generated, and the first horizontal synchronization signal, the first vertical synchronization signal, and the first image data read by the image data read circuit are displayed on the first display panel. And a display panel interface that supplies the second horizontal synchronization signal, the second vertical synchronization signal, and the second image data read by the image data read circuit to the second display panel. .
Here, it is preferable that the display panel interface generates the second vertical synchronization signal delayed by about one horizontal synchronization period or about one vertical synchronization period with respect to the first vertical synchronization signal.

  The memory may be a double buffer memory that stores first image data for two frames and second image data for two frames. In that case, in the first display mode in which the image data read circuit divides one screen into two images and displays the images on the two display panels, respectively, the first image data and the second image The frame of the first image data read from the memory is updated in synchronization with the first vertical synchronization signal generated immediately after the corresponding frame of data is written to the memory, and the first read from the memory The frame of the second image data read from the memory may be updated in synchronization with the second vertical synchronization signal generated immediately after the frame of the image data is updated.

Further, in the second display mode in which the image data read circuit displays two unrelated images on the two display panels, respectively, a first image generated immediately after the frame of the first image data is written in the memory. The frame of the first image data read from the memory is updated in synchronization with the vertical synchronizing signal of the second vertical synchronizing signal, and the second vertical synchronizing signal generated immediately after the second frame of image data is written to the memory. In synchronization, the frame of the second image data read from the memory may be updated. In these cases, the display controller may further include a register that stores a display mode selection signal that represents one of the first display mode and the second display mode.
An electronic apparatus according to one aspect of the present invention includes any one of the display controllers.

  According to the present invention, when displaying an image on two display panels, the second vertical synchronization signal delayed by a predetermined time with respect to the first vertical synchronization signal is generated, thereby the two display panels. By providing continuity in the display scan, the display of visually good images can be realized. Further, in the case of using a double buffer memory, in the first display mode in which one screen is divided into two images and these images are respectively displayed on the two display panels, the first image data and the second image data are displayed. By sequentially updating the images displayed on the two display panels after the corresponding frames of the image data are written in the memory, it is possible to perform screen switching with a sense of unity between the two display panels.

1 is a block diagram showing a circuit configuration of an electronic device according to a first embodiment of the present invention. The timing chart which shows transition of each signal in 1 vertical synchronizing period. The timing chart which shows transition of each signal in 1 horizontal synchronizing period. The figure which shows the relationship between the two vertical synchronizing signals supplied to two display panels. The figure which shows the display scan in the case of arrange | positioning two display panels side by side. The figure which shows the display scan in the case of arrange | positioning two display panels side by side vertically. FIG. 2 is a diagram showing a specific configuration example of a display panel interface shown in FIG. 1. The block diagram which shows the circuit structure of the electronic device which concerns on the 2nd Embodiment of this invention. FIG. 9 is a diagram showing timing in a first display mode of the electronic device shown in FIG. 8. FIG. 9B is a timing chart showing an image update operation in the broken line region of FIG. 9A. FIG. 9 is a diagram showing timing in a second display mode of the electronic device shown in FIG. 8. FIG. 10B is a timing chart showing an image update operation in the broken line area of FIG. 10A.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a block diagram showing a circuit configuration of an electronic apparatus using the display controller according to the first embodiment of the present invention. This electronic device is an electronic device such as a mobile phone or a portable OA device. In FIG. 1, only the portion related to image display is shown.

  As shown in FIG. 1, the electronic device includes a tuner 10 that receives a television broadcast and outputs image data, a host CPU 20 that performs control related to image display, and a display controller according to the first embodiment of the present invention. 30, an oscillation circuit 40 that supplies a clock signal CLK to the display controller 30, a display panel 51 that displays an image based on first image data DATA 1 and a synchronization signal supplied from the display controller 30, and the display controller 30 Display panel 52 for displaying an image based on the second image data DATA2 and the synchronization signal.

  The display panels 51 and 52 are display panels such as an LCD panel or an organic EL panel. In this way, by using the two display panels 51 and 52, for example, the screen obtained by the tuner 10 receiving the television broadcast is divided into an image A and an image B, and the image A and the image B are divided into two images. An operation screen generated by the host CPU 20 is displayed as an image B on the other display panel 52 while being displayed on each of the display panels 51 and 52, or while displaying a television broadcast screen as an image A on one display panel 51. It becomes possible to do.

  In the following, a mode in which one screen is divided into two images and these images are respectively displayed on two display panels is referred to as a first display mode, and two unrelated images are displayed on two display panels, respectively. The display mode is referred to as a second display mode.

  The display controller 30 includes an image data write circuit 31, a memory 32, image data read circuits 33 and 34, display panel interfaces 35 and 36, and a register 37. Here, the image data read circuits 33 and 34 may be integrated, or the display panel interfaces 35 and 36 may be integrated.

  The image data write circuit 31 is supplied with the image data DATA from the host CPU 20 and outputs the address signal ADD, the write control signal WR, and the image data DATA to the memory 32, thereby writing the image data DATA into the memory 32.

  For example, the image data write circuit 31 writes the first image data DATA1 representing the left half of the television broadcast screen into the storage area of the image A in the memory 32, and represents the right half of the same television broadcast screen. The second image data DATA 2 is written in the storage area of the image B in the memory 32.

  Alternatively, the image data write circuit 31 writes the first image data DATA1 representing the television broadcast screen into the storage area of the image A in the memory 32, and the second image data representing the operation screen generated by the host CPU 20. DATA2 is written in the storage area of the image B in the memory 32.

  The image data read circuit 33 is supplied with the first vertical synchronization signal VSYNC1 from the display panel interface 35, and outputs the address signal ADD and the read control signal RD to the memory 32 in synchronization with the first vertical synchronization signal VSYNC1. Thus, the first image data DATA1 is read from the memory 32. The first image data DATA1 read from the memory 32 is supplied to the display panel interface 35.

  The image data read circuit 34 is supplied with the second vertical synchronization signal VSYNC2 from the display panel interface 36, and outputs the address signal ADD and the read control signal RD to the memory 32 in synchronization with the second vertical synchronization signal VSYNC2. Thus, the second image data DATA2 is read from the memory 32. The second image data DATA2 read from the memory 32 is supplied to the display panel interface 36.

  The display panel interface 35 generates a first horizontal synchronization signal, a first vertical synchronization signal, and a first data enable signal based on the clock signal CLK supplied from the oscillation circuit 40, and outputs them to the first. The image data DATA1 and the like are supplied to the display panel 51.

  The display panel interface 36 generates a second horizontal synchronization signal, a second vertical synchronization signal, and a second data enable signal based on the clock signal CLK supplied from the oscillation circuit 40, and outputs them to the second data synchronization signal. The image data DATA2 and the like are supplied to the display panel 52.

The register 37 stores various setting values set by control signals supplied from the host CPU 20. Here, various setting values stored in the register 37 will be described.
FIG. 2 is a timing chart showing the transition of each signal in one vertical synchronization period. In FIG. 2, VT represents the period of the vertical synchronization signal VSYNC, that is, one vertical synchronization period (one frame period), VPW represents the pulse width of the vertical synchronization signal VSYNC, and VDSP represents vertical data. The output start position is represented, and VDP represents a vertical data valid period. The image data DATA is valid during the vertical data valid period VDP, and invalid during other periods.

  FIG. 3 is a timing chart showing the transition of each signal in one horizontal synchronization period. In FIG. 3, HT represents the period of the horizontal synchronization signal HSYNC, that is, one horizontal synchronization period (one line period), HPW represents the pulse width of the horizontal synchronization signal HSYNC, and HDSP represents horizontal data. The output start position is represented, and HDP represents the horizontal data effective period. FIG. 3 also shows a data enable signal DE and a clock signal CLK. The image data DATA is synchronized with the clock signal CLK, and is valid in the horizontal data valid period HDP in which the data enable signal DE is activated, and invalid in other periods.

  In order to generate a synchronization signal and the like as shown in FIGS. 2 and 3, the register 37 shown in FIG. 1 includes a vertical synchronization signal cycle VT, a vertical synchronization signal pulse width VPW, and a vertical data output start position VDSP. Parameters (setting values) including a vertical data valid period VDP, a horizontal synchronization signal period HT, a horizontal synchronization signal pulse width HPW, a horizontal data output start position HDSP, and a horizontal data valid period HDP Is stored.

  FIG. 4 is a timing chart showing a temporal relationship between two vertical synchronization signals supplied to two display panels. As described in the background section, when one screen is divided into two images and these images are respectively displayed on two display panels, two vertical synchronizations respectively supplied to the two display panels If the signals are not synchronized, there is a risk of visually unnatural images when displaying moving images. Further, by adjusting the timing relationship between the two vertical synchronization signals respectively supplied to the two display panels, the visual continuity of the images displayed across the two display panels changes.

  Therefore, the display controller according to the present embodiment has a timing relationship between the first vertical synchronization signal VSYNC1 and the second vertical synchronization signal VSYNC2 supplied to the two display panels, that is, the first vertical synchronization signal. The time interval ΔT between VSYNC1 and the second vertical synchronization signal VSYNC2 can be adjusted.

  FIG. 5 is a diagram showing a display scan when two display panels are arranged side by side in the horizontal direction. For example, in an LCD panel, a horizontal scan is performed in accordance with the update of an image signal supplied to a plurality of signal electrodes (segment electrodes) arranged in the horizontal direction of the LCD panel, and the LCD panel is arranged in the vertical direction of the LCD panel. A vertical scan is performed in accordance with a change in the scan electrode drive signal (common signal) supplied to the plurality of scan electrodes (common electrodes).

  As shown in FIG. 5, when two display panels 51 and 52 are arranged side by side in the horizontal direction (horizontal scan direction), the display is performed when the horizontal scan position on the display panel 51 moves from the left end to the right end. When the horizontal scan in the panel 52 is started from the left end, the display scan can be made continuous. For this purpose, the time interval ΔT between the first vertical synchronization signal and the second vertical synchronization signal may be set to be substantially equal to one horizontal synchronization period. On the other hand, this is achieved by delaying the second vertical synchronizing signal by approximately one horizontal synchronizing period.

  FIG. 6 is a diagram showing a display scan when two display panels are arranged in the vertical direction. As shown in FIG. 6, when two display panels 51 and 52 are arranged side by side in the vertical direction (vertical scan direction), the display is performed when the vertical scan position on the display panel 51 moves from the upper end to the lower end. When the vertical scan in the panel 52 is started from the upper end, the display scan can be made continuous. For this purpose, the time interval ΔT between the first vertical synchronization signal and the second vertical synchronization signal may be set to be substantially equal to one vertical synchronization period. On the other hand, it is achieved by delaying the second vertical synchronizing signal by approximately one vertical synchronizing period.

  The register 37 shown in FIG. 1 includes data (ΔT set value) representing the time interval ΔT between the first vertical synchronization signal and the second vertical synchronization signal, the first display mode, and the second display mode. Of the display mode, a first enable signal EN1 for controlling on / off of display on the display panel 51, and a second enable signal for controlling on / off of display on the display panel 52. EN2 and the like are further stored.

  As shown in FIG. 5 or FIG. 6, when the time interval ΔT between the first vertical synchronization signal and the second vertical synchronization signal is set to approximately one horizontal synchronization period or approximately one vertical synchronization period, the display panel If the display panel 51 and the display panel 52 have the same size, the two display panel interfaces 35 and 36 can share a circuit for generating a horizontal synchronizing signal.

  FIG. 7 is a diagram showing a specific configuration example of the display panel interface shown in FIG. This display panel interface is obtained by integrating the two display panel interfaces 35 and 36 shown in FIG. 1, and a circuit for generating a horizontal synchronizing signal supplied to the two display panels is shared.

  In the display panel interface shown in FIG. 7, the AND circuit 61 includes a clock signal CLK supplied from the oscillation circuit 40 (FIG. 1) and a first enable signal for controlling on / off of display on the display panel 51 (FIG. 1). A clock signal CLK1 supplied to the display panel 51 is generated by obtaining a logical product with EN1. Further, the AND circuit 62 obtains a logical product of the clock signal CLK and the second enable signal EN2 for controlling on / off of display in the display panel 52 (FIG. 1), thereby supplying the clock supplied to the display panel 52. A signal CLK2 is generated.

  The OR circuit 63 generates an enable signal supplied to the horizontal synchronization signal generation circuit 64 and the like by calculating a logical sum of the first enable signal EN1 and the second enable signal EN2.

  The horizontal synchronization signal generation circuit 64 includes a counter, and when the enable signal is activated, the count value is incremented in synchronization with the clock signal CLK. The horizontal synchronization signal generation circuit 64 generates the horizontal synchronization signal HSYNC by comparing the count value with the set value of the pulse width HPW and the period HT of the horizontal synchronization signal, and generates a pulse HPLS corresponding to the period of the horizontal synchronization signal. Generate. The count value is reset every period of the horizontal synchronization signal.

  The AND circuit 66 generates a first horizontal synchronization signal HSYNC1 to be supplied to the display panel 51 by obtaining a logical product of the horizontal synchronization signal HSYNC and the first enable signal EN1. The AND circuit 67 generates a second horizontal synchronization signal HSYNC2 supplied to the display panel 52 by obtaining a logical product of the horizontal synchronization signal HSYNC and the second enable signal EN2.

  The horizontal data enable signal generation circuit 65 includes a counter. When the enable signal is activated, the horizontal data enable signal generation circuit 65 increments the count value in synchronization with the clock signal CLK. The horizontal data enable signal generation circuit 65 compares the count value with the set value of the horizontal data output start position HDSP, and compares the increment of the count value after the start of horizontal data output with the set value of the horizontal data valid period HDP. Thus, a horizontal data enable signal is generated. The count value is reset every period of the horizontal synchronization signal.

  The vertical synchronization signal generation circuit 68 includes a counter. When the enable signal is activated, the vertical synchronization signal generation circuit 68 increments the count value in synchronization with the pulse HPLS corresponding to the period of the horizontal synchronization signal. The vertical synchronization signal generation circuit 68 generates the first vertical synchronization signal VSYNC1 by comparing the count value with the set value of the pulse width VPW and the period VT of the vertical synchronization signal, and the period of the first vertical synchronization signal. A pulse VPLS corresponding to is generated. The count value is reset every period of the first vertical synchronization signal.

  The vertical data enable signal generation circuit 69 includes a counter. When the enable signal is activated, the vertical data enable signal generation circuit 69 increments the count value in synchronization with the pulse HPLS corresponding to the period of the horizontal synchronization signal. The vertical data enable signal generation circuit 69 compares the count value with the set value of the vertical data output start position VDSP, and compares the increment of the count value after the start of vertical data output with the set value of the vertical data valid period VDP. Thus, the first vertical data enable signal is generated. The count value is reset every period of the first vertical synchronization signal.

  The AND circuit 70 obtains a logical product of the horizontal data enable signal and the first vertical data enable signal, thereby generating the first data enable signal DE1 supplied to the display panel 51. Further, the data gate circuit 71 outputs the first image data DATA1 read from the memory 32 to the display panel 51 when the first data enable signal DE1 is activated.

  The vertical synchronization signal generation circuit 72 is supplied with data (ΔT set value) representing the time interval ΔT between the first vertical synchronization signal VSYNC1 and the second vertical synchronization signal VSYNC2. The vertical synchronization signal generation circuit 72 includes a counter. When the enable signal is activated, the vertical synchronization signal generation circuit 72 increments the count value in synchronization with the pulse HPLS corresponding to the period of the horizontal synchronization signal. The vertical synchronization signal generation circuit 72 sets the phase of the second vertical synchronization signal VSYNC2 by comparing the increment of the count value after the generation of the pulse VPLS with the ΔT set value, and further sets the count value to the vertical synchronization signal. The second vertical synchronization signal VSYNC2 is generated by comparing with the set values of the pulse width VPW and the period VT. The count value is reset every cycle of the second vertical synchronization signal. In this way, the second vertical synchronization signal VSYNC2 delayed by a predetermined time with respect to the first vertical synchronization signal VSYNC1 is generated according to the ΔT set value.

  The vertical data enable signal generation circuit 73 includes a counter. When the enable signal is activated, the vertical data enable signal generation circuit 73 increments the count value in synchronization with the pulse HPLS corresponding to the period of the horizontal synchronization signal. The vertical data enable signal generation circuit 73 compares the count value with the set value of the vertical data output start position VDSP, and compares the increment of the count value after the start of vertical data output with the set value of the vertical data valid period VDP. Thus, the second vertical data enable signal is generated. The count value is reset every cycle of the second vertical synchronization signal.

  The AND circuit 74 obtains the logical product of the horizontal data enable signal and the second vertical data enable signal, thereby generating the second data enable signal DE2 supplied to the display panel 52. Further, the data gate circuit 75 outputs the second image data DATA2 read from the memory 32 to the display panel 52 when the second data enable signal DE2 is activated.

Next, a second embodiment of the present invention will be described.
FIG. 8 is a block diagram showing a circuit configuration of an electronic apparatus using the display controller according to the second embodiment of the present invention. The second embodiment is a double buffer memory in which the memory 32a of the display controller 30a stores the first image data for two frames and the second image data for two frames. The image data write circuit 31a, The image data read circuits 33a and 34a are different from those of the first embodiment in that they perform corresponding operations. The other points are the same as in the first embodiment.

  The image data write circuit 31a alternately writes a plurality of continuous frames of the first image data in the storage area of the image A1 and the storage area of the image A2 in the memory 32a, and a plurality of continuous frames of the second image data. Are alternately written in the storage area of the image B1 and the storage area of the image B2 in the memory 32a. The image data writing rate is, for example, 15 frames / second.

  The image data read circuit 33a reads the first image data from the storage area of the image A1 or the storage area of the image A2 in the memory 32a and supplies the first image data to the display panel interface 35. The image data read circuit 34a reads the second image data from the storage area of the image B1 or the storage area of the image B2 in the memory 32a, and supplies the second image data to the display panel interface 36. The image data read rate is, for example, 60 frames / second. Therefore, the same image data is read out a plurality of times.

  The operation of the image data read circuits 33a and 34a includes a first display mode in which one screen is divided into two images and these images are respectively displayed on two display panels, and two unrelated images are displayed in two The second display mode is different from the second display mode displayed on the display panel.

  FIG. 9A is a timing chart illustrating a relationship between image writing timing and display timing in the first display mode of the electronic device illustrated in FIG. 8. In the first display mode, the image data write circuit 31a stores the first image data for one frame representing the image A2 in the memory 32a while the images A1 and B1 are displayed on the panels 51 and 52, respectively. When the writing and writing of the image A2 are completed, the A1 / A2 selection signal is changed from the low level to the high level. Subsequently, the image data write circuit 31a writes the second image data for one frame representing the image B2 to the memory 32a. When the writing of the image B2 is completed, the B1 / B2 selection signal is changed from the low level to the high level. To do.

  The image data read circuit 33a is read from the memory 32a in synchronization with the first vertical synchronization signal VSYNC1 generated immediately after the corresponding frames of the first image data and the second image data are written to the memory 32a. The first image data frame is updated, and a frame update signal FUD indicating that the first image data frame has been updated is output to the image data read circuit 34a.

  The image data read circuit 34a reads the second image data read from the memory 32a in synchronization with the second vertical synchronization signal VSYNC2 generated immediately after the frame of the first image data read from the memory 32a is updated. Update the frame. In this way, the images A1 and B1 displayed on the panels 51 and 52 are sequentially updated to the images A2 and B2.

  FIG. 9B is a timing chart showing details of the image update operation in the broken line region of FIG. 9A. At time t1 after the first vertical synchronization signal VSYNC1 is activated to the low level, the writing of the image B2 is not yet completed even when the writing of the image A2 is completed. The first image data representing the image A1 is read from the memory 32a and supplied to the display panel interface 35. The display panel interface 35 supplies the first image data representing the image A1 to the display panel 51, whereby the display panel. 51 displays the image A1.

  After that, at time t2 after the second vertical synchronization signal VSYNC2 is activated to the low level immediately after the writing of the image B2, the display panel 51 displays the image A1, so that the image data read circuit 34a reads out the second image data representing the image B1 from the memory 32a and supplies it to the display panel interface 36, and the display panel interface 36 supplies the second image data representing the image B1 to the display panel 52. The display panel 52 displays the image B1.

  At time t3 after the first vertical synchronization signal VSYNC1 is activated to the low level again, the writing of the image B2 is completed, so the image data read circuit 33a stores the first image data representing the image A2 in the memory. The display panel 51 displays the image A2 by reading from the display 32a and supplying it to the display panel interface 35. The display panel interface 35 supplies the first image data representing the image A2 to the display panel 51. When the frame of the first image data read from the memory 32a is changed, the image data read circuit 33a outputs a frame change signal FUD indicating that to the image data read circuit 34a.

  At time t4 after the second vertical synchronization signal VSYNC2 is activated again to the low level, the display panel 51 displays the image A2, so that the image data read circuit 34a displays the second image representing the image B2. The image data is read from the memory 32a and supplied to the display panel interface 36. The display panel interface 36 supplies the second image data representing the image B2 to the display panel 52, so that the display panel 52 displays the image B2. .

  FIG. 10A is a timing chart illustrating a relationship between image writing timing and display timing in the second display mode of the electronic device illustrated in FIG. 8. Also in the second display mode, the image data write circuit 31a stores the first image data for one frame representing the image A2 in the memory 32a while the images A1 and B1 are displayed on the panels 51 and 52, respectively. When the writing and writing of the image A2 are completed, the A1 / A2 selection signal is changed from the low level to the high level. Subsequently, the image data write circuit 31a writes the second image data for one frame representing the image B2 to the memory 32a. When the writing of the image B2 is completed, the B1 / B2 selection signal is changed from the low level to the high level. To do.

  The image data read circuit 33a updates the frame of the first image data read from the memory 32a in synchronization with the first vertical synchronization signal generated immediately after the writing of the image A2 is completed. The image data read circuit 34a updates the frame of the second image data read from the memory 32a in synchronization with the second vertical synchronization signal generated immediately after the writing of the image B2. In this way, the images A1 and B1 displayed on the panels 51 and 52 are sequentially updated to the images A2 and B2.

  FIG. 10B is a timing chart showing details of the image update operation in the broken line region of FIG. 10A. At time t5 after the second vertical synchronization signal VSYNC2 is activated to the low level immediately after the writing of the image B2, the image data read circuit 34a receives the second image data representing the image B2 from the memory 32a. The data is read and supplied to the display panel interface 36. The display panel interface 36 supplies the second image data representing the image B2 to the display panel 52, so that the display panel 52 displays the image B2.

  As described above, when the double buffer memory 32a is used, in the first display mode in which one screen is divided into two images and these images are respectively displayed on the two display panels, the first image data and After the corresponding frame of the second image data is written in the memory 32a, the images displayed on the two display panels 51 and 52 are sequentially updated, so that the two display panels 51 and 52 have a sense of unity. Some screen switching can be performed.

  On the other hand, in the second display mode in which two unrelated images are displayed on the two display panels, the image displayed on the display panel 51 is displayed after the first image data frame is written in the memory 32a. Each of the display panels 51 and 52 can be quickly updated by independently updating the image displayed on the display panel 52 after the second image data frame is written in the memory 32a. Switching can be performed.

  10 tuner, 20 host CPU, 30, 30a display controller, 31, 31a image data write circuit, 32, 32a memory, 33, 34, 33a, 34a image data read circuit, 35, 36 display panel interface, 37 register, 40 oscillation Circuit, 51, 52 display panel, 61, 62, 66, 67, 70, 74 AND circuit, 63 OR circuit, 64 horizontal synchronization signal generation circuit, 65 horizontal data enable signal generation circuit, 68, 72 vertical synchronization signal generation circuit, 69, 73 Vertical data enable signal generation circuit, 71, 75 Data gate circuit

Claims (7)

A display controller capable of displaying images on two display panels,
A memory for storing the first image data and the second image data;
An image data read circuit that reads out the first image data from the memory in synchronization with a first vertical synchronization signal and reads out the second image data from the memory in synchronization with a second vertical synchronization signal;
Delayed by a predetermined time with respect to the first horizontal synchronization signal, the second horizontal synchronization signal, the first vertical synchronization signal, and the first vertical synchronization signal based on a clock signal supplied from the outside. And the first horizontal synchronization signal, the first vertical synchronization signal, and the first image data read out by the image data read circuit are generated as the first vertical synchronization signal. And the second horizontal synchronization signal, the second vertical synchronization signal, and the second image data read by the image data read circuit are supplied to the second display panel. A display panel interface to
A display controller.   2. The display controller according to claim 1, wherein the display panel interface generates the second vertical synchronization signal delayed by approximately one horizontal synchronization period or approximately one vertical synchronization period with respect to the first vertical synchronization signal.   The display controller according to claim 1, wherein the memory is a double buffer memory that stores first image data for two frames and second image data for two frames.   In the first display mode in which the image data read circuit divides one screen into two images and displays the images on two display panels, respectively, the first image data and the second image data The frame of the first image data read from the memory is updated and read from the memory in synchronization with the first vertical synchronization signal generated immediately after the corresponding frame is written to the memory. The frame of the second image data read from the memory is updated in synchronization with the second vertical synchronization signal generated immediately after the frame of the first image data is updated. Display controller as described.   In the second display mode in which the image data read circuit displays two unrelated images on two display panels, respectively, the image data read circuit is generated immediately after the frame of the first image data is written in the memory. The frame of the first image data read from the memory is updated in synchronization with the first vertical synchronization signal, and the frame of the second image data is generated immediately after the frame is written to the memory. The display controller according to claim 4, wherein a frame of the second image data read from the memory is updated in synchronization with a second vertical synchronization signal.   The display controller according to claim 4, further comprising a register that stores a display mode selection signal representing one of the first display mode and the second display mode.   The electronic device which comprises the display controller of any one of Claims 1-6.

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