JP2011040890A - Noncontact type information terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a noncontact type information terminal generating a negative power voltage based on electromagnetic waves received via an antenna, and appropriately driving a mounted depression type FET. <P>SOLUTION: A radio tag device Tag has an internal circuit formed with depression type FETs, is thereby configured to extract a negative voltage along with a positive voltage from energy of a magnetic field generated by a reader/writer, and appropriately drives each depression type FET based on the extracted positive and negative voltages. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a non-contact type information terminal device using a depletion type field effect FET.

  In recent years, it has information for identifying parts and books and other non-contact type in automatic parts transportation system in factories, article management in retail stores, library collection management in libraries, etc. The so-called wireless tag device (hereinafter also referred to as “RFID (Radio Frequency IDentification)” tag device) has started to be widely used.

  In addition, ID cards having a non-contact interface that records personal information, so-called IC (Integrated Circuit) cards (hereinafter referred to as “non-contact IC cards”) are used at the entrances of companies and laboratories and ticket gates of stations. The system that manages the entrance and exit of people using the system is also being introduced for convenience.

  These wireless tags and non-contact type IC cards can communicate with a read / write device (hereinafter referred to as “reader / writer”) using wireless communication. It is thought that it will develop further in the future.

  Such an information terminal device (hereinafter referred to as “non-contact information terminal device”) that performs non-contact data transmission / reception with a reader / writer using a magnetic field such as a non-contact type IC card or a wireless tag. The device itself does not have a power supply.

  For this reason, when a magnetic field is generated by passing a current through a transmission coil of a transmission / reception antenna provided in the reader / writer, and the magnetic field passes through a reception coil as a transmission / reception antenna provided in a non-contact type IC card or RFID tag device, The induced voltage generated according to the magnetic flux is driven as a power source.

  That is, a non-contact type IC card or RFID tag receives the energy of a magnetic field transmitted from a transmission coil of a reader / writer by a reception coil and obtains electric power necessary for driving (for example, Patent Document 1). .

Japanese Patent No. 3940144

  Such non-contact type information terminal devices are required to be downsized, sophisticated, and various types of processing speeded up from the viewpoint of convenience and expandability, and the price reduction is also required. This request is also required for various electronic circuits constituting the non-contact type information terminal device.

  In particular, semiconductor electronic circuits used in non-contact information terminal devices are desired to be easily manufactured and have excellent output characteristics. For example, polysilicon TFTs (Thin Film Transistors) and What was comprised by the oxide film TFT is desired.

However, since these TFTs are driven by applying a voltage between 0 V and the maximum voltage of the power supply voltage V _DD to the gate, the TFTs of the gate to which an external voltage is applied due to the influence of hysteresis or bias stress. The threshold voltage may be negative.

  When the threshold voltage of the gate becomes negative, these TFTs are driven even when a minimum voltage of 0 V is applied. That is, the TFTs are always turned on, and are normal. The output characteristics cannot be obtained.

  In addition, when the gate insulating film in the enhanced FET is generated at a low temperature by sputtering or the like, the voltage characteristic of the film quality of the gate insulating film is lowered, and an oxide film TFT is generated at a lower temperature by printing or the like. In some cases, it is more difficult to obtain good output characteristics at positive voltage.

  As a method of accurately driving such a TFT, it is necessary to shift the level of the input voltage applied to the gate to the minus side to accurately drive the TFT. For this purpose, a negative power source (negative power source) is required. Must be supplied to a semiconductor electronic circuit having these TFTs.

  That is, in a non-contact type information terminal device equipped with a semiconductor electronic circuit using such a TFT, a negative power source (negative power source) to be supplied to each semiconductor electronic circuit is acquired in order to operate normally. There is a need.

  The present invention has been made in order to solve the above-mentioned problems, and its purpose is to easily manufacture an electronic circuit using a depletion type FET and to detect electromagnetic waves received via an antenna. An object of the present invention is to provide a non-contact information terminal device that can generate a negative power supply voltage on the basis thereof and accurately drive the mounted depletion type FET.

  In order to solve the above-mentioned problem, the invention according to claim 1 is a non-contact information terminal device that performs non-contact transmission / reception of data with a read / write device using a magnetic field, and is generated by the read / write device. An antenna circuit that generates an induced voltage in response to a magnetic field, a rectifier circuit that extracts a DC power supply voltage based on the generated induced voltage, and storage means for storing predetermined information, which is output from the rectifier circuit A depletion-type rectifier that performs half-wave rectification for extracting a DC positive voltage as a positive power source based on the generated induced voltage, and storage means that operates based on the generated DC power source voltage. A first transistor, a depletion-type second transistor that performs half-wave rectification to extract a DC negative voltage as a negative power source based on the generated induced voltage, A first smoothing capacitor connected between the transistor and ground and used for smoothing; and a second smoothing capacitor connected between the second transistor and ground and used for smoothing. ing.

  With this configuration, the invention according to claim 1 can generate the DC negative voltage together with the DC positive voltage from the induced voltage generated in the resonance circuit, so that the entire apparatus can be driven by the DC negative voltage.

  Therefore, the invention according to claim 1 can use a depletion type transistor for each internal circuit. Therefore, even when each internal circuit is generated at a low temperature by printing or the like, high speed driving is possible and good. Output characteristics can be obtained, and if all the transistors in the device are constituted by depletion type transistors, the device itself can be easily manufactured.

  According to the first aspect of the present invention, since the transistor is a depletion type and its drivable voltage becomes wide, a signal transmitted from the read / write device can be efficiently obtained from the induced voltage, and a direct current positive voltage can be obtained. And a negative DC voltage can be generated efficiently.

  According to a second aspect of the present invention, in the noncontact information terminal device according to the first aspect, all the transistors used in the noncontact information terminal device including the first transistor and the second transistor are provided. It is composed of an n-type transistor.

  With this configuration, the invention according to claim 2 can generate a transistor by a single process at the time of manufacturing, and thus the device itself can be manufactured more easily.

  The invention according to claim 3 is the non-contact information terminal device according to claim 1 or 2, further comprising a voltage amplification circuit, which converts the DC positive voltage generated by the rectifier circuit into a constant voltage. And a second constant voltage output circuit that has a voltage amplifier circuit and converts a DC negative voltage generated by the rectifier circuit into a constant voltage.

  With this configuration, the invention according to claim 3 can provide the internal circuit with a stable voltage in the DC negative voltage as well as the DC positive voltage, so that the breakdown voltage in each element of the internal circuit such as a transistor is exceeded. The circuit can be generated in accordance with the DC positive voltage and the DC negative voltage to be stabilized.

  According to a fourth aspect of the present invention, in the non-contact information terminal device according to any one of the first to third aspects, each voltage amplifier circuit includes a plurality of third transistors and diffusion resistors. A differential amplifying circuit for amplifying and outputting a voltage level difference between a DC positive voltage and a DC negative voltage output from the rectifier circuit; and amplifying the voltage level of the voltage output from the differential amplifying circuit. An output amplifier circuit for outputting, and all of the transistors provided in the differential amplifier circuit and the output amplifier circuit are depletion type, and the output amplifier circuit is composed of one or more fourth transistors, The level shift circuit unit that shifts the voltage level of the voltage output from the differential amplifier circuit, and one or more fifth transistors, are level-shifted. An amplification circuit unit that inverts and amplifies the voltage level of the voltage, and the differentially amplified and level-shifted voltage is input to the gate of at least one fifth transistor of the amplification circuit unit. It has a configuration.

  With this configuration, the invention according to claim 4 can apply a level-shifted voltage to the gate of the transistor of the amplifier circuit unit in the output amplifier circuit, so that the transistor in the amplifier circuit unit is configured as a depletion type. Thus, the first constant voltage output circuit and the second constant voltage output circuit can be configured by depletion type transistors.

  Therefore, in the invention described in claim 4, since the depletion type transistors can be used for the first constant voltage output circuit and the second constant voltage output circuit, all the transistors in the device can be constituted by the depletion type transistors. It becomes possible.

  According to a fifth aspect of the present invention, in the contactless information terminal device according to any one of the first to fourth aspects, the storage unit is controlled using the voltage output from the rectifier circuit. And the control means is composed of one or more sixth transistors, and is composed of a level shift circuit unit for shifting the voltage level output from the rectifier circuit, and one or more seventh transistors. And an electronic circuit unit that performs a predetermined logical operation using the measured voltage, and the level shift circuit unit and all of the transistors provided in the electronic circuit unit are depletion type and are level-shifted A voltage input to the gate of at least one seventh transistor of the electronic circuit unit. That.

  With this configuration, the invention described in claim 5 can be driven by a DC negative voltage together with a DC positive voltage even in a control circuit having a depletion type transistor. However, high-speed driving is possible and good output characteristics can be obtained.

  According to a sixth aspect of the present invention, in the contactless information terminal device according to any one of the first to fourth aspects, the antenna circuit generates the induced voltage, and the antenna coil And the resonance capacitor constituting the resonance circuit, and the resonance circuit formed by the antenna coil and the resonance capacitor are connected in parallel, and the load value of the contactless information terminal device with respect to the read / write device is determined. A load modulation capacitor and a switching transistor used for load modulation to be changed, and a level shift circuit unit that shifts a voltage level for controlling the switching transistor, wherein the switching transistor is a depletion type. is doing.

  With this configuration, the invention according to claim 6 can input a voltage for controlling the depletion type switching transistor in the antenna circuit within a range in which the transistor is appropriately driven. The switching transistor can be driven accurately.

  Therefore, according to the sixth aspect of the present invention, since the parallel connection of the load modulation capacitor and the resonance capacitor in the switching transistor can be switched, the load (impedance) of the antenna circuit with reference to the read / write device can be reduced. It can be changed accurately.

  As a result, according to the sixth aspect of the present invention, the degree of modulation in load modulation can be increased as the impedance of the antenna circuit changes, so that predetermined data can be accurately transmitted to the read / write device.

  Since the present invention can use an electronic circuit using a depletion type transistor for each internal circuit, even if each internal circuit is generated at a low temperature by printing or the like, it can be driven at high speed and has good output characteristics. And the device itself can be easily manufactured.

It is a block diagram which shows the structure of one Embodiment of the wireless tag apparatus which concerns on this invention. It is a block diagram which shows the structure of a general inverter circuit. It is a figure for demonstrating a general inverter circuit, (a) is a graph which shows the characteristic of the input voltage _VIN -drain current _ID of a general inverter circuit, and (b) is general It is a graph which shows the output characteristic of the voltage in an inverter circuit. It is a figure for demonstrating the subject of this invention, (a) is a graph which shows the characteristic of the input voltage _VIN -drain current _ID of the general inverter circuit at the time of the threshold value shift of a gate voltage, and (B) is a graph which shows the output characteristic of the voltage in the general inverter circuit at that time. It is a block diagram which shows the structure of the 1st regulator (2nd regulator) in one Embodiment. It is a block diagram which shows the structure of the operational amplifier in one Embodiment. It is a block diagram which shows the structure of the control circuit (inverter circuit) in one Embodiment. It is a block diagram which shows the structure of the control circuit (NAND circuit) in one Embodiment. It is a block diagram which shows the structure of the control circuit (NOR circuit) in one Embodiment.

  Hereinafter, embodiments of the present application will be described with reference to the drawings.

  In the embodiment described below, the non-contact information terminal device of the present invention is used in a wireless tag device that communicates with a reader / writer using wireless communication and reads / writes predetermined information by the reader / writer. It is an embodiment in the case of applying.

  First, the schematic configuration and principle of the wireless tag device according to the present embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram illustrating a configuration of the wireless tag device according to the present embodiment, and is a block diagram illustrating a configuration of a general inverter circuit.

FIG. 3 is a diagram for explaining a general inverter circuit. FIG. 3A is a graph showing characteristics of the input voltage V _IN −drain current _ID of the general inverter circuit, and (b) ) Is a graph showing voltage output characteristics in a general inverter circuit.

FIG. 4 is a diagram for explaining the problem of the present invention. FIG. 4A is a diagram illustrating an input voltage V _IN −drain current I _{D of} a general inverter circuit when the threshold voltage of the gate voltage is shifted. (B) is a graph which shows the output characteristic of the voltage in the general inverter circuit at that time.

  The RFID tag device Tag of the present embodiment shown in FIG. 1 is a terminal device that performs near field communication, and a reader that reads and writes identification information and other information stored in the RFID tag device Tag.・ Communicates with a writer (not shown).

  In addition, this RFID tag device Tag transmits and receives signals (information) via a magnetic field generated by the reader / writer, and the device itself does not have a power source, so it is generated by this reader / writer. The energy of the magnetic field converted into electric power is used as a power source.

  In particular, the RFID tag device Tag according to the present embodiment, as will be described later, has an internal circuit configured by a depletion type TFT, and therefore extracts a negative voltage as well as a positive voltage from the energy of the magnetic field generated by the reader / writer. In this way, each depletion type TFT is accurately driven based on the extracted positive and negative voltages.

  Specifically, as shown in FIG. 1, the RFID tag device Tag of this embodiment includes an antenna circuit (including a receiving circuit) Ant that generates an induced voltage based on a magnetic field generated by a reader / writer, A rectifier circuit Rec that rectifies the generated induced voltage and extracts a negative voltage together with the positive voltage, a first regulator Reg1 that stabilizes the rectified positive voltage, and a second regulator Reg2 that stabilizes the rectified negative voltage. And have.

  Also, the RFID tag device Tag of this embodiment includes a transmission circuit SC that transmits predetermined data to a reader / writer by load modulation, a memory circuit Mem that stores predetermined data, and a reader / writer based on a received magnetic field. A detection circuit Dtc that extracts a signal transmitted from the writer and a control circuit Cnt that controls each unit based on the extracted signal are provided.

  For example, the antenna circuit Ant and the transmission circuit SC of the present embodiment constitute the antenna circuit of the present invention, and the rectifier circuit Rec constitutes the rectifier circuit of the present invention.

  Further, for example, the memory circuit Mem of the present embodiment constitutes the storage means of the present invention, and the first regulator Reg1 and the second regulator Reg2 include the first constant voltage output circuit and the second constant voltage output circuit of the present invention. Constitute.

  As described above, the RFID tag device Tag of this embodiment can be manufactured more easily than the enhanced type in the TFTs constituting the internal circuits such as the first regulator Reg1, the second regulator Reg2, the transmission circuit SC, and the control circuit Cnt. In addition, a depletion type TFT that has good driving characteristics and does not deteriorate even when manufactured at a low temperature is used.

  However, since the depletion type FET has a negative gate voltage threshold value, even if an input voltage is accurately applied to the gate, depending on how the voltage is applied, good output characteristics can be obtained in the FET. I can't.

  Normally, in the inverter circuit shown in FIG. 2, when a positive input voltage is applied to the gate of the FET and the threshold voltage of the gate of the FET exists on the positive side, as shown in FIG. (In other words, in the case of an enhanced FET), this inverter circuit has output characteristics as shown in FIG.

  However, in such an inverter circuit, when it is constituted by a depletion type transistor in which the threshold voltage of the gate of the transistor to which the input voltage is applied is shifted to the negative side, as shown in FIG. In addition, even if a positive input voltage is input, the switching operation at the gate of the FET does not move properly, so that this inverter circuit has an output characteristic as shown in FIG. It cannot be said that it is driving.

  Accordingly, since the RFID tag device Tag of this embodiment uses a depletion type FET in each internal circuit, it is adjusted to the threshold voltage of the gate of the depletion type FET before the depletion type FET is disposed. And a level shift circuit unit for shifting to the minus side.

  The wireless tag device Tag of the present embodiment uses the first regulator Reg1 and the second regulator to apply positive and negative voltages necessary for driving each level shift circuit unit to drive each level shift circuit unit accurately. It is generated by Reg2.

  By having such a configuration, the RFID tag device Tag according to the present embodiment can be driven at high speed and obtain good output characteristics even when each FET is generated at a low temperature by printing or the like. At the same time, the FET in the device is constituted by a depletion type FET, and the device itself can be easily manufactured.

  Next, a specific configuration and operation of the RFID tag device Tag according to the present embodiment will be described with reference to FIG.

  An antenna circuit (including a receiving circuit in this embodiment) Ant receives a magnetic field generated from a reader / writer, that is, a carrier wave transmitted from the reader / writer, and induces alternating current by electromagnetic induction. A voltage is generated, and the generated induced voltage is output to the rectifier circuit Rec and the detector circuit Dtc, respectively.

  In particular, the antenna circuit Ant has an antenna coil A10 and a resonance capacitor C10 connected in parallel with the antenna coil A10, and is generated at a preset specific frequency (for example, 13.56 MHz). The output of the induced voltage is maximized, that is, resonates.

  The rectifier circuit Rec is connected to the subsequent stage of the antenna circuit Ant, and extracts a positive DC voltage and a negative DC voltage by performing positive and negative half-wave rectification based on the induced voltage generated in the antenna circuit Ant. The extracted DC positive voltage and DC negative voltage are output to the memory circuit Mem and the control circuit Cnt.

  Specifically, the rectifier circuit Rec of the present embodiment is configured by two depletion type n-type TFTs that can be manufactured by the same process and two smoothing capacitors.

  For example, the rectifier circuit Rec of the present embodiment includes a first rectifier circuit n-type FET 51 for extracting a DC positive voltage, and a smoothing rectifier circuit first smoothing capacitor C20 used for extracting the DC positive voltage. And a second rectifier circuit n-type FET 52 for extracting a DC negative voltage, and a smoothing rectifier circuit second smoothing capacitor C30 used for extracting a DC positive voltage.

  The first n-type FET 51 for the rectifier circuit is a depletion type n-type FET, and is composed of, for example, a polysilicon TFT, an oxide TFT, or an organic transistor.

  The first rectifier circuit first n-type FET 51 is connected to one end of the antenna circuit Ant, a gate to which a voltage is applied, and a drain that is short-circuited to the gate and connected to one end of the antenna circuit Ant together with the gate. And a source connected to one end of the first smoothing capacitor C20 for the rectifier circuit and connected to a terminal for outputting a positive voltage to the first regulator Reg1.

  The first smoothing capacitor C20 for the rectifier circuit is connected between the source of the first n-type FET 51 for the rectifier circuit and the ground, and smoothes the rectified positive voltage output to the first regulator Reg1.

  The rectifier circuit second n-type FET 52 is a depletion-type n-type FET, similar to the rectifier circuit first n-type FET 51, and is composed of, for example, a polysilicon TFT, an oxide TFT, or an organic transistor.

  The rectifier circuit second n-type FET 52 is connected to one end of the rectifier circuit second smoothing capacitor C30 and connected to a terminal that outputs a negative voltage to the rectifier circuit second regulator Reg2, and a rectifier circuit. A drain connected to one end of the antenna circuit Ant together with the drain of the first n-type FET 51, and a terminal short-circuited to the gate and output to the second regulator Reg2 together with one end of the second smoothing capacitor C30 for the rectifier circuit. And a connected source.

  The second smoothing capacitor C30 for rectifier circuit is connected between the source of the second n-type FET 52 for rectifier circuit and the ground, and smoothes the rectified negative voltage output to the second regulator Reg2.

The first regulator Reg1 is a an external input terminal TI to the positive voltage rectified by the rectifier circuit Rec is input, and the V _SS terminal negative voltage rectified by the rectifier circuit Rec is input, the Yes.

Further, the first regulator Reg1, while utilizing the negative voltage as the power supply voltage V _SS, thereby stabilizing the positive voltage input and outputs to the memory circuit Mem and a control circuit Cnt.

  Details of the first regulator Reg1 in this embodiment will be described later together with details of the second regulator Reg2.

The second regulator Reg2 is a an external input terminal TI to the negative voltage rectified by the rectifier circuit Rec is input, a V _SS terminal positive voltage rectified by the rectifier circuit Rec is input, the Yes.

Further, the second regulator Reg2, while utilizing the positive voltage as a power supply voltage V _SS, thereby stabilizing the negative voltage input and outputs to the memory circuit Mem and a control circuit Cnt.

  Note that details of the second regulator Reg2 in the present embodiment will be described later together with details of the first regulator Reg1, as described above.

  The induced voltage output from the antenna circuit Ant is input to the detection circuit Dtc. The detection circuit Dtc extracts transmission data transmitted by the reader / writer from the input induced voltage. It has become. The detection circuit Dtc outputs the extracted transmission data to the control circuit Cnt.

  Based on the control of the control circuit Cnt, the transmission circuit SC changes the impedance of the antenna circuit Ant to generate a demagnetizing field in the antenna circuit Ant so as to control load modulation for transmitting information to the reader / writer. It has become.

  Specifically, the transmission circuit SC of this embodiment includes a load modulation capacitor C40 for changing the impedance, a switching FET for switching the impedance change, and a gate of the switching FET 53 under the control of the control circuit Cnt. It is composed of a level shift circuit unit 54 for a transmission circuit that performs level shift of an applied voltage.

  Details of the configuration and operation of the transmission circuit SC in this embodiment will be described later.

  The memory circuit Mem stores in advance identification information such as a mask ROM (Read Only Memory) such as a mask tag (Read Only Memory) and other read-only information, as well as an EEPEROM (Electrically Erasable Read Only Memory). And predetermined information that is read and written based on communication with a reader / writer such as FeRAM (Ferroelectric Random Access Memory).

  The memory circuit Mem is configured such that predetermined information is read or written under the control of the control circuit Cnt.

  In the memory circuit Mem of this embodiment, read-only information and predetermined information to be read and written are stored, but only one of the information may be stored.

  The control circuit Cnt is connected to the memory circuit Mem via the bus B, and controls the memory circuit Mem and the transmission circuit SC based on the information acquired by the detection circuit Dtc. For example, information to the memory circuit Mem Or reading information from the memory circuit Mem, transmitting information read from the memory circuit Mem via the transmission circuit SC, and various controls associated therewith.

  The control circuit Cnt is constituted by various logic circuits such as an inverter circuit, a NAND circuit, or a NOR circuit, and constitutes a circuit according to the function of the RFID tag device Tag.

  The control circuit Cnt drives various logic circuits such as an inverter circuit, a NAND circuit, and a NOR circuit using the positive voltage and the negative voltage output from the first regulator Reg1 and the second regulator Reg2. Yes.

  Details of various logic circuits constituting the control circuit Cnt in the present embodiment will be described later.

  Next, details of the first regulator Reg1 and the second regulator Reg2 in the present embodiment will be described with reference to FIG.

  FIG. 5 is a block diagram showing the configuration of the first regulator Reg1 and the second regulator Reg2 in the present embodiment.

  As shown in FIG. 5, the first regulator Reg1 of the present embodiment includes an operational amplifier OP, an output control n-type FET 310 for controlling the output of a positive DC voltage input to perform constant voltage output, and an operational amplifier. An input voltage adjusting n-type FET 320 for adjusting the voltage for input to the OP, an input voltage adjusting resistor 330 for adjusting the voltage for input to the operational amplifier OP, and an output adjustment for adjusting the output voltage Capacitor 340.

The operational amplifier OP includes a first input terminal T10-1 to which a first input voltage (for example, a reference voltage) is input, and a second input terminal to which a second input voltage (for example, a monitoring voltage for output fluctuation) is input. and T10-2, outputs a _{V DD} terminal to the positive supply voltage _{V DD} is input, a _{V SS} terminal a negative supply voltage _{V SS} is input, a ground terminal that is grounded, the amplified voltage The output terminal T20 has five terminals.

  The first input terminal T10-1 is connected to the external input terminal TI via an input voltage adjusting first resistor, and the first input terminal T10-1 is connected to an input voltage adjusting second resistor. It is connected to the external output terminal TO through a resistor.

An external input terminal TI is connected to the V _DD terminal, and an external power supply voltage _VSS is applied to the V _SS terminal.

  The details of the operational amplifier used in the first regulator Reg1 in this embodiment will be described later.

  The output control n-type FET 310 is a depletion-type n-type FET that can be manufactured by the same process as each depletion type FET constituting the operational amplifier OP, and includes a gate to which the output voltage of the operational amplifier OP is applied, and an external input. The drain is connected to the terminal TI and the source is connected to the external output terminal TO.

  For example, the input voltage adjusting n-type FET 320 of the present embodiment is a depletion type n-type FET that can be manufactured by the same process as each depletion type FET constituting the operational amplifier OP, and has a width of 30 mm. A channel having a length of 1 μm is provided.

  The input voltage adjusting n-type FET 320 includes a gate connected to the external input terminal TI, a drain connected to the external input terminal TI and the gate via the input voltage adjusting first resistor, and a source grounded to the ground. And.

  For example, the input voltage adjusting n-type FET 320 of this embodiment is a depletion-type n-type FET, and includes a channel having a width of 50 μm and a length of 20 μm.

  The input voltage adjusting first resistor 330-1 is an n-type diffusion resistor that can be manufactured by the same process as each of the diffusion resistors constituting the operational amplifier OP, and includes an external input terminal TI and an input voltage adjusting n-type. The FETs 320 are connected in series and have a resistance value of 200 kΩ, for example.

  The second resistor 330-2 for adjusting input voltage and the third resistor 330-3 for adjusting input voltage are n-type diffused resistors that can be manufactured by the same process as each diffused resistor constituting the operational amplifier OP. The connection is made in series between the drain of the output control n-type FET 310 and the ground terminal, and the input voltage adjusting second resistor 330-2 and the input voltage adjusting third resistor 330-3 are connected. The point is connected to the second input terminal T10-2 of the operational amplifier OP.

  For example, the second resistor 330-2 for input voltage adjustment of the present embodiment has a resistance value of 300 kΩ, and the third resistor 330-3 for input voltage adjustment has a resistance value of 500 kΩ.

  The output adjustment capacitor 340 has, for example, a capacity of 100 pF, is connected in series between the external output terminal TO and the ground, and serves as a smoothing capacitor for adjusting the voltage output from the external output terminal TO. It has come to be used.

The second regulator Reg2 of this embodiment, a negative voltage with used as an input voltage, other configurations except for using a positive voltage to the power supply voltage V _SS has the same configuration as the first regulator Reg1.

That is, the operational amplifier OP of the second regulator Reg2 includes a first input terminal T10-1 to which a first voltage is input, a second input terminal T10-2 to which a second voltage is input, and a negative power supply voltage V. Yes and V _{DD terminal DD} is input, and V _SS terminal positive supply voltage V _SS is input, a ground terminal that is grounded, an output terminal T20 for outputting the amplified voltage, a fifth terminal of the is doing.

  In addition, since the other structure of 2nd regulator Reg2 in this embodiment is the same as 1st regulator Reg1, the description is abbreviate | omitted.

  Next, details of the operational amplifiers used in the first regulator Reg1 and the second regulator Reg2 of this embodiment will be described with reference to FIG.

  FIG. 6 is a block diagram showing the configuration of the operational amplifier OP in the present embodiment.

  As shown in FIG. 6, the operational amplifier OP of the present embodiment is composed of a plurality of depletion type FETs and diffusion resistors, and a differential amplifier circuit 210 that amplifies the difference between two input voltages that are input, and the operational amplifier OP. A bias circuit 220 for supplying a bias power, a phase compensation capacitor 230, a source ground amplifier circuit 240 for further amplifying the voltage level of the input voltage differentially amplified by the differential amplifier circuit 210 and outputting the same to the outside, Consists of

  In particular, in the operational amplifier OP of the present embodiment, the common source amplifier circuit 240 as well as the differential amplifier circuit 210 are configured by a plurality of depletion type FETs.

  The common-source amplifier circuit 240 of the present embodiment inverts and amplifies the voltage level of the operational amplifier level shift circuit unit 250 that shifts the voltage level of the voltage output from the differential amplifier circuit 210 and the level-shifted voltage. And an amplifier circuit unit 260.

  That is, since the operational amplifier OP of this embodiment uses a depletion type FET as described above, the operational amplifier level shifts the input voltage to the amplification circuit unit 260 to the negative side in accordance with the threshold voltage of the gate. The operational amplifier OP is provided with a shift circuit unit 250, the amplification circuit unit 260 is composed of a depletion type FET, and can be driven at high speed, and has good output characteristics.

  Specifically, the differential amplifier circuit 210 includes two depletion-type input n-type FETs 212, an output adjusting first diffusion resistor 213, and a current source n-type FET that functions as a current source. Is composed of.

  The first n-type FET 211 is a depletion type FET, and is composed of a polysilicon TFT, an oxide TFT, or an organic transistor.

The first n-type FET 211 has a gate connected to the first input terminal T10-1 to which the first input voltage is applied, a drain connected to the power supply voltage V _DD , and a source of the second n-type FET 212. And a source to be the n-type FET 214 for current source.

  Similar to the first n-type FET 211, the second n-type FET 212 is a depletion type FET, and is composed of a polysilicon TFT, an oxide TFT, or an organic transistor, and forms a current mirror with the first n-type FET 211. Yes.

The second n-type FET 212 has a gate connected to the second input terminal T10-2 to which the second input voltage is applied, a drain connected to the power supply voltage V _DD , and a source of the first n-type FET 211. And a source to be the n-type FET 214 for current source.

The first diffusion resistor 213 is an n-type diffusion resistor and can be manufactured by the same process as each n-type FET. The first diffusion resistor 213 is connected to the power supply voltage V _DD and the drain of the second n-type FET 212.

  The output terminal of the differential amplifier circuit 210 is configured between the first diffusion resistor 213 and the drain of the second n-type FET 212.

  Similar to the first n-type FET 211 and the second n-type FET 212, the current-source n-type FET 214 is a depletion type FET, and is configured by a polysilicon TFT, an oxide TFT, or an organic transistor. A mirror is configured.

The n-type FET 214 for current source has a gate connected to the power supply voltage V _DD via a second diffusion resistor 222, which will be described later, and a drain connected to the sources of the first n-type FET 211 and the second n-type FET 212. And a source grounded to the ground.

  The bias circuit 220 of the present embodiment is configured as a differential amplifier circuit 210 and a current mirror, and includes a second diffusion resistor 222 and a bias n-type FET 121.

Note that the bias circuit 220 of the present embodiment operates in conjunction with the current source n-type FET 214 to set the reference voltage to the first n-type FET 211 and the second n-type in the differential amplifier circuit 210 from the intermediate potential of (power supply voltage V _DD / 2). A value obtained by subtracting the threshold voltage value of the FET 212 is used.

  Thus, the depletion type first n-type FET 211 and second n-type FET 212 can be operated in the saturation region, so that the capability of each FET can be utilized to the maximum.

Similar to the first diffusion resistor 213, the second diffusion resistor 222 is an n-type diffusion resistor, and can be manufactured by the same process as each n-type FET. The first diffusion resistor 213 is connected to the power supply voltage V _DD and the drain of the bias n-type FET 121.

  Like the first n-type FET 211 and the second n-type FET 212, the bias n-type FET 121 is a depletion type FET, and is configured by a polysilicon TFT, an oxide TFT, or an organic transistor.

  The bias n-type FET 221 is grounded to the gate connected to the second diffusion resistor 222 and the current source n-type FET 214, the gate short-circuited and connected to the second diffusion resistor 222, and ground. Source.

  The phase compensation capacitor 230 of the present embodiment is connected between the output terminal of the differential amplifier circuit 210 unit and the ground, and is used to suppress oscillation of the operational amplifier OP.

  The common-source amplifier circuit 240 of this embodiment is composed of two depletion type FETs, and is composed of an operational amplifier level shift circuit unit 250 that shifts the voltage level of the input voltage in the negative direction, and two depletion type FETs. And an amplification circuit unit 260 that inverts and amplifies the voltage level of the shifted voltage.

  As shown in FIG. 1, the operational amplifier level shift circuit unit 250 shifts the level of the voltage output from the differential amplifier circuit 210 in the negative direction and outputs it to the amplifier circuit unit 260.

In addition, the operational amplifier level shift circuit unit 250 includes two n-type FETs 251 and 252 that can be manufactured in the same process as the depletion-type FETs constituting the differential amplifier circuit 210 and the bias circuit 220. The FET includes a plurality of applied voltage adjusting diffusion resistors R1 and R2 for adjusting the power supply voltage V _DD .

  The third n-type FET 251 is a depletion type FET, similar to each depletion type FET constituting the differential amplifier circuit 210 and the bias circuit 220, and is constituted by a polysilicon TFT, an oxide TFT, or an organic transistor.

The third n-type FET 251 is connected to the output terminal of the differential amplifier circuit 210, to which a voltage output from the differential family circuit is applied, a drain connected to the power supply voltage V _DD , and a second n And a source connected to the output terminal of the operational amplifier level shift circuit unit 250 while being connected to the gate and drain of the type FET 212.

  The fourth n-type FET 252 is a depletion type FET, similar to each depletion type FET constituting the differential amplifier circuit 210 and the bias circuit 220, and is constituted by a polysilicon TFT, an oxide TFT or an organic transistor.

The fourth n-type FET 252 is connected to the gate connected to the power supply voltage V _DD via the second diffusion resistor 222, the source of the third n-type FET 251 and the output terminal of the operational amplifier level shift circuit unit 250. a drain, a source connected to the power supply voltage V _SS, composed.

  The plurality of diffusion resistors R for adjusting the applied voltage are n-type diffusion resistors, similar to the first diffusion resistor 213 and the second diffusion resistor 222, and can be manufactured in the same process as each n-type FET. It has become.

For example, the diffusion resistor R applied voltage adjustment of this embodiment is a two diffusion resistors R1, R2, these diffusion resistors R1, R2 are in series power supply voltage _{V SS} and the 4n-type FET252 Connected with the source. Further, the first end point of one diffusion resistor R1 and the second end point of another diffusion resistor R2 are connected, and the second end point of one diffusion resistor R1 and the first end point of another diffusion resistor R2 are connected. Are connected, and a power supply voltage _VSS is connected to a second end point of one diffusion resistor R1 and a first end point of another diffusion resistor R2.

Then, after the generation of the operational amplifier OP, based on the characteristics of the operational amplifier for level shifting circuit unit 250, adjusts the power supply voltage V _SS by changing the connection of the diffusion resistors R1, R2, i.e., the power supply voltage by thinning out the resistor V _SS is adjusted.

  The amplifier circuit unit 260 of this embodiment is configured to invert and amplify the voltage level of the voltage output from the operational amplifier level shift circuit unit 250 and output it to the output terminal T20.

  The amplifier circuit unit 260 includes a fifth n-type FET 261 and a third diffusion resistor 262 that can be manufactured by the same process as the depletion type FETs constituting the differential amplifier circuit 210 and the bias circuit 220.

  The fifth n-type FET 261 is a depletion type FET, similar to each depletion type FET constituting the differential amplifier circuit 210 and the bias circuit 220, and is constituted by a polysilicon TFT, an oxide TFT or an organic transistor.

  The fifth n-type FET 261 includes a gate to which the voltage output from the operational amplifier level shift circuit unit 250 is applied, a drain connected to the output terminal T20 in the amplifier circuit unit 260, and a source grounded to the ground. Composed.

  The third diffusion resistor 262 is an n-type diffusion resistor, like the first diffusion resistor 213 and the second diffusion resistor 222, and can be manufactured by the same process as each n-type FET. .

The third diffusion resistor 262 is connected to the power supply voltage V _DD and the drain of the fifth n-type FET 261 to adjust the output of the amplifier circuit unit 260.

  Next, the configuration and operation of the transmission circuit SC in the present embodiment will be described in detail with reference to FIG.

  As described above, the transmission circuit SC of the present embodiment has the load modulation capacitor C40 for changing the impedance, the switching FET 53 for switching the impedance change, and the gate of the switching FET 53 under the control of the control circuit Cnt. It is composed of a level shift circuit unit 54 for a transmission circuit that performs level shift of an applied voltage.

  This transmission circuit SC uses a depletion type FET for the switching FET 53. Therefore, as described above, in order to drive the switching FET 53 accurately, the transmission circuit level shift circuit unit 54 is provided in the preceding stage.

  The load modulation capacitor C40 is connected in parallel with the antenna coil A10 of the antenna circuit Ant and the resonance capacitor C10 together with the switching FET 53, and is connected to the first terminal connected to one end of the antenna circuit Ant and the drain of the switching FET 53. And a second terminal.

  The load modulation capacitor C40 is used to change the impedance of the antenna circuit Ant as the switching FET 53 is driven.

  The switching FET 53 is configured by a depletion type n-type FET so that it can be manufactured by the same process as a depletion type FET in other internal circuits. Like each depletion type FET, a polysilicon TFT, an oxide TFT or It is composed of organic transistors.

  The switching FET 53 has a gate to which the voltage output from the transmission circuit level shift circuit unit 54 is applied, a drain connected to the first terminal of the load modulation capacitor C40, and the other end of the antenna circuit Ant. Consists of a source grounded to ground.

The transmission circuit level shift circuit unit 54 shifts the voltage level of the voltage output from the control circuit Cnt to the minus side. Similarly to the operational amplifier level shift circuit unit 250, other depletions are provided. and two n-type FET can prepare in type FET and the same process, a plurality of the applied voltage adjusting diffusion resistors R1, R2 for adjusting the power supply voltage V _SS, composed.

  Note that the transmission circuit level shift circuit unit 54 of the present embodiment is the same as the operational amplifier level shift circuit unit 250, and therefore detailed description thereof is omitted.

  Next, details of various logic circuits constituting the control circuit Cnt in the present embodiment will be described with reference to FIGS.

  FIG. 7 is a block diagram showing the configuration of the inverter circuit in the present embodiment, and FIG. 8 is a block diagram showing the configuration of the NAND circuit in the present embodiment. FIG. 9 is a block diagram showing the configuration of the NOR in this embodiment.

  As described above, the control circuit Cnt of the present embodiment is configured by various logic circuits such as an inverter circuit, a NAND circuit, or a NOR circuit, and also configures a circuit according to the function of the RFID tag device Tag. Yes.

  Here, an inverter circuit, a NAND circuit, or a NOR circuit will be described as an example, but the circuit constituting the control circuit Cnt is not limited thereto.

(Inverter circuit)
First, the inverter circuit 100-1 including the level shift circuit unit 110 and the inverter circuit unit 120 according to this embodiment will be described with reference to FIG.

  As shown in FIG. 7, the inverter circuit 100-1 according to the present embodiment is composed of two depletion type FETs, and includes a level shift circuit unit 110 that shifts the voltage level of the input voltage in the negative direction, and two depletion type FETs. And an inverter circuit unit 120 that inverts the logic output using the level-shifted input voltage.

  As shown in FIG. 7, the level shift circuit unit 110 shifts the voltage level of the input voltage input via the input terminal 10 in the negative direction and outputs the result to the inverter circuit unit 120.

  The level shift circuit unit 110 includes two n-type FETs, a first n-type FET 111 and a second n-type FET 112, which can be manufactured by the same process.

  The first n-type FET 111 is a depletion type FET, and is constituted by a polysilicon TFT, an oxide TFT, or an organic transistor, and includes a channel having a width of 100 μm and a length of 10 μm, for example.

The first n-type FET 111 is connected to the input terminal 10, connected to the gate to which the input voltage is applied, the drain connected to the power supply voltage V _DD , the gate and the drain of the second n-type FET 112, and And a source connected to the output terminal of the level shift circuit unit 110 (that is, the input terminal of the inverter circuit unit 120).

In the present embodiment, the power supply voltage V _DD has a predetermined voltage value determined in advance. For example, a voltage of +10 V is applied to the drain of the first n-type FET 111.

  The second n-type FET 112 is a depletion-type FET, like the first n-type FET 111, and is composed of a polysilicon TFT, an oxide TFT, or an organic transistor, and has a width of 100 μm and a length of 10 μm, for example. With a channel.

The second n-type FET 112 is connected to the source of the first n-type FET, connected to the output terminal of the level shift circuit unit 110, and the drain connected to the gate and the source of the first n-type FET 111 in a short circuit. source and consists of which is connected to the negative supply voltage V _SS.

  The inverter circuit unit 120 of the present embodiment inverts the logic output based on the input voltage input from the input terminal 10 based on the voltage output from the level shift circuit unit 110 and outputs the result to the output terminal 20. Yes.

  The inverter circuit unit 120 includes two n-type FETs, a third n-type FET 121 and a fourth n-type FET 122, which can be manufactured by the same process as the first n-type FET 111 and the second n-type FET 112 in the level circuit unit.

  The third n-type FET 121 is a depletion type FET, similar to the first n-type FET 111 and the second n-type FET 112, and is composed of a polysilicon TFT, an oxide TFT, or an organic transistor, and has a width of 100 μm and a thickness of 10 μm, for example. A channel having a length is provided.

  The third n-type FET 121 includes a gate to which the voltage output from the level shift circuit unit 110 is applied, a drain connected to the output terminal 20, and a source grounded to the ground.

  Similar to the first n-type FET 111, the second n-type FET 112, and the third n-type FET 121, the fourth n-type FET 122 is a depletion type FET, and is configured by a polysilicon TFT, an oxide TFT, or an organic transistor, and has a thickness of 100 μm, for example. A channel having a width and a length of 10 μm is provided.

The fourth n-type FET 122 includes a gate connected to the output terminal 20, a drain connected to the power supply voltage V _DD , a short-circuit connected to the gate, and a source connected to the output terminal 20 together with the gate. Composed.

(NAND circuit)
Next, the NAND circuit 100-2 of this embodiment will be described with reference to FIG.

  As shown in FIG. 8, the NAND circuit 100-2 of the present embodiment is a digital circuit that performs, for example, a NAND operation of three inputs and one output, and is a first level shift circuit unit 110- provided at each input. 1 and a second level shift circuit unit 110-2 and a third level shift circuit unit 110-3, and a NAND circuit unit 130 that performs a NAND operation based on each input voltage whose level has been shifted. Is done.

  Each of the first, second, and third level shift circuit units 110 has a first input terminal 10-1, a second input terminal 10-2, and a third input terminal 10-3 in the same manner as the inverter circuit 100-1. The input level of each input voltage input via each is shifted to the minus side and output to the NAND circuit unit 130.

  Each of the first, second, and third level shift circuit units 110 includes two n-types of a first n-type FET 111 and a second n-type FET 112 that can be manufactured by the same process, similarly to the inverter circuit 100-1. Type FET.

  The NAND circuit unit 130 outputs, to the output terminal 20, an operation result of the negative OR based on the input voltage of three inputs based on each voltage output from the first, second, and third level shift circuit units 110. It has become.

The NAND circuit unit 130 includes three third n-type FETs 121 corresponding to the respective inputs, and a single fourth n-type FET 122 for adjusting the load of the power supply voltage V _DD .

  Each third n-type FET 121 is arranged in series between the source of the fourth n-type FET 122 and the ground reference potential.

  Each of the third n-type FETs 121 has a gate connected to the output of each level shift circuit unit 110, and the corresponding drain-source is connected based on the output voltage output from each level shift circuit unit 110. Energized.

The fourth n-type FET 122 has a gate, a source that is short-circuited to the gate and connected to the output terminal 20 and the drain of one third n-type FET 121, a drain to which the power supply voltage V _DD is applied as a reference voltage, And is used to adjust the load of the power supply voltage V _DD .

(NOR circuit)
Next, the NOR circuit 100-3 of this embodiment will be described with reference to FIG.

  As shown in FIG. 9, the NOR circuit 100-3 of the present embodiment is a digital circuit that performs a negative OR output of, for example, three inputs and one output, and is a first level shift circuit unit 110- provided at each input. 1, a second level shift circuit unit 110-2 and a third level shift circuit unit 110-3, and a NOR circuit unit 140 that performs a NAND operation based on the input voltage whose level is shifted. The

  Each of the first, second, and third level shift circuit units 110 has a first input terminal 10-1, a second input terminal 10-2, and a third input terminal 10-3 in the same manner as the inverter circuit 100-1. The input level of each input voltage input via each is shifted to the negative side and output to the NOR circuit unit 140.

  Each of the first, second, and third level shift circuit units 110 includes two n-types of a first n-type FET 111 and a second n-type FET 112 that can be manufactured by the same process, similarly to the inverter circuit 100-1. Type FET.

  The NOR circuit unit 140 outputs, to the output terminal 20, an operation result of the negative logical product based on the input voltage of three inputs based on each voltage output from the first, second, and third level shift circuit units 110. It has become.

The NOR circuit unit 140 includes three third n-type FETs 121 corresponding to the respective inputs and a single fourth n-type FET 122 for adjusting the load of the power supply voltage V _DD .

  Each third n-type FET 121 is disposed in parallel between the source of the fourth n-type FET 122 and the ground reference potential.

  Each of the third n-type FETs 121 has a gate connected to the output of each level shift circuit unit 110. Based on the output voltage output from each level shift circuit unit 110, the third n-type FET 121 is connected between the output terminal 20 and the grind ground. Are to be short-circuited.

The fourth n-type FET 122 includes a gate, a source that is short-circuited to the gate and connected to the output terminal 20 and the drain of each third n-type FET 121, and a drain to which the power supply voltage V _DD is applied as a reference voltage. , And is used to adjust the load of the power supply voltage V _DD .

  As described above, the RFID tag device Tag according to the present embodiment can generate a DC negative voltage together with a DC positive voltage from an induced voltage generated in the antenna coil A10. Therefore, the entire device is driven by the DC negative voltage. Can do.

  Therefore, the RFID tag device Tag of the present embodiment uses a depletion type FET for each internal circuit, so that it can be driven at high speed even when it is generated at a low temperature by printing or the like and obtains good output characteristics. And the device itself can be easily manufactured.

  In particular, the RFID tag device Tag of the present embodiment can configure the FET in each internal circuit as a depletion type n-type, and therefore can generate the FET by a single process at the time of manufacture.

  Further, since the RFID tag device Tag according to the present embodiment can provide each internal circuit with a stable voltage in the DC negative voltage as well as the DC positive voltage, the breakdown voltage in each element of the internal circuit such as the FET is exceeded. Can be prevented from being damaged, and each circuit can be generated in accordance with the stabilized DC positive voltage and DC negative voltage, which simplifies the device manufacturing process.

  Further, the RFID tag device Tag of the present embodiment can input a voltage for control within a range in which the transistor is appropriately driven to the depletion type switching FET 53 in the transmission circuit SC. The switching FET 53 can be driven accurately.

  Further, since the parallel connection of the load modulation capacitor C40 and the resonance capacitor C10 in the switching transistor of the present embodiment can be switched, the load (impedance) of the data transmission / reception circuit based on the reader / writer can be accurately determined. Can be changed.

  Accordingly, the RFID tag device Tag according to the present embodiment can increase the degree of modulation in the load modulation in accordance with the change in the impedance of the transmission circuit SC, and therefore can accurately transmit predetermined data to the reader / writer. At the same time, the depletion type switching FET 53 widens the driveable voltage, so that the signal transmitted from the reader / writer reader / writer can be efficiently obtained from the induced voltage, and the DC positive voltage and DC negative voltage can be efficiently obtained. Can be generated automatically.

Tag ... RFID tag device Ant ... Antenna circuit Rec ... Rectifier circuit Reg1 ... First regulator Reg2 ... Second regulator Mem ... Memory circuit
Cnt ... control circuit B ... bus A10 ... antenna coil C10 ... resonance capacitor C20 ... (for rectifier circuit) first smoothing capacitor C30 ... (for rectifier circuit) second smoothing capacitor C40 ... load modulation capacitors R1, R2 ... applied voltage Diffusion resistor for adjustment TI ... External input terminal TO ... External output terminal T10 ... Input terminal T20 ... Output terminal OP ... Operational amplifier 10 ... Input terminal 20 ... Output terminal 51 ... (for rectifier circuit) 1st n-type FET
52 ... (for rectifier circuit) 2nd n-type FET
53… Switching FET
54 ... (for transmission circuit) level shift circuit unit 100-1 ... inverter circuit 100-2 ... NAND circuit 100-3 ... NOR circuit 110 ... level shift circuit unit 111 ... first n-type FET
112 ... 2nd n-type FET
120: Inverter circuit 121: Third n-type FET
122… 4th n-type FET
130 ... NAND circuit unit 140 ... NOR circuit unit 210 ... Differential amplifier circuit 211 ... First n-type FET
212 ... 2nd n-type FET
213: First diffusion resistor 214: n-type FET for current source
220 ... Bias circuit 221 ... Bias n-type FET
222 ... second diffusion resistor 230 ... phase compensation capacitor 240 ... common source amplifier circuit 250 ... operational amplifier level shift circuit unit 251 ... third n-type FET
252 ... 4th n-type FET
260 ... Amplifier circuit unit 261 ... 5th n-type FET
262 ... Third diffusion resistor 300 ... Regulator 310 ... Output control n-type FET
320 ... n-type FET for input voltage adjustment
330 ... Input voltage adjusting resistor 340 ... Output adjusting capacitor

Claims (6)

A non-contact information terminal device that performs transmission and reception of data with a read / write device using a magnetic field in a non-contact manner,
An antenna circuit for generating an induced voltage in response to a magnetic field generated by the read / write device;
A rectifier circuit that extracts a DC power supply voltage based on the generated induced voltage;
Storage means for storing predetermined information, the storage means operating based on the DC power supply voltage output from the rectifier circuit;
With
The rectifier circuit is
A depletion-type first transistor that performs half-wave rectification to extract a positive DC voltage as a positive power source based on the generated induced voltage;
A depletion-type second transistor that performs half-wave rectification to extract a DC negative voltage as a negative power source based on the generated induced voltage;
A first smoothing capacitor connected between the first transistor and ground and used for smoothing;
A second smoothing capacitor connected between the second transistor and ground and used for smoothing;
A non-contact information terminal device comprising: In the non-contact information terminal device according to claim 1,
All the transistors used for the non-contact information terminal device including the first transistor and the second transistor are constituted by n-type transistors. In the non-contact information terminal device according to claim 1 or 2,
A first constant voltage output circuit that has a voltage amplification circuit and converts the positive DC voltage generated by the rectifier circuit into a constant voltage;
A second constant voltage output circuit having a voltage amplification circuit and converting a DC negative voltage generated by the rectifier circuit to a constant voltage;
A non-contact information terminal device comprising: In the non-contact information terminal device according to claim 3,
Each of the voltage amplification circuits is
A differential amplifier circuit configured by a plurality of third transistors and a diffusion resistor, and amplifying and outputting a voltage level difference between a DC positive voltage and a DC negative voltage output from the rectifier circuit;
An output amplifier circuit that amplifies and outputs the voltage level of the voltage output from the differential amplifier circuit;
With
All of the transistors provided in the differential amplifier circuit and the output amplifier circuit are depletion type,
The output amplifier circuit is
A level shift circuit unit configured by one or more fourth transistors and configured to shift a voltage level of a voltage output from the differential amplifier circuit;
An amplification circuit unit that includes one or more fifth transistors and inverts and amplifies the voltage level of the level-shifted voltage;
The non-contact type information terminal device, wherein the differentially amplified and level-shifted voltage is input to a gate of at least one fifth transistor of the amplifier circuit unit. In the non-contact information terminal device according to any one of claims 1 to 3,
Further comprising control means for controlling storage means operating based on the DC power supply voltage output from the rectifier circuit;
The control means is
A level shift circuit unit configured by one or more sixth transistors to shift the voltage level output from the rectifier circuit;
An electronic circuit unit that includes one or more seventh transistors and that performs a predetermined logical operation using a level-shifted voltage;
With
All of the transistors provided in the level shift circuit unit and the electronic circuit unit are depletion type, and the level shifted voltage is input to the gate of at least one seventh transistor of the electronic circuit unit. A non-contact type information terminal device. In the non-contact information terminal device according to any one of claims 1 to 4,
The antenna circuit is
An antenna coil for generating the induced voltage;
A resonant capacitor constituting a resonant circuit with the antenna coil;
A load modulation capacitor connected in parallel to a resonance circuit formed by the antenna coil and the resonance capacitor and used for load modulation for changing a load value of the non-contact information terminal device based on the read / write device And a switching transistor,
A level shift circuit unit for shifting a voltage level for controlling the switching transistor;
Have
The contactless information terminal device, wherein the switching transistor is a depletion type.

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