JP2011040807A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus that reduces noise to degrade image quality and obtains high-quality images. <P>SOLUTION: The solid-state imaging apparatus includes: an effective pixel part 4; an optical black part 6; a vertical signal line 9 which is a signal line for reading pixel signals from a pixel 7 for each column comprising the pixels 7 arranged in parallel in a first direction; a row selection circuit 8 for selecting the pixel 7 for reading the pixel signals by a row comprising the pixels 7 arranged in parallel in a second direction; a column AD conversion circuit 2 for converting the pixel signals from the pixels 7 to digital signals, respectively; and a signal processing circuit 3 for obtaining image signals by arithmetically processing the digital signals obtained in the column AD conversion circuit 2. The signal processing circuit 3 calculates, for each column, a difference between the pixel signals from the pixels 7 of the effective pixel part 4 and the pixel signals from the pixels 7 of the optical black part 6. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  Conventionally, as an example of a solid-state imaging device, there is a CMOS image sensor including a column type analog-digital conversion circuit (column type AD conversion circuit). Known factors that degrade image quality in a CMOS image sensor equipped with a column-type AD converter circuit include vertical streak noise that is generated for each vertical line, horizontal streak noise that is generated for each horizontal line, and random noise generated for each pixel. It has been. Of these, horizontal streak noise is caused by fluctuations in the power supply at the moment when the switching transistor is turned off in the readout operation for each horizontal line, and the waveform of the reference voltage for AD conversion varies for each horizontal line. This occurs when the signal level fluctuates.

  As a technique for reducing the horizontal stripe noise, for example, a technique for uniformly subtracting the average value of the pixel signal of the optical black (OB) portion from the pixel signal of the effective pixel portion for each horizontal line has been proposed (for example, Patent Documents). 1 and 2). In the effective pixel portion, pixel cells each including a photoelectric conversion element are arranged in parallel, and an effective pixel signal corresponding to the light intensity is output. In the OB unit, pixel cells each including a light-shielded photoelectric conversion element are arranged in parallel, and a black level signal indicating the lowest gradation is output. Since the component causing the horizontal stripe noise is included in the effective pixel signal and the black level signal equally, the horizontal stripe noise is reduced by the subtraction process. However, when the average value of the black level signal is uniformly subtracted, random noise included in the black level signal is also uniformly added to the effective pixel signal, which may hinder the effect of reducing horizontal stripe noise. Cause problems.

JP 2006-157263 A JP 2008-288816 A

  An object of the present invention is to provide a solid-state imaging device capable of reducing noise that causes image quality degradation and obtaining a high-quality image.

  According to an aspect of the present invention, among the pixel units in which pixel cells each including a photoelectric conversion element are arranged in a two-dimensional direction, the effective pixel unit that makes light incident on the photoelectric conversion element, and the pixel unit, An optical black portion in which a photoelectric conversion element is shielded from light, and a signal line for reading a pixel signal from the pixel cell for each column including the pixel cells arranged in parallel in a first direction of the two-dimensional directions, Row selection for selecting the pixel cell from which the pixel signal is read through the signal line by a row of the pixel cells arranged in parallel in a second direction perpendicular to the first direction in the two-dimensional direction. A circuit, a column type AD conversion circuit that converts the pixel signal from the pixel cell selected by the row selection circuit into a digital signal, and the digital signal obtained by the column type AD conversion circuit. A signal processing circuit that obtains an image signal by performing an arithmetic processing on the pixel signal, and the signal processing circuit includes the pixel signal from the pixel cell of the effective pixel unit and the pixel cell of the optical black unit. The solid-state imaging device is characterized in that a difference between the pixel signal from the pixel signal is calculated for each column.

  According to the present invention, it is possible to reduce noise that causes image quality degradation and to obtain a high-quality image.

FIG. 1 is a schematic configuration diagram of a CMOS image sensor according to the first embodiment. FIG. 2 is a circuit block diagram of the CMOS image sensor. FIG. 3 is a schematic configuration diagram of a CMOS image sensor according to the second embodiment. FIG. 4 is a circuit block diagram of the CMOS image sensor. FIG. 5 is a circuit block diagram of a CMOS image sensor according to a comparative example.

  Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a schematic configuration diagram of a CMOS image sensor 10 which is a solid-state imaging device according to the first embodiment. The CMOS image sensor 10 includes a pixel unit 1, a column type AD conversion circuit 2, and a signal processing circuit 3.

  The pixel unit 1 has a plurality of pixel cells. Each pixel cell includes a photoelectric conversion element that converts light from a subject into a signal charge, and a detection unit that converts the signal charge into a voltage. The pixel cells are juxtaposed in a two-dimensional direction, a vertical direction and a horizontal direction. Here, in each figure, the vertical direction parallel to the paper surface is defined as the vertical direction (first direction), and the horizontal direction parallel to the paper surface is defined as the horizontal direction (second direction). The first direction and the second direction are orthogonal to each other.

  The pixel unit 1 includes an effective pixel unit 4 that allows light to enter the photoelectric conversion element, and an invalid pixel unit 5 that is shielded from the photoelectric conversion element. The OB portion 6 is located vertically below the effective pixel portion 4 in the invalid pixel portion 5. In the pixel unit 1, the effective pixel unit 4 and the OB unit 6 are provided in parallel in the vertical direction. The effective pixel portion 4 and the OB portion 6 have substantially the same width in the horizontal direction. The column type AD conversion circuit 2 converts the pixel signal from the pixel cell into a digital signal. The signal processing circuit 3 obtains an image signal by performing arithmetic processing on the digital signal obtained by the column type AD conversion circuit 2.

  FIG. 2 is a circuit block diagram of the CMOS image sensor 10. The pixel cells 7 of the effective pixel unit 4 are arranged in an array with m rows in the vertical direction and n columns in the horizontal direction. The pixel cell 7 of the effective pixel unit 4 outputs an effective pixel signal corresponding to the light intensity. The vertical signal line 9 is a signal line for reading out a pixel signal from the pixel cell 7 for each column including the pixel cells 7 arranged in parallel in the vertical direction. The pixel cells 7 of the OB unit 6 are arranged in an array with k rows in the vertical direction and n columns in the horizontal direction. The pixel cell 7 of the OB unit 6 outputs a black level signal indicating the lowest gradation. Each column of pixel cells 7 arranged in parallel in the vertical direction in the pixel unit 1 includes a pixel cell 7 of the effective pixel unit 4 and a pixel cell 7 of the OB unit 6.

  The row selection circuit 8 selects the pixel cell 7 from which the pixel signal is read out by a row including the pixel cells 7 arranged in parallel in the horizontal direction. A pixel signal from the pixel cell 7 selected by the row selection circuit 8 is read out through the vertical signal line 9. The column type AD conversion circuit 2 converts the image signal from the image cell 7 selected by the row selection circuit 8 into a digital signal.

The column type AD conversion circuit 2 includes a plurality of AD converters (ADC) 13. For the n columns of pixel cells 7, 2 × n ADCs 13 are provided in the column type AD conversion circuit 2.
The column type AD conversion circuit 2 reads the effective pixel signal read from the image cell 7 of the effective pixel unit 4 into a digital signal and the ADC 13 (first AD converter), and reads from the pixel cell 7 of the OB unit 6. The ADC 13 (second AD converter) that converts the output black level signal into a digital signal is arranged in parallel so as to alternate.

  For each column of pixel cells 7 arranged in parallel in the vertical direction in the pixel unit 1, a pair of ADCs 13 for effective pixel signals and ADCs 13 for black level signals are provided. There are n vertical signal lines 9 connected to the pixel cell 7 of the effective pixel unit 4 and the ADC 13 for the effective pixel signal. There are n vertical signal lines 9 connected to the pixel cell 7 of the OB unit 6 and the ADC 13 for black level signal. The effective pixel signal ADC 13 and the black level signal ADC 13 have the same circuit configuration.

  The signal processing circuit 3 outputs a difference signal 12 between the ADC 13 for effective pixel signals and the ADC 13 for black level signals provided for one column of pixel cells 7 arranged in parallel in the vertical direction. The signal processing circuit 3 calculates the difference between the effective pixel signal converted into the digital signal and the black level signal for each column including the pixel cells 7 arranged in parallel in the vertical direction.

  Here, before describing the operation of the CMOS image sensor 10 according to the present embodiment, the configuration and operation of a typical conventional CMOS image sensor will be described. FIG. 5 is a circuit block diagram of a CMOS image sensor 30 according to a comparative example of the present embodiment. The pixel unit 1 of the CMOS image sensor 30 includes an OB unit 6 arranged in parallel with the effective pixel unit 4 in the horizontal direction. Each row of pixel cells 7 arranged in parallel in the horizontal direction in the pixel unit 1 includes a pixel cell 7 in the effective pixel unit 4 and a pixel cell 7 in the OB unit 6. The ADC 13 is provided for each column of pixel cells 7 arranged in parallel in the vertical direction in the effective pixel unit 4 and each column of pixel cells 7 arranged in parallel in the vertical direction in the OB unit 6.

  When the row selection circuit 8 selects a row, an effective pixel signal is read from the pixel cell 7 in the selected row in the effective pixel unit 4. Further, a black level signal is read from the pixel cells 7 in the selected row of the OB unit 6. The signal processing circuit 3 performs an averaging process on each black level signal read from the pixel cell 7 selected in the OB unit 6 and calculates an OB average value 31. Further, the signal processing circuit 3 calculates a difference from the OB average value 31 for each effective pixel signal read from the pixel cell 7 selected in the effective pixel unit 4.

  As factors that degrade the image quality in the CMOS image sensor 30, vertical stripe noise (Column Noise) generated for each vertical line, horizontal stripe noise (Row Noise) generated for each horizontal line, and random noise generated for each pixel cell 7 are known. Yes. In particular, the vertical streak noise and the horizontal streak noise that are generated in a linear shape are easily noticeable even if they are slight, so correction that reduces them as much as possible is necessary.

  Longitudinal streak noise is mostly caused by FPN (Fixed Pattern Noise), and a corresponding portion is removed by a technique such as CDS (Correlated Double Sampling). The horizontal streak noise is randomly generated mainly due to power supply fluctuation and reference voltage waveform fluctuation, and is difficult to remove.

  The fluctuation of the signal level that causes the horizontal stripe noise generated in the horizontal direction includes the effective pixel signal from the pixel cell 7 in the selected row of the effective pixel portion 4 and the pixel cell 7 in the selected row of the OB portion 6. Are equivalently included in the black level signal from. For this reason, the horizontal stripe noise is reduced by using the difference signal 12 as an image signal.

  Random noise generated for each pixel cell 7 is caused by flicker noise, thermal noise, or the like of the transistor of the pixel cell 7. If the OB average value 31 is uniformly subtracted from the effective pixel signal, random noise included in the black level signal is uniformly added to the effective pixel signal. If random noise of the black level signal is uniformly added to each effective pixel signal in the row selected by the row selection circuit 8, noise is generated for each horizontal line, and the effect of reducing the horizontal stripe noise may be hindered.

  By significantly increasing the number of pixel cells 7 in the horizontal direction in the OB unit 6 and taking the OB average value 31, the influence of random noise included in the black level signal can be reduced. For example, it is known that if the number of pixel cells 7 in the horizontal direction in the OB unit 6 is N times, random noise can be reduced to 1 / √N times by the averaging process. However, since the number of pixel cells 7 arranged in the pixel unit 1 is limited, an increase in the pixel cells 7 in the OB unit 6 causes a decrease in the pixel cells 7 in the effective pixel unit 4.

  Next, returning to FIG. 2, the operation of the CMOS image sensor 10 according to the present embodiment will be described. The row selection circuit 8 selects the row of the pixel cells 7 in the effective pixel portion 4 and the row of the pixel cells 7 in the OB portion 6.

  When the row selection circuit 8 selects a row, an effective pixel signal is output to the vertical signal line 9 connected to the pixel cell 7 of the effective pixel unit 4. A black level signal is output to the vertical signal line 9 connected to the pixel cell 7 of the OB unit 6. The effective pixel signal output from the pixel cell 7 of the effective pixel unit 4 and the black level signal output from the pixel cell 7 of the OB unit 6 are each converted into a digital signal by the ADC 13 and output to the signal processing circuit 3. The

  Next, the signal processing circuit 3 subtracts the black level signal value converted into the digital signal by the ADC 13 from the effective pixel signal value converted into the digital signal by the ADC 13 as signal processing for reducing horizontal stripe noise. Such signal processing is performed independently for each column of the pixel cells 7 between the effective pixel signal and the black level signal from the ADC 13 paired for each column of the pixel cells 7 arranged in parallel in the vertical direction. . Since the component causing the horizontal stripe noise is equally included in the effective pixel signal and the black level signal, the difference signal 12 from which the horizontal stripe noise component is removed is obtained by the subtraction process. By outputting the difference signal 12 as an image signal, an image with reduced horizontal stripe noise can be obtained.

  The CMOS image sensor 10 according to the present embodiment performs subtraction processing independently for each column of the pixel cells 7 arranged in parallel in the vertical direction, so that the black level signals from the plurality of pixel cells 7 in the OB unit 6 can be obtained. An averaging process becomes unnecessary. By eliminating the black level signal averaging process, random noise components included in the black level signal are not uniformly applied to the effective pixel signals in the row selected by the row selection circuit 8. By avoiding a random noise component from being uniformly applied to the pixel cells 7 arranged in parallel in the horizontal direction, it is possible to reduce noise generated for each horizontal line. As a result, it is possible to reduce noise that causes image quality degradation and to obtain a high-quality image.

(Second Embodiment)
FIG. 3 is a schematic configuration diagram of a CMOS image sensor 20 which is a solid-state imaging device according to the second embodiment. The CMOS image sensor 20 according to the present embodiment includes a first column type AD conversion circuit 21 and a second column type AD conversion circuit 22. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  The invalid pixel unit 5 includes a first OB unit 23 and a second OB unit 24. The first OB part 23 is located on the lower side of the invalid pixel part 5 with respect to the effective pixel part 4. The second OB unit 24 is positioned vertically above the effective pixel unit 4 in the invalid pixel unit 5. The first OB part 23 and the second OB part 24 are arranged at different positions. Both the first OB portion 23 and the second OB portion 24 have substantially the same width as the effective pixel portion 4 in the horizontal direction. The first OB unit 23 and the second OB unit 24 are provided in parallel in the vertical direction via the effective pixel unit 4.

  The first column type AD converter circuit 21 is provided at a position close to the first OB unit 23. The second column AD conversion circuit 22 is provided at a position close to the second OB unit 24. The first column type AD conversion circuit 21 and the second column type AD conversion circuit 22 are arranged at different positions. The first signal processing circuit 25 obtains an image signal by performing arithmetic processing on the digital signal obtained by the first column AD conversion circuit 21. The second signal processing circuit 26 obtains an image signal by performing arithmetic processing on the digital signal obtained by the second column type AD conversion circuit 22.

  FIG. 4 is a circuit block diagram of the CMOS image sensor 20. The pixel cells 7 of the first OB portion 23 are arranged in an array with k rows in the vertical direction and n columns in the horizontal direction. The pixel cells 7 of the second OB section 24 are also arranged in an array with k rows in the vertical direction and n columns in the horizontal direction. The pixel cell 7 of the first OB unit 23 and the pixel cell 7 of the second OB unit 24 output a black level signal. In each column of the pixel cells 7 arranged in parallel in the vertical direction in the pixel unit 1, the pixel cell 7 of the first OB unit 23, the pixel cell 7 of the effective pixel unit 4, and the pixel cell 7 of the second OB unit 24 are arranged. It is included.

  There are n vertical signal lines 9 connected to the pixel cells 7 of the effective pixel portion 4. The n vertical signal lines 9 are connected to the first column type AD converter circuit 21 at the lower end, and connected to the second column type AD converter circuit 22 at the upper end. , Alternate in the horizontal direction.

  The first column type AD conversion circuit 21 includes n ADCs 13. The first column AD conversion circuit 21 includes an ADC 13 (first AD converter) that converts an effective pixel signal read from the pixel cell 7 of the effective pixel unit 4 into a digital signal, and a first OB unit 23. The ADC 13 (second AD converter) for converting the black level signal read out from the pixel cell 7 into a digital signal is arranged in parallel so as to alternate.

  The second column AD conversion circuit 22 includes n ADCs 13. The second column AD conversion circuit 22 includes an ADC 13 (first AD converter) that converts an effective pixel signal read from the pixel cell 7 of the effective pixel unit 4 into a digital signal, and a second OB unit 24. The ADC 13 (second AD converter) for converting the black level signal read out from the pixel cell 7 into a digital signal is arranged in parallel so as to alternate. A configuration in which a pair of an effective pixel signal ADC 13 and a black level signal ADC 13 is vertically above and vertically below a column of pixel cells 7 arranged in parallel in the vertical direction in the pixel unit 1. And are arranged alternately.

  The first signal processing circuit 25 outputs the difference signal 12 between the ADC 13 for the effective pixel signal and the ADC 13 for the black level signal that are paired in the first column type AD conversion circuit 21. The second signal processing circuit 26 outputs the difference signal 12 between the ADC 13 for the effective pixel signal and the ADC 13 for the black level signal that are paired in the second column type AD conversion circuit 22.

  Next, the operation of the CMOS image sensor 20 will be described. The row selection circuit 8 selects a row of the pixel cell 7 for each of the effective pixel unit 4, the first OB unit 23, and the second OB unit 24. When the row selection circuit 8 selects a row, an effective pixel signal is output to the vertical signal line 9 connected to the pixel cell 7 of the effective pixel unit 4. Further, a black level signal is output to the vertical signal line 9 connected to the pixel cell 7 of the first OB portion 23 and to the vertical signal line 9 connected to the pixel cell 7 of the second OB portion 24. .

  The effective pixel signal from the pixel cell 7 connected to the first column AD conversion circuit 21 via the vertical signal line 9 in the effective pixel unit 4 and the black level from the pixel cell 7 of the first OB unit 23. Each signal is converted into a digital signal by the ADC 13 of the first column type AD converter circuit 21 and output to the first signal processing circuit 25. In the first signal processing circuit 25, the difference in which the horizontal stripe noise component has been removed by the subtraction process of subtracting the black level signal value converted into the digital signal by the ADC 13 from the effective pixel signal value converted into the digital signal by the ADC 13. A signal 12 is obtained.

  The effective pixel signal from the pixel cell 7 connected to the second column type AD converter circuit 22 through the vertical signal line 9 in the effective pixel unit 4 and the black level from the pixel cell 7 in the second OB unit 24. Each signal is converted into a digital signal by the ADC 13 of the second column type AD converter circuit 22 and output to the second signal processing circuit 26. In the second signal processing circuit 26, the difference in which the horizontal stripe noise component is removed by the subtraction process of subtracting the black level signal value converted into the digital signal by the ADC 13 from the effective pixel signal value converted into the digital signal by the ADC 13. A signal 12 is obtained.

  The CMOS image sensor 20 eliminates the black level signal averaging process by independently performing the subtraction process for each column of the pixel cells 7 arranged in parallel in the vertical direction. By avoiding a random noise component from being uniformly applied to the pixel cells 7 arranged in parallel in the horizontal direction, it is possible to reduce noise generated for each horizontal line. As a result, as in the first embodiment, it is possible to reduce noise that causes image quality degradation and obtain a high-quality image.

  In the CMOS image sensor 20, by arranging the ADC 13 separately in the first column type AD conversion circuit 21 and the second column type AD conversion circuit 22, it becomes easy to secure a space for arranging the ADC 13. The ADCs 13 can be arranged at substantially the same pitch as the pixel cells 7. In particular, the smaller the pixel cell 7 is, the more advantageous it is that the ADC 13 can be disposed with a margin.

  The first OB unit 23 and the second OB unit 24 are provided in parallel in the vertical direction via the effective pixel unit 4, so that the first OB unit 23 is provided in the vicinity of the first column type AD converter circuit 21. The second OB unit 24 can be arranged in the vicinity of the second column type AD converter circuit 22. The vertical signal lines 9 for reading out the black level signals from the first OB unit 23 and the second OB unit 24 can be arranged without penetrating the effective pixel unit 4. Thereby, the complexity of the wiring in the pixel portion 1 can be reduced.

  1 pixel unit, 2 column type AD converter circuit, 3 signal processing circuit, 4 effective pixel unit, 6 OB unit, 7 pixel cell, 10, 20 CMOS image sensor, 21 first column type AD converter circuit, 22 second Column type AD converter circuit, 23 1st OB part, 24 2nd OB part.

Claims (5)

Among the pixel units in which pixel cells each including a photoelectric conversion element are arranged in a two-dimensional direction, an effective pixel unit that allows light to enter the photoelectric conversion element;
Among the pixel portions, an optical black portion where the photoelectric conversion element is shielded from light,
A signal line for reading a pixel signal from the pixel cell for each column of the pixel cells arranged in parallel in the first direction of the two-dimensional directions;
Row selection for selecting the pixel cell from which the pixel signal is read through the signal line by a row of the pixel cells arranged in parallel in a second direction perpendicular to the first direction in the two-dimensional direction. Circuit,
A column AD conversion circuit for converting the pixel signals from the pixel cells selected by the row selection circuit into digital signals, respectively;
A signal processing circuit that obtains an image signal by performing arithmetic processing on the digital signal obtained by the column type AD conversion circuit,
The signal processing circuit calculates, for each column, a difference between the pixel signal from the pixel cell of the effective pixel portion and the pixel signal from the pixel cell of the optical black portion. Solid-state imaging device. The column type AD converter circuit includes a first AD converter that converts the pixel signal from the pixel cell of the effective pixel unit into the digital signal, and the pixel signal from the pixel cell of the optical black unit. A second AD converter for converting into the digital signal,
The solid-state imaging device according to claim 1, wherein the first AD converter and the second AD converter are provided for each of the columns.   3. The solid-state imaging device according to claim 1, wherein in the pixel portion, the effective pixel portion and the optical black portion are provided in parallel in the first direction. The optical black part includes a first optical black part, and a second optical black part arranged at a position different from the first optical black part in the pixel part,
The column type AD converter circuit includes:
A first column-type AD converter circuit that converts the pixel signal from the pixel cell of the effective pixel portion and the pixel signal from the pixel cell of the first optical black portion, respectively, into the digital signal;
A second column type AD converter circuit for converting the pixel signal from the pixel cell of the effective pixel portion and the pixel signal from the pixel cell of the second optical black portion, respectively, into the digital signal; The solid-state imaging device according to claim 1, further comprising:   5. The pixel portion, wherein the first optical black portion and the second optical black portion are provided in parallel in the first direction via the effective pixel portion. The solid-state imaging device described.

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