JP2011039135A - Display device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that when a display property having high speed response and high contrast is desired to obtain, the size of holding capacity is too large to achieve higher definition. <P>SOLUTION: A write-in transistor is separated from a drive transistor, electric charges are supplied stably to pixel electrodes by supplying an applied voltage to the pixel electrodes directly from either of a scanning line or a capacity line. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device and an electronic apparatus including the display device.

  Display devices using memory elements (memory) such as an electrophoretic display (hereinafter referred to as “EPD”) have a slow response speed but retain the same display state even after the power is turned off. Therefore, as an image display means replacing a printed matter on paper, it has begun to spread in the fields of electronic books, electronic posters, electronic leaflets, and the like. In these display devices, in order to improve display performance such as contrast, it is effective to drive the display element with a pixel circuit that is arranged and formed for each pixel and uses an active element such as a thin film transistor. In this specification, a substrate on which such a pixel circuit is formed is referred to as an active matrix substrate.

  As a specific configuration of the pixel circuit formed on the active matrix substrate, for example, as described in FIG. 5 in Patent Document 1 described above, a pixel circuit having one transistor and one capacitor is generally used. However, when a display element having a slow response speed is driven by an active matrix substrate on which such a pixel circuit is formed, high definition is hindered. That is, even if a desired voltage (potential) is applied to the pixel electrode in the display sequence, the active element is turned off (OFF) to enter a high impedance state, and then the pixel electrode voltage ( (Potential) is reduced, writing becomes insufficient to reach the original display state, resulting in a decrease in contrast. In order to prevent this voltage (potential) drop (writing shortage), it is necessary to increase the capacity of the capacitor (retention capacity). As a result, the area of the capacitor must be increased, which hinders high definition.

  As a solution to this problem, for example, as disclosed in Patent Document 2, a memory circuit using a CMOS SRAM configuration is provided in the pixel circuit, and a desired potential is stabilized with respect to the pixel electrode during the display sequence. If configured to be supplied, the voltage (potential) drop of the pixel electrode can be prevented, and such a problem does not occur.

Japanese Patent No. 3719172 JP 2003-84314 A

  However, when such a memory circuit is provided, the number of transistors increases, so that there is still a problem that high definition is difficult. In addition, since a CMOS process is required, there is a problem that the cost becomes higher as compared with the case of manufacturing by either NMOS or PMOS processes. Therefore, in a display device using a display element having a memory property (for example, EPD), a display device that has high definition and suppresses a decrease in display performance such as contrast is achieved by a technique that suppresses an increase in cost as much as possible. It was desired to provide.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following application examples.

  Application Example 1 Pixels arranged for each of a plurality of scanning lines, a plurality of data lines intersecting with the plurality of scanning lines, and a pixel provided corresponding to each intersection of the scanning lines and the data lines The pixel circuit includes a capacitor line provided along the scanning line, a pixel electrode, a first transistor, and a second transistor, and the first circuit includes a first transistor and a second transistor. In the transistor, a gate electrode is electrically connected to the scanning line, one of a source electrode or a drain electrode is electrically connected to the data line, and the other is electrically connected to the gate electrode of the second transistor, and the source electrode of the second transistor Alternatively, one of the drain electrodes is electrically connected to the scanning line or the capacitor line, and the other is electrically connected to the pixel electrode.

  According to this configuration, the voltage can be applied to the pixel electrode from the scanning line or the capacitor line by the second transistor whose on / off is controlled by the first transistor. As a result, since a stable voltage can be applied to the pixel electrode, the probability of occurrence of a problem such as insufficient writing is reduced. Therefore, it is possible to provide a display device in which a decrease in display performance such as contrast is suppressed. Further, since a separate power supply wiring for the second transistor is not required, a high-definition display device can be realized.

  Application Example 2 In the display device, in the pixel circuit, the first transistor is turned on, and a voltage for turning on the second transistor is applied to the gate electrode of the second transistor, and then the scanning is performed. The driving is performed so that a voltage corresponding to an image displayed by the pixel is applied to the pixel electrode from either the line or the capacitor line.

  According to this configuration, by controlling the voltage applied to the scan line and the data line, the first transistor controls the on / off of the second transistor, and by controlling the voltage of the scan line or the capacitor line, A voltage corresponding to the image to be displayed can be stably applied to the pixel electrode. Further, since a separate power supply wiring for the second transistor is not required, a high-definition display device can be realized.

  Application Example 3 In the display device, the two second transistors are provided, one of the two second transistors is a p-channel transistor and the other is an n-channel transistor, and the source electrode of the p-channel transistor Alternatively, one of the drain electrodes is electrically connected to the capacitor line and the other is electrically connected to the pixel electrode, and one of the source electrode and the drain electrode of the n-channel transistor is the scanning line and the other is the pixel electrode. In addition, each is electrically connected.

  According to this configuration, an inverter circuit is configured by p-channel and n-channel transistors, and a voltage to be displayed on the pixel can be stably applied to the pixel electrode from the scanning line or the capacitor line.

  Application Example 4 In the display device, a storage capacitor is electrically connected between the gate electrode of the second transistor and the capacitor line.

  According to this configuration, it is possible to maintain the operation state of the second transistor while suppressing a decrease in the gate voltage due to the leakage of the first transistor.

  Application Example 5 The display device includes a memory display element, and the pixel electrode is an electrode for applying a voltage to the memory display element.

  Since the memory-type display element has a capacity and charges move, a stable voltage supply is required in the display operation. Therefore, since the display device stably supplies a voltage to the pixel electrode, the charge can be supplied so as not to decrease the voltage applied to the memory display element.

  Application Example 6 In the display device, the memory display element is an electrophoretic element.

  Since the electrophoretic element is thin and consumes little power, the display element is thin and has low power consumption. Therefore, the display device including an electrophoretic element as a memory display element can realize a display device with high definition, high quality, and cost increase suppressed.

  Application Example 7 Electronic equipment including the display device.

  According to this configuration, it is possible to provide an electronic device that displays a stable and high-quality image without causing insufficient writing of the voltage corresponding to the image displayed on the pixel.

It is a figure which shows the display apparatus which concerns on embodiment, (a) is a perspective block diagram, (b) is a fragmentary sectional view. 1 is a configuration diagram of an active matrix substrate according to an embodiment. 1 is a block diagram illustrating an electronic device according to an embodiment. The pixel circuit diagram of the active matrix substrate of a prior art example. 1 is a pixel circuit diagram of an active matrix substrate of a first embodiment. FIG. 6 is a timing chart for explaining an erase sequence in the first embodiment. The timing chart for demonstrating the display sequence in 1st Example. FIG. 3 is a circuit diagram in which a storage capacitor element is removed from the pixel circuit of the first embodiment. The pixel circuit diagram of the active matrix board | substrate of 2nd Example. The timing chart for demonstrating the erase sequence in 2nd Example. The timing chart for demonstrating the display sequence in 2nd Example. FIG. 6 is a circuit diagram in which a storage capacitor element is removed from a pixel circuit according to a second embodiment.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings used in the following description may exaggerate the dimensions of the constituent elements for convenience of description, and of course do not necessarily indicate the actual size.

(Display device)
1A and 1B are diagrams showing a display device 910 according to the present embodiment, in which FIG. 1A is a perspective configuration diagram, and FIG. As shown in the figure, a display device 910 has a pixel electrode, and an active matrix substrate 101 in which a pixel circuit configured to apply a potential to the pixel electrode via a transistor is disposed, and a memory display element The electrophoretic element 921 and the protective sheet 922 are provided. The electrophoretic element 921 has a structure sandwiched between the active matrix substrate 101 and the protective sheet 922.

  Here, the electrophoretic element 921 has a particle diameter of about 50 μm, and is filled with capsules made of a polymer resin capable of transmitting light without gaps. Inside the capsule, a dispersant composed of an organic solvent, water and a surfactant, white pigment particles WR negatively charged as dispersoids, and black pigment particles BR positively charged are encapsulated.

  The protective sheet 922 is made of PET (Poly Ethylene Terephthalate) resin having a thickness of about 300 μm, and a common electrode COM made of an ITO (Indium Tin Oxide) thin film is formed on the contact surface with the electrophoretic element 921. The protective sheet 922 has one side longer than the electrophoretic element 921, and a conductive paste 931 is applied to a protruding portion where the electrophoretic element 921 does not exist, and the common electrode COM and a common electrode pad (described later) on the active matrix substrate 101. 2 (see FIG. 2, common electrode pad 330).

  Further, the active matrix substrate 101 has a larger area than the electrophoretic element 921 and the protective sheet 922, and a first FPC 951 as a flexible substrate and a second FPC as a flexible substrate are formed in the widened protruding portion. FPC961 is installed. A gate driver 952 is mounted on the first FPC 951, and a source driver 962 is mounted on the second FPC 961, respectively.

  In the present embodiment, the first FPC 951, the gate driver 952, the second FPC 961, and the source driver 962 are each constituted by one, but a plurality of them may be provided, and the gate driver 952 and the source driver 962 may be provided. A one-chip driver integrated into one IC may be used. Alternatively, an active matrix substrate with a built-in driving circuit in which the gate driver 952 and the source driver 962 are formed on the active matrix substrate 101 may be used.

  Next, the active matrix substrate 101 will be described. FIG. 2 is a configuration diagram of the active matrix substrate 101. On the active matrix substrate 101, 480 scanning lines 201 (201-1 to 201-480) and 1920 data lines 202 (202-1 to 202-1920) are formed to intersect with each other. The capacitor lines 203 (203-1 to 203-480) are arranged along the scanning lines 201 and alternately with the scanning lines 201. The capacitor lines 203-1 to 203-480 are connected to the mounting terminal 320 via the wiring 335, and the common electrode pad 330 is connected to the mounting terminal 321 via the common potential wiring 336. 2 is a region in which the electrophoretic element 921 shown in FIG. 1 overlaps in plan view when configured as a display device, and corresponds to the display region A.

  The scanning lines 201-1 to 201-480 are respectively connected to the mounting terminals 301-1 to 301-480, connected to the gate driver 952 via the first FPC 951, and a voltage signal is supplied at a predetermined timing. . Similarly, the data lines 202-1 to 202-1920 are connected to the mounting terminals 302-1 to 302-1920, respectively, and connected to the source driver 962 via the second FPC 961, so that a voltage signal corresponding to the image signal is received. Supplied. Similarly, the mounting terminal 320 and the mounting terminal 321 are connected to the source driver 962 via the second FPC 961 and supplied with a predetermined voltage signal.

  Further, the display device 910 of this embodiment includes a control circuit that controls a voltage supplied to the gate driver 952 and the source driver 962 and a timing at which the voltage is supplied to the pixel circuit. The control circuit is formed on a separate substrate (not shown) that is electrically connected to the first FPC 951 and the second FPC 961. Note that the control circuit may be formed on the active matrix substrate 101.

(Electronics)
FIG. 3 is a block diagram showing a specific configuration of the electronic apparatus 1000 according to the present embodiment. The electronic device 1000 includes a voltage generation circuit 784, an image processing circuit 780, a central processing circuit 781, an external I / F (interface) circuit 782, and an input / output device 783. The display device 910 is the display device described in FIG.

  The image processing circuit 780 supplies the image signal, and the voltage generation circuit 784 supplies the generated voltage signal to the gate driver 952 through the first FPC 951 and to the source driver 962 through the second FPC 961. The central processing circuit 781 acquires input data (display data) from the input / output device 783 via the external I / F circuit 782. Here, the input / output device 783 is, for example, a keyboard, a mouse, a trackball, a touch panel, an LED, a speaker, an antenna, or the like.

  The central arithmetic circuit 781 performs various arithmetic processes based on the display data input via the external I / F circuit 782, and transfers the result to the image processing circuit 780 as a command. Then, the image processing circuit 780 updates the image information based on the command from the central processing circuit 781 and supplies a new image signal corresponding to the image information to the gate driver 952 and the source driver 962. As a result, by controlling the voltage supplied to the pixel circuit, the voltage applied to the electrophoretic element 921 (see FIG. 1) in the display area A of the display device 910 is controlled, and the display device 910 displays a display image. Change.

  As a specific example of the electronic device 1000, although not shown, for example, a portable document reader, an electronic book, an electronic poster, an electronic flyer, a monitor, a TV, a notebook computer, a PDA, a digital camera, a video camera, a mobile phone, a portable photo viewer, Examples include portable video players, portable DVD players, and portable audio players.

  Here, the display principle of the display device 910 will be described. As shown in FIG. 1, the electrophoretic element 921 encloses negatively charged white pigment particles WR and positively charged black pigment particles BR as dispersoids. Therefore, if the potential of the common electrode COM is higher than the potential of the pixel electrode, the white pigment particles WR move to the protective sheet 922 side, and the black pigment particles BR move to the active matrix substrate 101 side, and white display appears when viewed from the protective sheet 922 side. Become. Conversely, if the potential of the common electrode COM is lower than the potential of the pixel electrode, each pigment particle moves, and when viewed from the protective sheet 922 side, black is displayed. The moving speed of each pigment particle is proportional to the difference between the potential of the common electrode COM and the potential of the pixel electrode. Further, if the potential of the common electrode COM and the potential of the pixel electrode are equal, the adjustment is made so that the pigment particles do not move, so the previous display state is maintained.

  Therefore, for example, when the common electrode COM is kept at 0 V and a positive potential is applied to each pixel electrode, black display can be performed, and when a negative potential is applied, white display can be performed. At this time, if the potential difference between the common electrode COM and each pixel electrode is maintained without being lowered, the movement of the pigment particles is not slowed and the final display contrast is also increased. In this embodiment, the monochrome display electrophoretic element 921 is used. However, an electrophoretic element 921 that performs color display using a capsule in which a pigment of a different color is sealed for each pixel may be used.

  In the present embodiment, the currently displayed image is filled with white to erase the entire display area A of the image, and the pixel corresponding to the image to be displayed is changed from white display to black display. The image display is performed by continuously performing the display sequence to be rewritten. As described in Patent Document 1 and the like, by separating the erase sequence and the display sequence in this manner, a sufficient potential can be applied even to a transistor with a low breakdown voltage, and the response speed and contrast can be increased. .

  In the display device 910 of the present embodiment, the electrophoretic element 921 that suppresses a decrease in display performance such as contrast is driven during image display. Prior to describing this driving technique, the driving technique of the conventional example is performed. Will be described. This is for the purpose of facilitating understanding of the effects of the first and second examples of the driving technique in the present embodiment, which will be described later, in the display device 910.

(Conventional example)
FIG. 4 is a circuit diagram showing a conventional pixel circuit. As an example, the m-th data line 202-m (m = 1 to 1920) and the n-th scan line 201-n (n = 1 to 480). The pixel circuit arranged and formed in the vicinity of the intersection of (integer) is shown. A write transistor 401-nm, which is an n-channel field effect transistor, is formed at the intersection of the scan line 201-n and the data line 202-m, and its gate electrode is connected to the scan line 201-n. The source electrode is connected to the data line 202-m, and the drain electrode is connected to one end of the first storage capacitor element 403-nm and the pixel electrode 405-nm. The other end of the first storage capacitor element 403-n-m is connected to the capacitor line 203-n. Further, the pixel electrode 405-nm and the common electrode COM on the protective sheet 922 are opposed to each other through the electrophoretic element 921 to form a capacitor.

  In the conventional pixel circuit configured as described above, insufficient writing occurs as described above. This will be described by taking a black display write operation in the display sequence as an example. In the display sequence, the scanning lines 201-1 to 201-480 are sequentially selected by the gate driver 952. In other words, in the present embodiment, the scanning line 201-n is supplied with a voltage signal that returns to 0 V after having been +20 V (selected) for 30 μsec. At this time, the potential of the common electrode COM is kept at 0V, and the potential of the capacitor line 203-n is 0V.

  When the scanning line 201-n is selected, 15V is supplied to the data line 202-m and 15V is written to the pixel electrode 405-n-m when corresponding to black display. At this time, the written potential 15 V of the pixel electrode 405 -n-m is held by the first holding capacitor element 403 -n-m inserted between the capacitor line 203 -n.

  Then, since the potential of the common electrode COM <the potential of the pixel electrode 405-nm, particle movement occurs, and the state changes to a black display state. After that, the write transistor 401-nm is turned off to be in a high impedance state, so that no charge is supplied from the data line 202-m. However, the charge held in the first storage capacitor element 403-nm Is supplied to the pixel electrode 405-nm.

  However, since the electric charge held in the first holding capacitor element 403-nm is finite, the potential of the pixel electrode 405-nm is lowered with the movement of the particles, and the contrast is lowered. The moving speed of pigment particles, that is, the response speed decreases. Therefore, in order to suppress such a potential drop, it is obvious that the capacitance should be increased so that the charge held in the first storage capacitor element 403-nm is increased. Since the formation region (planar area) of the storage capacitor element 403-nm is large, high definition cannot be achieved.

  Therefore, in this embodiment, in order to prevent a potential drop due to the movement of the pigment particles, a stable voltage is not supplied from the first holding capacitor element 403-n-m, but the scanning line 201-n or the capacitor line 203-n. To be able to. By doing so, the charge is stably supplied to the pixel electrode 405-nm, so that a voltage drop of the pixel electrode 405-nm is suppressed, and a high response in which a decrease in response speed is suppressed. A display device capable of speed can be provided. Accordingly, it is possible to provide a display device capable of displaying a high contrast without increasing the capacitance of the first storage capacitor element 403-nm as compared with the conventional one-transistor / one-capacitor configuration. Further, since no new wiring is required for power supply, a high-definition display device can be obtained.

(First embodiment)
Next, the driving technique of the first embodiment will be described with reference to FIGS. FIG. 5 is a pixel circuit diagram of this embodiment, and FIG. 6 is a timing chart of the erase sequence of this embodiment. FIG. 7 is a timing chart of the display sequence of this embodiment.

  The pixel circuit shown in FIG. 5 is a pixel near the intersection of the mth data line 202-m (m = 1 to 1920) and the nth scanning line 201-n (n = 1 to 480). Circuit. A write transistor 401-nm, which is an n-channel field effect transistor, is formed at each intersection of the scanning line 201-n and the data line 202-m, and its gate electrode is connected to the scanning line 201-n, the source The drain electrodes are connected to the data line 202-m and the intermediate electrode 402-nm, respectively. Note that the writing transistor 401-nm corresponds to the first transistor described in the application example.

  The intermediate electrode 402-nm is a gate electrode of a first driving transistor 404-nm that is an n-channel field effect transistor and a gate of a second driving transistor 406-nm that is a p-channel field effect transistor. The electrode is connected to one end of the first storage capacitor element 403-nm, and the drain electrodes of the first driving transistor 404-nm and the second driving transistor 406-nm are pixel electrodes 405-n- connected to m. Note that the first driving transistor 404-nm and the second driving transistor 406-nm correspond to the second transistor described in the application example.

  The pixel electrode 405-nm and the common electrode COM on the protective sheet 922 face each other through the electrophoretic element 921 to form a capacitor. The source electrode of the first driving transistor 404-nm is connected to the scanning line 201-n, and the source electrode of the second driving transistor 406-nm is connected to the capacitor line 203-n. The other end of the first storage capacitor element 403-nm is also connected to the capacitor line 203-n.

  Next, an erasing sequence and a display sequence performed by the pixel circuit of this embodiment having such a configuration will be described. According to the erasing sequence and the display sequence of this embodiment, a display with high contrast is obtained, and a display device 910 that suppresses a decrease in response speed is obtained.

  First, the erase sequence will be described with reference to FIG. As shown in the figure, in the erasing sequence of this embodiment, a voltage signal is applied from all the scanning lines 201-1 to 201-480 by a gate driver 952 that simultaneously applies + 20V for 20 μs and then maintains 0V. The common electrode COM and all the data lines 202-1 to 202-1920 have + 15V at the same time as the scanning lines 201-1 to 201-480 become + 20V, and after about 200 msec (specifically, 200.02 msec later). ) Is supplied from the source driver 962 to a voltage signal of 0V. During this period, a voltage signal that maintains a potential of 0 V is supplied to the capacitor lines 203-1 to 480.

  When the voltage signal is supplied in this way and the pixel circuit is driven, all the writing transistors 401-nm are turned on and all intermediate states are applied while + 20V is applied to the scanning lines 201-1 to 201-480 for 20 μsec. 15V is written to the electrode 402-nm. Then, all the first drive transistors 404-nm are turned on, and all the second drive transistors 406-nm are turned off. As a result, after the scanning lines 201-1 to 201-480 are inverted to 0 V, 0 V is written and held for 200 m seconds as the potential of the pixel electrode 405-nm.

  That is, since the potentials of all the pixel electrodes 405-nm are 15V lower than the potential of the common electrode COM, the white pigment particles WR are on the protective sheet 922 side and the black pigment particles BR are on the active matrix substrate 101 side in the entire display region. Start moving. At this time, since the electric charge is always supplied from the scanning line 201-n via the first driving transistor 404-nm, the potential (voltage) of the pixel electrode 405-nm is changed with the movement of the pigment particles. There is no change, and contrast and response speed do not decrease. In this embodiment, by holding this state for 200 msec, the pigment particles are driven so as to move sufficiently. As a result, the entire display area becomes white and erasure is completed. In this embodiment, the voltage holding time of the pixel electrode 405-nm is set to 200 milliseconds, but it is preferable to set the voltage holding time according to the time during which the pigment particles actually move sufficiently.

  Next, the display sequence will be described with reference to FIG. The display sequence is performed subsequent to the erase sequence. As shown in the drawing, a voltage signal for sequentially selecting the scanning lines 201-1 to 201-480 is supplied from the gate driver 952 in the display sequence. That is, the scanning line 201-1 becomes +20 V for 30 μsec (selected), and then returns to 0 V. Similarly, the scanning line 201-2 is selected for 30 μs at a timing delayed by 34.6 μs from the scanning line 201-1. Thereafter, all the scanning lines 201-n are sequentially selected with a phase shift of 34.6 μsec. In addition, the common electrode COM is supplied with a voltage signal that maintains the potential of 0V, and the capacitance lines 203-1 to 203-480 have the potential of 15V at the same time as the first scanning line 201-1 is selected. After this potential is maintained for 200 m seconds after the scanning lines 201-480 are turned off, a voltage signal that returns to 0 V is supplied.

  When the scanning line 201-n is selected, the data line 202-1 to 202-1920 has a potential corresponding to the opposite polarity of the image potential of the pixel electrodes 405-n-1 to 405-n-1920 to the source driver 962. Supplied by That is, when the pixel electrode 405-nm corresponds to white display, 15V is supplied to the data line 202-m. Then, 15V is applied to the intermediate electrode 402-nm, the first driving transistor 404-nm is turned on, and the second driving transistor 406-nm is turned off. In this state, after the scanning line 201-n returns to 0V, the 0V potential is applied to the pixel electrode 405-nm, and the potential of the common electrode COM = the potential of the pixel electrode 405-nm = 0V. Therefore, the previous display state, that is, the white display state is maintained. Note that while the scanning line 201-n is selected, the pixel electrode 405-nm approaches + 15V, but since the period is short, the particles hardly move and do not affect the display.

  On the other hand, when the pixel electrode 405-nm corresponds to black display, a voltage signal of 0V is supplied to the data line 202-m. Then, since the first driving transistor 404-nm is turned off and the second driving transistor 406-nm is turned on, the pixel electrode 405-nm has a potential of + 15V via the capacitor line 203-m. Is applied, the potential of the common electrode COM <the potential of the pixel electrode 405-nm, and the movement of particles occurs to change to a black display state. At this time, since the electric charge is always supplied from the capacitor line 203-m via the second driving transistor 406-nm, the potential of the pixel electrode 405-nm may decrease as the pigment particles move. And contrast and response speed do not decrease. In this way, a desired image is displayed after 200 milliseconds.

  When the display sequence is completed, since the intermediate electrode 402-nm is in a floating state, the potential slowly changes due to the leakage current of each transistor. For this reason, the second drive transistor 406-nm of the pixel displaying white may be slightly turned ON, and the black display may be slowly started. Therefore, in this embodiment, such a phenomenon is prevented by returning all the potentials of the capacitance lines 203-m to 0 V 200 msec after the movement of the particles is almost completed.

  As described above, in this embodiment, the supply of electric charges for preventing the potential decrease due to the movement of the pigment particles is not performed from the first storage capacitor element 403-n-m but the capacitor line 203-n or the scanning line 201-n. To do through. Therefore, the capacitance value of the first storage capacitor element 403-nm can be made smaller than that of the conventional one-transistor / one-capacitor configuration. Further, since the wiring for supplying charge is shared with the capacitor line and the scanning line, the pixel circuit area does not need to be increased. Accordingly, it is possible to provide a display device with high definition, high contrast, and a reduction in response speed.

  In this embodiment, in order to simplify the explanation, the erasing sequence and the display sequence are performed once, but a higher response speed and higher contrast may be obtained by performing each of them a plurality of times. Further, in order to erase the afterimage at the time of erasing, an inverted image of the image displayed immediately before may be written. If the withstand voltage of the element is sufficiently high or the potential difference applied to the display element may be low, the erase sequence may be omitted and only the display sequence may be performed. For example, if the selection potential applied to the scanning line is 35 V, the potential amplitude applied to the data line is 0/30 V, and the COM potential is +15 V in the display sequence of this embodiment, the erase sequence can be omitted. For example, when the potential difference applied to the display element operates at ± 7.5V, the potential applied to the scanning lines and data lines in the display sequence of this embodiment remains unchanged, and the COM potential is set to + 7.5V. In this case, the erase sequence can be omitted.

  Note that although the first storage capacitor element 403-nm is used in the pixel circuit of this embodiment, it is not necessary if the storage characteristics of the transistor are good and the leakage current is small. A configuration example of such a pixel circuit is shown in FIG.

  FIG. 8 is a circuit diagram showing the pixel circuit in which the first storage capacitor element 403-nm is removed from the pixel circuit of this embodiment shown in FIG. In FIG. 8, for example, if the leakage current between the source and drain of the write transistor 401-nm is small, the potential change of the intermediate electrode 402-nm is small, so the first storage capacitor element 403-nm is unnecessary. It is. As a result, since the area occupied by the pixel circuit can be reduced, there is a possibility that high definition can be achieved. In addition, since a capacitance formation process is unnecessary, an increase in cost can be suppressed.

(Second embodiment)
Next, the driving technique of the second embodiment will be described with reference to FIGS. FIG. 9 is a pixel circuit diagram of this embodiment, and FIG. 10 is a timing chart of the erase sequence of this embodiment. FIG. 11 is a timing chart of the display sequence of this embodiment. The same numbers are assigned to the same components as those of the pixel circuit of the first embodiment.

  The pixel circuit of this embodiment shown in FIG. 9 does not include the second drive transistor 406-nm as compared with the pixel circuit of the first embodiment. The source electrode of the first driving transistor 404-nm is connected to the capacitor line 203-n instead of the scanning line 201-n. On the other hand, a second storage capacitor element 407-nm is added, and one end is connected to the pixel electrode 405-nm and the other end is connected to the capacitor line 203-n. Since the other configuration is the same as that of the first embodiment (FIG. 5), description thereof is omitted.

  Next, an erasing sequence and a display sequence performed by the pixel circuit of this embodiment having such a configuration will be described. Similar to the first embodiment, the display device 910 can obtain a display with high contrast and suppress a decrease in response speed by the erase sequence and the display sequence of the present embodiment.

  First, the erase sequence will be described with reference to FIG. As shown in the drawing, in the erase sequence of this embodiment, a voltage signal to which +20 V is simultaneously applied to all the scanning lines 201-1 to 201-480 for 200 msec is supplied from the gate driver 952. All the data lines 202-1 to 202-1920 have + 15V at the same time as the scanning lines 201-1 to 201-480 become + 20V, and 100 μs earlier than the scanning lines 201-1 to 201-480 return to 0V. A voltage signal returning to 0 V is supplied from the source driver 962. The common electrode COM also becomes + 15V at the same timing, and a voltage signal held for 200 msec is supplied. In addition, voltage signals fixed to 0 V are supplied to the capacitor lines 203-1 to 203-480.

  When the voltage signal is supplied in this way and the pixel circuit is driven, all the writing transistors 401-nm are turned on for 200 m seconds, and a potential of 15 V is written to all the intermediate electrodes 402-nm. Then, all the first driving transistors 404-nm are turned on, and the potentials of the capacitor lines 203-1 to 203-480, that is, 0V are written into the pixel electrodes 405-nm, and are held for 200 msec. The

  That is, since the potentials of all the pixel electrodes 405-nm are 15V lower than the potential of the common electrode COM, the white pigment particles start moving toward the protective sheet 922 and the black pigment particles begin moving toward the active matrix substrate 101 in the entire display region. . In this embodiment, this state is maintained for 199.9 msec so that the particles are sufficiently moved, so that the entire display area becomes white and erasure is completed. In this embodiment, the voltage holding time of the pixel electrode 405-nm is 199.9 mSec. However, as in the first embodiment, the voltage holding time depends on the time during which the pigment particles actually move sufficiently. Is preferably set.

  Thereafter, since the data lines 202-1 to 202-1920 return to 0V, the potential of the intermediate electrode 402-nm also returns to 0V, and all the first driving transistors 404-nm are turned off. The erase sequence ends with the potential of the pixel electrode 405-nm maintained at 0V.

  Next, the display sequence will be described with reference to FIG. In this embodiment, the display sequence is always performed following the erase sequence. Therefore, the potential of the pixel electrode 405-nm at the start of the display sequence is 0 V or less (the reason why it becomes lower than 0 V will be described later), and all the first drive transistors 404-nm are turned off. As shown in the figure, in the display sequence of the present embodiment, the voltage signal supplied to the capacitor lines 203-1 to 203-480 is a signal except that a 10V potential lower than 15V is applied for 300 msec. A voltage signal similar to 7 is supplied. However, the voltage signal supplied to the data line 202-m has a potential relationship opposite to that in FIG. 6 in the first embodiment.

  That is, when the pixel electrode 405-nm corresponds to white display, 0 V is supplied to the data line 202-m. Then, 0 V is written to the intermediate electrode 402-nm and the first driving transistor 404-nm remains off, so that the potential of the pixel electrode 405-nm is the second storage capacitor element 407. -N-m holds 0V at the end of the erase sequence. Accordingly, the potential of the common electrode COM and the potential of the pixel electrode 405-nm are equal, and the pigment particles do not move and remain white.

  Actually, the potential of the pixel electrode 405-nm falls below 0V due to the capacitive coupling of the second storage capacitor element 407-nm as the common electrode COM is inverted from 15⇒0V at the end of the erase sequence. To do. Further, the intermediate electrode 402-nm is similarly lowered from 0 V due to the capacitive coupling of the first storage capacitor element 403-nm. Next, the potential of the pixel electrode 405-nm and the intermediate electrode 402-nm rises due to capacitive coupling caused by the capacitance line 203-n being inverted from 0 to 10V during the display sequence. At this time, the voltage signal supply timing and the second storage capacitor element 407-n- are set so that the former decrease amount and the latter increase amount are equal, and the erasing and display sequences are continuously performed without any time interval. It is preferable to adjust the size of m and design the pixel electrode 405-nm to be approximately 0V at the timing when the capacitance line 203-n is inverted from 0 to 10V.

  Next, when the pixel electrode 405-nm corresponds to black display, a voltage signal having a potential of 15V is supplied to the data line 202-m. Then, 15V is written to the intermediate electrode 402-nm and the first driving transistor 404-nm is turned on, so that the pixel electrode 405-nm has the same potential as the capacitor line 203-n, that is, 10V. Written. As a result, the potential of the common electrode COM <the potential of the pixel electrode 405-nm, and the movement of the pigment particles occurs to change to the black display state.

  At this time, since the electric charge is always supplied from the capacitor line 203-m via the first driving transistor 404-nm, the potential of the pixel electrode 405-nm may decrease as the pigment particles move. And contrast and response speed do not decrease. In this way, a desired image is displayed after 300 milliseconds. Note that image degradation due to leakage current is prevented by returning all the potentials of the capacitor lines 203-m to 0 V after 300 milliseconds. This is the same as the description for FIG. 7 in the first embodiment.

  In this embodiment, since an n-channel transistor is used to apply a potential to the pixel electrode 405-nm, the potential of the pixel electrode 405-nm decreases by the threshold (Vth). Incidentally, in this embodiment, the threshold value of the first driving transistor 404-nm is 5V, and the potential applied to the pixel electrode 405-nm is 10V. That is, since the potential difference applied to the electrophoretic element 921 is different between the erase sequence and the display sequence, the moving speed of the pigment particles is also different. Therefore, in this embodiment, the time until the pigment particles sufficiently move when the applied potential to the pixel electrode 405-nm is 10V is set to 200 milliseconds in the erasing sequence in which the potential difference is 15V, and the potential difference is 15V. The applied erasing sequence is set to 300 msec, and the voltage holding time of the pixel electrode 405-nm in each sequence is set. Naturally, the voltage holding time is preferably set according to the time during which the pigment particles actually move sufficiently.

  By the way, also in the pixel circuit of this embodiment, the first holding capacitor element 403-nm is unnecessary for the same reason as described in the first embodiment as long as the holding characteristics of the transistor are sufficient. Similarly, the second storage capacitor element 407-nm is unnecessary. An example of such a configuration is shown in FIG.

  FIG. 12 is a circuit diagram showing a pixel circuit in which the first storage capacitor element 403-nm and the second storage capacitor element 407-nm are removed from the pixel circuit of the present embodiment shown in FIG. is there. In FIG. 12, for example, if the leakage current between the source and the drain of the writing transistor 401-nm is small, the potential change of the intermediate electrode 402-nm is small, so that the first storage capacitor element 403-nm is It is unnecessary. Further, if the leakage current between the source and drain of the first driving transistor 404-nm is small, the potential change of the pixel electrode 405-nm is small, and therefore the second storage capacitor element 407-nm is It is unnecessary. As a result, since the area occupied by the pixel circuit can be reduced, there is a possibility that high definition can be achieved. In addition, since a capacitance formation process is unnecessary, an increase in cost can be suppressed.

  In this embodiment, compared with the configuration described in the pixel circuit (FIG. 5) in the first embodiment, since the second driving transistor 406-nm is not present, it is more suitable for higher definition. In addition, since the p-channel transistor is not required in the pixel circuit, the active matrix substrate 101 can be manufactured not by the CMOS process but by the NMOS process. Therefore, it is superior to the first embodiment in that an increase in manufacturing cost is suppressed. In this embodiment, the pixel circuit is composed of n-channel transistors, but it is needless to say that the pixel circuit is composed of p-channel transistors. In this case, all the drive signals are given in reverse polarity.

  On the other hand, since an n-channel transistor is always used to apply a potential to the pixel electrode 405-nm in the first embodiment, as described above, the pixel electrode 405- The potential of nm decreases. That is, in this embodiment, since the potential difference when moving from white display to black display is smaller than that in the first embodiment (in this embodiment, 5 V), the response speed and contrast are disadvantageous. Therefore, the pixel circuit of the first embodiment or the pixel circuit of the second embodiment may be selected in consideration of the advantages and disadvantages described above.

  As described above, the present invention has been described using the embodiments. However, the present invention is not limited to these embodiments, and may be implemented in various forms without departing from the spirit of the present invention. is there.

  For example, the display device 910 of the above embodiment uses an electrophoretic element as a memory display element. However, the display device 910 is not limited to this and is a liquid crystal element having a memory property such as a ferroelectric liquid crystal. May be. Furthermore, the present invention can be applied to a display element that is not a memory display element as long as the display element has a low response speed and low holding performance of an applied voltage.

  DESCRIPTION OF SYMBOLS 101 ... Active matrix board | substrate, 201 ... Scan line, 202 ... Data line, 203 ... Capacitance line, 301, 302, 320, 321 ... Mounting terminal, 330 ... Common electrode pad, 335 ... Wiring, 336 ... Common potential wiring, 401 ... Write transistor, 402 ... intermediate electrode, 403 ... first storage capacitor, 404 ... first drive transistor, 405 ... pixel electrode, 406 ... second drive transistor, 407 ... second storage capacitor, 780 ... image Processing circuit, 781... Central processing circuit, 782. External I / F circuit, 783 ... Input / output device, 784 ... Voltage generation circuit, 910 ... Display device, 921 ... Electrophoretic element, 922 ... Protection sheet, 931 ... Conductive paste, 951 ... first FPC, 952 ... gate driver, 961 ... second FPC, 962 ... source driver, 000 ... electronic devices.

Claims (7)

A plurality of scan lines;
A plurality of data lines intersecting the plurality of scanning lines;
A pixel circuit arranged for each pixel provided corresponding to each intersection of the scanning line and the data line;
A display device comprising:
The pixel circuit includes a capacitor line provided along the scanning line, a pixel electrode, a first transistor, and a second transistor,
In the first transistor, a gate electrode is electrically connected to the scanning line, one of a source electrode or a drain electrode is electrically connected to the data line, and the other is electrically connected to a gate electrode of the second transistor,
One display electrode of the second transistor is electrically connected to the scanning line or the capacitor line, and the other electrode is electrically connected to the pixel electrode. . The display device according to claim 1,
In the pixel circuit, after the first transistor is turned on and a voltage at which the second transistor is turned on is applied to the gate electrode of the second transistor, the scanning line connected to the one electrode or the The display device is driven so that a voltage corresponding to an image displayed by the pixel is applied to the pixel electrode from any of the capacitor lines. The display device according to claim 1, wherein
Two second transistors,
One of the two second transistors is a p-channel transistor and the other is an n-channel transistor;
Of the source or drain electrodes of the p-channel transistor, one is electrically connected to the capacitor line and the other is electrically connected to the pixel electrode.
One of the source and drain electrodes of the n-channel transistor is electrically connected to the scanning line and the other is electrically connected to the pixel electrode, respectively. A display device according to any one of claims 1 to 3,
A display device, wherein a storage capacitor is electrically connected between the gate electrode of the second transistor and the capacitor line. The display device according to any one of claims 1 to 4,
A memory display element;
The display device, wherein the pixel electrode is an electrode for applying a voltage to the memory display element. The display device according to claim 5,
The memory display element is an electrophoretic element.   An electronic apparatus comprising the display device according to claim 1.

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