JP2011035944A - Analog/digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable constant visual observation of a scanning position on a document surface or a position just before (just after) the scanning position by receiving light in an optical path vertically inclined with respect to the document surface. <P>SOLUTION: In a drawing image input means, reflected and scattered light from a document surface 2 is received through a lens system by a one-dimensional image sensor to perform main scanning and a housing 1 covering the document surface 2 is moved by manual feeding to perform sub scanning. The drawing image input means includes: the one-dimensional image sensor which is mounted in an upper part inside the housing and set so that its light receiving plane becomes parallel with a drawing; and the lens system which is inclined with respect to a plane vertical to the document surface 2 and including a sensor column direction axis and constitutes an optical path surface orthogonal with the sensor column direction axis. Main scanning is performed in a covered-side terminal part of the housing 1. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an AD (analog-digital) converter that converts an analog signal into a digital signal, and more particularly to a differential successive approximation AD converter.

  At present, as an AD converter with a wide range of product applications, which is realized with a relatively simple circuit configuration, is highly compatible with a CMOS process that can be manufactured at a relatively low cost, and can achieve moderate conversion time and intermediate conversion accuracy. A successive approximation type AD converter is known. As conventional circuits of these successive approximation AD converters, for example, circuits shown in Patent Documents 1-5 and Non-Patent Documents 1 and 2 are known.

<< Example 1 of charge redistribution AD converter >>
FIG. 19 shows a differential capacitance DAC (digital analog converter) of a charge redistribution type AD converter, which is typical among them. Non-patent document 1 shows a similar circuit.

  In FIG. 19, SW1 to SW18 are switches, C1 to C12 are capacitors (a combination of capacitors only is also referred to as a capacitor array), VINP is a positive side (also referred to as positive or positive phase) analog input, and VINN is a negative side ( COMP1 is a comparator, TOP + is a positive side top plate of the capacitive array, TOP− is a negative side top plate of the capacitive array, and Vrefp is a positive side reference potential (5V). Vrefn is a negative reference potential (0 V), R1 and R2 are resistors, BUF1 is a buffer amplifier, CINP and CINN are comparator inputs, VCM is a comparator input bias potential during sampling, and COUT1 is a comparator. VIC and VICB are internal node names given for explanation, and the (+) side capacitor DAC is C1 to C6. The DAC comprised of the capacitor array (-) side capacitance DAC is a DAC composed of a capacitor array of the C12 from the C7, shown.

  The values of nC (n is an integer) written together from C1 to C12 indicate the relative relationship between the respective capacities, and are weighted in binary as shown in 1C, 2C, 4C, 8C, and 16C. Yes. C1 to C12 in FIG. 19 constitute a 4-bit DAC.

  The state of the switch shown in FIG. 19 indicates the state at the time of sampling. At the time of sampling, the potential of the positive side analog input VINP is charged to the capacitors C1 to C6, and the negative side analog input VINN is charged to the capacitors C7 to C12. The potential is charged.

  At the time of sampling, the output of the buffer amplifier BUF1, which is a voltage follower, is connected to the top plates TOP + and TOP− through SW17 and SW18. That is, SW17 and SW18 are closed. In addition, the potential of the node VIC becomes an intermediate potential between the potential of VINP and the potential of VINN by R1 and R2. The potential of the node VICB is also made equal to the potential of the VIC by the voltage follower (BUF1). When the potential of VINP and the potential of VINN are expressed by VINP and VINN, respectively, the potential of VICB is (VINP + VINN) / 2.

  Since the switches SW17 and SW18 are closed at the time of sampling, the potentials of the + side top plate TOP + and the − side top plate TOP− are both (VINP + VINN) / 2.

  At this time, the bias potential VCM is supplied to both the differential input terminals of the comparator COMP1 by the switches SW13 and SW14. That is, at the time of sampling, SW13 and SW14 are closed (conductive). Further, the top plates TOP + and TOP− are disconnected from the differential input terminal of the comparator COMP1 by switches SW15 and SW16. That is, at the time of sampling, SW15 and SW16 are opened (opened).

  The electric charge QSAMPP stored in the top plate TOP + of the (+) side capacitor DAC composed of C1 to C6 is expressed by the equation (1) (the total capacity of C1 to C6 is expressed by 32C).

QSAMPP = −32C (VINP− (VINP + VINN) / 2);
QSAMPP = −32C (VINP−VINN) / 2; Formula (1)
The electric charge QSAMPN stored in the top plate TOP− of the (−) side capacitor DAC constituted by C7 to C12 is expressed by Expression (2).

QSAMPN = −32C (−VINP + VINN) / 2; Formula (2)
That is, by setting the potential of the top plates TOP + and TOP− during sampling to the input common potential (VINP + VINN) / 2, the charges sampled in the (+) side capacitor DAC and the (−) side capacitor DAC are absolute values thereof. Are equal and the polarity is reversed.

  After sampling is completed, SW13, SW14, SW17, and SW18 are opened, and SW15 and SW16 are closed. By switching from SW1 to SW12, the potential of the bottom plate of C1 to C12 (on the electrode connected to SW1 to SW12) is changed to either Vrefp or Vrefn to correspond to the sampled analog potential difference (VINP minus VINN). The digital codes thus obtained are compared and searched using COUT1. Hereinafter, an example of a search procedure will be briefly described.

<Determination of sign bit>
First, SW6 is connected to Vrefp, and SW1 to SW5 are connected to Vrefn. The bottom plate potential of the total capacity 16C of C1 to C5 becomes Vrefn, and the bottom plate potential of the capacity 16C of C6 becomes Vrefp. Since the charge QSAMPP stored in the (+) side top plate (TOP +) of Expression (1) is stored, the (+) side top plate (TOP +) potential Vtp at this time is expressed by Expressions (3) and (4). Given in.

−16C (Vrefp−Vtp) + 16C (Vtp−Vrefn)
= −32C (VINP−VINN) / 2; Formula (3)
Vtp = − (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2; Formula (4)

  The switch of the (−) side capacitor DAC is operated symmetrically with the switch of the (+) side capacitor DAC. SW12 is connected to Vrefn, and SW7 to SW11 are connected to Vrefp. The bottom plate potential of the total capacity 16C of C7 to C11 becomes Vrefp, and the bottom plate potential of the capacity 16C of C12 becomes Vrefn. Since the charge QSAMPN stored in the (−) side top plate (TOP−) of Expression (2) is stored, the (−) side top plate (TOP−) potential Vtn at this time is expressed by Expressions (5) and ( 6).

−16C (Vrefp−Vtp) + 16C (Vtp−Vrefn) = 32C (VINP−VINN) / 2; Formula (5)
Vtn = (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2;
)

  That is, when VINP−VINN> 0, Vtp <Vtn, and it can be determined which of VINP and VINN is higher. Since the circuit of FIG. 19 is a circuit that can handle a differential signal including a sign, the sign bit can be determined by this first comparison.

  At this time, the common potential of the potential Vtp of the (+) side top plate TOP + and the potential Vtn of the (−) side top plate TOP− becomes (Vrefp + Vrefn) / 2, which can be the center potential of the reference potential. Can be set with the largest operating margin. Here, the common potential means the center potential of the differential input.

<Decision of MSB (most significant bit)>
Hereinafter, in order to simplify the description, a case where VINP−VINN> 0 (a case where the sign is +) is considered.

  When VINP−VINN> 0, SW6 is connected to Vrefp and SW12 is connected to Vrefn. The switches (SW1 to SW5) of the (+) side capacitor DAC are connected to Vrefp if the corresponding digital code is 1, and to Vrefn if the corresponding digital code is 0. The switches SW7 to SW11 of the (−) side capacitor DAC are connected to Vrefn if the corresponding digital code is 1, and to Vrefp if the corresponding digital code is 0 (if VINP−VINN> 0, SW1 is connected to Vrefn, SW7 Is connected to Vrefp). Therefore, the (+) side capacitor DAC and the (−) side capacitor DAC are respectively connected to the + side reference potential Vrefp or the − side reference potential Vrefn symmetrically with respect to the same digital code.

  Hereinafter, determination of the most significant bit (excluding the sign bit) will be described. SW6 is connected to Vrefp, SW1 to SW4 are connected to Vrefn, and SW5 is connected to Vrefp. The bottom plate potential of the total capacity 8C from C1 to C4 becomes Vrefn, and the bottom plate potential of the total capacity 24C of C5 and C6 becomes Vrefp. Since the charge QSAMPP stored in the (+) side top plate TOP + of the equation (1) is stored, the potential Vtp of the (+) side top plate TOP + at this time is given by the equations (7) and (8). .

−24C (Vrefp−Vtp) + 8C (Vtp−Vrefn) = − 32C (VINP−VINN) / 2; Formula (7)
Vtp = − (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2 + (Vrefp−Vrefn) / (2 × 2); Formula (8)

  SW12 is connected to Vrefn, SW7 to SW10 are connected to Vrefp, and SW11 is connected to Vrefn (note that SW7 is connected to the negative reference potential Vrefn when generating 2's complement). The bottom plate potential of the total capacity 8C from C7 to C10 becomes Vrefp, and the bottom plate potential of the total capacity 24C of C11 and C12 becomes Vrefn. Since the charge QSAMPN stored in the (−) side top plate TOP− of the equation (2) is stored, the potential Vtn of the (−) side top plate TOP− at this time is expressed by the equations (9) and (10). Given.

−8C (Vrefp−Vtp) + 24C (Vtp−Vrefn) = 32C (VINP−VINN) / 2; Formula (9)
Vtn = (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2− (Vrefp−Vrefn) / (2 × 2); Formula (10)

  The potential of the top plate becomes the differential inputs CINP and CINN of the comparator. When the difference potential Vtp−Vtn is considered, Expression (11) is obtained.

Vtp−Vtn = − (VINP−VINN) + (Vrefp−Vrefn) / 2;
Formula (11)
In other words, the comparator COMP1 can determine the magnitude relationship between the input potential difference VINP−VINN and a value obtained by halving the reference potential difference (Vrefp−Vrefn).

<Process after the next bit of MSB>
Thus, digital codes corresponding to SW5 and SW11 corresponding to MSB (Most Significant Bit) can be determined. Next, determination of codes (second high-order bits excluding the sign bit) corresponding to the switches SW4 and SW10 will be described.

  Assume that the digital code corresponding to SW5 and SW11 is determined to be 0, and (VINP−VINN) is smaller than (Vrefp−Vrefn) / 2. In this case, (VINP−VINN) and (Vrefp−Vrefn) / 4 are compared, the magnitude relationship is examined, and the range of the value of (VINP−VINN) is narrowed.

  Specifically, in the (+) side capacitor DAC, SW6 corresponding to the sign bit is connected to Vrefp, SW1 to SW3, and SW5 corresponding to the MSB are connected to Vrefn, and SW4 is connected to Vrefp. The bottom plate potential of the total capacity 12C of C1 to C3 and C5 becomes Vrefn, and the bottom plate potential of the total capacity 20C of C4 and C6 becomes Vrefp. The (+) side top plate (TOP +) potential Vtp at this time is given by the equations (12) and (13).

  −20C (Vrefp−Vtp) + 12C (Vtp−Vrefn) = − 32C (VINP−VINN) / 2 Formula (12)

  Vtp = − (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2 + (Vrefp−Vrefn) / (2 × 4) Equation (13)

  Further, the (−) side capacitor DAC is connected symmetrically to the (+) side capacitor DAC. That is, SW12 corresponding to the sign bit is connected to Vrefn, SW7 to SW9 and SW11 are connected to Vrefp, and SW10 corresponding to the MSB is connected to Vrefn. The bottom plate potential of the total capacity 12C of C7 to C9 and C11 becomes Vrefp, and the bottom plate potential of the total capacity 20C of C10 and C12 becomes Vrefn. The (−) side top plate (TOP−) potential Vtn at this time is given by the equations (14) and (15).

  −12C (Vrefp−Vtp) + 20C (Vtp−Vrefn) = 32C (VINP−VINN) / 2; Formula (14)

  Vtn = (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2− (Vrefp−Vrefn) / (2 × 4); Formula (15)

  The potential of the top plate becomes the differential inputs CINP and CINN of the comparator. When the difference potential Vtp−Vtn is considered, Expression (16) is obtained.

Vtp−Vtn = − (VINP−VINN) + (Vrefp−Vrefn) / 4;
Formula (16)

  With this connection, the MSB (SW5, SW11) is set to the digital code 0, the next bit of the MSB (SW4, SW10) is set to the digital code 1, respectively, and the bits lower than the next bit of the MSB are set to the digital code 0, respectively. Corresponding analog data is generated by the (+) side capacitor DAC and (−) side capacitor DAC. Thus, the comparator COMP1 can determine the magnitude relationship between the input potential difference VINP−VINN and a value obtained by multiplying the reference potential (Vrefp−Vrefn) by ¼. Thus, SW1 to SW12 are operated, and the bottom plate potential of C1 to C12 is set to Vrefp or Vrefn. As a result, the magnitude relationship between the potential difference of VINP−VINN and the potential obtained by dividing Vrefp−Vrefn can be determined, whereby the range of the potential difference value of the sampled VINP−VINN is successively narrowed down to the final. A digital value can be determined.

  By setting the potentials of the top plates TOP + and TOP− at the time of sampling to the input common potential (VINP + VINN) / 2, the charges sampled in the (+) side capacitor DAC and (−) side capacitor DAC have the same absolute value. The polarity is reversed. Accordingly, by operating the switches of the (+) side capacitor DAC and the (−) side capacitor DAC symmetrically, the respective capacitor DAC outputs can be operated symmetrically. The common potential of the (+) side top plate (TOP +) potential Vtp and the (−) side top plate (TOP−) potential Vtn is (Vrefp + Vrefn) / 2 (formula (4) + formula (6), (Refer Formula (8) + Formula (10), Formula (13) + Formula (15)). That is, since this common potential can be the center potential of the reference potential, the operation margin can be maximized. With such a circuit and its control method, an operation for converting a differential analog input signal into a digital value has been realized.

<< Example 2 of another successive approximation AD converter >>
FIG. 20A shows an outline of a circuit of another successive approximation AD converter. A similar circuit is shown in Non-Patent Document 2.)

  SW13 to SW16, S1, S2P, S2N, S3P, and S3N in FIG. 20 are switches, VINP is a (+) analog input, VINN is a (−) analog input, COMP1 is a comparator, and TOP + is a capacitor array. + Side top plate, TOP− is the −side top plate of the capacitor array, Vrefp is the + side reference potential (for example, 5V), Vrefn is the −side reference potential (for example, 0V), and CDACP is (+ ) Side capacitor DAC, CDACN is the (−) side capacitor DAC, CINP and CINN are comparator inputs, VCM is the comparator input bias potential during sampling, COUT1 is the comparator output, and NODE1 and NODE2 are internal Indicates the node.

  In the conventional circuit of FIG. 19, the top plate potentials TOP + and TOP− during sampling are set to the input common potential ((VINP + VINN) / 2) by the buffer amplifier BUF1 and the resistors R1 and R2.

  In the conventional circuit of FIG. 20, the potentials of the top plates TOP + and TOP− during sampling are set to the input common potential ((VINP + VINN) / 2) by operating the switches S1, S2P, S2N, S3P, and S3N.

  Here, in the conventional circuit shown in FIG. 20, a mechanism for setting the top plate potentials TOP + and TOP− during sampling to the input common potential ((VINP + VINN) / 2) will be described.

First, prior to sampling the analog input signals VINP and VINN, the switches S3P and S3N are turned on (see FIG. 20B). At this time, the switches S2P and S2N are open. By turning on S3P and S3N, the charges in the capacitances of CDACP and CDACN become zero. Thereafter, S3P and S3N are turned OFF, and S1, S2P and S2N are turned ON (see FIG. 20B). By turning on S2P and S2N, the potential of NODE1 becomes VINP and the potential of NODE2 becomes VINN. Since the charge of CDACP is 0 and the charge of CDACN is 0, if the sampling capacity of CDACP is equal to the sampling capacity of CDACN, the potentials of TOP + and TOP- The potential is ((VINP + VINN) / 2).

  Thus, as in the conventional circuit of FIG. 19, the charges sampled in the (+) side capacitor DAC and the (−) side capacitor DAC have the same absolute value and the opposite polarities. Accordingly, by operating the switches of the (+) side capacitor DAC and the (−) side capacitor DAC symmetrically, the respective capacitor DAC outputs can be operated symmetrically. Similarly to the case of FIG. 19, by operating the capacitor DAC, the common potential of the potential Vtp of the (+) side top plate TOP + and the potential Vtn of the (−) side top plate TOP− is (Vrefp + Vrefn) / 2. Become. Therefore, since this common potential can be made the center potential of the reference potential, the operation margin can be maximized. With such a circuit and its control method, an operation for converting a differential analog input signal into a digital value has been realized.

JP-A-6-164399 US Pat. No. 5,581,252 US Pat. No. 4,998,002 U.S. Pat. No. 4,833,381 US Pat. No. 4,803,462 JP 2000-201077 A Japanese Patent Laid-Open No. 11-17543

RK Hester et al., "Fully Differential ADC with Rail-to-Rail Common-Mode Range and Nonlinear Capacitor Compensation", IEEE Journal of Solid-State Circuits, (USA), Feb. 1990, Vol. 25, No. 1, p.173-183 G. Promitzer, "12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS / s", IEEE Journal of Solid-State Circuits, (USA), July 2001, Vol. 36, No. 7, p.1138-1143

  Conventionally, as represented by an LSI called a system LSI or a mixed-signal LSI, with the progress of miniaturization, the demand for integration of a CMOS digital circuit and a CMOS analog circuit on the same chip has increased. It is required to integrate CMOS analog circuits that ensure the performance commensurate with the high speed of a fine CMOS digital circuit at as low a cost as possible and with low power consumption.

  For this reason, as described above, the differential successive approximation type AD converter that realizes a small area, medium conversion time, and medium conversion accuracy is realized by the conventional technique. Therefore, further cost reduction, lower power consumption, and higher speed are required.

  However, in the conventional technique shown in FIG. 19 (for example, Non-Patent Document 1), in order to set the top plate potentials TOP + and TOP− during sampling to the input common potential (VINP + VINN) / 2, the common of VINP and VINN is used. The buffer amplifier BUF1 for supplying the common potential generated by the resistors R1, R2 and R1, R2 for generating the potential to the top plate is necessary. This is because it is necessary to increase the current supplied to the top plate while increasing the values of R1 and R2 to decrease the current in the input circuit (increase the sensitivity).

  For this reason, power consumption in the buffer amplifier BUF1 is required, and there is a problem that it is difficult to reduce power consumption.

  On the other hand, the prior art (Non-Patent Document 2) shown in FIG. 20 does not use a buffer amplifier as shown in FIG. However, the performance (input range characteristics) for converting an analog input signal in a range sufficiently close to the limit of the power supply voltage range has not been achieved.

  An object of the present invention is to provide an AD converter that operates with a small area and low power and can convert an analog input signal sufficiently close to the limit of a power supply voltage range (rail-to-rail range).

The present invention employs the following means in order to solve the above problems. That is, the present invention
A first analog terminal to which the first analog signal is input; a first input switch for inputting the first analog signal to the first analog terminal; a second analog terminal to which the second analog signal is input; and a second analog terminal. A second input switch for inputting a second analog signal, a first reference voltage connection terminal for receiving a first reference voltage, a second reference voltage connection terminal for receiving a second reference voltage, and a first analog terminal A first analog-to-analog converter that captures and holds sample data of the first analog signal from and generates a first comparison signal to be compared with the first analog signal, and a sample of the second analog signal from the second analog terminal A second digital-analog converter that captures and holds data and generates a second comparison signal to be compared with the second analog signal; and a first digital A first switch that opens or conducts an output side of the analog converter and an output side of the second digital analog converter; a difference value between the first analog signal and the second analog signal; an output signal of the first digital analog converter; And a comparator that compares a difference value between output signals of the two digital-to-analog converters.

  Further, the first digital-analog converter has input terminals of the first plurality of capacitance elements and the first plurality of capacitance elements as the first analog terminal, the first reference voltage terminal, and the second reference voltage terminal, respectively. A plurality of first switch groups connected to any one of the first plurality of capacitive elements, and a first common terminal that connects an output side terminal facing each input side terminal of the first plurality of capacitive elements.

  Further, the second digital-analog converter has input terminals of the second plurality of capacitive elements and the second plurality of capacitive elements respectively connected to the second analog terminal, the first reference voltage terminal, and the second reference voltage terminal. A plurality of second switch groups connected to any one of the plurality of second switch groups, and a second common terminal connecting the output side terminals facing the respective input side terminals of the second plurality of capacitive elements.

The first plurality of capacitive elements includes a first capacitive element having a capacity corresponding to ½ of the total capacity of the first plurality of capacitive elements, and after the sampling of the sample data of the first analog signal is completed. The input terminal of the capacitive element other than the first capacitive element is connected to either the first reference voltage terminal or the second reference voltage terminal based on the comparison result of the comparator, and the input of the first capacitive element The first reference voltage terminal is connected to the side terminal regardless of the comparison result of the comparator,
The second plurality of capacitive elements includes a second capacitive element having a capacity corresponding to ½ of the overall capacity of the second plurality of capacitive elements, and after the sample data acquisition of the second analog signal is completed,
One of the first reference voltage terminal and the second reference voltage terminal is connected to the input side terminal of the capacitive element other than the second capacitive element based on the comparison result of the comparator, and the input side terminal of the second capacitive element Is connected to the second reference voltage terminal regardless of the result of comparison by the comparator.

  According to the present invention, it is possible to provide an analog-to-digital converter that operates with a small area and low power and can convert an analog input signal sufficiently close to the limit of the power supply voltage range.

It is a circuit diagram showing an AD converter concerning a 1st embodiment of the present invention. It is a figure which shows the control timing of the AD converter of FIG. It is a figure which illustrates the composition of a switch. It is a circuit diagram which shows the AD converter which concerns on 2nd Embodiment of this invention. It is a circuit diagram which shows the AD converter which concerns on 3rd Embodiment of this invention. It is a figure which shows the structure of resistance DAC contained in AD converter. It is a circuit diagram which shows the AD converter which concerns on 4th Embodiment of this invention. It is a figure which shows the structure of resistance DAC contained in AD converter. It is a figure which shows the comparator applicable to the AD converter which concerns on each embodiment of this invention. It is a block diagram of the successive approximation type AD converter circuit concerning a 5th embodiment of the present invention. It is a figure which shows the example of operation timing. It is a circuit simulation result example (the 1). It is a circuit simulation result example (the 1). It is a circuit simulation result example (the 1). It is the enlarged view which expanded the time at the time of transfering from sampling to a comparison in FIG. 12A. It is a circuit simulation result example (the 2). It is a circuit simulation result example (the 2). It is a circuit simulation result example (the 2). It is a circuit simulation result example (the 3). It is a circuit simulation result example (the 3). It is a circuit simulation result example (the 3). It is a circuit diagram which shows the AD converter which concerns on 6th Embodiment of this invention. It is a circuit diagram which shows the AD converter which concerns on 7th Embodiment of this invention. It is a circuit diagram which shows the AD converter which concerns on 8th Embodiment of this invention. It is a circuit diagram which shows the AD converter which concerns on 8th Embodiment of this invention. It is a figure which shows the conventional charge redistribution type AD converter. It is a figure which shows the circuit of the conventional successive approximation type AD converter. It is a figure which shows the control timing of the conventional successive approximation type AD converter. It is a figure for demonstrating the problem of AD converter.

  Hereinafter, an AD (analog-digital) converter according to an embodiment (hereinafter referred to as an embodiment) will be described with reference to the drawings. The configuration of the following embodiment is an exemplification, and the present invention is not limited to the configuration of the embodiment.

FIG. 21 is a diagram for explaining problems of the AD converter of FIG. In FIG. 21, SW13 to SW16, S1 are switches, VINP is a (+) analog input, VINN is a (−) analog input, COMP1 is a comparator, TOP + is a + side top plate of the capacitor array, TOP− Is the negative side top plate of the capacitor array, Vrefp is the positive side reference potential (for example, 5V), Vrefn is the negative side reference potential (for example, 0V), CDACP is the positive side capacitor DAC, CDACN (−) Side capacitance DAC, CINP and CINN are comparator inputs, VCM is a comparator input bias potential during sampling, COUT1 is a comparator output, PM1 to PM4 are PMOS transistors, and NM1 to NM4 are NMOS Transistors, CS2P, CS3P are PMOS transistor control signals, S2N, CS3N is a control signal of the NMOS transistor, NODE1, NODE2 are internal nodes, shown.

  FIG. 21 shows the switches, S2P, S2N, S3P, and S3N of FIG. 20 as transistor level circuit diagrams so that the problem of the circuit of FIG. 20 can be easily explained.

  First, prior to sampling of the analog input signals VINP and VINN, PM2, NM2, PM3, and NM3 are turned ON (for example, CS3P is set to 0V and CS3N is set to 5V). At this time, PM1, NM1, PM4, and NM4 are turned off (CS2P is set to 5V and CS2N is set to 0V). Thereafter, PM2, NM2, PM3, and NM3 are turned off (for example, CS3P is set to 5V and CS3N is set to 0). Also, PM1, NM1, PM4, NM4, and S1 are turned ON (for example, CS2P is set to 0V and CS2N is set to 5V). Thus, the potentials of TOP + and TOP− become the input common potential ((VINP + VINN) / 2), the potential of the bottom plate NODE1 of the (+) side capacitor DAC becomes VINP, and the potential of the bottom plate NODE2 of the (−) side capacitor DAC. The potential is VINN, and the same charge as that of the conventional circuit of FIG. 19 is stored in the sampling capacitor of the (+) side capacitor DAC and the sampling capacitor of the (−) side capacitor DAC.

  After this sampling is completed, the switch S1 is turned OFF, and PM1, NM1, PM4, and NM4 are turned OFF, and the potential of each bottom plate of the (+) side capacitor DAC and each bottom of the (−) side capacitor DAC. Manipulate the potential of the plate and move on to the comparator operation.

  In order to turn off PM1, NM1, PM4, and NM4, the control signal CS2P changes from L to H (from 0V to 5V). Further, the control signal CS2N changes from H to L (from 5V to 0V).

  At this time, for example, it is assumed that the power supply voltage and the reference voltage are both 5V, and the case where the potential of VINP is 5V and the potential of VINN is 0V is considered. That is, consider a case where the power supply voltage and the reference voltage are substantially equal to the analog input signal to be converted.

  When the potential of VINP is 5V, the potential of NODE1 is 5V, the potential of CS2P is 0V, and the potential of CS2N is 5V, NM1 is not inverted, so the capacitance between its gate, drain and source is as small as the overlap capacitance. It is a value. In the case of the NMOS transistor NM1, the gate potential is 5V, but the source and drain potentials are also 5V. In order for the MOS transistor to invert, the gate-source voltage needs to exceed the threshold voltage Vth (for example, 0.7 V). Therefore, in NM1 where the source and drain potentials are 5 V, the inversion layer is formed. Not. For this reason, the gate oxide film capacitance is not effectively connected between the gate and the source (or drain).

On the other hand, since PM1 has an inversion layer, a gate oxide film capacitance exists between the gate, the drain, and the source. That is, in the case of the PMOS transistor PM1, since the gate potential is 0V and the source and drain are both 5V, the gate-source voltage is larger than the threshold voltage Vth, and a channel is formed. Therefore, the capacitance due to the gate oxide film is connected between the gate and the source (or drain).

  In this state, when the potential of CS2P changes from 0V to 5V and the potential of CS2N changes from 5V to 0V, the potential of NODE1 rises via the gate capacitance of PM1 (this is shown in the waveform diagram of FIG. 21). ). At this time, since both PM1 and NM1 are turned off, the increased potential of NODE1 is maintained.

  Similarly, when the potential of VINN is 0V, the potential of NODE2 is 0V, the potential of CS2P is 0V, and the potential of CS2N is 5V, PM4 is not inverted, so the capacitance between its gate, drain and source is an overlap capacitance The value is small. On the other hand, since an inversion layer is formed in NM4, a gate oxide film capacitance exists between the gate, the drain, and the source.

  When the potential of CS2P changes from 0V to 5V and the potential of CS2N changes from 5V to 0V, the potential of NODE2 becomes low via the gate capacitance of NM4 (this is shown in the waveform diagram of FIG. 21). At this time, since both PM4 and NM4 are turned off, the lowered potential of NODE2 is maintained.

  That is, at the end of sampling, the potential of NODE1 rises above the power supply voltage 5V through the gate capacities of PM1 and NM4, and the potential of NODE2 may be maintained at a potential lower than the power supply voltage 0V. .

  After the sampling is completed, the switch S1 is turned OFF, the potential of each bottom plate of the (+) side capacitor DAC and the potential of each bottom plate of the (−) side capacitor DAC are operated, and the comparison operation by the comparator is started. At this time, if the potential of NODE1 is higher than the power supply voltage 5V, even if the gate potential of PM2 is set to 5V and PM2 is turned off, the source potential of PM2 is the potential of NODE1, so the potential of NODE1 is A voltage is applied between the gate and source of PM2 by the amount of the potential that has risen beyond the power supply voltage of 5V. For this reason, a slight current flows from NODE1 to TOP + via PM2. This changes the charge stored in TOP +, which causes a failure to obtain a correct conversion result.

  Similarly, when the potential of NODE2 is lower than the power supply voltage 0V, even if the gate potential of NM3 is set to 0V and NM3 is turned off, the source potential of NM3 is the potential of NODE2, so the potential of NODE2 is lower than 0V. A voltage is applied between the gate and source of NM3 by the amount of the lower potential, and a slight current flows from TOP− to NODE2 via NM3. This changes the charge stored in TOP−, and a correct conversion result cannot be obtained.

  In the circuit of FIG. 21, in order to avoid this problem, the maximum value of the analog input potential VINP is set to a potential lower than the power supply voltage, the minimum potential of VINN is set to a potential higher than 0 V, and the potentials of NODE1 and NODE2 are coupled. It was necessary to ensure that the power supply voltage range was not exceeded even if it changed due to the above. For this reason, the circuit configuration of FIG. 21 cannot realize the performance of converting the analog input signal in the power supply voltage range (rail-to-rail range).

  In the present embodiment, as a first feature, a differential successive approximation AD converter capable of reducing power consumption without requiring a buffer amplifier required in the conventional circuit of FIG. 19 is illustrated. The circuit of FIG. 21 illustrates a differential successive approximation AD converter that can convert an analog input signal in a power supply voltage range (rail-to-rail range) that has not been achieved. That is, a circuit that achieves both a low power consumption characteristic that does not require a buffer amplifier and a characteristic that converts an analog input signal in a power supply voltage range (rail-to-rail range) is illustrated.

  In the conventional circuit of FIG. 19, the digital value obtained by converting the analog input signal is expressed in two's complement, but there is a problem that the conversion time is increased by the cycle of the code determination. In the present embodiment, as a second feature, when the magnitude relationship between the (+) side analog input signal and the (−) side analog input signal can be predicted, the analog signal is assumed in advance by assuming a sign. The circuit which converts into a digital value is illustrated.

  Furthermore, in this embodiment, since the circuit that converts the analog signal into a digital value assuming the sign and achieving the second feature is used, if necessary, the analog signal including the sign is converted into a digital value. The circuit to convert is illustrated.

  In order to achieve the first feature described above, in this embodiment (FIG. 1), the top plate TOP + and the bottom plate (terminals connected to the switches C1 to C6) of the (+) side capacitor DAC of the differential capacitor DAC are provided. A switch (FIG. 1, S3P) is provided that equalizes the potential and discharges the sampling capacitor of the (+) side capacitor DAC. Further, the switch (FIG. 1, S3N) discharges the sampling capacitor of the (−) side capacitor DAC by equalizing the potentials of the top plate TOP− and the bottom plate (terminal connected to the switches C7 to C12) of the (−) side capacitor DAC. ).

  Furthermore, in this embodiment, when the switches S3P and S3N for discharging the sampling capacitor are ON, the (+) side analog input signal VINP, the (−) side analog input signal VINN, and the bottom plate of the capacitor DAC are disconnected. Switches S2P and S2N are provided. Further, a switch S1 is provided for equalizing the potential of the (+) side top plate TOP + and the potential of the (−) side top plate TOP− when sampling the analog input signal.

  At the end of sampling, the switches S2P and S2N that supply the analog input signals VINP and VINN to the bottom plate are turned off. At this time, a switch S4 for equalizing the potentials of NODE1 and NODE2 is provided so that the potentials of the internal nodes NODE1 and NODE2 do not exceed the power supply voltage range.

  In order to achieve the second feature described above, in the present embodiment (FIG. 1), the potential of the bottom plate of the capacitor C6 having a half of the total sampling capacity of the (+) side capacitor DAC. Are set to the + reference voltage Vrefp simultaneously with the start of comparison by the comparator. The remaining binary weighted capacitance bottom plate is connected to a positive reference voltage Vrefp if the corresponding DAC input is 1, and to a negative reference voltage Vrefn if the corresponding DAC input is 0. Further, over the comparison period, the potential of the bottom plate of the capacitor C6 corresponding to the sign bit is set to the + reference voltage Vrefp regardless of the comparison result in the comparator COMP1.

  Further, the potential of the bottom plate of the capacitor C12 (corresponding to the sign bit) having a half of the total sampling capacity of the (−) side capacitor DAC is set to the − reference voltage Vrefn simultaneously with the start of comparison by the comparator. And The remaining binary weighted capacitance bottom plate is connected to a negative reference voltage Vrefn if the corresponding DAC input is 1, and to a positive reference voltage Vrefp if the corresponding DAC input is 0. In addition, over the comparison period, the potential of the bottom plate of the capacitor C12 corresponding to the sign bit is set to a negative reference voltage Vrefn regardless of the comparison result in the comparator COMP1.

Even when the switches S2P and S2N for supplying the analog input signals VINP and VINN to the bottom plate are turned off at the end of sampling of the analog input signal, the potentials of the nodes NODE1 and NODE2 are equalized by the switch S4 (FIG. 1). , S2N connected to the bottom plate, the potentials of the nodes NODE1, NODE2 do not exceed the power supply voltage range. By keeping the potentials of the nodes NODE1 and NODE2 within the power supply voltage range, the switch S3
It is possible to prevent current from flowing through the top plates TOP + and TOP− through P and S3N. As a result, it is possible to prevent the charges of the top plates TOP + and TOP− from being lost and to obtain a correct conversion result.

  Also, it is assumed that the analog input VINP supplied to the bottom plate of the (+) side capacitor DAC is greater than or equal to the analog input VINN supplied to the bottom plate of the (−) side capacitor DAC by the above operation. Thus, the analog input potential difference (VINP−VINN) can be converted into a digital value.

  In other words, when VINP−VINN> = 0 is predicted in advance, the conventional circuit (FIG. 19) can perform AD conversion by omitting a cycle for determining a necessary code. Thereby, the conversion time can be shortened by the time required for code determination.

<< First Embodiment >>
Hereinafter, the first embodiment of the present invention will be described in detail. FIG. 1 is a circuit diagram showing an AD converter according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating control timings of the switches S1, S2P, S2N, S3P, S3N, and S4 in FIG.

  In FIG. 1, SW2 to SW5, SW8 to SW11, SW13 to SW16, SW19 to SW22, S1, S2P, S2N, S3P, S3N, and S4 are switches, C1 to C12 are capacitors, and VINP is a (+) analog input. , VINN is the (−) analog input, TOP + is the + side top plate of the capacitor array, TOP− is the −side top plate of the capacitor array, Vrefp is the + side reference potential (for example, 5V), and Vrefn is -Side reference potential (eg, 0V), COMP1 is a comparator, CINP and CINN are comparator inputs, COUT1 is a comparator output, and VCM is a comparator input bias potential (eg 2.5V) during sampling. NODE1 and NODE2 are internal nodes, and the (+) side capacitor DAC is C1 to C6. The DAC comprised of the capacitor array (-) side capacitance DAC is a DAC composed of a capacitor array of the C12 from the C7, shown. The parts corresponding to the circuit elements of the conventional circuit in FIGS. 19 and 20 and the elements having the same functions are given the same element names and terminal names.

  The comparator COMP1 corresponds to the comparator of the present invention, the (+) side capacitor DAC corresponds to the first digital-analog converter, the (-) side capacitor DAC corresponds to the second digital-analog converter, and the + side reference The terminal to which the potential Vrefp is connected corresponds to the first reference voltage connection terminal, and the terminal to which the − side reference potential Vrefn is connected corresponds to the second reference voltage connection terminal.

  Here, the top plate TOP + refers to a terminal of the capacitor DAC that is opposed to a terminal (bottom plate) that is connected to NODE1 to which an analog signal on the + side is input via the switches SW19, SW2-SW5, and SW21. In addition, the top plate TOP− is a terminal facing the terminal (bottom plate) connected to the NODE2 to which the negative analog signal is input through the switches SW20, SW8-SW11, and SW22 in the capacitor DAC.

  The value of bC (b is an integer) written together with the capacitance Ca (a is an integer) indicates the relative relationship between the sizes of the respective capacitances, as shown in 1C, 2C, 4C, 8C, 16C (etc.). Weighted. C1 to C12 in FIG. 1 constitute a 4-bit DAC.

  The state of the switch illustrated in FIG. 1 indicates the sampling state of the capacitor DAC. At the time of sampling, the potential of VINP is charged from C1 to C6, and the potential of VINN is charged from C7 to C12.

  First, prior to sampling of the analog input signals VINP and VINN, the discharge switches S3P and S3N are turned ON (see FIG. 2). At this time, the analog signal input switches S2P and S2N are opened (more precisely, it is not essential to turn off both of them, and one of them, for example, S2N may be turned on).

  Further, for example, S1 is turned ON, and SW2 to SW5, SW19, and SW21 are connected to NODE1. For example, SW8 to SW11, SW20, and SW22 are connected to NODE2. By turning on S3P and S3N, the potentials of the top plates (TOP +, TOP−) of C1 to C12 and the potentials of the bottom plates of C1 to C12 become equal, and the (+) side capacitance DAC and (−) side capacitance DAC The charge stored in the sampling capacitors C1 to C12 is zero.

  Thereafter, S3P and S3N are turned OFF, and S1, S2P and S2N are turned ON (see FIG. 2). At this time, a positive analog signal (corresponding to the first analog signal) is input to NODE1 (corresponding to the first analog terminal of the present invention) through the switch S2P (corresponding to the first input switch of the present invention). . Further, a negative analog signal (corresponding to a second analog signal) is input to NODE2 (corresponding to a second analog terminal of the present invention) through a switch S2N (corresponding to a second input switch of the present invention).

However, for S1, S3P and S3N may be in the ON state and S1 may be in the ON state, and the ON state may be maintained. By turning on S2P and S2N, the potential of NODE1 becomes VINP and the potential of NODE2 becomes VINN. SW2 to SW5, SW19, and SW21 are connected to NODE1, and SW8 to SW11, SW20, and SW22 are connected to NODE2. Since the total sampling capacity of the (+) side capacitor DAC (total capacity 32C from C1 to C6) and the total sampling capacity of the (−) side capacity DAC (total capacity 32C from C7 to C12) are equal, , S1 are ON, and the potentials of the top plates TOP + and TOP− are equal, so the potentials of the top plates TOP + and TOP− become the input common potential ((VINP + VINN) / 2). (VINP and VINN represent the potential of the (+) analog input VINP and the potential of the (−) analog input VINN, respectively.)
The electric charge QSAMPP stored in the top plate (TOP +) of the (+) side capacitor DAC composed of C1 to C6 is expressed by Expression (17). (The total capacity of C1 to C6 is represented by 32C.)

QSAMPP = −32C (VINP− (VINP + VINN) / 2);
QSAMPP = −32C (VINP−VINN) / 2; Formula (17)
The electric charge QSAMPN stored in the top plate (TOP−) of the (−) side capacitor DAC composed of C7 to C12 is expressed by Expression (18).

QSAMPN = −32C (−VINP + VINN) / 2; Formula (18)
That is, by setting the potential of the top plates TOP + and TOP− during sampling to the input common potential (VINP + VINN) / 2, the charges sampled in the (+) side capacitor DAC and the (−) side capacitor DAC are absolute values thereof. Are equal and the polarity is reversed.

  After completion of sampling, S1 is opened (opened). S2P and S2N are also open (open). By opening S1 first, the top plates TOP + and TOP− are in a floating state, so that the charges on the top plates C1 to C12 are stored.

FIG. 3 shows an example of a transistor level circuit of SW2 to SW5, SW8 to SW11, and SW19 to SW22, taking SW2 as an example.

  In FIG. 3, PM5 and PM6 are PMOS transistors, NM5 and NM6 are NMOS transistors, C2 is a capacitor, NODE1, TOP + are node names, Vrefp is a reference potential on the + side (for example, 5V), and Vrefn is a − side. The reference potential (for example, 0 V) is shown. In FIG. 3, the nodes corresponding to FIG. 1 are given the same names as in FIG. By connecting transistors as shown in FIG. 3, for example, the function of SW2 in FIG. 1 can be realized.

  Returning to the description of FIG. After S1 is opened (opened), SW2 to SW5, SW8 to SW11, and SW19 to SW22 are operated to set the potential of the bottom plates of the capacitors C1 to C12 to Vrefp or Vrefn. At this time, if a switch (for example, SW2) is configured with a circuit as shown in FIG. 3, PM5 and NM5 are turned off before the potential of the bottom plate of C2 is set to Vrefp or Vrefn, and then the bottom plate of C2 is turned off. The potential is set to Vrefp or Vrefn.

  When the switches SW2 to SW5, SW8 to SW11, and SW19 to SW22 are operated at such switch timing, SW2 to SW5, SW19, and SW21 are also floating as viewed from NODE1 before and after S2P is turned off. Therefore, as described with reference to FIG. 21, when the potential of VINP is close to a positive power supply voltage, the potential of NODE1 is positive due to the gate capacitance of the PMOS transistor that constitutes S2P when the switch S2P is turned off. May exceed the power supply voltage of

  Similarly, before and after S2N is turned OFF, SW8 to SW11, SW20, and SW22 are also floating as viewed from NODE2. For this reason, when the potential of VINN is close to the negative power supply voltage, the potential of NODE2 may decrease beyond the negative power supply voltage due to the gate capacitance of the NMOS transistor constituting S2N as the switch S2N is turned off. There is.

  In order to prevent this, after turning off S2P and S2N, a switch S4 (corresponding to the potential control circuit of the present invention and the second switch) for equalizing the potentials of NODE1 and NODE2 is turned on (see FIG. 2). As a result, the potentials of NODE1 and NODE2 become equal and become an intermediate potential. Therefore, even if one of NODE1 and NODE2 immediately before turning off S2P and S2N is a potential close to a positive power supply voltage or a potential close to a negative power supply voltage, the potential difference between NODE1 and NODE2 is somewhat. If it is larger, the potentials of NODE1 and NODE2 can be prevented from exceeding the power supply voltage range when S2P is turned off or S2N is turned off.

  If the potentials of NODE1 and NODE2 exceed the power supply voltage range, even if S3P and S3N are turned off, the forward direction current flows easily between the gates and sources of the MOS transistors constituting them. Therefore, there is a problem that a slight current flows from NODE1 to TOP + or from TOP− to NODE2 through S3P and S3N, changing the charge stored in the top plates TOP + and TOP−. (This is as described in the explanation of the problem of the circuit of FIG. 21).

  Therefore, as in the circuit of FIG. 1, S4 is provided, and after the end of sampling, the analog input signal in the power supply voltage range is sampled by preventing the potentials of NODE1 and NODE2 from exceeding the power supply voltage range by S4. However, the potentials of the internal nodes NODE1 and NODE2 can be prevented from exceeding the power supply voltage range. Therefore, the sampled charge can be prevented from being destroyed, and a correct conversion result can be obtained.

At the end of sampling, S1 is turned OFF, S2P and S2N are turned OFF, SW2
To SW5, SW8 to SW11, SW19 to SW22 are made floating (S3P and S3N are OFF from the start of sampling), and S4 is turned ON. Further, SW13 and SW14 are turned off, and SW15 and SW16 are turned on. Thus, preparation for successive comparison by the comparator is completed.

  SW13 and SW14 function as switches for applying a bias VCM to the inputs CINP and CINN of the comparator COMP1 during sampling. For example, if VCM is set equal to the final common potential ((Vrefp + Vrefn) / 2) for comparison by the comparator, the offset voltage of the comparator COMP1 is stored in, for example, a capacitor during the sampling period, and the auto− The influence of offset can be reduced by zero.

  Further, SW15 and SW16 function as switches for separating TOP + and TOP− from the comparator input terminals (CINP and CINN) in order to set the potential of TOP + and TOP− to the analog input common potential.

  After sampling, by operating SW2 to SW5, SW8 to SW11, SW19 to SW22, and setting the potential of the bottom plate of the capacitors C1 to C12 to Vrefp or Vrefn, a voltage obtained by dividing the reference voltage, The magnitude relation of the sampled potential difference is determined (using COUT1), and a digital value corresponding to the analog input potential difference is searched.

  In this embodiment, since it is assumed that VINP−VINN> = 0, SW21 is connected to Vrefp, and SW22 is connected to Vrefn. The switches SW2 to SW5 of the (+) side capacitor DAC are connected to Vrefp if the corresponding digital code is 1, and to Vrefn if the corresponding digital code is 0. SW19, which generates a 1-bit addition value to generate a 2's complement, is connected to Vrefn (corresponding to digital code 0). This is because it is not necessary to generate 2's complement data.

  The switches SW8 to SW11 of the (−) side capacitor DAC are connected to Vrefn if the corresponding digital code is 1, and to Vrefp if the corresponding digital code is 0. In this embodiment, since it is assumed that VINP−VINN> = 0, SW20 is connected to Vrefp (corresponding to digital code 0). This is to always generate 2's complement data.

  In FIG. 19, SW1 corresponding to SW19 needs to be connected to Vrefp when VINP <VINN. This is for the purpose of obtaining a digital value represented by two's complement as a conversion result when VINP <VINN. On the other hand, in the circuit of the invention of FIG. 1, since only VINP> VINN is assumed, it is sufficient to always assume a positive number as the + side potential. Therefore, SW19 need only be connected to Vrefn. Similarly, a negative number may always be assumed as the negative side potential, and SW20 may be connected to Vrefp.

<Search procedure>
In the conventional circuit of FIG. 19, SW6 is connected to Vrefp, SW1 to SW5 are connected to Vrefn, SW12 is connected to Vrefn, and SW7 to SW11 are connected to Vrefp, thereby determining the magnitude relationship between VINP and VINN and determining the sign. . However, in actual application, the magnitude relationship between VINP and VINN may be predicted in advance. If the code can be predicted, it can be said that the comparison cycle for determining the code is redundant.

Therefore, the AD conversion circuit of the present embodiment provides a search method and circuit for determining a digital value on the assumption that VINP is larger than VINN (assuming a sign). Since VINP> VINN is assumed, higher-speed conversion is possible as much as code determination is not required (VIN
(The circuit when P> VINN is not satisfied will be described in the seventh embodiment)
In the circuit of this embodiment, SW21 in FIG. 1 corresponds to SW6 in FIG. 19 which is a conventional circuit, and SW22 in FIG. 1 corresponds to SW12 in FIG.

  Since it is assumed that VINP> VINN, the comparison by the comparator starts with, for example, comparison with VINP> VINN and the reference voltage / 2, and if (VINP−VINN) is larger than the reference voltage / 2, the reference voltage × 3 / 4 is compared with (VINP-VINN). If (VINP−VINN) is smaller than the reference voltage / 2, the reference voltage × 1/4 is compared with (VINP−VINN). Furthermore, if (VINP−VINN) is larger than the reference voltage × 1/4, the reference voltage × 3/8 is compared with (VINP−VINN). Alternatively, if (VINP−VINN) is smaller than the reference voltage × 1/4, the reference voltage × 1/8 is compared with (VINP−VINN). That is, the magnitude relationship between the potential difference of (VINP−VINN) and the potential obtained by dividing the reference voltage (Vrefp−Vrefn) is determined, the range of potential difference values of (VINP−VINN) sampled is sequentially narrowed, and finally The correct digital value.

<Decision of MSB (most significant bit)>
SW21 is connected to Vrefp, SW2 to SW4, SW19 are connected to Vrefn, and SW5 is connected to Vrefp. The bottom plate potential of the total capacity 8C of C1 to C4 becomes Vrefn, and the bottom plate potential of the total capacity 24C of C5 and C6 becomes Vrefp. Since the charge QSAMPP stored in the (+) side top plate (TOP +) of Expression (17) is stored, the (+) side top plate (TOP +) potential Vtp at this time is expressed by Expressions (19) and (20). Given in.

−24C (Vrefp−Vtp) + 8C (Vtp−Vrefn) = − 32C (VINP−VINN) / 2; Formula (19)
Vtp = − (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2 + (Vrefp−Vrefn) / (2 × 2); Formula (20)
SW22 is connected to Vrefn, SW8 to SW10, SW20 are connected to Vrefp, and SW11 is connected to Vrefn. The bottom plate potential of the total capacity 8C from C7 to C10 becomes Vrefp, and the bottom plate potential of the total capacity 24C of C11 and C12 becomes Vrefn. Since the charge QSAMPP stored in the (−) side top plate (TOP−) of the equation (18) is stored, the (−) side top plate (TOP−) potential Vtn at this time is expressed by the equations (21) and ( 22).

−8C (Vrefp−Vtp) + 24C (Vtp−Vrefn) = 32C (VINP−VINN) / 2; Formula (21)
Vtn = (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2− (Vrefp−Vrefn) / (2 × 2); Formula (22)
The potential of the top plate becomes the differential inputs CINP and CINN of the comparator. When the difference potential Vtp−Vtn is considered, Expression (23) is obtained.

Vtp−Vtn = − (VINP−VINN) + (Vrefp−Vrefn) / 2;
Formula (23)
In other words, the comparator COMP1 can determine the magnitude relationship between the input potential difference VINP−VINN and a value obtained by halving the reference potential (Vrefp−Vrefn).

<Determination after the next bit of MSB>
Thus, since the digital code corresponding to SW5 and SW11 can be determined, determination of the code (second upper bit) corresponding to SW4 and SW10 will be described.

  Suppose that the digital code corresponding to SW5 and SW11 is determined to be 1, and (VINP−VINN) is larger than (Vrefp−Vrefn) / 2. In this case, (VINP−VINN) and (Vrefp−Vrefn) × 3/4 are compared, the magnitude relation is examined, and the range of the value of (VINP−VINN) is narrowed.

  Specifically, SW21 is connected to Vrefp, SW19, SW2, and SW3 are connected to Vrefn, and SW4 and SW5 are connected to Vrefp. The bottom plate potential of the total capacitance 4C from C1 to C3 becomes Vrefn, and the bottom plate potential of the total capacitance 28C of C4, C5, and C6 becomes Vrefp. The (+) side top plate (TOP +) potential Vtp at this time is given by the equations (24) and (25).

−28C (Vrefp−Vtp) + 4C (Vtp−Vrefn) = − 32C (VINP−VINN) / 2; Formula (24)
Vtp = − (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2 + 3 × (Vrefp−Vrefn) / (2 × 4); Formula (25)

  SW22 is connected to Vrefn, SW20, SW8 and SW9 are connected to Vrefp, and SW10 and SW11 are connected to Vrefn. The bottom plate potential of the total capacity 4C from C7 to C9 becomes Vrefp, and the bottom plate potential of the total capacity 28C of C10, C11, and C12 becomes Vrefn. The (−) side top plate (TOP−) potential Vtn at this time is given by Expression (26) and Expression (27).

−4C (Vrefp−Vtp) + 28C (Vtp−Vrefn) = 32C (VINP−VINN) / 2; Formula (26)
Vtn = (VINP−VINN) / 2 + (Vrefp + Vrefn) / 2−3 × (Vrefp−Vrefn) / (2 × 4) Equation (27)

  The potential of the top plate becomes the differential inputs CINP and CINN of the comparator. When the difference potential Vtp−Vtn is considered, Expression (28) is obtained.

Vtp−Vtn = − (VINP−VINN) + 3 × (Vrefp−Vrefn) / 4;
Formula (28)
That is, the comparator COMP1 can determine the magnitude relationship between the input potential difference VINP−VINN and a value obtained by multiplying the reference potential (Vrefp−Vrefn) by 3/4. Thus, by operating SW2 to SW5, SW8 to SW11, SW19 to SW22, and setting the bottom plate potential of C1 to C12 to Vrefp or Vrefn, the potential difference of VINP−VINN and the potential obtained by dividing Vrefp−Vrefn Can be determined, whereby the range of potential difference values of the sampled VINP-VINN can be sequentially narrowed to determine the final digital value.

<Effect>
As described above, by setting the top plate potentials TOP + and TOP− during sampling to the input common potential (VINP + VINN) / 2, the charges sampled in the (+) side capacitor DAC and (−) side capacitor DAC Are equal in absolute value and opposite in polarity. Therefore, by operating the switches of the (+) side capacitor DAC and the (−) side capacitor DAC symmetrically, the respective capacitor DAC outputs can be operated symmetrically. Further, the common potential of the (+) side top plate (TOP +) potential Vtp and the (−) side top plate (TOP−) potential Vtn is (Vrefp + Vrefn) / 2, which can be the center potential of the reference potential (formula (20) + Expression (22), Expression (25) + Expression (27)), and the operation margin can be maximized.

  As described above, the operation of converting the differential analog input signal into a digital value on the assumption of a sign (assuming VINP> VINN) can be realized by the circuit configuration of FIG.

  In addition, since S4 is provided and S4 is turned on after the sampling is completed, the potentials of NODE1 and NODE2 can be prevented from exceeding the power supply voltage range. Therefore, the charges on top plates TOP + and TOP− are destroyed through S3P and S3N. Therefore, even when an analog input signal having a large amplitude over the power supply voltage range is converted, a correct conversion result can be obtained.

  Furthermore, assuming the sign (assuming VINP> VINN), the analog input potential difference is converted into a digital value, so that the comparison cycle for sign determination can be omitted, and the conversion time can be increased accordingly. .

  In FIG. 1, as an example, a successive approximation AD converter is configured with a 4-bit capacitor DAC, and an example in which the concept of the present invention is applied is shown. However, the number of bits of the DAC is a general case (3 bits or less, Needless to say, it may be 5 bits or more.

<< Second Embodiment >>
An AD converter according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the switch S2P that connects the (+) side analog input to NODE1 and the switch S2N that connects the (−) side analog input VINN to NODE2 are turned OFF, and then the potentials of NODE1 and NODE2 are equal. By turning on the switch S4, the potential fluctuations of NODE1 and NODE2 were suppressed.

  In the present embodiment, in addition to the action of the switch S4, a potential fluctuation suppressing unit that further suppresses potential fluctuations of NODE1 and NODE2 is exemplified. Alternatively, the potential fluctuation suppressing means of this embodiment that replaces the action of the switch S4 is illustrated. Also in this embodiment, at the end of sampling, the switches S2P and S2N that supply the analog input signals VINP and VINN to the bottom plate are turned off. In the present embodiment, at this time, a cup for supplying NODE1 and NODE2 with charges opposite to those injected from the gate capacitances of the switches S2P and S2N so that the potentials of the internal nodes NODE1 and NODE2 do not exceed the power supply voltage range. Ring capacitors NM7, PM7, NM8, and PM8 are provided.

  Other configurations and operations of the present embodiment are the same as those of the first embodiment. That is, in FIG. 4, among the differential capacitors DAC, the potentials of the top plate TOP + and the bottom plate (terminals connected to the switches C1 to C6) of the (+) side capacitor DAC are equalized, and the sampling capacitor of the (+) side capacitor DAC. Of the switch (Fig. 1, S3P), the potential of the top plate TOP- and the bottom plate (terminal connected to the switches C7 to C12) of the (-) side capacitor DAC are equalized, and the sampling of the (-) side capacitor DAC A switch (FIG. 1, S3N) for discharging the capacitance is provided. When the sampling capacitors discharging switches S3P and S3N are ON, the (+) side analog input signal VINP and the (−) side analog input signal VINN and the switches S2P and S2N for separating the bottom plate of the capacitor DAC are provided. A switch S1 is provided for equalizing the potential of the (+) side top plate TOP + and the potential of the (−) side top plate TOP− during sampling of the analog input signal.

In the present embodiment, coupling capacitors NM7, PM7, NM8, and PM8 (FIG. 4) that supply NODE1 and NODE2 with charges opposite to those injected from the gate capacitors of the switches S2P and S2N are provided, and the switches S2P, By driving the capacitors NM7, PM7, NM8, and PM8 with signals (NG7, PG7, NG8, and PG8) that are opposite in phase to the control signal of S2N, the charges injected from the switches S2P and S2N are canceled, and the internal nodes Control can be performed so that the potentials of NODE1 and NODE2 do not exceed the power supply voltage range. Accordingly, it is possible to prevent current from flowing through the top plates TOP + and TOP− through the switches S3P and S3N, and the charges on the top plates TOP + and TOP− are not lost, so that a correct conversion result is obtained.

<Configuration>
In FIG. 4, SW2 to SW5, SW8 to SW11, SW15, SW16, SW19 to SW22, S1, S2P, S2N, S3P, S3N, and S4 are switches, C1 to C12 are capacitors, and VINP is a (+) analog input. , VINN is the (−) analog input, TOP + is the + side top plate of the capacitor array, TOP− is the −side top plate of the capacitor array, Vrefp is the + side reference potential (for example, 5V), and Vrefn is − Side reference potential (for example, 0V), CINP and CINN are comparator inputs, NODE1 and NODE2 are internal nodes, and the (+) side capacitor DAC is a DAC composed of a capacitor array of C1 to C6. The (−) side capacitor DAC is a DAC composed of a capacitor array of C7 to C12, and NM7 and NM8 are NMOS transistors. , PM7, PM8 is a PMOS transistor, NG7, PG 7, NG8, the PG 8 is a gate signal for each NM7, PM7, NM8, PM8 control shows. Also in FIG. 4, portions corresponding to the circuit elements in FIGS. 19, 20, and 1, and elements having the same functions are given the same element names.

  The value of bC (b is an integer) written together with the capacitance Ca (a is an integer) indicates the relative relationship between the sizes of the respective capacitances, as shown in 1C, 2C, 4C, 8C, 16C (etc.). Weighted. C1 to C12 in FIG. 4 constitute a 4-bit DAC.

  The state of the switch illustrated in FIG. 4 indicates the sampling state of the capacitor DAC. At the time of sampling, the potential of VINP is charged from C1 to C6, and the potential of VINN is charged from C7 to C12.

  The main part of the circuit of FIG. 4 is the same as the circuit of FIG. 1. The circuit of FIG. 4 differs from the circuit of FIG. 1 in that NMOS transistors NM7 and NM8 and PMOS transistors PM7 and PM8 are added. is there. Therefore, in the present embodiment, the operation of the NMOS transistors NM7 and NM8 and the PMOS transistors PM7 and PM8 will be mainly described. Parts not specifically described are assumed to operate in the same manner as the circuit of FIG.

  NM7, PM7, NM8, and PM8 function as capacitors for controlling the potentials of NODE1 and NODE2 so as not to exceed the power supply voltage range when the switches S2P and S2N are turned OFF after the sampling is completed. In the circuit example of FIG. 4, the circuit example in which NM7, PM7, NM8, PM8 and the switch S4 are used together is shown, but only NM7, PM7, NM8, and PM8 may be applied. Further, as described in the first embodiment, S4 may be used alone.

  At the end of sampling, the switch S1 is opened (opened), and the switches SW2 to SW5, SW19, and SW21 are floating as viewed from NODE1. The switches SW8 to SW11, SW20, and SW22 are also floating as viewed from NODE2. Further, the switches S2P and S2N are turned off.

As described in the description of FIG. 1, when the potential of the analog input VINP on the + side is a potential close to the positive power supply voltage, the potential of NODE1 is set to the positive power supply voltage due to the gate capacitance of the PMOS transistor constituting the switch S2P. There is a possibility to rise beyond. When VINP and NODE1 are close to the positive power supply voltage (5V) and the switch S2P is closed (conductive, the gate is the negative power supply voltage 0V), an inversion layer is formed immediately below the gate of the PMOS transistor, and the gate oxide film This is because the capacitance due to is inserted between the gate and drain (and source).

  In addition, when the potential of the negative analog input VINN is close to the negative power supply voltage, the potential of NODE2 may be lowered beyond the negative power supply voltage due to the gate capacitance of the NMOS transistor that constitutes S2N. . When VINN and NODE2 are close to the negative power supply voltage (0V) and the switch S2N is closed (conductive, gate is positive power supply voltage 5V), an inversion layer is formed immediately below the gate of the NMOS transistor, and the gate oxide film This is because the capacitance due to is inserted between the gate and drain (and source).

  In order to prevent this, in the circuit of FIG. 1, after turning off S2P and S2N, the switch S4 for equalizing the potentials of NODE1 and NODE2 is turned on. In the circuit of FIG. 4, in addition to the switch S4, NMOS transistors NM7 and NM8 and PMOS transistors PM7 and PM8 are provided. When the switches S2P and S2N are turned OFF, the gate potential NG7 of NM7 is changed from L to H (ON). Further, the gate potential PG7 of PM7 is changed from H to L (ON). Similarly, the gate potential NG8 of NM8 is changed from L to H (ON). Further, the gate potential PG8 of PM8 is changed from H to L (ON).

  PM7 and NM7 correspond to the first adjustment MOS transistor of the present invention. PM8 and NM8 correspond to the second adjustment MOS transistor of the present invention. PM7 and PM8 correspond to the third MOS transistor of the present invention. NM7 and NM8 correspond to the fourth MOS transistor of the present invention.

  If the gate capacitance of the PMOS constituting the switch S2P and the capacitance of the PM7 are made substantially equal, when turning off the PMOS constituting the S2P, the charge to increase the potential of NODE1 is changed from H to L. This can be offset. Similarly, if the gate capacity of the NMOS constituting the switch S2P is substantially equal to the capacity of the NM7, the charge injected from the S2P to the NODE1 when turning off the NMOS constituting the switch S2P is set to L Can be offset by setting H to H.

  If the gate capacitance of the PMOS constituting the switch S2N and the capacitance of the PM8 are substantially equal, when turning off the PMOS constituting the S2N, the charge to lower the potential of NODE2 is changed from H to L. This can be offset. Similarly, if the gate capacity of the NMOS constituting the switch S2N and the capacity of the NM8 are substantially equal, when the NMOS constituting the S2N is turned off, the charge injected from the S2N to the NODE2 is changed from the NG8 to the L. It can be offset by setting H.

  As described above, the potentials of NODE1 and NODE2 can be prevented from exceeding the power supply voltage range also by NM7, PM7, NM8, and PM8 in FIG.

  In the description of FIG. 1, as an example, S2P and S2N are described as being turned off simultaneously. However, S1 is turned off, SW2 to SW5, SW19, and SW21 are floating, and SW8 to SW11, SW20, and SW22 are floating. Thus, the electric charges of the top plates TOP + and TOP− are preserved. Therefore, conversion is possible without necessarily turning off both S2P and S2N. Moreover, if the timing which turns off S2P and S2N is after the completion | finish time of a sampling, it can be set as a late time as needed. Furthermore, it is not essential that the timings for turning off S2P and S2N are the same.

When the times when S2P and S2N are OFF are different, the gate potential NG7 of NM7 is changed from L to H at the time when S2P is OFF. At that time, the gate potential PG7 of PM7 is changed from H to L. At the time when S2N is turned OFF, the gate potential NG8 of NM8 is changed from L to H. At that time, the gate potential PG8 of PM8 is changed from H to L.

  By turning ON S4 in FIG. 1, one of the potentials of NODE1 and NODE2 (that is, the analog input potential VINP and VINN) immediately before turning off S2P and S2N is a potential close to the positive power supply voltage or negative Even if the potential is close to the power supply voltage, the potential of NODE1 and NODE2 can be prevented from exceeding the power supply voltage range if the potential difference between NODE1 and NODE2 is large to some extent.

  However, for example, when the potentials of VINP and VINN are both close to the negative power supply voltage and the potential difference is small, the effect of S4 is small. By using the capacitors NM7, PM7, NM8, and PM8 that cancel the charges injected from S2P and S2N as in the circuit of FIG. 6, even when both VINP and VINN are 0 V, for example, the potentials of NODE1 and NODE2 Can be controlled within the power supply voltage range. Needless to say, if NM7, PM7, NM8, PM8 and S4 are used in combination, the design becomes easier.

  Similarly, for example, when the potentials of VINP and VINN are both close to a positive power supply voltage and the potential difference is small, capacitors NM7, PM7, NM8, and PM8 that cancel out charges injected from S2P and S2N. By using this, the potentials of NODE1 and NODE2 can be controlled within the power supply voltage range.

  As described above, the circuit configuration of FIG. 4 also suppresses the potentials of NODE1 and NODE2 from exceeding the power supply voltage range by S4, NM7, PM7, NM8, and PM8, as in the circuit of FIG. Therefore, it is possible to avoid the destruction of the charges of the top plates TOP + and TOP− through S3P and S3N, and a correct conversion result can be obtained even when converting an analog input signal in the power supply voltage range.

  Since the circuits other than NM7, PM7, NM8, and PM8 are the same as the circuit of FIG. 1, the differential analog input signal is converted into a digital value by assuming a sign (assuming VINP> VINN) as in the circuit of FIG. The operation can be realized, the comparison cycle for code determination can be omitted, and the conversion time can be increased accordingly.

<< Third Embodiment >>
5 and 6 are circuit diagrams showing an AD converter according to the third embodiment of the present invention. In FIG. 5, SW2 to SW5, SW8 to SW11, SW13 to SW16, SW19 to SW22, S1, S2P, S2N, S3P, S3N, and S4 are switches, C1 to C12 are capacitors, and VINP is a (+) analog input. , VINN is the (−) analog input, TOP + is the + side top plate of the capacitor array, TOP− is the −side top plate of the capacitor array, Vrefp is the + side reference potential (for example, 5V), and Vrefn is -Side reference potential (for example, 0V), COMP1 is a comparator, CINP and CINN are comparator inputs, COUT1 is a comparator output, VCM is a bias potential of the comparator input at the time of sampling, NODE1 and NODE2 are internal The node is composed of a capacitor array of C1 to C6 on the (+) side capacitor DAC The DAC that, (-) side capacitance DAC is a DAC composed of a capacitor array of the C12 from the C7, shown. In FIG. 6, RDACP and RDACN indicate resistor DAC outputs, RDAC1 indicates a resistor DAC, RD0 to RD7 indicate resistors, NRD1 to NRD7 indicate internal nodes of the resistor DAC, and SEL1 and SEL2 indicate selectors. In FIG. 5, parts corresponding to the circuit elements in FIGS. 1 and 4 and elements having the same function are given the same element names.

  The resistor DAC is a circuit that generates analog data by taking out a voltage divided by a resistor corresponding to digital data.

  The value of bC (b is an integer) written together with the capacitance Ca (a is an integer) indicates the relative relationship between the sizes of the respective capacitances, as shown in 1C, 2C, 4C, 8C, 16C (etc.). Weighted. C1 to C12 in FIG. 5 constitute a 4-bit DAC. Further, in the circuit of FIG. 5, only the switch S4 is illustrated as in the circuit of FIG. 1, but the NMOS transistors NM7 and NM8 and the PMOS transistors PM7 and PM8 described in the second embodiment (FIG. 4) are used. You can also NM7, PM7, NM8, and PM8 are omitted from FIG. 5 for the purpose of simplifying the drawing. Accordingly, in the following drawings including FIG. 5, NMOS transistors NM7 and NM8 and PMOS transistors PM7 and PM8 may be used in place of S4 in the portion using the switch S4. Further, S4 and NM7, PM7, NM8, PM8 may be used in combination.

  The circuit of the present embodiment (FIGS. 5 and 6) is different from the circuits of FIGS. 1 and 4 in that the AD converter circuit is configured by only a capacitor DAC (for example, 4 bits) in the circuits of FIGS. In contrast, the circuit of the present embodiment is configured such that the AD conversion is performed by the CR double stage DAC in which the upper bit is determined by the capacitor DAC and the lower bit is determined by the resistor DAC. is there. As shown in FIGS. 5 and 6, the concept of the present invention can be applied to a composite DAC of capacitance and resistance.

  In the operation of the circuits of FIGS. 5 and 6, the description of the same parts as those of the circuit of FIG. 1 and the circuit of FIG. In the circuit of FIG. 1, when searching for a digital code corresponding to an analog input, the bottom plate of C1 is fixed to Vrefn, the bottom plate of C6 is fixed to Vrefp, and the bottom plates of C2 to C5 are connected to corresponding digital values. Is connected to Vrefp if the corresponding digital value is 0 (the negative side capacitor DAC is symmetrical to the positive side capacitor DAC, and if the corresponding digital value is 1, the corresponding digital value is 0. If it is connected to Vrefp, the bottom plate is fixed to Vrefp symmetrically with C1 for C7, and the bottom plate is fixed to Vrefn symmetrically with C6 for C12).

  As shown in FIG. 1, when an AD converter circuit is configured with only one stage of DAC, for example, when 10-bit resolution is required, 2048 unit capacitors are required on one side only, There was a problem that would increase. The problem of the occupied area can be solved by making the DAC a double stage DAC. An example of combining the double stage DAC and the idea of the present invention is shown in FIG.

  As shown in FIG. 5, a CR double stage DAC can be configured by connecting the resistor DAC output RDACP to the bottom plate of C1. Further, by connecting the resistor DAC output RDACN to the C7 bottom plate of the negative side capacitor DAC, a CR double stage DAC can also be configured for the negative side capacitor DAC.

  RDAC1 in FIG. 6 shows an example of a resistor DAC for converting the lower 3 bits. The unit resistors RD0 to RD7 divide the reference voltage (potential difference between Vrefp and Vrefn) into 8 equal parts (from the lower potential in order from NRD1 to NRD7). Gave the sign). SEL1 selects Vrefn and the potential of one of the internal nodes NRD1 to NRD7 of the resistor DAC based on the input digital value, and outputs it to RDACP (in the most straightforward configuration, Vrefn is output when the input digital value is 000. As the digital value increases, values up to NRD7 are output).

SEL2 selects one of the potentials Vrefp and NRD7 to NRD1 based on the input digital value, and outputs it to RDACN (in contrast to RDACP, when the input digital value is 000, Vrefp is output and the digital value is output. As the value increases, the potential is gradually lowered to a value up to NRD1).

  By connecting the resistor DAC output RDACP to the bottom plate of C1 and connecting the resistor DAC output RDACN to the C7 bottom plate of the negative side capacitor DAC, the influence of the resistor DAC outputs RDACP and RDACN on the top plate potential can be reduced. The number of DACs can be reduced by an amount corresponding to the number of bits. In the case of FIGS. This is because, for example, the resistor DAC output is added to the top plate potential TOP + via the unit capacitor 1C having a magnitude of 1/32 with respect to the total sampling capacitor of the (+) side capacitor DAC.

  By the way, as can be seen from the equations (19) to (23) used in the description of FIG. 1, the input analog potential is ½ when only one DAC is considered. That is, paying attention to the one-side capacitor DAC, the equation is a comparison between a signal having a half amplitude of the input potential difference VINP−VINN and a signal having a half amplitude of the reference potential difference Vrefp−Vrefn. In consideration of the difference between the output signals of the capacitive DACs on both sides (the potential difference between the + side TOP + and the −side TOP−), an equation for comparing the signal of the input potential difference VINP−VINN and the signal of the reference potential difference Vrefp−Vrefn It has become.

  Therefore, the resistance DAC output (RDACP, RDACN) attenuated to 1/32 is equivalent to being attenuated to 1/16 for TOP + and TOP−, corresponding to the number of bits of the 4-bit capacitor DAC. The weight is small. As a result, the DAC of FIG. 5 works as a 7-bit DAC in total.

  As shown in FIGS. 5 and 6, even if the DAC is a double-stage DAC including a capacitor and a resistor, the circuit portion including the switches S2P, S2N, S1, S3P, S3N, and S4 shown in the circuit of FIG. Since the operation of the circuit does not need to be changed, the same effect as that of the circuits of FIGS.

  As described above, the present invention can be applied even when a CR double stage DAC is used. That is, the potential fluctuation suppressing technology of NODE1 and NODE2 by the combination of the switch S4 (or NMOS transistors NM7, NM8 and PMOS transistors PM7, PM8) and the switches S1, S2P, S2N, S3P, S3N can be applied as it is. Therefore, the advantage of the double-stage DAC that can occupy a small area, the characteristics that a correct conversion result can be obtained even when converting an analog input signal in the power supply voltage range, and the conversion by omitting the comparison cycle for sign determination Both speeding up of time can be achieved.

<< 4th Embodiment >>
7 and 8 are circuit diagrams showing an AD converter according to the fourth embodiment of the present invention. In FIG. 7, SW2 to SW5, SW8 to SW11, SW15, SW16, SW19 to SW24, S1, S2P, S2N, S3P, S3N, S4 are switches, C1 to C14 are capacities, TOP + is the + side top plate of the capacity array TOP− is the negative side top plate of the capacitor array, Vrefp is the positive side reference potential (for example, 5V), Vrefn is the negative side reference potential (for example, 0V), and CINP and CINN are the inputs of the comparator. , NODE1 and NODE2 are internal nodes, the (+) side capacitor DAC is a DAC composed of C1 to C6 and C13 capacitor arrays, and the (−) side capacitor DAC is composed of C7 to C12 and C14 capacitor arrays. The DAC is shown. In FIG. 8, RDACLP, RDACUP, RDACLN, and RDACUN indicate resistance DAC outputs, VOFFP and VOFFN indicate bias potentials for giving an offset to the conversion result, RDAC2 indicates resistance DAC, RU1 to RU14, and RH1 to RH8 indicate resistances. , NRU1 to NRU4, NRU8, NRU12 to NRU15 are resistance DACs
SEL3, SEL4, SEL5, and SEL6 indicate selectors.

  Parts corresponding to circuit elements in FIGS. 1, 4, 5, etc., and elements having the same functions are given the same names. In order to simplify the drawing, there are some parts omitted from the drawing, such as VINP, VINN, S2P, S2N, and comparator COMP1, but the omitted parts are shown in FIG. Assume that the configuration is the same as in FIGS.

  The value of bC (b is an integer) written together with the capacitance Ca (a is an integer) indicates the relative relationship between the sizes of the respective capacitances, as shown in 1C, 2C, 4C, 8C, 16C (etc.). Weighted.

  5 and 6 show examples of supplying the resistor DAC output to the bottom plates of C1 and C7. In the circuits of FIGS. 7 and 8, C13 and C14 are provided in addition to C1 and C7. In this example, the resistor DAC output is supplied to the bottom plates of C1, C13, C7, and C14, and the respective resistor DAC outputs are added by the capacitors using C1, C7, or C13 and C14. In this embodiment, even in the circuit configurations as shown in FIGS. 7 and 8, the configuration of the switches S1, S2P, S2N, S3P, S3N, S4 (and NM7, PM7, NM8, PM8) is not changed. It shows that the invention is equally applicable.

  The circuit of FIG. 7 is different from the circuit of FIG. 5 or the like in the circuit of FIG. 5 or the like in which the upper bit is determined by the capacitor DAC and the lower bit is determined by a single resistor DAC. In FIG. 7, capacitors C13 and C14 for adding another resistor DAC output are provided.

  In the operation of the circuits of FIGS. 7 and 8, the description of the same parts as those of the circuits of FIGS.

  First, the configuration of the resistor DAC will be described with reference to FIG. RDAC2 in FIG. 8 functions as a resistor DAC for converting the lower 4 bits. RU1 to RU14 and RH1 to RH8 represent unit resistors having the same resistance value. Since RH1 to RH4 are connected in series with two unit resistors connected in parallel, four resistors are eventually equivalent to one unit resistor. Similarly for RH5 to RH8, the combined resistance is equivalent to the unit resistance with four resistors. Therefore, the reference voltage (potential difference between Vrefp and Vrefn) is divided into 16 equal parts by RU1 to RU14 and RH1 to RH8. NRUe (e is an integer) is given to the internal node of the resistor DAC in ascending order of potential. Here, e of NRUe corresponds to e / 16 of the reference potential divided into 16 equal parts.

  VOFFN obtained by further dividing the potential difference between NRU15 and Vrefp by RH5 to RH8 into two becomes (Vrefp−Vrefn) / 32 lower potential than Vrefp. Similarly, VOFFP obtained by further dividing the potential difference between NRU1 and Vrefn by RH1 to RH4 into two becomes (Vrefp−Vrefn) / 32 higher potential than Vrefn.

  RDAC2 receives a 4-bit digital signal, outputs a potential corresponding to the upper 2 bits to RDACUN and RDACUP, and outputs a potential corresponding to the lower 2 bits to RDACLN and RDACLP. Works as.

  One of the potentials of Vrefn, NRU1, NRU2, and NRU3 is selected by SEL5 and output to RDACLP. When the lower two input bits of RDAC2 are 00, Vrefn is output, and higher potentials NRU1, NRU2, and NRU3 are selected corresponding to 01, 10, and 11, respectively.

  RDACLN outputs a potential symmetrical to RDACLP. One of the potentials of Vrefp, NRU15, NRU14, and NRU13 is selected by SEL4 and output to RDACLN. When the input lower 2 bits of RDAC2 are 00, Vrefp is output, and lower potentials NRU15, NRU14, and NRU13 are selected corresponding to 01, 10, and 11, respectively.

  Next, the potential of RDACUP will be described. One of the potentials of Vrefn, NRU4, NRU8, and NRU12 is selected by SEL6 and output to RDACUP. When the input upper 2 bits of RDAC2 are 00, Vrefn is output, and higher potentials NRU4, NRU8, and NRU12 are selected corresponding to 01, 10, and 11, respectively.

  Next, the potential of RDACUN will be described. RDACUN outputs a potential symmetrical to RDACUP. One of the potentials Vrefp, NRU12, NRU8, and NRU4 is selected by SEL3 and output to RDACUN. When the upper two input bits of RDAC2 are 00, Vrefp is output, and lower potentials NRU12, NRU8, and NRU4 are selected corresponding to 01, 10, and 11, respectively.

  By supplying RDACUP, RDACLP, RDACUN, and RDACLN having such characteristics to the bottom plates of the minimum capacitors C1, C13, C7, and C14 of the capacitor DAC as shown in FIG. 7, the resistor DAC output is added to the capacitor. A CR double stage DAC can be constructed.

  C1 and C7 in FIG. 7 also function as sampling capacitors, like C1 in the circuit in FIG. 5 and C1 and C7 in the circuit in FIG. C13 and C14 are provided in parallel with this. Since C13 and C14 are not capacitors for sampling VINP and VINN, the operation of the capacitor DAC itself is equivalent to the circuit of FIG. 5 considering C1 to C12.

  In the circuit of FIG. 7, C13 and C14 are added to these circuit portions, and it can be considered that the potential of RDACLP and the potential of RDACLN are added to the potentials of the top plate potential TOP + and TOP− at C13 and C14. .

  In FIG. 1 or FIG. 5, even if there is a parasitic capacitance between the top plate and a predetermined potential, if the parasitic capacitance is equal between TOP + and TOP-, the result is not affected. That is, the operation of the capacitive DAC is roughly the same in FIG. 7 with and without C13 and C14. Therefore, C13 and C14 are separately provided, a resistance DAC output is added to the bottom plate, and the RDACLP potential and the RDACLN potential are set to the top plates TOP + and TOP− (the total capacitance and the capacitance of 1C). You will understand the validity of adding (with a determined weight).

  Here, the purpose of VOFFP and VOFFN will be described. In the AD conversion circuit, in the input / output characteristics of the analog input potential and the digital conversion result, the transition point of the digital code (conversion result) is shifted by 1/2 × LSB from the characteristics realized by the circuits of FIGS. Sometimes it is desirable. C13 and C14 in FIG. 7 and VOFFP and VOFFN supplied to these bottom plates at the time of sampling are for that purpose.

As already described, the potential of VOFFN is a potential that is (Vrefp−Vrefn) / 32 lower than Vrefp. VOFFP has a potential higher than (Vrefp−Vrefn) / 32 from Vrefn. Since each voltage NRUe (e is an integer) divided into 16 by RDAC2 corresponds to the LSB of the AD converter circuit of FIG. 8, VOFFP and VOFFN are sampled from a positive / negative reference voltage to a voltage equivalent to 1/2 × LSB. Sometimes it is supplied to the bottom plates of C13 and C14.

  Considering the signal on the + side, at the time of sampling, a voltage equivalent to 1/2 × LSB is supplied to C13 having a capacity of 1/32 of the entire + side capacitor DAC. At the time of search, a voltage of 0/16, 1/16, 2/16, or 3/16 (voltage corresponding to 0 to 3LSB) is input to C13 as a resistor DAC output VOFFP with 0V as a reference. Will be. The same applies to the negative side capacitor DAC and the resistor DAC output VOFFN.

  Thus, the sampling result is shifted by a potential equivalent to 1/2 × LSB at the start of conversion.

  7 and 8 show the case where the resolution of the capacitive DAC is 4 bits and the resolution of the resistor DAC is 4 bits (2 bits + 2 bits) as an example. However, the present invention is not limited to the cases of FIGS. Including the circuit of FIG. 5, the concept of the present invention can be easily applied in the case of general resolution (both the capacitive DAC and the resistor DAC).

  By adopting the configuration shown in FIGS. 7 and 8, in addition to the effect of the present embodiment, the effect of reducing the area can be obtained.

  Even if the capacitive DAC is changed to a complex CR double stage DAC as shown in FIGS. 7 and 8, the control necessary for S1, S2P, S2N, S3P, S3N, and S4 described in FIG. 1 or FIG. There is no effect on its work. As described above, the successive approximation AD converter circuit configured by the CR double stage DAC (a circuit that generates digital data by shifting the sampling result by 1/2 × LSB) configured as shown in FIGS. Also, the idea of the present invention can be applied.

<Comparator configuration>
Here, with reference to FIG. 9, a comparator applicable to the AD converter according to each embodiment of the present invention will be described. 1, FIG. 4 to FIG. 8 have mainly described the configuration example of the circuit up to the capacitive DAC and the concept of operation of the switch S4 and the like. FIG. 9 shows a circuit example of a comparator that detects the capacitive DAC output and the potential difference between TOP + and TOP−.

  In FIG. 9, SW13 to SW16, SW25 to SW29, S1 are switches, CC1 to CC5 are coupling capacitances, TOP + is a positive side top plate of the capacitance array, TOP− is a negative side top plate of the capacitance array, CINP, CINN Is a comparator input, VCM is a comparator bias potential (2.5 V) at the time of sampling, early, late, conv are timing signals shown in the figure, AMP1 to AMP4 are amplifier circuits, NC1 to NC10 are internal nodes , COUT2 indicates the comparison result of the comparator. The node names and the like corresponding to those in FIGS. 1 and 5 to 8 are given the same element names and node names.

  The timing signal name written together with the switch indicates the timing when the switch is closed. The switch state in FIG. 9 indicates the control of the switch in a state where the potentials of VINP and VINN are sampled in the capacitor DAC.

  First, a state in which the potentials VINP and VINN in FIG. 9 are sampled in the capacitor DAC will be described.

  As already described, the top plates TOP + and TOP− of the capacitor DAC are controlled by S1 so as to have the same potential and the common potential of the input analog potential.

  At the end of the comparison period in which the capacitor DAC switch is operated and the bit is determined by the comparator, the final potentials of TOP +, TOP-, and comparator inputs CINP and CINN are approximately VCM (1 / V of the reference potential). 2). This is because the comparator COMP1 described in the first to fourth embodiments includes the output signal of the (+) side capacitor DAC (the potential of the + side top plate TOP +) and the output signal of the − side capacitor DAC (the − side top plate TOP). This is because the (+) side capacitor DAC and the (+) side capacitor DAC are controlled so that the potential difference is eliminated. That is, at the final point of the comparison period, the final potentials of TOP +, TOP-, and comparator inputs CINP and CINN are ½ of the reference potential if the offset of the comparator COMP1 is ignored.

  In this case, it is desirable to store the offset voltage of the comparator by some means while applying a common potential that is ½ of the reference potential, and execute auto zero.

  However, the potentials of TOP + and TOP− during sampling become the common potential of the analog inputs VINP and VINN. In general, it cannot be expected that the common potential of the analog inputs VINP and VINN and 1/2 of the reference potential ((Vrefp + Vrefn) / 2) match. Therefore, during sampling, CINP and CINN are separated from TOP + and TOP− by SW15 and SW16, and 1/2 of the reference potential ((Vrefp + Vrefn) / 2), that is, VCM is separately applied to CINP and CINN. , Store the offset voltage and execute auto zero.

  For example, if there is an offset in AMP1 in FIG. 9, even if the same VCM ((Vrefp + Vrefn) / 2) potential is applied to CINP and CINN, their outputs NC1 and NC2 do not become the same potential. By storing this in CC1 and CC2, the offset voltage can be canceled.

  For example, equal potential VCM is applied to CINP and CINN. At this time, the potentials of NC1 and NC2 are not equal due to the offset voltage of AMP1. Assume that the potential of NC1 is 1/2 + 100 mV of the power supply voltage and the potential of NC2 is 1 / 2-100 mV of the power supply voltage. SW25 and SW26 are closed. The potentials of NC3 and NC4 are equivalent to the offset voltage of AMP2.

  Assuming that the offset voltage of AMP2 is 10 mV (assuming that when NC4 is 10 mV greater than NC3, the output potential of AMP2 is about 1/2 of the power supply voltage), the potential of NC4 is 1/2 + 5 mV of the power supply voltage, NC3 Is ½-5 mV of the power supply voltage. The potential of NC1 is 1/2 + 100 mV of the power supply voltage, and the potential of NC2 is 1 / 2-100 mV of the power supply voltage. That is, the potential at both ends of CC1 is 1/2 + 100 mV of the power supply voltage and 1 / 2-5 mV of the power supply voltage, and the potential at both ends of CC2 is 1 / 2-100 mV of the power supply voltage and 1/2 + 5 mV of the power supply voltage. .

  Even if there is an offset voltage in AMP1 and AMP2, the potentials of NC5 and NC6 can be made substantially equal by storing charges in CC1 and CC2 during sampling. Thus, when a potential difference between CINP and CINN occurs, the potentials of NC5 and NC6 change, and the magnitude relationship between CINP and CINN can be determined without being affected by the offset voltage.

As described above, SW25, SW26, SW27, SW28, and SW29 are closed during a period in which VINP and VINN are sampled into the capacitor DAC. By closing SW25 and SW26, the potential difference between NC3 and NC4 becomes a value about the offset voltage of AMP2.

  Similarly, for AMP3, an offset voltage is stored in the coupling capacitors CC3 and CC4. Since the potentials of NC7 and NC9 are equal, if the amplification factor is very large, the potential difference between NC8 and NC7 is equal to the offset voltage. This is because, when the potential difference between NC8 and NC7 is not equal to the offset voltage, the output voltage becomes a value about the power supply voltage of + or-. (It is easy to understand if the limit of the amplification factor is very large.) Information that the potential difference between NC7 and NC8 is equal to the offset voltage of AMP3 is stored in CC3 and CC4. When the potential changes from the state at the time of sampling and either of them changes higher or lower, the magnitude relationship can be determined by AMP3 without being affected by the offset voltage of AMP3.

Further, for AMP4, an offset voltage is stored in the coupling capacitor CC5.
For example, it is assumed that NC9 is 1/2 of the ideal value power supply voltage. If the logic threshold value of AMP4 is ½ of the power supply voltage, the offset of AMP4 is 0. Actually, however, the logic threshold value of AMP4 deviates from ½ of the power supply voltage due to manufacturing conditions. Even in such a case, the potential of NC10 during sampling can be set to the logic threshold value of AMP4 by equalizing the potentials of NC10 and COUT2 by SW29. Thereby, it can be detected by AMP4 and CC5 whether the potential of NC9 is higher or lower than the potential during sampling.

  After VINP and VINN are sampled into the capacitor DAC, the switch with early written together is opened. Next, the switch with “late” is opened, and the switch with “conv” is closed.

  As an example, the circuit as shown in FIG. 9 can detect the potential difference between the output TOP + and TOP− of the capacitor DAC and determine the magnitude relationship.

<< 5th Embodiment >>
FIG. 10 shows an example of a block diagram of a successive approximation AD converter circuit according to the fifth embodiment of the present invention, and FIG. 11 shows an example of operation timing thereof. Here, the circuit including the switch S1 and the PMOS transistors PM7 and PM8 and the MNOS transistors NM7 and NM8 shown in FIG. 4 is used as the capacitor DAC.

  In FIG. 10, VINP is a (+) analog input, VINN is a (−) analog input, TOP + is a positive side top plate of the capacitor array, TOP− is a negative side top plate of the capacitor array, and COUT is a comparator circuit. RDO is the resistor DAC output, CNTR is the resistor DAC control signal, CNTC is the capacitor DAC control signal, CLK is the clock input that defines the overall timing of the AD converter circuit, SPC is the sampling period, S3P, A signal that defines a discharge period for turning ON S3N (a period for initializing the charge of the sampling capacitor to 0), D [11: 0] is a (for example) 12-bit AD conversion result, CDAC1 is a capacitor DAC, COMP Denotes a comparator, RDAC3 denotes a resistor DAC, and CNT denotes a control circuit that controls successive approximation. In FIG. 10, the same element names and terminal names are given to the portions corresponding to the circuits of FIGS.

The operation of the circuit of FIG. 10 will be described with reference to FIG. Assume that a clock signal CLK is input as shown in FIG. After the control signal SPC changes to H, for example, during a period of 2.5 clocks (CLK cycle time), S3P and S3N are turned ON, and the charge of the sampling capacitor of the capacitor DAC is initialized to zero. Next, VINP and VINN are sampled until one clock period after SPC changes from H to L (the period in which S3P and S3N are ON is the “discharge period” in FIG. 11, and the analog input signal thereafter The sampling period for sampling the signal is shown as “sampling period”).

  After the end of the sampling period, input signals of the capacitor DAC (CDAC1) and the resistor DAC (RDAC3) are controlled to determine from the MSB to the LSB in order (shown as a compare period in FIG. 11). After the LSB determination is completed, the conversion result D [11: 0] becomes valid.

  An example in which the circuit of the invention of FIG. 10 is designed to operate at the timing of FIG. 11 and the waveform of each part is obtained by circuit simulation is shown in FIGS. 12A to 12D, 13A to 13C, and 14A to 14C. . Here, the circuit shown in FIG. 4 was used as the circuit of the CDAC1 that is the capacitive DAC shown in FIG. Each of the switches S1, S2P, S2N, S3N, S3P, and S4 is configured by combining a PMOS transistor and an NMOS transistor, such as PM5 and NM5 in FIG.

  These NMOS transistors, PMOS transistors, and PM7, NM7, PM8, NM8, etc. shown in FIG. 4 use a MOS model assuming a 5V withstand voltage MOS transistor with a channel length of about 0.7 um, and operate with a SPICE simulator. The waveform was obtained.

  12A to 12D show the waveform of each part when the power supply voltage is 5 V, Vrefp = 5 V, Vrefn = 0 V, VINP = 1.2 mV, and VINN = 0 V (when 1/4096 obtained by dividing 5V into 4096 is input) Show). However, FIG. 12D is a result of enlarging the time point of shifting from sampling to comparison by the comparator in the waveform of FIG. 12A.

  13A to 13C show the waveform of each part when the power supply voltage is 5V, Vrefp = 5V, Vrefn = 0V, VINP = 4.998V, VINN = 0V (4094/4096 obtained by dividing 5V into 4096) Show the case).

  14A to 14C show the waveform of each part when the power supply voltage is 5V, Vrefp = 5V, Vrefn = 0V, VINP = 1.666V, VINN = 0V (1365/4096 obtained by dividing 5V into 4096) Show the case).

  Since this is an example of 12-bit AD conversion, the expected conversion results are 000000000001 in the case of FIGS. 12A to 12C, 111111111110 in the case of FIGS. 13A to 13C, and 010101010101 in the case of FIGS. 14A to 14C.

  The waveform in FIG. 12A shows a waveform corresponding to NODE1 and NODE2 in FIG. 1, FIG. 4 or FIG. 12A to 12C, in the discharge period (the period in which the charge of the sampling capacitor is initially set to 0), the potential of NODE2, the potential of VINN, the top plate TOP +, TOP−, and the potential of NODE1 are also VINN. The switch is controlled to be equal to the potential. Since the inputs are very small, VINP = 1.2 mV and VINN = 0V, the potentials of NODE1 and NODE2 appear almost 0V in FIG. 12A.

In the graph of FIG. 12A, it seems that the potentials of NODE1 and NODE2 do not exceed the power supply voltage range during the comparison period of the comparator. However, as shown in FIG. 12D, when the time point of shifting from sampling to comparison by the comparator is enlarged, a finer phenomenon is clearly shown. According to FIG. 12D, it can be seen that the potential of NODE2 has dropped to about −0.08 V at the time of shifting from sampling to comparison with a comparator. As described above, in FIG. 4, when the potential of VINN is approximately 0V and the potential of NODE2 is approximately 0V and the switch S2N is cut off, an inversion layer is formed in the NMOS transistor that constitutes S2N. Therefore, the gate capacitance is connected between the gate, drain, and source through the inversion layer, and the gate potential of the NMOS transistor that constitutes S2N changes from 5V to 0V, so that the potential of NODE2 is changed via the gate capacitance. This is because it becomes lower.

  However, in the simulation result of FIG. 12D, as described in FIG. 4, when S2P and S2N are shut off, NODE1 and NODE2 are equalized by S4. Further, the gate potentials of the transistors NM7, NM8, PM7, and PM8 connected to NODE1 and NODE2 are changed in the opposite direction to the gate potentials of the transistors that constitute S2P and S2N (the transistors are turned on). As a result, it can be seen that the potential of NODE2 once lowered to about -0.08 V rises and falls within the power supply voltage range. Further, it is understood that the potentials of NODE1 and NODE2 are equal to each other by equalization.

  In this way, by controlling the potentials of the nodes NODE1 and NODE2 within the power supply voltage range as much as possible, the current flowing through the top plates TOP + and TOP− through the switches S3P and S3N can be reduced. As a result, the loss of the charges on the top plates TOP + and TOP− is suppressed, and a more accurate conversion result can be obtained.

  After completion of sampling, comparison by the comparator is started (in FIG. 12A, the comparison is made by the comparator). It can be seen that the comparator output has changed to 000000000001 (waveform diagram in FIG. 12C). This is consistent with the expectation stated above.

  FIG. 12B (shown as a waveform of the capacitive DAC output) shows the waveforms of TOP + and TOP−. During the sampling period, the potentials of TOP + and TOP− become the input common potential, and thus are approximately 0V. When the comparison starts, the common potential becomes about 2.5 V, and gradually changes from a state where the potential difference is large to a state where the potential difference is small. Eventually, the potentials of TOP + and TOP− substantially coincide with each other.

  In FIGS. 13A to 13C, the potentials of NODE1 and NODE2 are 0 V given by VINN during the discharge period. From FIG. 13A, it can be seen that during the sampling period, the potentials of VINP and VINN are about 5V and 0V, respectively, so that the potentials of NODE1 and NODE2 are about 5V and 0V, respectively. It can be seen from the waveforms of TOP + and TOP− in FIG. 13B that the potential of TOP + and TOP− is about 2.5 V during the sampling period. It can also be seen that the potentials of NODE1 and NODE2 do not exceed the power supply voltage range during the comparison period of the comparator.

  FIG. 13C also shows that the comparator output matches the expected value 111111111110. TOP + and TOP− gradually change from a state in which the potential difference is large to a state in which the potential difference is small. Finally, the potentials of TOP + and TOP− almost coincide with each other. The sign is opposite to that in FIG.

  14A to 14C, the potentials of NODE1 and NODE2 are 0 V given by VINN during the discharge period. FIG. 14A shows that the potentials of VINP and VINN are approximately 1.6 V and 0 V during the sampling period, and therefore the potentials of NODE1 and NODE2 are approximately 1.6 V and 0 V, respectively. It can be seen from the waveforms of TOP + and TOP− in FIG. 14B that the potential of TOP + and TOP− is about 0.8 V during the sampling period. It can also be seen that the potentials of NODE1 and NODE2 do not exceed the power supply voltage range during the comparison period of the comparator.

  From FIG. 14C, the comparator output changes to 010101010101, and the sign of the potential difference alternately changes corresponding to the change of the comparator output of 010101010101. From FIG. 14B, at the end of the comparison, the potentials of TOP + and TOP− are substantially the same.

  As described above, it can be understood from the waveform diagrams that the circuits shown in FIGS. 10, 11 and others operate as described in the explanation of the respective drawings.

<< 6th Embodiment >>
<Overview>
With reference to FIG. 15, an AD converter according to a sixth embodiment of the present invention will be described. In the present embodiment, switches (SW30, SW31, SW32, SW33) are provided at the input portion of an AD converter that converts a differential analog input into a digital value assuming a sign. Further, a comparator COMP2 for determining the magnitude relationship between the (+) side analog input signal VINP and the (−) side analog input signal VINN is provided. An AD converter that converts a differential analog input to a digital value assuming a sign converts the analog difference potential (ICDACP-ICDACN) to a digital value assuming that its input ICDACP is greater than or equal to ICDACN, If VINP is greater than VINN, VINP is supplied to ICDACP and VINN is supplied to ICDACN. Conversely, if VINP is smaller than VINN, the switches (SW30, SW31, SW32, SW33) may be operated so as to supply VINP to ICDACN and VINN to ICDACP.

  With these ideas, it is possible to realize a circuit that converts an analog signal including a sign into a digital value, if necessary, using an AD circuit that assumes the sign and converts the analog signal into a digital value.

<Example>
FIG. 15 shows an example of a block diagram of the successive approximation AD converter circuit of this embodiment. In FIG. 15, VINP is a (+) analog input, VINN is a (−) analog input, TOP + is a + side top plate of the capacitor array, TOP− is a −side top plate of the capacitor array, and COUT is a comparator circuit. RDO is the resistor DAC output, CNTR is the resistor DAC control signal, CNTC is the capacitor DAC control signal, CLK is the clock input that defines the overall timing of the AD converter circuit, SPC is the sampling period, S3P, A signal that defines a discharge period for turning ON S3N (a period for initializing the charge of the sampling capacitor to 0), D [11: 0] is a (for example) 12-bit AD conversion result, CDAC1 is a capacitor DAC, COMP Is a comparator, RDAC3 is a resistor DAC, ICDACP and ICDACN are inputs of a capacitor DAC. CNT is a control circuit for controlling the sequential comparison, the switch SW33 from the SW 30, COMP2 is a comparator determining the sign of the input, SIGN is the sign which is determined by the comparator, shown. In the circuit of FIG. 15, portions corresponding to the circuit of FIG. 10 are given the same element names and terminal names.

  In the circuits of FIGS. 1 and 4 to 10, it is possible to save the conversion cycle and increase the speed by performing AD conversion on the assumption that VINP is larger than VINN (VINP> VINN). explained. When it is guaranteed that VINP is larger than VINN in application, the circuits of FIGS. 1 and 4 to 10 may be applied as they are.

  If it is not always guaranteed that VINP is larger than VINN, for example, the circuit configuration shown in FIG. 15 is used to digitally convert the analog signal potential difference including the sign without impairing the advantages of this embodiment. A circuit can be realized.

The circuit of FIG. 15 has almost the same configuration as the circuit of FIG.
Since it is P2, SW30 to SW33, the description of the overlapping part is omitted, and the description is focused on the part different from the circuit of FIG.

  SW30 to SW33 are provided in the input portion of the circuit of FIG. 10, and the magnitude relationship between VINP and VINN is examined by the comparator COMP2. When VINP> VINN, SW31 and SW32 are turned ON, and VINP is supplied to the + side input of CDAC1, and VINN is supplied to the −side input of CDAC1 (SW30 to SW33 are controlled by COMP2 output SIGN). Conversely, when VINP <VINN, SW30 and SW33 are turned on, and VINP is supplied to the negative input of CDAC1, and VINN is supplied to the positive input of CDAC1.

  By controlling in this way, for the AD converters after CDAC, the + side input can always be made larger than the − side input, and therefore will be described with reference to FIGS. 1, 6, 7, 8, and 10. The correct results can always be obtained with this circuit. If the circuit is configured in this way, the sign determination cycle can be omitted and the speed can be increased when the sign of the signal does not change so much in application and the sign is easy to predict.

<< 7th Embodiment >>
FIG. 16 is a circuit diagram showing an AD converter according to the seventh embodiment of the present invention. In FIG. 16, SW2 to SW5, SW8 to SW11, SW15, SW16, SW19 to SW22, S1, S2PA, S2PB, S2NA, S2NB, S3P, S3N, and S4 are switches, C1 to C12 are capacities, and VINP is (+) VIN + is the (−) analog input, TOP + is the + side top plate of the capacitor array, TOP− is the −side top plate of the capacitor array, and Vrefp is the + side reference potential (for example, 5V). Vrefn is a negative reference potential (for example, 0 V), COMP1 is a comparator, CINP and CINN are comparator inputs, NODE1 and NODE2 are internal nodes, and (+)-side capacitance DAC is C1 to C6. The (-)-side capacitance DAC indicates a DAC configured from C7 to C12. Parts corresponding to circuit elements such as the circuits of FIGS. 1 and 4 and elements having the same functions are given the same element names and node names.

  The circuit in FIG. 16 has almost the same configuration as the circuit in FIG. 1, and the differences are S2PA, S2PB, S2NA, and S2NB. Therefore, the description of the overlapping parts is omitted, and the parts that are different from the circuit in FIG. The explanation is recommended.

  FIG. 15 shows a circuit example to which the concept of the present invention is applied when VINP <VINN. FIG. 15 shows an example of a circuit in which a switch is newly provided at the input portion of the capacitor DAC of the circuit of FIG. 1, for example, but a method as shown in FIG.

  In FIG. 16, S2PA, S2PB, S2NA, and S2NB are provided instead of S2P and S2N in FIG. When VINP> VINN, S2PA and S2NA are turned ON, and VINP is supplied to NODE1 and VINN is supplied to NODE2 (for example, the switch is controlled by COMP2 output SIGN). Conversely, when VINP <VINN, S2PB and S2NB are turned ON, and VINP is supplied to NODE2 and VINN is supplied to NODE1.

  With the configuration as shown in FIG. 16, when the increase in the switches becomes a problem with the configuration as shown in FIG. 15, the effect of reducing the number of switches can be obtained.

  By configuring the circuit as shown in FIG. 16, the circuit of FIG. 16 can be operated in the same manner as the circuit of FIG.

<< Eighth Embodiment >>
17 and 18 are circuit diagrams showing an eighth embodiment of the present invention. In FIG. 17, SW2 to SW5, SW8 to SW11, SW15, SW16, SW19 to SW24, S1, S2P, S2N, S3P, S3N, S4 are switches, C1 to C14 are capacities, TOP + is the + side top plate of the capacity array TOP− is the negative side top plate of the capacitor array, Vrefp is the positive side reference potential (for example, 5V), Vrefn is the negative side reference potential (for example, 0V), and CINP and CINN are the inputs of the comparator. , NODE1 and NODE2 are internal nodes, the (+) side capacitor DAC is a DAC composed of C1 to C6 and C13, the (−) side capacitor DAC is a DAC composed of C7 to C12 and C14, RDACLP, RDACUP, RDACLN, and RDACUN indicate resistance DAC output, and VOFFP and VOFFN indicate conversion results. A bias potential for providing a set, indicates.

  The elements, nodes, etc. in FIG. 18 are the same as those in FIG. 17 and 18, parts corresponding to the circuit elements in FIGS. 8 and 9 and elements having the same function are given the same names. In order to simplify the drawing, there are some parts omitted from the drawings, such as VINP, VINN, S2P, S2N, RDAC2, etc., but the omitted parts are shown in FIG. 6, 7, 8, 9, and the like.

  The circuit in FIG. 17 has almost the same circuit configuration as the circuit in FIG. 8, and the difference is in the connection between C13 and C14. The circuit shown in FIG. 18 is the same as that shown in FIG. 9 except that the connection destinations of C13 and C14 are entered. Portions overlapping with those in FIGS. 8 and 9 are omitted, and portions unique to FIG. 17 will be described with reference to FIG.

  In the circuit of FIG. 8, the top plates of C13 and C14 are TOP + and TOP−. Since C13 and C14 are not sampling capacitors for sampling the analog input signals VINP and VINN, they function the same as the parasitic capacitance for TOP + and TOP−. That is, the final common potential at the time of comparison by the comparator is somewhat shifted from the ideal value. In many cases, the circuit configuration of FIG. 8 has no problem in practice, but when it is desired to minimize the deviation of the common potential, the configuration of FIG. 17 is possible.

  In FIG. 17, the top plates of C13 and C14 are nodes different from the top plates TOP + and TOP− of the capacitive DAC. Since C1 to C6 and C7 to C12 are connected to TOP + and TOP-, respectively, the operation of the capacitor DAC is the same as that of the circuit of FIG.

  Since C13 and C14 are not sampling capacitors, it is convenient if the potential of the top plate is the common potential VCM of the comparator input. For this reason, the top plates of C13 and C14 are connected to the comparator inputs CINP and CINN of FIG.

  Since CINP and CINN are at the VCM potential during sampling, the potentials of the top plates of C13 and C14 are also at VCM. During the sampling period, the potentials of TOP + and TOP− become the common potential of the input analog potential, but there is no problem because TOP +, TOP− and CINP and CINN are separated by SW15 and SW16. When the comparison by the comparator is started, SW15 and SW16 are turned ON, CINP and CINN and TOP + and TOP- become the same potential, and the common potential becomes the reference voltage / 2. Since CINP and CINN have the same potential as TOP + and TOP−, as shown in FIG. 17, even if the top plates of C13 and C14 are separate nodes from TOP + and TOP−, when the comparison operation starts, the circuit of FIG. It can be operated similarly.

17 and FIG. 18, it is possible to separate C13 and C14, which do not contribute to sampling, from TOP + and TOP− while realizing the same operation as in FIG. 8, so that TOP + and TOP− It is possible to reduce the deviation of the final common potential from the ideal value.

  17 and 18, the concept of the present invention can be applied using a complex CR double stage DAC as in the configuration of FIG. 8.

<< Effects of the Embodiment >>
As described above, in the AD converters according to the first to eighth embodiments, by providing the switch S4 or the NMOS transistors NM7 and NM8 and the PMOS transistors PM7 and PM8, the potentials of the internal nodes NODE1 and NODE2 can be increased. Control can be performed so that the power supply voltage range is not maintained. As a result, it is possible to reduce the loss of the charge on the top plate through S3P and S3N, so that a more accurate conversion result can be obtained even when the analog input signal in the power supply voltage range is converted to a digital value.

  Further, according to the AD converters according to the first to eighth embodiments, the analog input VINP supplied to the bottom plate of the (+) side capacitor DAC is supplied to the bottom plate of the (−) side capacitor DAC. If the analog input potential difference (VINP−VINN) is converted to a digital value by assuming that the analog input VINN is greater than or equal to the analog input VINN, and VINP−VINN> = 0 in advance, In the conventional circuit (FIG. 2), AD conversion can be performed by omitting a necessary cycle for determining a code. Thereby, the conversion time can be shortened by the time required for code determination.

  A switch is provided at the input part of the AD converter that converts the differential analog input into a digital value assuming the sign. When VINP is lower than VINN, the sign is assumed by replacing the input signal with the switch. An AD circuit that converts an analog signal into a digital value can be used to realize a circuit that converts an analog signal into a digital value including a sign if necessary.

<Others>
(Appendix 1)
A first analog terminal to which a first analog signal is input;
A first input switch for inputting a first analog signal to the first analog terminal;
A second analog terminal to which a second analog signal is input;
A second input switch for inputting a second analog signal to the second analog terminal;
A first reference voltage connection terminal that receives supply of the first reference voltage;
A second reference voltage connection terminal that receives supply of the second reference voltage;
A first digital-to-analog converter that captures and holds sample data of the first analog signal from the first analog terminal and generates a comparison signal to be compared with the first analog signal;
A second digital-to-analog converter that captures and holds sample data of the second analog signal from the second analog terminal and generates a comparison signal to be compared with the second analog signal;
A first switch for connecting the output sides of the first digital-analog converter and the second digital converter to each other so as to be openable and closable;
When the first switch is opened, a difference value between the first analog signal and the second analog signal and a difference value between the output signal of the first digital-analog converter and the output signal of the second digital-analog converter are obtained. A comparator to compare;
A potential control circuit for controlling potential fluctuations of the first analog terminal and the second analog terminal;
The first digital-analog converter connects a plurality of capacitive elements and respective input side terminals of the plurality of capacitive elements to any one of the first analog terminal, the first reference voltage terminal, and the second reference voltage terminal. A first common terminal that commonly connects a plurality of first switch groups and a plurality of output side terminals facing the input side terminals of the plurality of capacitive elements;
The second digital-analog converter connects a plurality of capacitive elements and respective input-side terminals of the plurality of capacitive elements to any one of the second analog terminal, the first reference voltage terminal, and the second reference voltage terminal. A plurality of second switch groups and a second common terminal commonly connecting a plurality of output side terminals opposed to respective input side terminals of the plurality of capacitive elements;
When the first input switch and the second input switch input the first analog signal and the second analog signal to the first analog terminal and the second analog terminal, the first digital-analog converter and the second digital-analog conversion When the sampler captures the sample data of the first analog signal and the second analog signal, the first common terminal and the second common terminal are connected to each other by the first switch, and when the capture is completed, the first common terminal The connection between the terminal and the second common terminal is released;
When the first input switch and the second input switch are opened after the sampling of the sample data of the first analog signal and the second analog signal is completed, the potential control circuit 2Analog-to-digital conversion circuit that suppresses fluctuations in potential at analog terminals.

(Appendix 2)
The potential control circuit includes a second switch that connects the first analog terminal and the second analog terminal so as to be openable and closable with each other.
When the first input switch and the second input switch are opened after the sampling of the sample data of the first digital signal and the second digital signal is completed, the connection by the first switch is released, and the first switch is opened by the second switch. The analog-digital converter according to appendix 1, wherein one analog terminal and a second analog terminal are connected to each other.

(Appendix 3)
Each of the first input switch and the second input switch has a MOS transistor that opens and closes when a gate voltage is controlled between the first reference voltage and the second reference voltage,
The potential control circuit includes:
A first adjustment MOS transistor having a source and a drain connected to the first analog terminal and a gate controlled between the first reference voltage and a second reference voltage;
A second adjustment MOS transistor having a source and a drain connected to the second analog terminal and a gate controlled between the first reference voltage and the second reference voltage;
After the sampling of the sample data of the first digital signal and the second digital signal is completed, the gate voltage of the MOS transistor of the first input switch is controlled between the first reference voltage and the second reference voltage. When the one input switch is opened, the gate voltage of the first adjustment MOS transistor is controlled in the direction opposite to the gate voltage of the MOS transistor of the first input switch, and the gate voltage of the MOS transistor of the second input switch When the second input switch is opened by controlling between the first reference voltage and the second reference voltage, the gate voltage of the second adjustment MOS transistor is set to the gate voltage of the MOS transistor of the second input switch. The analog-digital converter of Claim 1 which has a gate control circuit controlled to a reverse direction.

(Appendix 4)
Each of the first switch and the second switch includes a first conductivity type first MOS transistor and a second conductivity type second MOS transistor, and the gate voltage of the first MOS transistor is used as a first reference voltage and the second MOS transistor is used. And the gate voltage of the first MOS transistor is set to the second reference voltage and the gate voltage of the second MOS transistor is set to the first reference voltage.
The first adjustment MOS transistor and the second adjustment MOS transistor each have a first conductivity type third MOS transistor and a second conductivity type fourth MOS transistor, and the gate voltage of the first MOS transistor is a second reference voltage. When the gate voltage of the second MOS transistor is the first reference voltage, the gate voltage of the third MOS transistor is the first reference voltage, and the gate voltage of the fourth MOS transistor is the second reference voltage. The analog-digital converter according to Appendix 3.

(Appendix 5)
A first analog terminal to which a first analog signal is input;
A first input switch for inputting a first analog signal to the first analog terminal;
A second analog terminal to which a second analog signal is input;
A second input switch for inputting a second analog signal to the second analog terminal;
A first reference voltage connection terminal that receives supply of the first reference voltage;
A second reference voltage connection terminal that receives supply of the second reference voltage;
A first digital-to-analog converter that captures and holds sample data of the first analog signal from the first analog terminal and generates a comparison signal to be compared with the first analog signal;
A second digital-to-analog converter that captures and holds sample data of the second analog signal from the second analog terminal and generates a comparison signal to be compared with the second analog signal;
A first switch for connecting the output sides of the first digital-analog converter and the second digital converter to each other so as to be openable and closable;
A comparator that compares the difference value between the first analog signal and the second analog signal and the difference value between the output signal of the first digital-analog converter and the output signal of the second digital-analog converter;
The first digital-analog converter connects a plurality of capacitive elements and respective input side terminals of the plurality of capacitive elements to any one of the first analog terminal, the first reference voltage terminal, and the second reference voltage terminal. A first common terminal that connects a plurality of first switch groups and an output side terminal facing each input side terminal of the plurality of capacitive elements;
The second digital-analog converter connects a plurality of capacitive elements and respective input-side terminals of the plurality of capacitive elements to any one of the second analog terminal, the first reference voltage terminal, and the second reference voltage terminal. A second common terminal for connecting a plurality of second switch groups and an output side terminal facing each input side terminal of the plurality of capacitive elements;
The plurality of capacitive elements of the first digital-analog converter include a first capacitive element having a capacity corresponding to ½ of the total capacity of the plurality of capacitive elements, and the sample data of the first digital signal is captured. After completion, one of the first reference voltage terminal and the second reference voltage terminal is connected to the input side terminal of the capacitive element other than the first capacitive element based on the comparison result of the comparator, The first reference voltage terminal is connected to the input side terminal of the first capacitive element regardless of the comparison result of the comparator,
The plurality of capacitive elements of the second digital-analog converter include a second capacitive element having a capacity corresponding to ½ of the total capacity of the plurality of capacitive elements, and the sample data of the second digital signal is captured. After completion, one of the first reference voltage terminal and the second reference voltage terminal is connected to the input side terminal of the capacitive element other than the second capacitive element based on the comparison result of the comparator, An analog-to-digital conversion circuit in which the second reference voltage terminal is connected to an input side terminal of the second capacitive element regardless of a result of comparison by the comparator.

(Appendix 6)
A comparator that compares the signal level of the first analog signal with the signal level of the second analog signal;
According to the result of the comparison, the first analog signal and the second analog signal are switched, and a switch is further provided so that the signal level input to the first analog terminal is higher than the signal level input to the second analog terminal. The analog-digital converter according to appendix 5.

COMP1 Comparator NODE1
NODE2
S1, S2P, S2N, S3P, S3N, S4, SW2-SW5, SW8-SW11, SW13, SW14, SW15, SW16, SW19, SW20, SW21, SW22
Switch Vrefp + side reference potential Vrefn − side reference potential TOP + + side top plate TOP− − side top plate NM7, NM8 NMOS transistor PM7, PM8 PMOS transistor

Claims (2)

A first analog terminal to which a first analog signal is input;
A first input switch for inputting the first analog signal to the first analog terminal;
A second analog terminal to which a second analog signal is input;
A second input switch for inputting the second analog signal to the second analog terminal;
A first reference voltage connection terminal that receives supply of the first reference voltage;
A second reference voltage connection terminal that receives supply of the second reference voltage;
A first digital-to-analog converter that captures and holds sample data of the first analog signal from the first analog terminal and generates a first comparison signal to be compared with the first analog signal;
A second digital-to-analog converter that captures and holds sample data of the second analog signal from the second analog terminal and generates a second comparison signal to be compared with the second analog signal;
A first switch that opens or conducts an output side of the first digital-analog converter and an output side of the second digital-analog converter;
A comparator for comparing a difference value between the first analog signal and the second analog signal and a difference value between an output signal of the first digital-analog converter and an output signal of the second digital-analog converter;
In the first digital-analog converter, the input terminals of the first plurality of capacitive elements and the first plurality of capacitive elements are connected to the first analog terminal, the first reference voltage terminal, and the second reference, respectively. A plurality of first switch groups connected to any one of the voltage terminals and a first common terminal connecting an output side terminal facing each input side terminal of the first plurality of capacitive elements;
The second digital-to-analog converter has input terminals of the second plurality of capacitive elements and the second plurality of capacitive elements as the second analog terminal, the first reference voltage terminal, and the second reference, respectively. A plurality of second switch groups connected to any one of the voltage terminals, and a second common terminal connecting an output side terminal facing each input side terminal of the second plurality of capacitive elements,
The first plurality of capacitive elements includes a first capacitive element having a capacity corresponding to ½ of the total capacity of the first plurality of capacitive elements, and capturing of sample data of the first analog signal has been completed. Later, either the first reference voltage terminal or the second reference voltage terminal is connected to an input side terminal of a capacitive element other than the first capacitive element based on a result of comparison of the comparator, The first reference voltage terminal is connected to the input side terminal of the first capacitive element regardless of the result of the comparison of the comparator,
The second plurality of capacitive elements includes a second capacitive element having a capacity corresponding to ½ of the overall capacity of the second plurality of capacitive elements, and capturing of the sample data of the second analog signal has been completed. Later, either the first reference voltage terminal or the second reference voltage terminal is connected to the input side terminal of the capacitive element other than the second capacitive element based on the comparison result of the comparator, An analog-to-digital converter in which the second reference voltage terminal is connected to the input-side terminal of the second capacitance element regardless of the comparison result of the comparator. A comparator that compares the signal level of the first analog signal with the signal level of the second analog signal;
Depending on the result of the comparator, the first analog signal and the second analog signal are interchanged so that the signal level input to the first analog terminal is higher than the signal level input to the second analog terminal. The analog-digital converter according to claim 1, further comprising a second switch.

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