JP2011034620A - Shift register - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a pulse waveform proportional to an optional pulse width of an input to perform shift operation by clock synchronization. <P>SOLUTION: In a shift register used for a pixel row drive circuit or a pixel drive control circuit of a display device, a scan drive circuit of a solid state imaging element of CCD/CMOS etc., all transistors T1-T12 that constitute each register have single polarity. Each register has input terminals D and Dx which have positive polarity and negative polarity, respectively, is synchronized with a clock CLK and latches inputs from the input terminals, respectively. The shift register changes latched voltage signals Va and Vb to a voltage which exceeds a power supply voltage by charge pump circuits T7, T8, and C1-C4, switches the output stage transistors T9 and T11 to the power supply voltage using the changed voltage signals, and outputs the latch signals of the positive polarity and the negative polarity which are synchronized with a clock. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a shift register used for a pixel column driving circuit or a pixel driving control circuit of a display device, a scanning driving circuit of a solid-state imaging device such as a CCD / CMOS, or the like.

  FIG. 1 shows a configuration example of a basic register circuit constituting a conventional shift register, and FIG. 2 shows signal waveforms at various points in the shift register.

  Prior to the widespread use of the shift register having the configuration shown in FIG. 1, an inverter circuit using a resistor or a depletion type transistor as an active load was used in the register circuit.・ It is not used normally for reliability reasons. In addition, as disclosed in Patent Document 1, there is an example in which an active load composed of enhancement type transistors is used.

  Between the power supply VDD and the negative power supply VSS, a series connection of transistors M1 and M2, a series connection of transistors M3 and M4, a series connection of transistors M7 and M8, and a series connection of transistors M9 and M10 are arranged. Yes. The series connection of the output stage transistors M5 and M6 is arranged between the clock CLK1 and the negative power supply VSS, and the series connection of the output stage transistors M11 and M12 is arranged between the clock CLK2 and the negative power supply VSS. In this example, the transistors M1 to M12 are all composed of NMOS.

  An input D is supplied to the gates of the transistors M1 and M4, the gates of the transistors M2 and M6 are connected to the intermediate point (signal Va1) of the transistors M3 and M4, and the intermediate point (signal Vb1) of the transistors M1 and M2 is the transistor M5. Connected to the gate. The clock CLK3 is supplied to the gate of the transistor M3.

  The intermediate points (output signal Q1) of the transistors M5 and M6 in the output stage are supplied to the gates of the transistors M7 and M10, and the intermediate points (signal Va2) of the transistors M9 and M10 are connected to the gates of the transistors M8 and M12. An intermediate point (signal Vb2) between M7 and M8 is connected to the gate of the transistor M11. The clock CLK1 is supplied to the gate of the transistor M9. Then, a signal Q2 is output from an intermediate point between the transistors M11 and M12.

  The drain of the transistor M5 on the pull-up side of the output stage is connected to CLK1, and when this transistor is turned on, the gate potential of the transistor is bootstrapped by this connected CLK, and the output (Q1) level is the power supply. The voltage is raised to the vicinity of the voltage VDD, and the operation of the register after the next stage is ensured.

  The operation and bootstrap of the circuit of FIG. 1 will be described below with reference to FIG. Here, Hi of D and the clocks (CLK1 to CLK3) is VDD, and Low is VSS. When D is Hi (VDD level), M1 and M4 are turned on. When M4 is turned on, Va1 is pulled down to VSS by M4. As a result, the gate voltages of M2 and M6 become VSS and M2 and M6 are turned off. Vb1 is a VDD-Vth voltage that is lower than the D potential by the threshold voltage of M1. M3 is turned on because CLK3 becomes Hi, but its current drive capability (transistor size) is designed to be smaller than M4 and does not pull up Va1. When CLK1 becomes Hi, CLK1 jumps into Vb1 by ΔV through parasitic capacitance Ct5 (mainly parasitic capacitance between gate-drain / gate-source such as Cgs and Cgd) related to the transistor M5. This ΔV can be defined as follows by the parasitic capacitance Cl, Ct5 between the line Vb1 and VSS and the amplitude Vclk1 of CLK1.

  When CLK1 in FIG. 2 becomes Hi, Va1 is increased by ΔV from VDD−Vth. Since the parasitic capacitance depends on the layout change and the process change, when a reliable operation is desired, these capacitances are installed as actual capacitances independent of the parasitic capacitance. This bootstrap ensures that Q1 is pulled up to the high level (VDD level) of CLK1.

  When D goes low, M1 / M4 is turned off, and then the first CLK3 Hi, Va1 is pulled up to VDD by the transistor M3 and becomes Hi, M2 / M6 is turned from off to on, and Vb1 is pulled down to VSS. Q1 is similarly pulled down to VSS.

Various things have been proposed since this example,
1) Output stage using bootstrap 2) It is configured to discharge the accumulated charge in the register with CLK or the register output of the subsequent stage, and it has a simple circuit configuration and a reliable operation. It has been improved.

JP 2001-176288 A US Pat. No. 5,222,082 JP-A-8-263027 JP 2000-155550 A

  Here, when the input D is a pulse having an arbitrary width, the period during which the input D is Hi is limited, and the output becomes two pulses divided by the clock as shown in FIG. 3, and this propagates through the shift register. It will be. This is inconvenient for the purpose of propagating an input D having an arbitrary width as it is in clock synchronization. Moreover, even if an attempt is made to create a target waveform using a logic combination circuit, there may be a problem that the target pulse is not obtained due to CLK timing or skew. As a countermeasure, it is conceivable to connect the drains of the pull-up side transistors M5 and M11 of the bootstrap circuit based on the CLK of the output stage to the power supply as shown on the right side of FIG. In this case, the Hi level of the output gradually decreases by the threshold voltage of the transistor for each stage (VDD−Vth), the signal cannot be driven to the register, and pulse propagation is interrupted after several stages.

  The present invention is a shift register used in a pixel column driving circuit or a pixel driving control circuit of a display device, a scanning driving circuit of a solid-state imaging device such as a CCD / CMOS, etc., and all the transistors constituting each register are single. Each register has positive and negative input terminals, latches the input from the input terminal in synchronization with the clock, and the latched voltage signal is supplied to the power supply voltage by the charge pump circuit. The output stage transistor is switched to the power supply voltage by using the voltage signal thus shifted, and positive and negative latch signals synchronized with the clock are output.

  Further, it is preferable that the transistors constituting each register are NMOS.

  In addition, it is preferable that the transistor constituting each register is a PMOS.

  In each register, it is preferable that a third terminal excluding the gate terminal and the terminal connected to the output terminal in the output stage transistor is connected to the power source.

  The charge pump circuit includes a transistor that receives a latched internal voltage signal line at a gate, a clock is supplied to one terminal, and the other terminal is connected to the latched internal voltage signal line through a capacitor. It is preferable to utilize the voltage change that the clock voltage change has on the latched internal voltage signal line when the transistor is on.

  According to the present invention, in a PMOS-type or NMOS-type shift register, a pulse waveform proportional to an input arbitrary pulse width can be shifted in synchronization with a clock.

It is a figure which shows the structure of the conventional register | resistor. It is a figure which shows an example of the signal waveform of each place of the structure of FIG. It is a figure which shows an example of the signal waveform of each place of the structure of FIG. It is a figure which shows the modification of an output stage. 2 is a diagram illustrating a configuration of a register according to the first embodiment. FIG. It is a figure which shows an example of the signal waveform of each place of the structure of FIG. It is a figure which shows the structure at the time of providing the register | resistor of Embodiment 1 in multistage. 6 is a diagram illustrating a configuration of a register according to the second embodiment. FIG.

In this embodiment, the basic configuration of a conventional circuit.
1) Output stage using bootstrap,
2) Discharge the accumulated charge in the register with CLK or the register output at the subsequent stage.
The two circuit configurations are not used.

That is,
a) Output stage without bootstrap,
b) Do not discharge the accumulated charge in the register with CLK or the subsequent register output.
The structure is taken.

And in order to realize the configuration a)
c) Increase the internal holding voltage with the charge pump to ensure Hi output.
In order to realize the configuration b),
d) Bipolar output of Q output and Qx output having opposite polarity.
By adopting such a configuration, a shift register that reliably propagates data is configured.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

“Embodiment 1”
FIG. 5 shows a circuit diagram of a register composed of NMOS as the first embodiment. Here, it is assumed that the Hi level of D, Dx, CLK, and CLKx is VDD, and the Low level is VSS. It should be noted that the Hi level of CLK and CLKx is preferably VDD + Vth or higher.

  The drain of the transistor T1 is connected to VDD, the gate is connected to CLK, and the source is connected to the drain of the transistor T2. The input D is supplied to the gate of the transistor T2, and the source is connected to the drain of the transistor T3. The source of the transistor T3 is connected to VSS. The drain of the transistor T4 is connected to VDD, the gate is connected to CLK, and the source is connected to the drain of the transistor T5. An input Dx is supplied to the gate of the transistor T5, and the source is connected to the drain of the transistor T6. The source of the transistor T6 is connected to VSS. The gate of the transistor T6 and the Va line are connected to an intermediate point between the transistors T2 and T3. The gate of the transistor T3 and the Vb line are connected to an intermediate point between the transistors T5 and T6.

  The Va line is connected to VSS via a capacitor C1, and the Vb line is connected to VSS via a capacitor C2.

  The Va line is connected to the gate of the transistor T7, the drain of the transistor T7 is connected to CLKx, and the source is connected to the Va line via the capacitor C3. The gate of the transistor T8 is connected to the Vb line, the drain of the transistor T8 is connected to CLKx, and the source is connected to the Vb line via the capacitor C4.

  The Va line is connected to the gate of the transistor T9, the drain of the transistor T9 is connected to VDD, and the source is connected to the drain of the transistor T10. The gate of the transistor T10 is connected to the Vb line, and the source is connected to VSS. The gate of the transistor T11 is connected to the Vb line, the drain of the transistor T11 is connected to VDD, and the source is connected to the drain of the transistor T12. The gate of the transistor T12 is connected to the Va line, and the source is connected to VSS.

  An intermediate point between the transistors T9 and T10 is connected to the output Q line, and an intermediate point between the transistors T11 and T12 is connected to the output Qx line.

  In such a circuit, the clock-synchronized latch composed of the first-stage transistors T1 to T6 performs a latch operation on the Hi side of either the input D or the inverting input Dx. Although the capacitors C1 and C2 are explicitly inserted, the parasitic capacitance of the circuit can be used.

  As shown in FIG. 6, the clocks CLK and CLKx are pulses having opposite polarities, and the inputs D and Dx are also signals having opposite polarities.

  When the input D is Hi (input Dx is Low), T2 is turned on, T1 is turned on when CLK is Hi, the Va line is Hi, and since the input Dx is Low, T5 is turned off and T6 is turned on. Therefore, the Vb line becomes Low.

  Here, when the input D is Hi, T7 and C3 operate as a charge pump circuit. That is, when the input D is Hi and the CLK is Hi, the Va line is at a potential that is lower than the Hi potential (VDD) of the input D and the threshold voltage Vth of T1, and the signal line is in a low impedance state. At this time, since CLKx is Low, C3 is clamped to the Va line. Next, when CLK becomes low, T1 is turned off and the Va line becomes high impedance. On the other hand, since CLKx becomes Hi, this Hi raises the Va voltage via C3 and operates as a charge pump.

  When D is low, Va is low level and low impedance, so T7 is turned off and the charge pump circuit stops operating. The transistor T8 and the capacitor C4 similarly operate as a charge pump circuit when the inverting input Dx is Hi.

  Therefore, when the voltage of the Va line and the Vb line is Hi, the respective charge pump circuits maintain a voltage higher than VDD−Vth by ΔV during the period when the corresponding CLK or CLKx is Hi (VDD−Vth + ΔV). Similarly to the case described in the bootstrap, assuming that the rising voltage of the Va line is ΔVx and the rising voltage of the Vb line is ΔVy, respectively, the following equations are given.

  Here, Cla is a parasitic capacitance to the VSS of the Va line, similarly Clb is a parasitic capacitance to the VSS of the Vb line, and Vclkx is a voltage of CLKx.

  The output Q on the positive polarity side has an output stage composed of a pull-up transistor T9 and a pull-down transistor T10. The transistor T9 is responsible for Hi output and T10 is responsible for Low output. When the transistor T9 performs Hi output, the gate voltage Va is VDD−Vth when CLKx is Low and VDD−Vth + ΔVx as described above when CLKx is Hi. If the capacitance values of the capacitors C1 and C3 are appropriately set and Vclkx is a sufficient voltage, VDD−Vth + ΔVx is a voltage exceeding VDD. Therefore, the transistor T9 is reliably turned on when the CLKx is in the Hi period, the output Q becomes VDD, and a sufficient voltage is output to the next stage.

  Since the next input stage is configured to be sampled with the opposite phase CLKx, the VDD level is used as an input, and reliable signal propagation is performed. Similarly, the output Qx on the input negative polarity side is constituted by the pull-up transistor T11 and the pull-down transistor T12 and performs the same operation as that on the positive polarity side.

  FIG. 7 shows a configuration when the registers of FIG. 5 are connected in multiple stages. In this way, a pair of outputs (middle point between the transistors Tm9 and Tm10 and the middle point between the transistors Tm11 and Tm12) Qm, Qmx (m = 1, 2, 3,...) Are registers in the next stage. Are input to the gates of the transistors Tn2 and Tn5.

“Embodiment 2”
The configuration of the second embodiment is shown in FIG. A transistor T21 is used instead of the transistors T1 and T2, and a transistor T22 is used instead of the transistors T4 and T5.

  In the transistor T21, the input D is supplied to the drain, the source is connected to the drain of the transistor T3, and CLK is supplied to the gate. In the transistor T22, the input Dx is supplied to the drain, the source is connected to the drain of the transistor T6, and CLK is supplied to the gate.

  According to this configuration, when CLK is Hi, the transistors T21 and T22 are turned on, the input D is supplied to the Va line, the input Dx is supplied to the Vb line, and the operation timing is the same as in the circuit of the first embodiment. Become. The second embodiment has a simpler configuration than that of the first embodiment.

"Other"
In the first and second embodiments described above, NMOS is used as the transistor. However, even if PMOS is used for all the transistors, the on-timing of the transistors is opposite, and the charge pump operation is only on the low side. It operates in the same way.

  T1-T12 transistor, C1-C4 capacitance, Cla-Clb parasitic capacitance.

Claims (5)

A shift register comprising a plurality of registers,
All the transistors that make up each register have a single polarity,
Each register is
Has both positive and negative input terminals,
Each input from the input terminal is latched in synchronization with the clock,
Transition the latched voltage signal to a voltage exceeding the power supply voltage with the charge pump circuit,
A shift register that outputs positive and negative latch signals synchronized with the clock by switching the output stage transistor to the power supply voltage using the voltage signal that has been changed. The shift register according to claim 1,
A shift register in which the transistors constituting each register are NMOS. The shift register according to claim 1,
A shift register in which the transistors constituting each register are PMOS. The shift register according to any one of claims 1 to 3,
Each register is
A shift register in which a third terminal of the output stage transistor is connected to a power source except for a gate terminal and a terminal connected to the output terminal. A shift register according to any one of claims 1 to 4,
The charge pump circuit includes a transistor that receives a latched internal voltage signal line at a gate, a clock is supplied to one terminal, and the other terminal is connected to the latched internal voltage signal line via a capacitor. A shift register that utilizes a voltage change applied to a latched internal voltage signal line when a transistor voltage is turned on.

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